drivers/net/igb/e1000_defines.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_DEFINES_H_
  29 #define _E1000_DEFINES_H_
  30
  31 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
  32 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
  33 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
  34
  35 /* Definitions for power management and wakeup registers */
  36 /* Wake Up Control */
  37 #define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
  38
  39 /* Wake Up Filter Control */
  40 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  41 #define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  42 #define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  43 #define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
  44 #define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  45 #define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
  46 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
  47 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
  48 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
  49 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
  50 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
  51 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
  52 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
  53
  54 /* Wake Up Status */
  55
  56 /* Wake Up Packet Length */
  57
  58 /* Four Flexible Filters are supported */
  59 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
  60
  61 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
  62 #define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
  63
  64
  65 /* Extended Device Control */
  66 #define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
  67 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
  68 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
  69 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
  70 #define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
  71 #define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
  72 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
  73 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
  74 #define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
  75 #define E1000_CTRL_EXT_EIAME          0x01000000
  76 #define E1000_CTRL_EXT_IRCA           0x00000001
  77 /* Interrupt delay cancellation */
  78 /* Driver loaded bit for FW */
  79 #define E1000_CTRL_EXT_DRV_LOAD       0x10000000
  80 /* Interrupt acknowledge Auto-mask */
  81 /* Clear Interrupt timers after IMS clear */
  82 /* packet buffer parity error detection enabled */
  83 /* descriptor FIFO parity error detection enable */
  84 #define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
  85 #define E1000_I2CCMD_REG_ADDR_SHIFT   16
  86 #define E1000_I2CCMD_PHY_ADDR_SHIFT   24
  87 #define E1000_I2CCMD_OPCODE_READ      0x08000000
  88 #define E1000_I2CCMD_OPCODE_WRITE     0x00000000
  89 #define E1000_I2CCMD_READY            0x20000000
  90 #define E1000_I2CCMD_ERROR            0x80000000
  91 #define E1000_MAX_SGMII_PHY_REG_ADDR  255
  92 #define E1000_I2CCMD_PHY_TIMEOUT      200
  93
  94 /* Receive Decriptor bit definitions */
  95 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
  96 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
  97 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
  98 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
  99 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum caculated */
 100 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
 101 #define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
 102 #define E1000_RXD_ERR_CE        0x01    /* CRC Error */
 103 #define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
 104 #define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
 105 #define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
 106 #define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
 107 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
 108
 109 #define E1000_RXDEXT_STATERR_CE    0x01000000
 110 #define E1000_RXDEXT_STATERR_SE    0x02000000
 111 #define E1000_RXDEXT_STATERR_SEQ   0x04000000
 112 #define E1000_RXDEXT_STATERR_CXE   0x10000000
 113 #define E1000_RXDEXT_STATERR_TCPE  0x20000000
 114 #define E1000_RXDEXT_STATERR_IPE   0x40000000
 115 #define E1000_RXDEXT_STATERR_RXE   0x80000000
 116
 117 /* mask to determine if packets should be dropped due to frame errors */
 118 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
 119     E1000_RXD_ERR_CE  |                \
 120     E1000_RXD_ERR_SE  |                \
 121     E1000_RXD_ERR_SEQ |                \
 122     E1000_RXD_ERR_CXE |                \
 123     E1000_RXD_ERR_RXE)
 124
 125 /* Same mask, but for extended and packet split descriptors */
 126 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
 127     E1000_RXDEXT_STATERR_CE  |            \
 128     E1000_RXDEXT_STATERR_SE  |            \
 129     E1000_RXDEXT_STATERR_SEQ |            \
 130     E1000_RXDEXT_STATERR_CXE |            \
 131     E1000_RXDEXT_STATERR_RXE)
 132
 133 #define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
 134 #define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
 135 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
 136 #define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
 137 #define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
 138
 139
 140 /* Management Control */
 141 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
 142 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
 143 #define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
 144 /* Enable Neighbor Discovery Filtering */
 145 #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
 146 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
 147 /* Enable MAC address filtering */
 148 #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
 149 /* Enable MNG packets to host memory */
 150 #define E1000_MANC_EN_MNG2HOST   0x00200000
 151 /* Enable IP address filtering */
 152
 153
 154 /* Receive Control */
 155 #define E1000_RCTL_EN             0x00000002    /* enable */
 156 #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
 157 #define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
 158 #define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
 159 #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
 160 #define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
 161 #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
 162 #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
 163 #define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
 164 #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
 165 #define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
 166 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
 167 #define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
 168 #define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
 169 #define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
 170 #define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
 171 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
 172 #define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
 173 #define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
 174 #define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
 175 #define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
 176 #define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
 177 #define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
 178 #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
 179
 180 /*
 181  * Use byte values for the following shift parameters
 182  * Usage:
 183  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
 184  *                  E1000_PSRCTL_BSIZE0_MASK) |
 185  *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
 186  *                  E1000_PSRCTL_BSIZE1_MASK) |
 187  *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
 188  *                  E1000_PSRCTL_BSIZE2_MASK) |
 189  *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
 190  *                  E1000_PSRCTL_BSIZE3_MASK))
 191  * where value0 = [128..16256],  default=256
 192  *       value1 = [1024..64512], default=4096
 193  *       value2 = [0..64512],    default=4096
 194  *       value3 = [0..64512],    default=0
 195  */
 196
 197 #define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
 198 #define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
 199 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
 200 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
 201
 202 #define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
 203 #define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
 204 #define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
 205 #define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
 206
 207 /* SWFW_SYNC Definitions */
 208 #define E1000_SWFW_EEP_SM   0x1
 209 #define E1000_SWFW_PHY0_SM  0x2
 210 #define E1000_SWFW_PHY1_SM  0x4
 211
 212 /* FACTPS Definitions */
 213 /* Device Control */
 214 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 215 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
 216 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
 217 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
 218 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
 219 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
 220 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
 221 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
 222 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
 223 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
 224 /* Defined polarity of Dock/Undock indication in SDP[0] */
 225 /* Reset both PHY ports, through PHYRST_N pin */
 226 /* enable link status from external LINK_0 and LINK_1 pins */
 227 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 228 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 229 #define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
 230 #define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
 231 #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
 232 #define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
 233 #define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
 234 #define E1000_CTRL_RST      0x04000000  /* Global reset */
 235 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 236 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
 237 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 238 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
 239 /* Initiate an interrupt to manageability engine */
 240 #define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
 241
 242 /* Bit definitions for the Management Data IO (MDIO) and Management Data
 243  * Clock (MDC) pins in the Device Control Register.
 244  */
 245
 246 #define E1000_CONNSW_ENRGSRC             0x4
 247 #define E1000_PCS_LCTL_FLV_LINK_UP       1
 248 #define E1000_PCS_LCTL_FSV_100           2
 249 #define E1000_PCS_LCTL_FSV_1000          4
 250 #define E1000_PCS_LCTL_FDV_FULL          8
 251 #define E1000_PCS_LCTL_FSD               0x10
 252 #define E1000_PCS_LCTL_FORCE_LINK        0x20
 253 #define E1000_PCS_LCTL_AN_ENABLE         0x10000
 254 #define E1000_PCS_LCTL_AN_RESTART        0x20000
 255 #define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
 256
 257 #define E1000_PCS_LSTS_LINK_OK           1
 258 #define E1000_PCS_LSTS_SPEED_100         2
 259 #define E1000_PCS_LSTS_SPEED_1000        4
 260 #define E1000_PCS_LSTS_DUPLEX_FULL       8
 261 #define E1000_PCS_LSTS_SYNK_OK           0x10
 262
 263 /* Device Status */
 264 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 265 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 266 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 267 #define E1000_STATUS_FUNC_SHIFT 2
 268 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 269 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 270 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 271 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 272 /* Change in Dock/Undock state. Clear on write '0'. */
 273 /* Status of Master requests. */
 274 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
 275 /* BMC external code execution disabled */
 276
 277 /* Constants used to intrepret the masked PCI-X bus speed. */
 278
 279 #define SPEED_10    10
 280 #define SPEED_100   100
 281 #define SPEED_1000  1000
 282 #define HALF_DUPLEX 1
 283 #define FULL_DUPLEX 2
 284
 285
 286 #define ADVERTISE_10_HALF                 0x0001
 287 #define ADVERTISE_10_FULL                 0x0002
 288 #define ADVERTISE_100_HALF                0x0004
 289 #define ADVERTISE_100_FULL                0x0008
 290 #define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
 291 #define ADVERTISE_1000_FULL               0x0020
 292
 293 /* 1000/H is not supported, nor spec-compliant. */
 294 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
 295                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
 296                                                       ADVERTISE_1000_FULL)
 297 #define E1000_ALL_NOT_GIG      (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
 298                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 299 #define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 300 #define E1000_ALL_10_SPEED     (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL)
 301 #define E1000_ALL_FULL_DUPLEX  (ADVERTISE_10_FULL  |  ADVERTISE_100_FULL | \
 302                                                       ADVERTISE_1000_FULL)
 303 #define E1000_ALL_HALF_DUPLEX  (ADVERTISE_10_HALF  |  ADVERTISE_100_HALF)
 304
 305 #define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
 306
 307 /* LED Control */
 308 #define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
 309 #define E1000_LEDCTL_LED0_MODE_SHIFT      0
 310 #define E1000_LEDCTL_LED0_IVRT            0x00000040
 311 #define E1000_LEDCTL_LED0_BLINK           0x00000080
 312
 313 #define E1000_LEDCTL_MODE_LED_ON        0xE
 314 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 315
 316 /* Transmit Descriptor bit definitions */
 317 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 318 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 319 #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 320 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 321 #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 322 #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 323 /* Extended desc bits for Linksec and timesync */
 324
 325 /* Transmit Control */
 326 #define E1000_TCTL_EN     0x00000002    /* enable tx */
 327 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
 328 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
 329 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
 330 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
 331
 332 /* Transmit Arbitration Count */
 333
 334 /* SerDes Control */
 335 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
 336
 337 /* Receive Checksum Control */
 338 #define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
 339 #define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
 340 #define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
 341
 342 /* Header split receive */
 343
 344 /* Collision related configuration parameters */
 345 #define E1000_COLLISION_THRESHOLD       15
 346 #define E1000_CT_SHIFT                  4
 347 #define E1000_COLLISION_DISTANCE        63
 348 #define E1000_COLD_SHIFT                12
 349
 350 /* Ethertype field values */
 351 #define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 352
 353 #define MAX_JUMBO_FRAME_SIZE    0x3F00
 354
 355 /* Extended Configuration Control and Size */
 356 #define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
 357
 358 /* PBA constants */
 359 #define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
 360 #define E1000_PBA_24K 0x0018
 361 #define E1000_PBA_34K 0x0022
 362
 363 #define IFS_MAX       80
 364 #define IFS_MIN       40
 365 #define IFS_RATIO     4
 366 #define IFS_STEP      10
 367 #define MIN_NUM_XMITS 1000
 368
 369 /* SW Semaphore Register */
 370 #define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
 371 #define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
 372
 373 /* Interrupt Cause Read */
 374 #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
 375 #define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
 376 #define E1000_ICR_LSC           0x00000004 /* Link Status Change */
 377 #define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
 378 #define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
 379 #define E1000_ICR_RXO           0x00000040 /* rx overrun */
 380 #define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
 381 #define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
 382 #define E1000_ICR_RXCFG         0x00000400 /* RX /c/ ordered set */
 383 #define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
 384 #define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
 385 #define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
 386 #define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
 387 #define E1000_ICR_TXD_LOW       0x00008000
 388 #define E1000_ICR_SRPD          0x00010000
 389 #define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
 390 #define E1000_ICR_MNG           0x00040000 /* Manageability event */
 391 #define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
 392 /* If this bit asserted, the driver should claim the interrupt */
 393 #define E1000_ICR_INT_ASSERTED  0x80000000
 394 /* queue 0 Rx descriptor FIFO parity error */
 395 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000
 396 /* queue 0 Tx descriptor FIFO parity error */
 397 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000
 398 /* host arb read buffer parity error */
 399 #define E1000_ICR_HOST_ARB_PAR  0x00400000
 400 #define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
 401 /* queue 1 Rx descriptor FIFO parity error */
 402 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000
 403 /* queue 1 Tx descriptor FIFO parity error */
 404 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000
 405 /* FW changed the status of DISSW bit in the FWSM */
 406 #define E1000_ICR_DSW           0x00000020
 407 /* LAN connected device generates an interrupt */
 408 #define E1000_ICR_PHYINT        0x00001000
 409 #define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */
 410
 411 /* Extended Interrupt Cause Read */
 412 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
 413 #define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
 414 #define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
 415 #define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
 416 #define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
 417 #define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
 418 #define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
 419 #define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
 420 #define E1000_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
 421 #define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
 422 /* TCP Timer */
 423
 424 /*
 425  * This defines the bits that are set in the Interrupt Mask
 426  * Set/Read Register.  Each bit is documented below:
 427  *   o RXT0   = Receiver Timer Interrupt (ring 0)
 428  *   o TXDW   = Transmit Descriptor Written Back
 429  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 430  *   o RXSEQ  = Receive Sequence Error
 431  *   o LSC    = Link Status Change
 432  */
 433 #define IMS_ENABLE_MASK ( \
 434     E1000_IMS_RXT0   |    \
 435     E1000_IMS_TXDW   |    \
 436     E1000_IMS_RXDMT0 |    \
 437     E1000_IMS_RXSEQ  |    \
 438     E1000_IMS_LSC)
 439
 440 /* Interrupt Mask Set */
 441 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
 442 #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
 443 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 444 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 445 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
 446 /* queue 0 Rx descriptor FIFO parity error */
 447 /* queue 0 Tx descriptor FIFO parity error */
 448 /* host arb read buffer parity error */
 449 /* packet buffer parity error */
 450 /* queue 1 Rx descriptor FIFO parity error */
 451 /* queue 1 Tx descriptor FIFO parity error */
 452
 453 /* Extended Interrupt Mask Set */
 454 #define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
 455 #define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 456
 457 /* Interrupt Cause Set */
 458 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 459 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 460 /* queue 0 Rx descriptor FIFO parity error */
 461 /* queue 0 Tx descriptor FIFO parity error */
 462 /* host arb read buffer parity error */
 463 /* packet buffer parity error */
 464 /* queue 1 Rx descriptor FIFO parity error */
 465 /* queue 1 Tx descriptor FIFO parity error */
 466
 467 /* Extended Interrupt Cause Set */
 468
 469 /* Transmit Descriptor Control */
 470 /* Enable the counting of descriptors still to be processed. */
 471
 472 /* Flow Control Constants */
 473 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
 474 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
 475 #define FLOW_CONTROL_TYPE         0x8808
 476
 477 /* 802.1q VLAN Packet Size */
 478 #define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
 479 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 480
 481 /* Receive Address */
 482 /*
 483  * Number of high/low register pairs in the RAR. The RAR (Receive Address
 484  * Registers) holds the directed and multicast addresses that we monitor.
 485  * Technically, we have 16 spots.  However, we reserve one of these spots
 486  * (RAR[15]) for our directed address used by controllers with
 487  * manageability enabled, allowing us room for 15 multicast addresses.
 488  */
 489 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
 490
 491 /* Error Codes */
 492 #define E1000_ERR_NVM      1
 493 #define E1000_ERR_PHY      2
 494 #define E1000_ERR_CONFIG   3
 495 #define E1000_ERR_PARAM    4
 496 #define E1000_ERR_MAC_INIT 5
 497 #define E1000_ERR_RESET   9
 498 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
 499 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
 500 #define E1000_BLK_PHY_RESET   12
 501 #define E1000_ERR_SWFW_SYNC 13
 502 #define E1000_NOT_IMPLEMENTED 14
 503
 504 /* Loop limit on how long we wait for auto-negotiation to complete */
 505 #define COPPER_LINK_UP_LIMIT              10
 506 #define PHY_AUTO_NEG_LIMIT                45
 507 #define PHY_FORCE_LIMIT                   20
 508 /* Number of 100 microseconds we wait for PCI Express master disable */
 509 #define MASTER_DISABLE_TIMEOUT      800
 510 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
 511 #define PHY_CFG_TIMEOUT             100
 512 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
 513 /* Number of milliseconds for NVM auto read done after MAC reset. */
 514 #define AUTO_READ_DONE_TIMEOUT      10
 515
 516 /* Flow Control */
 517 #define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
 518
 519 /* Transmit Configuration Word */
 520 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
 521
 522 /* Receive Configuration Word */
 523
 524 /* PCI Express Control */
 525 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
 526 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
 527 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
 528 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
 529 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
 530 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
 531
 532 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
 533                            E1000_GCR_RXDSCW_NO_SNOOP      | \
 534                            E1000_GCR_RXDSCR_NO_SNOOP      | \
 535                            E1000_GCR_TXD_NO_SNOOP         | \
 536                            E1000_GCR_TXDSCW_NO_SNOOP      | \
 537                            E1000_GCR_TXDSCR_NO_SNOOP)
 538
 539 /* PHY Control Register */
 540 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 541 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 542 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 543 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
 544 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
 545 #define MII_CR_SPEED_1000       0x0040
 546 #define MII_CR_SPEED_100        0x2000
 547 #define MII_CR_SPEED_10         0x0000
 548
 549 /* PHY Status Register */
 550 #define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
 551 #define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
 552
 553 /* Autoneg Advertisement Register */
 554 #define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
 555 #define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
 556 #define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
 557 #define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
 558 #define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
 559 #define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
 560
 561 /* Link Partner Ability Register (Base Page) */
 562 #define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
 563 #define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
 564
 565 /* Autoneg Expansion Register */
 566
 567 /* 1000BASE-T Control Register */
 568 #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
 569 #define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
 570                                         /* 0=DTE device */
 571 #define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
 572                                         /* 0=Configure PHY as Slave */
 573 #define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
 574                                         /* 0=Automatic Master/Slave config */
 575
 576 /* 1000BASE-T Status Register */
 577 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
 578 #define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
 579
 580
 581 /* PHY 1000 MII Register/Bit Definitions */
 582 /* PHY Registers defined by IEEE */
 583 #define PHY_CONTROL      0x00 /* Control Register */
 584 #define PHY_STATUS       0x01 /* Status Regiser */
 585 #define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
 586 #define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
 587 #define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
 588 #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
 589 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
 590 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
 591
 592 /* NVM Control */
 593 #define E1000_EECD_SK        0x00000001 /* NVM Clock */
 594 #define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
 595 #define E1000_EECD_DI        0x00000004 /* NVM Data In */
 596 #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
 597 #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
 598 #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
 599 #define E1000_EECD_PRES      0x00000100 /* NVM Present */
 600 /* NVM Addressing bits based on type 0=small, 1=large */
 601 #define E1000_EECD_ADDR_BITS 0x00000400
 602 #define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
 603 #define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
 604 #define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
 605 #define E1000_EECD_SIZE_EX_SHIFT     11
 606
 607 /* Offset to data in NVM read/write registers */
 608 #define E1000_NVM_RW_REG_DATA   16
 609 #define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
 610 #define E1000_NVM_RW_REG_START  1    /* Start operation */
 611 #define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
 612 #define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
 613
 614 /* NVM Word Offsets */
 615 #define NVM_ID_LED_SETTINGS        0x0004
 616 /* For SERDES output amplitude adjustment. */
 617 #define NVM_INIT_CONTROL2_REG      0x000F
 618 #define NVM_INIT_CONTROL3_PORT_A   0x0024
 619 #define NVM_ALT_MAC_ADDR_PTR       0x0037
 620 #define NVM_CHECKSUM_REG           0x003F
 621
 622 #define E1000_NVM_CFG_DONE_PORT_0  0x40000 /* MNG config cycle done */
 623 #define E1000_NVM_CFG_DONE_PORT_1  0x80000 /* ...for second port */
 624
 625 /* Mask bits for fields in Word 0x0f of the NVM */
 626 #define NVM_WORD0F_PAUSE_MASK       0x3000
 627 #define NVM_WORD0F_ASM_DIR          0x2000
 628
 629 /* Mask bits for fields in Word 0x1a of the NVM */
 630
 631 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 632 #define NVM_SUM                    0xBABA
 633
 634 #define NVM_PBA_OFFSET_0           8
 635 #define NVM_PBA_OFFSET_1           9
 636 #define NVM_WORD_SIZE_BASE_SHIFT   6
 637
 638 /* NVM Commands - Microwire */
 639
 640 /* NVM Commands - SPI */
 641 #define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
 642 #define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
 643 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
 644 #define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
 645 #define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
 646
 647 /* SPI NVM Status Register */
 648 #define NVM_STATUS_RDY_SPI         0x01
 649
 650 /* Word definitions for ID LED Settings */
 651 #define ID_LED_RESERVED_0000 0x0000
 652 #define ID_LED_RESERVED_FFFF 0xFFFF
 653 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
 654                               (ID_LED_OFF1_OFF2 <<  8) | \
 655                               (ID_LED_DEF1_DEF2 <<  4) | \
 656                               (ID_LED_DEF1_DEF2))
 657 #define ID_LED_DEF1_DEF2     0x1
 658 #define ID_LED_DEF1_ON2      0x2
 659 #define ID_LED_DEF1_OFF2     0x3
 660 #define ID_LED_ON1_DEF2      0x4
 661 #define ID_LED_ON1_ON2       0x5
 662 #define ID_LED_ON1_OFF2      0x6
 663 #define ID_LED_OFF1_DEF2     0x7
 664 #define ID_LED_OFF1_ON2      0x8
 665 #define ID_LED_OFF1_OFF2     0x9
 666
 667 #define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
 668 #define IGP_ACTIVITY_LED_ENABLE 0x0300
 669 #define IGP_LED3_MODE           0x07000000
 670
 671 /* PCI/PCI-X/PCI-EX Config space */
 672 #define PCI_HEADER_TYPE_REGISTER     0x0E
 673 #define PCIE_LINK_STATUS             0x12
 674
 675 #define PCI_HEADER_TYPE_MULTIFUNC    0x80
 676 #define PCIE_LINK_WIDTH_MASK         0x3F0
 677 #define PCIE_LINK_WIDTH_SHIFT        4
 678
 679 #define PHY_REVISION_MASK      0xFFFFFFF0
 680 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
 681 #define MAX_PHY_MULTI_PAGE_REG 0xF
 682
 683 /* Bit definitions for valid PHY IDs. */
 684 /*
 685  * I = Integrated
 686  * E = External
 687  */
 688 #define M88E1111_I_PHY_ID    0x01410CC0
 689 #define IGP03E1000_E_PHY_ID  0x02A80390
 690 #define M88_VENDOR           0x0141
 691
 692 /* M88E1000 Specific Registers */
 693 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
 694 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
 695 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
 696
 697 #define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
 698 #define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
 699
 700 /* M88E1000 PHY Specific Control Register */
 701 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
 702 /* 1=CLK125 low, 0=CLK125 toggling */
 703 #define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
 704                                                /* Manual MDI configuration */
 705 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
 706 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
 707 #define M88E1000_PSCR_AUTO_X_1000T     0x0040
 708 /* Auto crossover enabled all speeds */
 709 #define M88E1000_PSCR_AUTO_X_MODE      0x0060
 710 /*
 711  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold
 712  * 0=Normal 10BASE-T RX Threshold
 713  */
 714 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
 715 #define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
 716
 717 /* M88E1000 PHY Specific Status Register */
 718 #define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
 719 #define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
 720 #define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
 721 /*
 722  * 0 = <50M
 723  * 1 = 50-80M
 724  * 2 = 80-110M
 725  * 3 = 110-140M
 726  * 4 = >140M
 727  */
 728 #define M88E1000_PSSR_CABLE_LENGTH       0x0380
 729 #define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
 730 #define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
 731
 732 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 733
 734 /* M88E1000 Extended PHY Specific Control Register */
 735 /*
 736  * 1 = Lost lock detect enabled.
 737  * Will assert lost lock and bring
 738  * link down if idle not seen
 739  * within 1ms in 1000BASE-T
 740  */
 741 /*
 742  * Number of times we will attempt to autonegotiate before downshifting if we
 743  * are the master
 744  */
 745 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
 746 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
 747 /*
 748  * Number of times we will attempt to autonegotiate before downshifting if we
 749  * are the slave
 750  */
 751 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
 752 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 753 #define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
 754
 755 /* M88EC018 Rev 2 specific DownShift settings */
 756 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
 757 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
 758
 759 /* MDI Control */
 760 #define E1000_MDIC_REG_SHIFT 16
 761 #define E1000_MDIC_PHY_SHIFT 21
 762 #define E1000_MDIC_OP_WRITE  0x04000000
 763 #define E1000_MDIC_OP_READ   0x08000000
 764 #define E1000_MDIC_READY     0x10000000
 765 #define E1000_MDIC_ERROR     0x40000000
 766
 767 /* SerDes Control */
 768 #define E1000_GEN_CTL_READY             0x80000000
 769 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
 770 #define E1000_GEN_POLL_TIMEOUT          640
 771
 772 #endif