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[ARM] Add fallocate syscall entry
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / scsi / gdth.c
blob55e4d2dc2bbe227ea62dcb730d7a50516e27f3c1
1 /************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
30 * Linux kernel 2.4.x, 2.6.x supported *
31 * *
32 * $Log: gdth.c,v $
33 * Revision 1.74 2006/04/10 13:44:47 achim
34 * Community changes for 2.6.x
35 * Kernel 2.2.x no longer supported
36 * scsi_request interface removed, thanks to Christoph Hellwig
37 *
38 * Revision 1.73 2004/03/31 13:33:03 achim
39 * Special command 0xfd implemented to detect 64-bit DMA support
40 *
41 * Revision 1.72 2004/03/17 08:56:04 achim
42 * 64-bit DMA only enabled if FW >= x.43
43 *
44 * Revision 1.71 2004/03/05 15:51:29 achim
45 * Screen service: separate message buffer, bugfixes
46 *
47 * Revision 1.70 2004/02/27 12:19:07 achim
48 * Bugfix: Reset bit in config (0xfe) call removed
49 *
50 * Revision 1.69 2004/02/20 09:50:24 achim
51 * Compatibility changes for kernels < 2.4.20
52 * Bugfix screen service command size
53 * pci_set_dma_mask() error handling added
54 *
55 * Revision 1.68 2004/02/19 15:46:54 achim
56 * 64-bit DMA bugfixes
57 * Drive size bugfix for drives > 1TB
58 *
59 * Revision 1.67 2004/01/14 13:11:57 achim
60 * Tool access over /proc no longer supported
61 * Bugfixes IOCTLs
62 *
63 * Revision 1.66 2003/12/19 15:04:06 achim
64 * Bugfixes support for drives > 2TB
65 *
66 * Revision 1.65 2003/12/15 11:21:56 achim
67 * 64-bit DMA support added
68 * Support for drives > 2 TB implemented
69 * Kernels 2.2.x, 2.4.x, 2.6.x supported
70 *
71 * Revision 1.64 2003/09/17 08:30:26 achim
72 * EISA/ISA controller scan disabled
73 * Command line switch probe_eisa_isa added
74 *
75 * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
76 * Minor cleanups in gdth_ioctl.
77 *
78 * Revision 1.62 2003/02/27 15:01:59 achim
79 * Dynamic DMA mapping implemented
80 * New (character device) IOCTL interface added
81 * Other controller related changes made
82 *
83 * Revision 1.61 2002/11/08 13:09:52 boji
84 * Added support for XSCALE based RAID Controllers
85 * Fixed SCREENSERVICE initialization in SMP cases
86 * Added checks for gdth_polling before GDTH_HA_LOCK
87 *
88 * Revision 1.60 2002/02/05 09:35:22 achim
89 * MODULE_LICENSE only if kernel >= 2.4.11
90 *
91 * Revision 1.59 2002/01/30 09:46:33 achim
92 * Small changes
93 *
94 * Revision 1.58 2002/01/29 15:30:02 achim
95 * Set default value of shared_access to Y
96 * New status S_CACHE_RESERV for clustering added
97 *
98 * Revision 1.57 2001/08/21 11:16:35 achim
99 * Bugfix free_irq()
100 *
101 * Revision 1.56 2001/08/09 11:19:39 achim
102 * Scsi_Host_Template changes
103 *
104 * Revision 1.55 2001/08/09 10:11:28 achim
105 * Command HOST_UNFREEZE_IO before cache service init.
106 *
107 * Revision 1.54 2001/07/20 13:48:12 achim
108 * Expand: gdth_analyse_hdrive() removed
109 *
110 * Revision 1.53 2001/07/17 09:52:49 achim
111 * Small OEM related change
112 *
113 * Revision 1.52 2001/06/19 15:06:20 achim
114 * New host command GDT_UNFREEZE_IO added
115 *
116 * Revision 1.51 2001/05/22 06:42:37 achim
117 * PCI: Subdevice ID added
118 *
119 * Revision 1.50 2001/05/17 13:42:16 achim
120 * Support for Intel Storage RAID Controllers added
121 *
122 * Revision 1.50 2001/05/17 12:12:34 achim
123 * Support for Intel Storage RAID Controllers added
124 *
125 * Revision 1.49 2001/03/15 15:07:17 achim
126 * New __setup interface for boot command line options added
127 *
128 * Revision 1.48 2001/02/06 12:36:28 achim
129 * Bugfix Cluster protocol
130 *
131 * Revision 1.47 2001/01/10 14:42:06 achim
132 * New switch shared_access added
133 *
134 * Revision 1.46 2001/01/09 08:11:35 achim
135 * gdth_command() removed
136 * meaning of Scsi_Pointer members changed
137 *
138 * Revision 1.45 2000/11/16 12:02:24 achim
139 * Changes for kernel 2.4
140 *
141 * Revision 1.44 2000/10/11 08:44:10 achim
142 * Clustering changes: New flag media_changed added
143 *
144 * Revision 1.43 2000/09/20 12:59:01 achim
145 * DPMEM remap functions for all PCI controller types implemented
146 * Small changes for ia64 platform
147 *
148 * Revision 1.42 2000/07/20 09:04:50 achim
149 * Small changes for kernel 2.4
150 *
151 * Revision 1.41 2000/07/04 14:11:11 achim
152 * gdth_analyse_hdrive() added to rescan drives after online expansion
153 *
154 * Revision 1.40 2000/06/27 11:24:16 achim
155 * Changes Clustering, Screenservice
156 *
157 * Revision 1.39 2000/06/15 13:09:04 achim
158 * Changes for gdth_do_cmd()
159 *
160 * Revision 1.38 2000/06/15 12:08:43 achim
161 * Bugfix gdth_sync_event(), service SCREENSERVICE
162 * Data direction for command 0xc2 changed to DOU
163 *
164 * Revision 1.37 2000/05/25 13:50:10 achim
165 * New driver parameter virt_ctr added
166 *
167 * Revision 1.36 2000/05/04 08:50:46 achim
168 * Event buffer now in gdth_ha_str
169 *
170 * Revision 1.35 2000/03/03 10:44:08 achim
171 * New event_string only valid for the RP controller family
172 *
173 * Revision 1.34 2000/03/02 14:55:29 achim
174 * New mechanism for async. event handling implemented
175 *
176 * Revision 1.33 2000/02/21 15:37:37 achim
177 * Bugfix Alpha platform + DPMEM above 4GB
178 *
179 * Revision 1.32 2000/02/14 16:17:37 achim
180 * Bugfix sense_buffer[] + raw devices
181 *
182 * Revision 1.31 2000/02/10 10:29:00 achim
183 * Delete sense_buffer[0], if command OK
184 *
185 * Revision 1.30 1999/11/02 13:42:39 achim
186 * ARRAY_DRV_LIST2 implemented
187 * Now 255 log. and 100 host drives supported
188 *
189 * Revision 1.29 1999/10/05 13:28:47 achim
190 * GDT_CLUST_RESET added
191 *
192 * Revision 1.28 1999/08/12 13:44:54 achim
193 * MOUNTALL removed
194 * Cluster drives -> removeable drives
195 *
196 * Revision 1.27 1999/06/22 07:22:38 achim
197 * Small changes
198 *
199 * Revision 1.26 1999/06/10 16:09:12 achim
200 * Cluster Host Drive support: Bugfixes
201 *
202 * Revision 1.25 1999/06/01 16:03:56 achim
203 * gdth_init_pci(): Manipulate config. space to start RP controller
204 *
205 * Revision 1.24 1999/05/26 11:53:06 achim
206 * Cluster Host Drive support added
207 *
208 * Revision 1.23 1999/03/26 09:12:31 achim
209 * Default value for hdr_channel set to 0
210 *
211 * Revision 1.22 1999/03/22 16:27:16 achim
212 * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
213 *
214 * Revision 1.21 1999/03/16 13:40:34 achim
215 * Problems with reserved drives solved
216 * gdth_eh_bus_reset() implemented
217 *
218 * Revision 1.20 1999/03/10 09:08:13 achim
219 * Bugfix: Corrections in gdth_direction_tab[] made
220 * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
221 *
222 * Revision 1.19 1999/03/05 14:38:16 achim
223 * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
224 * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
225 * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
226 * with BIOS disabled and memory test set to Intensive
227 * Enhanced /proc support
228 *
229 * Revision 1.18 1999/02/24 09:54:33 achim
230 * Command line parameter hdr_channel implemented
231 * Bugfix for EISA controllers + Linux 2.2.x
232 *
233 * Revision 1.17 1998/12/17 15:58:11 achim
234 * Command line parameters implemented
235 * Changes for Alpha platforms
236 * PCI controller scan changed
237 * SMP support improved (spin_lock_irqsave(),...)
238 * New async. events, new scan/reserve commands included
239 *
240 * Revision 1.16 1998/09/28 16:08:46 achim
241 * GDT_PCIMPR: DPMEM remapping, if required
242 * mdelay() added
243 *
244 * Revision 1.15 1998/06/03 14:54:06 achim
245 * gdth_delay(), gdth_flush() implemented
246 * Bugfix: gdth_release() changed
247 *
248 * Revision 1.14 1998/05/22 10:01:17 achim
249 * mj: pcibios_strerror() removed
250 * Improved SMP support (if version >= 2.1.95)
251 * gdth_halt(): halt_called flag added (if version < 2.1)
252 *
253 * Revision 1.13 1998/04/16 09:14:57 achim
254 * Reserve drives (for raw service) implemented
255 * New error handling code enabled
256 * Get controller name from board_info() IOCTL
257 * Final round of PCI device driver patches by Martin Mares
258 *
259 * Revision 1.12 1998/03/03 09:32:37 achim
260 * Fibre channel controller support added
261 *
262 * Revision 1.11 1998/01/27 16:19:14 achim
263 * SA_SHIRQ added
264 * add_timer()/del_timer() instead of GDTH_TIMER
265 * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
266 * New error handling included
267 *
268 * Revision 1.10 1997/10/31 12:29:57 achim
269 * Read heads/sectors from host drive
270 *
271 * Revision 1.9 1997/09/04 10:07:25 achim
272 * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
273 * register_reboot_notifier() to get a notify on shutown used
274 *
275 * Revision 1.8 1997/04/02 12:14:30 achim
276 * Version 1.00 (see gdth.h), tested with kernel 2.0.29
277 *
278 * Revision 1.7 1997/03/12 13:33:37 achim
279 * gdth_reset() changed, new async. events
280 *
281 * Revision 1.6 1997/03/04 14:01:11 achim
282 * Shutdown routine gdth_halt() implemented
283 *
284 * Revision 1.5 1997/02/21 09:08:36 achim
285 * New controller included (RP, RP1, RP2 series)
286 * IOCTL interface implemented
287 *
288 * Revision 1.4 1996/07/05 12:48:55 achim
289 * Function gdth_bios_param() implemented
290 * New constant GDTH_MAXC_P_L inserted
291 * GDT_WRITE_THR, GDT_EXT_INFO implemented
292 * Function gdth_reset() changed
293 *
294 * Revision 1.3 1996/05/10 09:04:41 achim
295 * Small changes for Linux 1.2.13
296 *
297 * Revision 1.2 1996/05/09 12:45:27 achim
298 * Loadable module support implemented
299 * /proc support corrections made
300 *
301 * Revision 1.1 1996/04/11 07:35:57 achim
302 * Initial revision
303 *
304 ************************************************************************/
305
306 /* All GDT Disk Array Controllers are fully supported by this driver.
307 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
308 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
309 * list of all controller types.
310 *
311 * If you have one or more GDT3000/3020 EISA controllers with
312 * controller BIOS disabled, you have to set the IRQ values with the
313 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
314 * the IRQ values for the EISA controllers.
315 *
316 * After the optional list of IRQ values, other possible
317 * command line options are:
318 * disable:Y disable driver
319 * disable:N enable driver
320 * reserve_mode:0 reserve no drives for the raw service
321 * reserve_mode:1 reserve all not init., removable drives
322 * reserve_mode:2 reserve all not init. drives
323 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
324 * h- controller no., b- channel no.,
325 * t- target ID, l- LUN
326 * reverse_scan:Y reverse scan order for PCI controllers
327 * reverse_scan:N scan PCI controllers like BIOS
328 * max_ids:x x - target ID count per channel (1..MAXID)
329 * rescan:Y rescan all channels/IDs
330 * rescan:N use all devices found until now
331 * virt_ctr:Y map every channel to a virtual controller
332 * virt_ctr:N use multi channel support
333 * hdr_channel:x x - number of virtual bus for host drives
334 * shared_access:Y disable driver reserve/release protocol to
335 * access a shared resource from several nodes,
336 * appropriate controller firmware required
337 * shared_access:N enable driver reserve/release protocol
338 * probe_eisa_isa:Y scan for EISA/ISA controllers
339 * probe_eisa_isa:N do not scan for EISA/ISA controllers
340 * force_dma32:Y use only 32 bit DMA mode
341 * force_dma32:N use 64 bit DMA mode, if supported
342 *
343 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
344 * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
345 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
346 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
347 *
348 * When loading the gdth driver as a module, the same options are available.
349 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
350 * options changes slightly. You must replace all ',' between options
351 * with ' ' and all ':' with '=' and you must use
352 * '1' in place of 'Y' and '0' in place of 'N'.
353 *
354 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
355 * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
356 * probe_eisa_isa=0 force_dma32=0"
357 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
358 */
359
360 /* The meaning of the Scsi_Pointer members in this driver is as follows:
361 * ptr: Chaining
362 * this_residual: Command priority
363 * buffer: phys. DMA sense buffer
364 * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
365 * buffers_residual: Timeout value
366 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
367 * Message: Additional info (gdth_do_cmd()), DMA direction
368 * have_data_in: Flag for gdth_wait_completion()
369 * sent_command: Opcode special command
370 * phase: Service/parameter/return code special command
371 */
372
373
374 /* interrupt coalescing */
375 /* #define INT_COAL */
376
377 /* statistics */
378 #define GDTH_STATISTICS
379
380 #include <linux/module.h>
381
382 #include <linux/version.h>
383 #include <linux/kernel.h>
384 #include <linux/types.h>
385 #include <linux/pci.h>
386 #include <linux/string.h>
387 #include <linux/ctype.h>
388 #include <linux/ioport.h>
389 #include <linux/delay.h>
390 #include <linux/interrupt.h>
391 #include <linux/in.h>
392 #include <linux/proc_fs.h>
393 #include <linux/time.h>
394 #include <linux/timer.h>
395 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
396 #include <linux/dma-mapping.h>
397 #else
398 #define DMA_32BIT_MASK 0x00000000ffffffffULL
399 #define DMA_64BIT_MASK 0xffffffffffffffffULL
400 #endif
401
402 #ifdef GDTH_RTC
403 #include <linux/mc146818rtc.h>
404 #endif
405 #include <linux/reboot.h>
406
407 #include <asm/dma.h>
408 #include <asm/system.h>
409 #include <asm/io.h>
410 #include <asm/uaccess.h>
411 #include <linux/spinlock.h>
412 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
413 #include <linux/blkdev.h>
414 #else
415 #include <linux/blk.h>
416 #include "sd.h"
417 #endif
418
419 #include "scsi.h"
420 #include <scsi/scsi_host.h>
421 #include "gdth_kcompat.h"
422 #include "gdth.h"
423
424 static void gdth_delay(int milliseconds);
425 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
426 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
427 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
428 static int gdth_async_event(int hanum);
429 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
430
431 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
432 static void gdth_next(int hanum);
433 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
434 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
435 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
436 ushort idx, gdth_evt_data *evt);
437 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
438 static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
439 gdth_evt_str *estr);
440 static void gdth_clear_events(void);
441
442 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
443 char *buffer,ushort count);
444 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
445 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
446
447 static int gdth_search_eisa(ushort eisa_adr);
448 static int gdth_search_isa(ulong32 bios_adr);
449 static int gdth_search_pci(gdth_pci_str *pcistr);
450 static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
451 ushort vendor, ushort dev);
452 static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
453 static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
454 static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
455 static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
456
457 static void gdth_enable_int(int hanum);
458 static int gdth_get_status(unchar *pIStatus,int irq);
459 static int gdth_test_busy(int hanum);
460 static int gdth_get_cmd_index(int hanum);
461 static void gdth_release_event(int hanum);
462 static int gdth_wait(int hanum,int index,ulong32 time);
463 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
464 ulong64 p2,ulong64 p3);
465 static int gdth_search_drives(int hanum);
466 static int gdth_analyse_hdrive(int hanum, ushort hdrive);
467
468 static const char *gdth_ctr_name(int hanum);
469
470 static int gdth_open(struct inode *inode, struct file *filep);
471 static int gdth_close(struct inode *inode, struct file *filep);
472 static int gdth_ioctl(struct inode *inode, struct file *filep,
473 unsigned int cmd, unsigned long arg);
474
475 static void gdth_flush(int hanum);
476 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
477 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
478 static void gdth_scsi_done(struct scsi_cmnd *scp);
479
480 #ifdef DEBUG_GDTH
481 static unchar DebugState = DEBUG_GDTH;
482
483 #ifdef __SERIAL__
484 #define MAX_SERBUF 160
485 static void ser_init(void);
486 static void ser_puts(char *str);
487 static void ser_putc(char c);
488 static int ser_printk(const char *fmt, ...);
489 static char strbuf[MAX_SERBUF+1];
490 #ifdef __COM2__
491 #define COM_BASE 0x2f8
492 #else
493 #define COM_BASE 0x3f8
494 #endif
495 static void ser_init()
496 {
497 unsigned port=COM_BASE;
498
499 outb(0x80,port+3);
500 outb(0,port+1);
501 /* 19200 Baud, if 9600: outb(12,port) */
502 outb(6, port);
503 outb(3,port+3);
504 outb(0,port+1);
505 /*
506 ser_putc('I');
507 ser_putc(' ');
508 */
509 }
510
511 static void ser_puts(char *str)
512 {
513 char *ptr;
514
515 ser_init();
516 for (ptr=str;*ptr;++ptr)
517 ser_putc(*ptr);
518 }
519
520 static void ser_putc(char c)
521 {
522 unsigned port=COM_BASE;
523
524 while ((inb(port+5) & 0x20)==0);
525 outb(c,port);
526 if (c==0x0a)
527 {
528 while ((inb(port+5) & 0x20)==0);
529 outb(0x0d,port);
530 }
531 }
532
533 static int ser_printk(const char *fmt, ...)
534 {
535 va_list args;
536 int i;
537
538 va_start(args,fmt);
539 i = vsprintf(strbuf,fmt,args);
540 ser_puts(strbuf);
541 va_end(args);
542 return i;
543 }
544
545 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
546 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
547 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
548
549 #else /* !__SERIAL__ */
550 #define TRACE(a) {if (DebugState==1) {printk a;}}
551 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
552 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
553 #endif
554
555 #else /* !DEBUG */
556 #define TRACE(a)
557 #define TRACE2(a)
558 #define TRACE3(a)
559 #endif
560
561 #ifdef GDTH_STATISTICS
562 static ulong32 max_rq=0, max_index=0, max_sg=0;
563 #ifdef INT_COAL
564 static ulong32 max_int_coal=0;
565 #endif
566 static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
567 static struct timer_list gdth_timer;
568 #endif
569
570 #define PTR2USHORT(a) (ushort)(ulong)(a)
571 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
572 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
573
574 #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
575 #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
576 #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
577
578 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
579
580 #define gdth_readb(addr) readb(addr)
581 #define gdth_readw(addr) readw(addr)
582 #define gdth_readl(addr) readl(addr)
583 #define gdth_writeb(b,addr) writeb((b),(addr))
584 #define gdth_writew(b,addr) writew((b),(addr))
585 #define gdth_writel(b,addr) writel((b),(addr))
586
587 static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
588 static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
589 static unchar gdth_polling; /* polling if TRUE */
590 static unchar gdth_from_wait = FALSE; /* gdth_wait() */
591 static int wait_index,wait_hanum; /* gdth_wait() */
592 static int gdth_ctr_count = 0; /* controller count */
593 static int gdth_ctr_vcount = 0; /* virt. ctr. count */
594 static int gdth_ctr_released = 0; /* gdth_release() */
595 static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
596 static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
597 static unchar gdth_write_through = FALSE; /* write through */
598 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
599 static int elastidx;
600 static int eoldidx;
601 static int major;
602
603 #define DIN 1 /* IN data direction */
604 #define DOU 2 /* OUT data direction */
605 #define DNO DIN /* no data transfer */
606 #define DUN DIN /* unknown data direction */
607 static unchar gdth_direction_tab[0x100] = {
608 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
609 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
610 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
611 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
612 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
613 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
614 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
615 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
616 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
617 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
618 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
619 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
620 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
621 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
622 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
623 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
624 };
625
626 /* LILO and modprobe/insmod parameters */
627 /* IRQ list for GDT3000/3020 EISA controllers */
628 static int irq[MAXHA] __initdata =
629 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
630 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
631 /* disable driver flag */
632 static int disable __initdata = 0;
633 /* reserve flag */
634 static int reserve_mode = 1;
635 /* reserve list */
636 static int reserve_list[MAX_RES_ARGS] =
637 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
638 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
639 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
640 /* scan order for PCI controllers */
641 static int reverse_scan = 0;
642 /* virtual channel for the host drives */
643 static int hdr_channel = 0;
644 /* max. IDs per channel */
645 static int max_ids = MAXID;
646 /* rescan all IDs */
647 static int rescan = 0;
648 /* map channels to virtual controllers */
649 static int virt_ctr = 0;
650 /* shared access */
651 static int shared_access = 1;
652 /* enable support for EISA and ISA controllers */
653 static int probe_eisa_isa = 0;
654 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
655 static int force_dma32 = 0;
656
657 /* parameters for modprobe/insmod */
658 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
659 module_param_array(irq, int, NULL, 0);
660 module_param(disable, int, 0);
661 module_param(reserve_mode, int, 0);
662 module_param_array(reserve_list, int, NULL, 0);
663 module_param(reverse_scan, int, 0);
664 module_param(hdr_channel, int, 0);
665 module_param(max_ids, int, 0);
666 module_param(rescan, int, 0);
667 module_param(virt_ctr, int, 0);
668 module_param(shared_access, int, 0);
669 module_param(probe_eisa_isa, int, 0);
670 module_param(force_dma32, int, 0);
671 #else
672 MODULE_PARM(irq, "i");
673 MODULE_PARM(disable, "i");
674 MODULE_PARM(reserve_mode, "i");
675 MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
676 MODULE_PARM(reverse_scan, "i");
677 MODULE_PARM(hdr_channel, "i");
678 MODULE_PARM(max_ids, "i");
679 MODULE_PARM(rescan, "i");
680 MODULE_PARM(virt_ctr, "i");
681 MODULE_PARM(shared_access, "i");
682 MODULE_PARM(probe_eisa_isa, "i");
683 MODULE_PARM(force_dma32, "i");
684 #endif
685 MODULE_AUTHOR("Achim Leubner");
686 MODULE_LICENSE("GPL");
687
688 /* ioctl interface */
689 static const struct file_operations gdth_fops = {
690 .ioctl = gdth_ioctl,
691 .open = gdth_open,
692 .release = gdth_close,
693 };
694
695 #include "gdth_proc.h"
696 #include "gdth_proc.c"
697
698 /* notifier block to get a notify on system shutdown/halt/reboot */
699 static struct notifier_block gdth_notifier = {
700 gdth_halt, NULL, 0
701 };
702 static int notifier_disabled = 0;
703
704 static void gdth_delay(int milliseconds)
705 {
706 if (milliseconds == 0) {
707 udelay(1);
708 } else {
709 mdelay(milliseconds);
710 }
711 }
712
713 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
714 static void gdth_scsi_done(struct scsi_cmnd *scp)
715 {
716 TRACE2(("gdth_scsi_done()\n"));
717
718 if (scp->request)
719 complete((struct completion *)scp->request);
720 }
721
722 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
723 int timeout, u32 *info)
724 {
725 Scsi_Cmnd *scp;
726 DECLARE_COMPLETION_ONSTACK(wait);
727 int rval;
728
729 scp = kmalloc(sizeof(*scp), GFP_KERNEL);
730 if (!scp)
731 return -ENOMEM;
732 memset(scp, 0, sizeof(*scp));
733 scp->device = sdev;
734 /* use request field to save the ptr. to completion struct. */
735 scp->request = (struct request *)&wait;
736 scp->timeout_per_command = timeout*HZ;
737 scp->request_buffer = gdtcmd;
738 scp->cmd_len = 12;
739 memcpy(scp->cmnd, cmnd, 12);
740 scp->SCp.this_residual = IOCTL_PRI; /* priority */
741 scp->done = gdth_scsi_done; /* some fn. test this */
742 gdth_queuecommand(scp, gdth_scsi_done);
743 wait_for_completion(&wait);
744
745 rval = scp->SCp.Status;
746 if (info)
747 *info = scp->SCp.Message;
748 kfree(scp);
749 return rval;
750 }
751 #else
752 static void gdth_scsi_done(Scsi_Cmnd *scp)
753 {
754 TRACE2(("gdth_scsi_done()\n"));
755
756 scp->request.rq_status = RQ_SCSI_DONE;
757 if (scp->request.waiting)
758 complete(scp->request.waiting);
759 }
760
761 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
762 int timeout, u32 *info)
763 {
764 Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
765 unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
766 DECLARE_COMPLETION_ONSTACK(wait);
767 int rval;
768
769 if (!scp)
770 return -ENOMEM;
771 scp->cmd_len = 12;
772 scp->use_sg = 0;
773 scp->SCp.this_residual = IOCTL_PRI; /* priority */
774 scp->request.rq_status = RQ_SCSI_BUSY;
775 scp->request.waiting = &wait;
776 scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
777 wait_for_completion(&wait);
778
779 rval = scp->SCp.Status;
780 if (info)
781 *info = scp->SCp.Message;
782
783 scsi_release_command(scp);
784 return rval;
785 }
786 #endif
787
788 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
789 int timeout, u32 *info)
790 {
791 struct scsi_device *sdev = scsi_get_host_dev(shost);
792 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
793
794 scsi_free_host_dev(sdev);
795 return rval;
796 }
797
798 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
799 {
800 *cyls = size /HEADS/SECS;
801 if (*cyls <= MAXCYLS) {
802 *heads = HEADS;
803 *secs = SECS;
804 } else { /* too high for 64*32 */
805 *cyls = size /MEDHEADS/MEDSECS;
806 if (*cyls <= MAXCYLS) {
807 *heads = MEDHEADS;
808 *secs = MEDSECS;
809 } else { /* too high for 127*63 */
810 *cyls = size /BIGHEADS/BIGSECS;
811 *heads = BIGHEADS;
812 *secs = BIGSECS;
813 }
814 }
815 }
816
817 /* controller search and initialization functions */
818
819 static int __init gdth_search_eisa(ushort eisa_adr)
820 {
821 ulong32 id;
822
823 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
824 id = inl(eisa_adr+ID0REG);
825 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
826 if ((inb(eisa_adr+EISAREG) & 8) == 0)
827 return 0; /* not EISA configured */
828 return 1;
829 }
830 if (id == GDT3_ID) /* GDT3000 */
831 return 1;
832
833 return 0;
834 }
835
836
837 static int __init gdth_search_isa(ulong32 bios_adr)
838 {
839 void __iomem *addr;
840 ulong32 id;
841
842 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
843 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
844 id = gdth_readl(addr);
845 iounmap(addr);
846 if (id == GDT2_ID) /* GDT2000 */
847 return 1;
848 }
849 return 0;
850 }
851
852
853 static int __init gdth_search_pci(gdth_pci_str *pcistr)
854 {
855 ushort device, cnt;
856
857 TRACE(("gdth_search_pci()\n"));
858
859 cnt = 0;
860 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
861 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
862 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
863 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
864 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
865 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
866 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
867 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
868 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
869 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
870 PCI_DEVICE_ID_INTEL_SRC);
871 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
872 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
873 return cnt;
874 }
875
876 /* Vortex only makes RAID controllers.
877 * We do not really want to specify all 550 ids here, so wildcard match.
878 */
879 static struct pci_device_id gdthtable[] __maybe_unused = {
880 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
881 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
882 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
883 {0}
884 };
885 MODULE_DEVICE_TABLE(pci,gdthtable);
886
887 static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
888 ushort vendor, ushort device)
889 {
890 ulong base0, base1, base2;
891 struct pci_dev *pdev;
892
893 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
894 *cnt, vendor, device));
895
896 pdev = NULL;
897 while ((pdev = pci_find_device(vendor, device, pdev))
898 != NULL) {
899 if (pci_enable_device(pdev))
900 continue;
901 if (*cnt >= MAXHA)
902 return;
903 /* GDT PCI controller found, resources are already in pdev */
904 pcistr[*cnt].pdev = pdev;
905 pcistr[*cnt].irq = pdev->irq;
906 base0 = pci_resource_flags(pdev, 0);
907 base1 = pci_resource_flags(pdev, 1);
908 base2 = pci_resource_flags(pdev, 2);
909 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
910 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
911 if (!(base0 & IORESOURCE_MEM))
912 continue;
913 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
914 } else { /* GDT6110, GDT6120, .. */
915 if (!(base0 & IORESOURCE_MEM) ||
916 !(base2 & IORESOURCE_MEM) ||
917 !(base1 & IORESOURCE_IO))
918 continue;
919 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
920 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
921 pcistr[*cnt].io = pci_resource_start(pdev, 1);
922 }
923 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
924 pcistr[*cnt].pdev->bus->number,
925 PCI_SLOT(pcistr[*cnt].pdev->devfn),
926 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
927 (*cnt)++;
928 }
929 }
930
931
932 static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
933 {
934 gdth_pci_str temp;
935 int i, changed;
936
937 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
938 if (cnt == 0)
939 return;
940
941 do {
942 changed = FALSE;
943 for (i = 0; i < cnt-1; ++i) {
944 if (!reverse_scan) {
945 if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
946 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
947 PCI_SLOT(pcistr[i].pdev->devfn) >
948 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
949 temp = pcistr[i];
950 pcistr[i] = pcistr[i+1];
951 pcistr[i+1] = temp;
952 changed = TRUE;
953 }
954 } else {
955 if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
956 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
957 PCI_SLOT(pcistr[i].pdev->devfn) <
958 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
959 temp = pcistr[i];
960 pcistr[i] = pcistr[i+1];
961 pcistr[i+1] = temp;
962 changed = TRUE;
963 }
964 }
965 }
966 } while (changed);
967 }
968
969
970 static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
971 {
972 ulong32 retries,id;
973 unchar prot_ver,eisacf,i,irq_found;
974
975 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
976
977 /* disable board interrupts, deinitialize services */
978 outb(0xff,eisa_adr+EDOORREG);
979 outb(0x00,eisa_adr+EDENABREG);
980 outb(0x00,eisa_adr+EINTENABREG);
981
982 outb(0xff,eisa_adr+LDOORREG);
983 retries = INIT_RETRIES;
984 gdth_delay(20);
985 while (inb(eisa_adr+EDOORREG) != 0xff) {
986 if (--retries == 0) {
987 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
988 return 0;
989 }
990 gdth_delay(1);
991 TRACE2(("wait for DEINIT: retries=%d\n",retries));
992 }
993 prot_ver = inb(eisa_adr+MAILBOXREG);
994 outb(0xff,eisa_adr+EDOORREG);
995 if (prot_ver != PROTOCOL_VERSION) {
996 printk("GDT-EISA: Illegal protocol version\n");
997 return 0;
998 }
999 ha->bmic = eisa_adr;
1000 ha->brd_phys = (ulong32)eisa_adr >> 12;
1001
1002 outl(0,eisa_adr+MAILBOXREG);
1003 outl(0,eisa_adr+MAILBOXREG+4);
1004 outl(0,eisa_adr+MAILBOXREG+8);
1005 outl(0,eisa_adr+MAILBOXREG+12);
1006
1007 /* detect IRQ */
1008 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
1009 ha->oem_id = OEM_ID_ICP;
1010 ha->type = GDT_EISA;
1011 ha->stype = id;
1012 outl(1,eisa_adr+MAILBOXREG+8);
1013 outb(0xfe,eisa_adr+LDOORREG);
1014 retries = INIT_RETRIES;
1015 gdth_delay(20);
1016 while (inb(eisa_adr+EDOORREG) != 0xfe) {
1017 if (--retries == 0) {
1018 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
1019 return 0;
1020 }
1021 gdth_delay(1);
1022 }
1023 ha->irq = inb(eisa_adr+MAILBOXREG);
1024 outb(0xff,eisa_adr+EDOORREG);
1025 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
1026 /* check the result */
1027 if (ha->irq == 0) {
1028 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
1029 for (i = 0, irq_found = FALSE;
1030 i < MAXHA && irq[i] != 0xff; ++i) {
1031 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
1032 irq_found = TRUE;
1033 break;
1034 }
1035 }
1036 if (irq_found) {
1037 ha->irq = irq[i];
1038 irq[i] = 0;
1039 printk("GDT-EISA: Can not detect controller IRQ,\n");
1040 printk("Use IRQ setting from command line (IRQ = %d)\n",
1041 ha->irq);
1042 } else {
1043 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
1044 printk("the controller BIOS or use command line parameters\n");
1045 return 0;
1046 }
1047 }
1048 } else {
1049 eisacf = inb(eisa_adr+EISAREG) & 7;
1050 if (eisacf > 4) /* level triggered */
1051 eisacf -= 4;
1052 ha->irq = gdth_irq_tab[eisacf];
1053 ha->oem_id = OEM_ID_ICP;
1054 ha->type = GDT_EISA;
1055 ha->stype = id;
1056 }
1057
1058 ha->dma64_support = 0;
1059 return 1;
1060 }
1061
1062
1063 static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
1064 {
1065 register gdt2_dpram_str __iomem *dp2_ptr;
1066 int i;
1067 unchar irq_drq,prot_ver;
1068 ulong32 retries;
1069
1070 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
1071
1072 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
1073 if (ha->brd == NULL) {
1074 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
1075 return 0;
1076 }
1077 dp2_ptr = ha->brd;
1078 gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
1079 /* reset interface area */
1080 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
1081 if (gdth_readl(&dp2_ptr->u) != 0) {
1082 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
1083 iounmap(ha->brd);
1084 return 0;
1085 }
1086
1087 /* disable board interrupts, read DRQ and IRQ */
1088 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1089 gdth_writeb(0x00, &dp2_ptr->io.irqen);
1090 gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
1091 gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
1092
1093 irq_drq = gdth_readb(&dp2_ptr->io.rq);
1094 for (i=0; i<3; ++i) {
1095 if ((irq_drq & 1)==0)
1096 break;
1097 irq_drq >>= 1;
1098 }
1099 ha->drq = gdth_drq_tab[i];
1100
1101 irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
1102 for (i=1; i<5; ++i) {
1103 if ((irq_drq & 1)==0)
1104 break;
1105 irq_drq >>= 1;
1106 }
1107 ha->irq = gdth_irq_tab[i];
1108
1109 /* deinitialize services */
1110 gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
1111 gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
1112 gdth_writeb(0, &dp2_ptr->io.event);
1113 retries = INIT_RETRIES;
1114 gdth_delay(20);
1115 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
1116 if (--retries == 0) {
1117 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
1118 iounmap(ha->brd);
1119 return 0;
1120 }
1121 gdth_delay(1);
1122 }
1123 prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
1124 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1125 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1126 if (prot_ver != PROTOCOL_VERSION) {
1127 printk("GDT-ISA: Illegal protocol version\n");
1128 iounmap(ha->brd);
1129 return 0;
1130 }
1131
1132 ha->oem_id = OEM_ID_ICP;
1133 ha->type = GDT_ISA;
1134 ha->ic_all_size = sizeof(dp2_ptr->u);
1135 ha->stype= GDT2_ID;
1136 ha->brd_phys = bios_adr >> 4;
1137
1138 /* special request to controller BIOS */
1139 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
1140 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
1141 gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
1142 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
1143 gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
1144 gdth_writeb(0, &dp2_ptr->io.event);
1145 retries = INIT_RETRIES;
1146 gdth_delay(20);
1147 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
1148 if (--retries == 0) {
1149 printk("GDT-ISA: Initialization error\n");
1150 iounmap(ha->brd);
1151 return 0;
1152 }
1153 gdth_delay(1);
1154 }
1155 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1156 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1157
1158 ha->dma64_support = 0;
1159 return 1;
1160 }
1161
1162
1163 static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
1164 {
1165 register gdt6_dpram_str __iomem *dp6_ptr;
1166 register gdt6c_dpram_str __iomem *dp6c_ptr;
1167 register gdt6m_dpram_str __iomem *dp6m_ptr;
1168 ulong32 retries;
1169 unchar prot_ver;
1170 ushort command;
1171 int i, found = FALSE;
1172
1173 TRACE(("gdth_init_pci()\n"));
1174
1175 if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
1176 ha->oem_id = OEM_ID_INTEL;
1177 else
1178 ha->oem_id = OEM_ID_ICP;
1179 ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
1180 ha->stype = (ulong32)pcistr->pdev->device;
1181 ha->irq = pcistr->irq;
1182 ha->pdev = pcistr->pdev;
1183
1184 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
1185 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1186 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
1187 if (ha->brd == NULL) {
1188 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1189 return 0;
1190 }
1191 /* check and reset interface area */
1192 dp6_ptr = ha->brd;
1193 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1194 if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
1195 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1196 pcistr->dpmem);
1197 found = FALSE;
1198 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1199 iounmap(ha->brd);
1200 ha->brd = ioremap(i, sizeof(ushort));
1201 if (ha->brd == NULL) {
1202 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1203 return 0;
1204 }
1205 if (gdth_readw(ha->brd) != 0xffff) {
1206 TRACE2(("init_pci_old() address 0x%x busy\n", i));
1207 continue;
1208 }
1209 iounmap(ha->brd);
1210 pci_write_config_dword(pcistr->pdev,
1211 PCI_BASE_ADDRESS_0, i);
1212 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
1213 if (ha->brd == NULL) {
1214 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1215 return 0;
1216 }
1217 dp6_ptr = ha->brd;
1218 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1219 if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
1220 printk("GDT-PCI: Use free address at 0x%x\n", i);
1221 found = TRUE;
1222 break;
1223 }
1224 }
1225 if (!found) {
1226 printk("GDT-PCI: No free address found!\n");
1227 iounmap(ha->brd);
1228 return 0;
1229 }
1230 }
1231 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
1232 if (gdth_readl(&dp6_ptr->u) != 0) {
1233 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1234 iounmap(ha->brd);
1235 return 0;
1236 }
1237
1238 /* disable board interrupts, deinit services */
1239 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1240 gdth_writeb(0x00, &dp6_ptr->io.irqen);
1241 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
1242 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
1243
1244 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
1245 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
1246 gdth_writeb(0, &dp6_ptr->io.event);
1247 retries = INIT_RETRIES;
1248 gdth_delay(20);
1249 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
1250 if (--retries == 0) {
1251 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1252 iounmap(ha->brd);
1253 return 0;
1254 }
1255 gdth_delay(1);
1256 }
1257 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
1258 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1259 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1260 if (prot_ver != PROTOCOL_VERSION) {
1261 printk("GDT-PCI: Illegal protocol version\n");
1262 iounmap(ha->brd);
1263 return 0;
1264 }
1265
1266 ha->type = GDT_PCI;
1267 ha->ic_all_size = sizeof(dp6_ptr->u);
1268
1269 /* special command to controller BIOS */
1270 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
1271 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
1272 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
1273 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
1274 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
1275 gdth_writeb(0, &dp6_ptr->io.event);
1276 retries = INIT_RETRIES;
1277 gdth_delay(20);
1278 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
1279 if (--retries == 0) {
1280 printk("GDT-PCI: Initialization error\n");
1281 iounmap(ha->brd);
1282 return 0;
1283 }
1284 gdth_delay(1);
1285 }
1286 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1287 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1288
1289 ha->dma64_support = 0;
1290
1291 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1292 ha->plx = (gdt6c_plx_regs *)pcistr->io;
1293 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
1294 pcistr->dpmem,ha->irq));
1295 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
1296 if (ha->brd == NULL) {
1297 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1298 iounmap(ha->brd);
1299 return 0;
1300 }
1301 /* check and reset interface area */
1302 dp6c_ptr = ha->brd;
1303 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1304 if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
1305 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1306 pcistr->dpmem);
1307 found = FALSE;
1308 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1309 iounmap(ha->brd);
1310 ha->brd = ioremap(i, sizeof(ushort));
1311 if (ha->brd == NULL) {
1312 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1313 return 0;
1314 }
1315 if (gdth_readw(ha->brd) != 0xffff) {
1316 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1317 continue;
1318 }
1319 iounmap(ha->brd);
1320 pci_write_config_dword(pcistr->pdev,
1321 PCI_BASE_ADDRESS_2, i);
1322 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1323 if (ha->brd == NULL) {
1324 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1325 return 0;
1326 }
1327 dp6c_ptr = ha->brd;
1328 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1329 if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1330 printk("GDT-PCI: Use free address at 0x%x\n", i);
1331 found = TRUE;
1332 break;
1333 }
1334 }
1335 if (!found) {
1336 printk("GDT-PCI: No free address found!\n");
1337 iounmap(ha->brd);
1338 return 0;
1339 }
1340 }
1341 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1342 if (gdth_readl(&dp6c_ptr->u) != 0) {
1343 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1344 iounmap(ha->brd);
1345 return 0;
1346 }
1347
1348 /* disable board interrupts, deinit services */
1349 outb(0x00,PTR2USHORT(&ha->plx->control1));
1350 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1351
1352 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1353 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1354
1355 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1356 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1357
1358 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1359
1360 retries = INIT_RETRIES;
1361 gdth_delay(20);
1362 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1363 if (--retries == 0) {
1364 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1365 iounmap(ha->brd);
1366 return 0;
1367 }
1368 gdth_delay(1);
1369 }
1370 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
1371 gdth_writeb(0, &dp6c_ptr->u.ic.Status);
1372 if (prot_ver != PROTOCOL_VERSION) {
1373 printk("GDT-PCI: Illegal protocol version\n");
1374 iounmap(ha->brd);
1375 return 0;
1376 }
1377
1378 ha->type = GDT_PCINEW;
1379 ha->ic_all_size = sizeof(dp6c_ptr->u);
1380
1381 /* special command to controller BIOS */
1382 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1383 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1384 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1385 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1386 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1387
1388 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1389
1390 retries = INIT_RETRIES;
1391 gdth_delay(20);
1392 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1393 if (--retries == 0) {
1394 printk("GDT-PCI: Initialization error\n");
1395 iounmap(ha->brd);
1396 return 0;
1397 }
1398 gdth_delay(1);
1399 }
1400 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
1401
1402 ha->dma64_support = 0;
1403
1404 } else { /* MPR */
1405 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1406 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1407 if (ha->brd == NULL) {
1408 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1409 return 0;
1410 }
1411
1412 /* manipulate config. space to enable DPMEM, start RP controller */
1413 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1414 command |= 6;
1415 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1416 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1417 pci_resource_start(pcistr->pdev, 8) = 0UL;
1418 i = 0xFEFF0001UL;
1419 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1420 gdth_delay(1);
1421 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1422 pci_resource_start(pcistr->pdev, 8));
1423
1424 dp6m_ptr = ha->brd;
1425
1426 /* Ensure that it is safe to access the non HW portions of DPMEM.
1427 * Aditional check needed for Xscale based RAID controllers */
1428 while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1429 gdth_delay(1);
1430
1431 /* check and reset interface area */
1432 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1433 if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1434 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1435 pcistr->dpmem);
1436 found = FALSE;
1437 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1438 iounmap(ha->brd);
1439 ha->brd = ioremap(i, sizeof(ushort));
1440 if (ha->brd == NULL) {
1441 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1442 return 0;
1443 }
1444 if (gdth_readw(ha->brd) != 0xffff) {
1445 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1446 continue;
1447 }
1448 iounmap(ha->brd);
1449 pci_write_config_dword(pcistr->pdev,
1450 PCI_BASE_ADDRESS_0, i);
1451 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1452 if (ha->brd == NULL) {
1453 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1454 return 0;
1455 }
1456 dp6m_ptr = ha->brd;
1457 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1458 if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1459 printk("GDT-PCI: Use free address at 0x%x\n", i);
1460 found = TRUE;
1461 break;
1462 }
1463 }
1464 if (!found) {
1465 printk("GDT-PCI: No free address found!\n");
1466 iounmap(ha->brd);
1467 return 0;
1468 }
1469 }
1470 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1471
1472 /* disable board interrupts, deinit services */
1473 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1474 &dp6m_ptr->i960r.edoor_en_reg);
1475 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1476 gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1477 gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1478
1479 gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1480 gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1481 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1482 retries = INIT_RETRIES;
1483 gdth_delay(20);
1484 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1485 if (--retries == 0) {
1486 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1487 iounmap(ha->brd);
1488 return 0;
1489 }
1490 gdth_delay(1);
1491 }
1492 prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
1493 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1494 if (prot_ver != PROTOCOL_VERSION) {
1495 printk("GDT-PCI: Illegal protocol version\n");
1496 iounmap(ha->brd);
1497 return 0;
1498 }
1499
1500 ha->type = GDT_PCIMPR;
1501 ha->ic_all_size = sizeof(dp6m_ptr->u);
1502
1503 /* special command to controller BIOS */
1504 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1505 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1506 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1507 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1508 gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1509 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1510 retries = INIT_RETRIES;
1511 gdth_delay(20);
1512 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1513 if (--retries == 0) {
1514 printk("GDT-PCI: Initialization error\n");
1515 iounmap(ha->brd);
1516 return 0;
1517 }
1518 gdth_delay(1);
1519 }
1520 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1521
1522 /* read FW version to detect 64-bit DMA support */
1523 gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1524 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1525 retries = INIT_RETRIES;
1526 gdth_delay(20);
1527 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1528 if (--retries == 0) {
1529 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1530 iounmap(ha->brd);
1531 return 0;
1532 }
1533 gdth_delay(1);
1534 }
1535 prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1536 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1537 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1538 ha->dma64_support = 0;
1539 else
1540 ha->dma64_support = 1;
1541 }
1542
1543 return 1;
1544 }
1545
1546
1547 /* controller protocol functions */
1548
1549 static void __init gdth_enable_int(int hanum)
1550 {
1551 gdth_ha_str *ha;
1552 ulong flags;
1553 gdt2_dpram_str __iomem *dp2_ptr;
1554 gdt6_dpram_str __iomem *dp6_ptr;
1555 gdt6m_dpram_str __iomem *dp6m_ptr;
1556
1557 TRACE(("gdth_enable_int() hanum %d\n",hanum));
1558 ha = HADATA(gdth_ctr_tab[hanum]);
1559 spin_lock_irqsave(&ha->smp_lock, flags);
1560
1561 if (ha->type == GDT_EISA) {
1562 outb(0xff, ha->bmic + EDOORREG);
1563 outb(0xff, ha->bmic + EDENABREG);
1564 outb(0x01, ha->bmic + EINTENABREG);
1565 } else if (ha->type == GDT_ISA) {
1566 dp2_ptr = ha->brd;
1567 gdth_writeb(1, &dp2_ptr->io.irqdel);
1568 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1569 gdth_writeb(1, &dp2_ptr->io.irqen);
1570 } else if (ha->type == GDT_PCI) {
1571 dp6_ptr = ha->brd;
1572 gdth_writeb(1, &dp6_ptr->io.irqdel);
1573 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1574 gdth_writeb(1, &dp6_ptr->io.irqen);
1575 } else if (ha->type == GDT_PCINEW) {
1576 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1577 outb(0x03, PTR2USHORT(&ha->plx->control1));
1578 } else if (ha->type == GDT_PCIMPR) {
1579 dp6m_ptr = ha->brd;
1580 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1581 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1582 &dp6m_ptr->i960r.edoor_en_reg);
1583 }
1584 spin_unlock_irqrestore(&ha->smp_lock, flags);
1585 }
1586
1587
1588 static int gdth_get_status(unchar *pIStatus,int irq)
1589 {
1590 register gdth_ha_str *ha;
1591 int i;
1592
1593 TRACE(("gdth_get_status() irq %d ctr_count %d\n",
1594 irq,gdth_ctr_count));
1595
1596 *pIStatus = 0;
1597 for (i=0; i<gdth_ctr_count; ++i) {
1598 ha = HADATA(gdth_ctr_tab[i]);
1599 if (ha->irq != (unchar)irq) /* check IRQ */
1600 continue;
1601 if (ha->type == GDT_EISA)
1602 *pIStatus = inb((ushort)ha->bmic + EDOORREG);
1603 else if (ha->type == GDT_ISA)
1604 *pIStatus =
1605 gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1606 else if (ha->type == GDT_PCI)
1607 *pIStatus =
1608 gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1609 else if (ha->type == GDT_PCINEW)
1610 *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1611 else if (ha->type == GDT_PCIMPR)
1612 *pIStatus =
1613 gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1614
1615 if (*pIStatus)
1616 return i; /* board found */
1617 }
1618 return -1;
1619 }
1620
1621
1622 static int gdth_test_busy(int hanum)
1623 {
1624 register gdth_ha_str *ha;
1625 register int gdtsema0 = 0;
1626
1627 TRACE(("gdth_test_busy() hanum %d\n",hanum));
1628
1629 ha = HADATA(gdth_ctr_tab[hanum]);
1630 if (ha->type == GDT_EISA)
1631 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1632 else if (ha->type == GDT_ISA)
1633 gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1634 else if (ha->type == GDT_PCI)
1635 gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1636 else if (ha->type == GDT_PCINEW)
1637 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1638 else if (ha->type == GDT_PCIMPR)
1639 gdtsema0 =
1640 (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1641
1642 return (gdtsema0 & 1);
1643 }
1644
1645
1646 static int gdth_get_cmd_index(int hanum)
1647 {
1648 register gdth_ha_str *ha;
1649 int i;
1650
1651 TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
1652
1653 ha = HADATA(gdth_ctr_tab[hanum]);
1654 for (i=0; i<GDTH_MAXCMDS; ++i) {
1655 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1656 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1657 ha->cmd_tab[i].service = ha->pccb->Service;
1658 ha->pccb->CommandIndex = (ulong32)i+2;
1659 return (i+2);
1660 }
1661 }
1662 return 0;
1663 }
1664
1665
1666 static void gdth_set_sema0(int hanum)
1667 {
1668 register gdth_ha_str *ha;
1669
1670 TRACE(("gdth_set_sema0() hanum %d\n",hanum));
1671
1672 ha = HADATA(gdth_ctr_tab[hanum]);
1673 if (ha->type == GDT_EISA) {
1674 outb(1, ha->bmic + SEMA0REG);
1675 } else if (ha->type == GDT_ISA) {
1676 gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1677 } else if (ha->type == GDT_PCI) {
1678 gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1679 } else if (ha->type == GDT_PCINEW) {
1680 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1681 } else if (ha->type == GDT_PCIMPR) {
1682 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1683 }
1684 }
1685
1686
1687 static void gdth_copy_command(int hanum)
1688 {
1689 register gdth_ha_str *ha;
1690 register gdth_cmd_str *cmd_ptr;
1691 register gdt6m_dpram_str __iomem *dp6m_ptr;
1692 register gdt6c_dpram_str __iomem *dp6c_ptr;
1693 gdt6_dpram_str __iomem *dp6_ptr;
1694 gdt2_dpram_str __iomem *dp2_ptr;
1695 ushort cp_count,dp_offset,cmd_no;
1696
1697 TRACE(("gdth_copy_command() hanum %d\n",hanum));
1698
1699 ha = HADATA(gdth_ctr_tab[hanum]);
1700 cp_count = ha->cmd_len;
1701 dp_offset= ha->cmd_offs_dpmem;
1702 cmd_no = ha->cmd_cnt;
1703 cmd_ptr = ha->pccb;
1704
1705 ++ha->cmd_cnt;
1706 if (ha->type == GDT_EISA)
1707 return; /* no DPMEM, no copy */
1708
1709 /* set cpcount dword aligned */
1710 if (cp_count & 3)
1711 cp_count += (4 - (cp_count & 3));
1712
1713 ha->cmd_offs_dpmem += cp_count;
1714
1715 /* set offset and service, copy command to DPMEM */
1716 if (ha->type == GDT_ISA) {
1717 dp2_ptr = ha->brd;
1718 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1719 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1720 gdth_writew((ushort)cmd_ptr->Service,
1721 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1722 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1723 } else if (ha->type == GDT_PCI) {
1724 dp6_ptr = ha->brd;
1725 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1726 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1727 gdth_writew((ushort)cmd_ptr->Service,
1728 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1729 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1730 } else if (ha->type == GDT_PCINEW) {
1731 dp6c_ptr = ha->brd;
1732 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1733 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1734 gdth_writew((ushort)cmd_ptr->Service,
1735 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1736 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1737 } else if (ha->type == GDT_PCIMPR) {
1738 dp6m_ptr = ha->brd;
1739 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1740 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1741 gdth_writew((ushort)cmd_ptr->Service,
1742 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1743 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1744 }
1745 }
1746
1747
1748 static void gdth_release_event(int hanum)
1749 {
1750 register gdth_ha_str *ha;
1751
1752 TRACE(("gdth_release_event() hanum %d\n",hanum));
1753 ha = HADATA(gdth_ctr_tab[hanum]);
1754
1755 #ifdef GDTH_STATISTICS
1756 {
1757 ulong32 i,j;
1758 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1759 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1760 ++i;
1761 }
1762 if (max_index < i) {
1763 max_index = i;
1764 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1765 }
1766 }
1767 #endif
1768
1769 if (ha->pccb->OpCode == GDT_INIT)
1770 ha->pccb->Service |= 0x80;
1771
1772 if (ha->type == GDT_EISA) {
1773 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1774 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1775 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1776 } else if (ha->type == GDT_ISA) {
1777 gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1778 } else if (ha->type == GDT_PCI) {
1779 gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1780 } else if (ha->type == GDT_PCINEW) {
1781 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1782 } else if (ha->type == GDT_PCIMPR) {
1783 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1784 }
1785 }
1786
1787
1788 static int gdth_wait(int hanum,int index,ulong32 time)
1789 {
1790 gdth_ha_str *ha;
1791 int answer_found = FALSE;
1792
1793 TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
1794
1795 ha = HADATA(gdth_ctr_tab[hanum]);
1796 if (index == 0)
1797 return 1; /* no wait required */
1798
1799 gdth_from_wait = TRUE;
1800 do {
1801 gdth_interrupt((int)ha->irq,ha);
1802 if (wait_hanum==hanum && wait_index==index) {
1803 answer_found = TRUE;
1804 break;
1805 }
1806 gdth_delay(1);
1807 } while (--time);
1808 gdth_from_wait = FALSE;
1809
1810 while (gdth_test_busy(hanum))
1811 gdth_delay(0);
1812
1813 return (answer_found);
1814 }
1815
1816
1817 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
1818 ulong64 p2,ulong64 p3)
1819 {
1820 register gdth_ha_str *ha;
1821 register gdth_cmd_str *cmd_ptr;
1822 int retries,index;
1823
1824 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1825
1826 ha = HADATA(gdth_ctr_tab[hanum]);
1827 cmd_ptr = ha->pccb;
1828 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1829
1830 /* make command */
1831 for (retries = INIT_RETRIES;;) {
1832 cmd_ptr->Service = service;
1833 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1834 if (!(index=gdth_get_cmd_index(hanum))) {
1835 TRACE(("GDT: No free command index found\n"));
1836 return 0;
1837 }
1838 gdth_set_sema0(hanum);
1839 cmd_ptr->OpCode = opcode;
1840 cmd_ptr->BoardNode = LOCALBOARD;
1841 if (service == CACHESERVICE) {
1842 if (opcode == GDT_IOCTL) {
1843 cmd_ptr->u.ioctl.subfunc = p1;
1844 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1845 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1846 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1847 } else {
1848 if (ha->cache_feat & GDT_64BIT) {
1849 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1850 cmd_ptr->u.cache64.BlockNo = p2;
1851 } else {
1852 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1853 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1854 }
1855 }
1856 } else if (service == SCSIRAWSERVICE) {
1857 if (ha->raw_feat & GDT_64BIT) {
1858 cmd_ptr->u.raw64.direction = p1;
1859 cmd_ptr->u.raw64.bus = (unchar)p2;
1860 cmd_ptr->u.raw64.target = (unchar)p3;
1861 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1862 } else {
1863 cmd_ptr->u.raw.direction = p1;
1864 cmd_ptr->u.raw.bus = (unchar)p2;
1865 cmd_ptr->u.raw.target = (unchar)p3;
1866 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1867 }
1868 } else if (service == SCREENSERVICE) {
1869 if (opcode == GDT_REALTIME) {
1870 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1871 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1872 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1873 }
1874 }
1875 ha->cmd_len = sizeof(gdth_cmd_str);
1876 ha->cmd_offs_dpmem = 0;
1877 ha->cmd_cnt = 0;
1878 gdth_copy_command(hanum);
1879 gdth_release_event(hanum);
1880 gdth_delay(20);
1881 if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
1882 printk("GDT: Initialization error (timeout service %d)\n",service);
1883 return 0;
1884 }
1885 if (ha->status != S_BSY || --retries == 0)
1886 break;
1887 gdth_delay(1);
1888 }
1889
1890 return (ha->status != S_OK ? 0:1);
1891 }
1892
1893
1894 /* search for devices */
1895
1896 static int __init gdth_search_drives(int hanum)
1897 {
1898 register gdth_ha_str *ha;
1899 ushort cdev_cnt, i;
1900 int ok;
1901 ulong32 bus_no, drv_cnt, drv_no, j;
1902 gdth_getch_str *chn;
1903 gdth_drlist_str *drl;
1904 gdth_iochan_str *ioc;
1905 gdth_raw_iochan_str *iocr;
1906 gdth_arcdl_str *alst;
1907 gdth_alist_str *alst2;
1908 gdth_oem_str_ioctl *oemstr;
1909 #ifdef INT_COAL
1910 gdth_perf_modes *pmod;
1911 #endif
1912
1913 #ifdef GDTH_RTC
1914 unchar rtc[12];
1915 ulong flags;
1916 #endif
1917
1918 TRACE(("gdth_search_drives() hanum %d\n",hanum));
1919 ha = HADATA(gdth_ctr_tab[hanum]);
1920 ok = 0;
1921
1922 /* initialize controller services, at first: screen service */
1923 ha->screen_feat = 0;
1924 if (!force_dma32) {
1925 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
1926 if (ok)
1927 ha->screen_feat = GDT_64BIT;
1928 }
1929 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1930 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
1931 if (!ok) {
1932 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1933 hanum, ha->status);
1934 return 0;
1935 }
1936 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1937
1938 #ifdef GDTH_RTC
1939 /* read realtime clock info, send to controller */
1940 /* 1. wait for the falling edge of update flag */
1941 spin_lock_irqsave(&rtc_lock, flags);
1942 for (j = 0; j < 1000000; ++j)
1943 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1944 break;
1945 for (j = 0; j < 1000000; ++j)
1946 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1947 break;
1948 /* 2. read info */
1949 do {
1950 for (j = 0; j < 12; ++j)
1951 rtc[j] = CMOS_READ(j);
1952 } while (rtc[0] != CMOS_READ(0));
1953 spin_unlock_irqrestore(&rtc_lock, flags);
1954 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1955 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1956 /* 3. send to controller firmware */
1957 gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
1958 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1959 #endif
1960
1961 /* unfreeze all IOs */
1962 gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
1963
1964 /* initialize cache service */
1965 ha->cache_feat = 0;
1966 if (!force_dma32) {
1967 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
1968 if (ok)
1969 ha->cache_feat = GDT_64BIT;
1970 }
1971 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1972 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
1973 if (!ok) {
1974 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1975 hanum, ha->status);
1976 return 0;
1977 }
1978 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1979 cdev_cnt = (ushort)ha->info;
1980 ha->fw_vers = ha->service;
1981
1982 #ifdef INT_COAL
1983 if (ha->type == GDT_PCIMPR) {
1984 /* set perf. modes */
1985 pmod = (gdth_perf_modes *)ha->pscratch;
1986 pmod->version = 1;
1987 pmod->st_mode = 1; /* enable one status buffer */
1988 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1989 pmod->st_buff_indx1 = COALINDEX;
1990 pmod->st_buff_addr2 = 0;
1991 pmod->st_buff_u_addr2 = 0;
1992 pmod->st_buff_indx2 = 0;
1993 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1994 pmod->cmd_mode = 0; // disable all cmd buffers
1995 pmod->cmd_buff_addr1 = 0;
1996 pmod->cmd_buff_u_addr1 = 0;
1997 pmod->cmd_buff_indx1 = 0;
1998 pmod->cmd_buff_addr2 = 0;
1999 pmod->cmd_buff_u_addr2 = 0;
2000 pmod->cmd_buff_indx2 = 0;
2001 pmod->cmd_buff_size = 0;
2002 pmod->reserved1 = 0;
2003 pmod->reserved2 = 0;
2004 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
2005 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
2006 printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
2007 }
2008 }
2009 #endif
2010
2011 /* detect number of buses - try new IOCTL */
2012 iocr = (gdth_raw_iochan_str *)ha->pscratch;
2013 iocr->hdr.version = 0xffffffff;
2014 iocr->hdr.list_entries = MAXBUS;
2015 iocr->hdr.first_chan = 0;
2016 iocr->hdr.last_chan = MAXBUS-1;
2017 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
2018 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
2019 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
2020 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
2021 ha->bus_cnt = iocr->hdr.chan_count;
2022 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2023 if (iocr->list[bus_no].proc_id < MAXID)
2024 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
2025 else
2026 ha->bus_id[bus_no] = 0xff;
2027 }
2028 } else {
2029 /* old method */
2030 chn = (gdth_getch_str *)ha->pscratch;
2031 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
2032 chn->channel_no = bus_no;
2033 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2034 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2035 IO_CHANNEL | INVALID_CHANNEL,
2036 sizeof(gdth_getch_str))) {
2037 if (bus_no == 0) {
2038 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
2039 hanum, ha->status);
2040 return 0;
2041 }
2042 break;
2043 }
2044 if (chn->siop_id < MAXID)
2045 ha->bus_id[bus_no] = chn->siop_id;
2046 else
2047 ha->bus_id[bus_no] = 0xff;
2048 }
2049 ha->bus_cnt = (unchar)bus_no;
2050 }
2051 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
2052
2053 /* read cache configuration */
2054 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
2055 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
2056 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
2057 hanum, ha->status);
2058 return 0;
2059 }
2060 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
2061 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
2062 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
2063 ha->cpar.write_back,ha->cpar.block_size));
2064
2065 /* read board info and features */
2066 ha->more_proc = FALSE;
2067 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
2068 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
2069 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
2070 sizeof(gdth_binfo_str));
2071 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
2072 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
2073 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
2074 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
2075 ha->more_proc = TRUE;
2076 }
2077 } else {
2078 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
2079 strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
2080 }
2081 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
2082
2083 /* read more informations */
2084 if (ha->more_proc) {
2085 /* physical drives, channel addresses */
2086 ioc = (gdth_iochan_str *)ha->pscratch;
2087 ioc->hdr.version = 0xffffffff;
2088 ioc->hdr.list_entries = MAXBUS;
2089 ioc->hdr.first_chan = 0;
2090 ioc->hdr.last_chan = MAXBUS-1;
2091 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
2092 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
2093 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
2094 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2095 ha->raw[bus_no].address = ioc->list[bus_no].address;
2096 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
2097 }
2098 } else {
2099 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2100 ha->raw[bus_no].address = IO_CHANNEL;
2101 ha->raw[bus_no].local_no = bus_no;
2102 }
2103 }
2104 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2105 chn = (gdth_getch_str *)ha->pscratch;
2106 chn->channel_no = ha->raw[bus_no].local_no;
2107 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2108 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2109 ha->raw[bus_no].address | INVALID_CHANNEL,
2110 sizeof(gdth_getch_str))) {
2111 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
2112 TRACE2(("Channel %d: %d phys. drives\n",
2113 bus_no,chn->drive_cnt));
2114 }
2115 if (ha->raw[bus_no].pdev_cnt > 0) {
2116 drl = (gdth_drlist_str *)ha->pscratch;
2117 drl->sc_no = ha->raw[bus_no].local_no;
2118 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
2119 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2120 SCSI_DR_LIST | L_CTRL_PATTERN,
2121 ha->raw[bus_no].address | INVALID_CHANNEL,
2122 sizeof(gdth_drlist_str))) {
2123 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
2124 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
2125 } else {
2126 ha->raw[bus_no].pdev_cnt = 0;
2127 }
2128 }
2129 }
2130
2131 /* logical drives */
2132 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
2133 INVALID_CHANNEL,sizeof(ulong32))) {
2134 drv_cnt = *(ulong32 *)ha->pscratch;
2135 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
2136 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
2137 for (j = 0; j < drv_cnt; ++j) {
2138 drv_no = ((ulong32 *)ha->pscratch)[j];
2139 if (drv_no < MAX_LDRIVES) {
2140 ha->hdr[drv_no].is_logdrv = TRUE;
2141 TRACE2(("Drive %d is log. drive\n",drv_no));
2142 }
2143 }
2144 }
2145 alst = (gdth_arcdl_str *)ha->pscratch;
2146 alst->entries_avail = MAX_LDRIVES;
2147 alst->first_entry = 0;
2148 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
2149 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2150 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
2151 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
2152 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
2153 for (j = 0; j < alst->entries_init; ++j) {
2154 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
2155 ha->hdr[j].is_master = alst->list[j].is_master;
2156 ha->hdr[j].is_parity = alst->list[j].is_parity;
2157 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
2158 ha->hdr[j].master_no = alst->list[j].cd_handle;
2159 }
2160 } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2161 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
2162 0, 35 * sizeof(gdth_alist_str))) {
2163 for (j = 0; j < 35; ++j) {
2164 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
2165 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
2166 ha->hdr[j].is_master = alst2->is_master;
2167 ha->hdr[j].is_parity = alst2->is_parity;
2168 ha->hdr[j].is_hotfix = alst2->is_hotfix;
2169 ha->hdr[j].master_no = alst2->cd_handle;
2170 }
2171 }
2172 }
2173 }
2174
2175 /* initialize raw service */
2176 ha->raw_feat = 0;
2177 if (!force_dma32) {
2178 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
2179 if (ok)
2180 ha->raw_feat = GDT_64BIT;
2181 }
2182 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
2183 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
2184 if (!ok) {
2185 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
2186 hanum, ha->status);
2187 return 0;
2188 }
2189 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
2190
2191 /* set/get features raw service (scatter/gather) */
2192 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
2193 0,0)) {
2194 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
2195 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
2196 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
2197 ha->info));
2198 ha->raw_feat |= (ushort)ha->info;
2199 }
2200 }
2201
2202 /* set/get features cache service (equal to raw service) */
2203 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
2204 SCATTER_GATHER,0)) {
2205 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
2206 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
2207 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
2208 ha->info));
2209 ha->cache_feat |= (ushort)ha->info;
2210 }
2211 }
2212
2213 /* reserve drives for raw service */
2214 if (reserve_mode != 0) {
2215 gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
2216 reserve_mode == 1 ? 1 : 3, 0, 0);
2217 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
2218 ha->status));
2219 }
2220 for (i = 0; i < MAX_RES_ARGS; i += 4) {
2221 if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
2222 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
2223 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
2224 reserve_list[i], reserve_list[i+1],
2225 reserve_list[i+2], reserve_list[i+3]));
2226 if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
2227 reserve_list[i+1], reserve_list[i+2] |
2228 (reserve_list[i+3] << 8))) {
2229 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
2230 hanum, ha->status);
2231 }
2232 }
2233 }
2234
2235 /* Determine OEM string using IOCTL */
2236 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
2237 oemstr->params.ctl_version = 0x01;
2238 oemstr->params.buffer_size = sizeof(oemstr->text);
2239 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2240 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
2241 sizeof(gdth_oem_str_ioctl))) {
2242 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
2243 printk("GDT-HA %d: Vendor: %s Name: %s\n",
2244 hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
2245 /* Save the Host Drive inquiry data */
2246 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2247 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
2248 sizeof(ha->oem_name));
2249 #else
2250 strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
2251 ha->oem_name[7] = '\0';
2252 #endif
2253 } else {
2254 /* Old method, based on PCI ID */
2255 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
2256 printk("GDT-HA %d: Name: %s\n",
2257 hanum,ha->binfo.type_string);
2258 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2259 if (ha->oem_id == OEM_ID_INTEL)
2260 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
2261 else
2262 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
2263 #else
2264 if (ha->oem_id == OEM_ID_INTEL)
2265 strcpy(ha->oem_name,"Intel ");
2266 else
2267 strcpy(ha->oem_name,"ICP ");
2268 #endif
2269 }
2270
2271 /* scanning for host drives */
2272 for (i = 0; i < cdev_cnt; ++i)
2273 gdth_analyse_hdrive(hanum,i);
2274
2275 TRACE(("gdth_search_drives() OK\n"));
2276 return 1;
2277 }
2278
2279 static int gdth_analyse_hdrive(int hanum,ushort hdrive)
2280 {
2281 register gdth_ha_str *ha;
2282 ulong32 drv_cyls;
2283 int drv_hds, drv_secs;
2284
2285 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
2286 if (hdrive >= MAX_HDRIVES)
2287 return 0;
2288 ha = HADATA(gdth_ctr_tab[hanum]);
2289
2290 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
2291 return 0;
2292 ha->hdr[hdrive].present = TRUE;
2293 ha->hdr[hdrive].size = ha->info;
2294
2295 /* evaluate mapping (sectors per head, heads per cylinder) */
2296 ha->hdr[hdrive].size &= ~SECS32;
2297 if (ha->info2 == 0) {
2298 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
2299 } else {
2300 drv_hds = ha->info2 & 0xff;
2301 drv_secs = (ha->info2 >> 8) & 0xff;
2302 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
2303 }
2304 ha->hdr[hdrive].heads = (unchar)drv_hds;
2305 ha->hdr[hdrive].secs = (unchar)drv_secs;
2306 /* round size */
2307 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
2308
2309 if (ha->cache_feat & GDT_64BIT) {
2310 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
2311 && ha->info2 != 0) {
2312 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
2313 }
2314 }
2315 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
2316 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
2317
2318 /* get informations about device */
2319 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
2320 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
2321 hdrive,ha->info));
2322 ha->hdr[hdrive].devtype = (ushort)ha->info;
2323 }
2324
2325 /* cluster info */
2326 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
2327 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
2328 hdrive,ha->info));
2329 if (!shared_access)
2330 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
2331 }
2332
2333 /* R/W attributes */
2334 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
2335 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
2336 hdrive,ha->info));
2337 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2338 }
2339
2340 return 1;
2341 }
2342
2343
2344 /* command queueing/sending functions */
2345
2346 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
2347 {
2348 register gdth_ha_str *ha;
2349 register Scsi_Cmnd *pscp;
2350 register Scsi_Cmnd *nscp;
2351 ulong flags;
2352 unchar b, t;
2353
2354 TRACE(("gdth_putq() priority %d\n",priority));
2355 ha = HADATA(gdth_ctr_tab[hanum]);
2356 spin_lock_irqsave(&ha->smp_lock, flags);
2357
2358 if (scp->done != gdth_scsi_done) {
2359 scp->SCp.this_residual = (int)priority;
2360 b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
2361 t = scp->device->id;
2362 if (priority >= DEFAULT_PRI) {
2363 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2364 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2365 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2366 scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
2367 }
2368 }
2369 }
2370
2371 if (ha->req_first==NULL) {
2372 ha->req_first = scp; /* queue was empty */
2373 scp->SCp.ptr = NULL;
2374 } else { /* queue not empty */
2375 pscp = ha->req_first;
2376 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2377 /* priority: 0-highest,..,0xff-lowest */
2378 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2379 pscp = nscp;
2380 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2381 }
2382 pscp->SCp.ptr = (char *)scp;
2383 scp->SCp.ptr = (char *)nscp;
2384 }
2385 spin_unlock_irqrestore(&ha->smp_lock, flags);
2386
2387 #ifdef GDTH_STATISTICS
2388 flags = 0;
2389 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2390 ++flags;
2391 if (max_rq < flags) {
2392 max_rq = flags;
2393 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2394 }
2395 #endif
2396 }
2397
2398 static void gdth_next(int hanum)
2399 {
2400 register gdth_ha_str *ha;
2401 register Scsi_Cmnd *pscp;
2402 register Scsi_Cmnd *nscp;
2403 unchar b, t, l, firsttime;
2404 unchar this_cmd, next_cmd;
2405 ulong flags = 0;
2406 int cmd_index;
2407
2408 TRACE(("gdth_next() hanum %d\n",hanum));
2409 ha = HADATA(gdth_ctr_tab[hanum]);
2410 if (!gdth_polling)
2411 spin_lock_irqsave(&ha->smp_lock, flags);
2412
2413 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2414 this_cmd = firsttime = TRUE;
2415 next_cmd = gdth_polling ? FALSE:TRUE;
2416 cmd_index = 0;
2417
2418 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2419 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2420 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2421 if (nscp->done != gdth_scsi_done) {
2422 b = virt_ctr ?
2423 NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
2424 t = nscp->device->id;
2425 l = nscp->device->lun;
2426 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2427 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2428 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2429 continue;
2430 }
2431 } else
2432 b = t = l = 0;
2433
2434 if (firsttime) {
2435 if (gdth_test_busy(hanum)) { /* controller busy ? */
2436 TRACE(("gdth_next() controller %d busy !\n",hanum));
2437 if (!gdth_polling) {
2438 spin_unlock_irqrestore(&ha->smp_lock, flags);
2439 return;
2440 }
2441 while (gdth_test_busy(hanum))
2442 gdth_delay(1);
2443 }
2444 firsttime = FALSE;
2445 }
2446
2447 if (nscp->done != gdth_scsi_done) {
2448 if (nscp->SCp.phase == -1) {
2449 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2450 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2451 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2452 b, t, l));
2453 /* TEST_UNIT_READY -> set scan mode */
2454 if ((ha->scan_mode & 0x0f) == 0) {
2455 if (b == 0 && t == 0 && l == 0) {
2456 ha->scan_mode |= 1;
2457 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2458 }
2459 } else if ((ha->scan_mode & 0x0f) == 1) {
2460 if (b == 0 && ((t == 0 && l == 1) ||
2461 (t == 1 && l == 0))) {
2462 nscp->SCp.sent_command = GDT_SCAN_START;
2463 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2464 | SCSIRAWSERVICE;
2465 ha->scan_mode = 0x12;
2466 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2467 ha->scan_mode));
2468 } else {
2469 ha->scan_mode &= 0x10;
2470 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2471 }
2472 } else if (ha->scan_mode == 0x12) {
2473 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2474 nscp->SCp.phase = SCSIRAWSERVICE;
2475 nscp->SCp.sent_command = GDT_SCAN_END;
2476 ha->scan_mode &= 0x10;
2477 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2478 ha->scan_mode));
2479 }
2480 }
2481 }
2482 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2483 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2484 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2485 /* always GDT_CLUST_INFO! */
2486 nscp->SCp.sent_command = GDT_CLUST_INFO;
2487 }
2488 }
2489 }
2490
2491 if (nscp->SCp.sent_command != -1) {
2492 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
2493 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2494 this_cmd = FALSE;
2495 next_cmd = FALSE;
2496 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
2497 if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2498 this_cmd = FALSE;
2499 next_cmd = FALSE;
2500 } else {
2501 memset((char*)nscp->sense_buffer,0,16);
2502 nscp->sense_buffer[0] = 0x70;
2503 nscp->sense_buffer[2] = NOT_READY;
2504 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2505 if (!nscp->SCp.have_data_in)
2506 nscp->SCp.have_data_in++;
2507 else
2508 nscp->scsi_done(nscp);
2509 }
2510 } else if (nscp->done == gdth_scsi_done) {
2511 if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
2512 this_cmd = FALSE;
2513 next_cmd = FALSE;
2514 } else if (b != ha->virt_bus) {
2515 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2516 !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2517 this_cmd = FALSE;
2518 else
2519 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2520 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2521 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2522 nscp->cmnd[0], b, t, l));
2523 nscp->result = DID_BAD_TARGET << 16;
2524 if (!nscp->SCp.have_data_in)
2525 nscp->SCp.have_data_in++;
2526 else
2527 nscp->scsi_done(nscp);
2528 } else {
2529 switch (nscp->cmnd[0]) {
2530 case TEST_UNIT_READY:
2531 case INQUIRY:
2532 case REQUEST_SENSE:
2533 case READ_CAPACITY:
2534 case VERIFY:
2535 case START_STOP:
2536 case MODE_SENSE:
2537 case SERVICE_ACTION_IN:
2538 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2539 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2540 nscp->cmnd[4],nscp->cmnd[5]));
2541 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2542 /* return UNIT_ATTENTION */
2543 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2544 nscp->cmnd[0], t));
2545 ha->hdr[t].media_changed = FALSE;
2546 memset((char*)nscp->sense_buffer,0,16);
2547 nscp->sense_buffer[0] = 0x70;
2548 nscp->sense_buffer[2] = UNIT_ATTENTION;
2549 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2550 if (!nscp->SCp.have_data_in)
2551 nscp->SCp.have_data_in++;
2552 else
2553 nscp->scsi_done(nscp);
2554 } else if (gdth_internal_cache_cmd(hanum,nscp))
2555 nscp->scsi_done(nscp);
2556 break;
2557
2558 case ALLOW_MEDIUM_REMOVAL:
2559 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2560 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2561 nscp->cmnd[4],nscp->cmnd[5]));
2562 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2563 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2564 nscp->result = DID_OK << 16;
2565 nscp->sense_buffer[0] = 0;
2566 if (!nscp->SCp.have_data_in)
2567 nscp->SCp.have_data_in++;
2568 else
2569 nscp->scsi_done(nscp);
2570 } else {
2571 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2572 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2573 nscp->cmnd[4],nscp->cmnd[3]));
2574 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2575 this_cmd = FALSE;
2576 }
2577 break;
2578
2579 case RESERVE:
2580 case RELEASE:
2581 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2582 "RESERVE" : "RELEASE"));
2583 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2584 this_cmd = FALSE;
2585 break;
2586
2587 case READ_6:
2588 case WRITE_6:
2589 case READ_10:
2590 case WRITE_10:
2591 case READ_16:
2592 case WRITE_16:
2593 if (ha->hdr[t].media_changed) {
2594 /* return UNIT_ATTENTION */
2595 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2596 nscp->cmnd[0], t));
2597 ha->hdr[t].media_changed = FALSE;
2598 memset((char*)nscp->sense_buffer,0,16);
2599 nscp->sense_buffer[0] = 0x70;
2600 nscp->sense_buffer[2] = UNIT_ATTENTION;
2601 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2602 if (!nscp->SCp.have_data_in)
2603 nscp->SCp.have_data_in++;
2604 else
2605 nscp->scsi_done(nscp);
2606 } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2607 this_cmd = FALSE;
2608 break;
2609
2610 default:
2611 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2612 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2613 nscp->cmnd[4],nscp->cmnd[5]));
2614 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2615 hanum, nscp->cmnd[0]);
2616 nscp->result = DID_ABORT << 16;
2617 if (!nscp->SCp.have_data_in)
2618 nscp->SCp.have_data_in++;
2619 else
2620 nscp->scsi_done(nscp);
2621 break;
2622 }
2623 }
2624
2625 if (!this_cmd)
2626 break;
2627 if (nscp == ha->req_first)
2628 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2629 else
2630 pscp->SCp.ptr = nscp->SCp.ptr;
2631 if (!next_cmd)
2632 break;
2633 }
2634
2635 if (ha->cmd_cnt > 0) {
2636 gdth_release_event(hanum);
2637 }
2638
2639 if (!gdth_polling)
2640 spin_unlock_irqrestore(&ha->smp_lock, flags);
2641
2642 if (gdth_polling && ha->cmd_cnt > 0) {
2643 if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
2644 printk("GDT-HA %d: Command %d timed out !\n",
2645 hanum,cmd_index);
2646 }
2647 }
2648
2649 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
2650 char *buffer,ushort count)
2651 {
2652 ushort cpcount,i;
2653 ushort cpsum,cpnow;
2654 struct scatterlist *sl;
2655 gdth_ha_str *ha;
2656 char *address;
2657
2658 cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
2659 ha = HADATA(gdth_ctr_tab[hanum]);
2660
2661 if (scp->use_sg) {
2662 sl = (struct scatterlist *)scp->request_buffer;
2663 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
2664 unsigned long flags;
2665 cpnow = (ushort)sl->length;
2666 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2667 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2668 if (cpsum+cpnow > cpcount)
2669 cpnow = cpcount - cpsum;
2670 cpsum += cpnow;
2671 if (!sl->page) {
2672 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2673 hanum);
2674 return;
2675 }
2676 local_irq_save(flags);
2677 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2678 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2679 memcpy(address,buffer,cpnow);
2680 flush_dcache_page(sl->page);
2681 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2682 #else
2683 address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
2684 memcpy(address,buffer,cpnow);
2685 flush_dcache_page(sl->page);
2686 kunmap_atomic(address, KM_BH_IRQ);
2687 #endif
2688 local_irq_restore(flags);
2689 if (cpsum == cpcount)
2690 break;
2691 buffer += cpnow;
2692 }
2693 } else {
2694 TRACE(("copy_internal() count %d\n",cpcount));
2695 memcpy((char*)scp->request_buffer,buffer,cpcount);
2696 }
2697 }
2698
2699 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
2700 {
2701 register gdth_ha_str *ha;
2702 unchar t;
2703 gdth_inq_data inq;
2704 gdth_rdcap_data rdc;
2705 gdth_sense_data sd;
2706 gdth_modep_data mpd;
2707
2708 ha = HADATA(gdth_ctr_tab[hanum]);
2709 t = scp->device->id;
2710 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2711 scp->cmnd[0],t));
2712
2713 scp->result = DID_OK << 16;
2714 scp->sense_buffer[0] = 0;
2715
2716 switch (scp->cmnd[0]) {
2717 case TEST_UNIT_READY:
2718 case VERIFY:
2719 case START_STOP:
2720 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2721 break;
2722
2723 case INQUIRY:
2724 TRACE2(("Inquiry hdrive %d devtype %d\n",
2725 t,ha->hdr[t].devtype));
2726 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2727 /* you can here set all disks to removable, if you want to do
2728 a flush using the ALLOW_MEDIUM_REMOVAL command */
2729 inq.modif_rmb = 0x00;
2730 if ((ha->hdr[t].devtype & 1) ||
2731 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2732 inq.modif_rmb = 0x80;
2733 inq.version = 2;
2734 inq.resp_aenc = 2;
2735 inq.add_length= 32;
2736 strcpy(inq.vendor,ha->oem_name);
2737 sprintf(inq.product,"Host Drive #%02d",t);
2738 strcpy(inq.revision," ");
2739 gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
2740 break;
2741
2742 case REQUEST_SENSE:
2743 TRACE2(("Request sense hdrive %d\n",t));
2744 sd.errorcode = 0x70;
2745 sd.segno = 0x00;
2746 sd.key = NO_SENSE;
2747 sd.info = 0;
2748 sd.add_length= 0;
2749 gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
2750 break;
2751
2752 case MODE_SENSE:
2753 TRACE2(("Mode sense hdrive %d\n",t));
2754 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2755 mpd.hd.data_length = sizeof(gdth_modep_data);
2756 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2757 mpd.hd.bd_length = sizeof(mpd.bd);
2758 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2759 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2760 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2761 gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
2762 break;
2763
2764 case READ_CAPACITY:
2765 TRACE2(("Read capacity hdrive %d\n",t));
2766 if (ha->hdr[t].size > (ulong64)0xffffffff)
2767 rdc.last_block_no = 0xffffffff;
2768 else
2769 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2770 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2771 gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
2772 break;
2773
2774 case SERVICE_ACTION_IN:
2775 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2776 (ha->cache_feat & GDT_64BIT)) {
2777 gdth_rdcap16_data rdc16;
2778
2779 TRACE2(("Read capacity (16) hdrive %d\n",t));
2780 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2781 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2782 gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
2783 } else {
2784 scp->result = DID_ABORT << 16;
2785 }
2786 break;
2787
2788 default:
2789 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2790 break;
2791 }
2792
2793 if (!scp->SCp.have_data_in)
2794 scp->SCp.have_data_in++;
2795 else
2796 return 1;
2797
2798 return 0;
2799 }
2800
2801 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
2802 {
2803 register gdth_ha_str *ha;
2804 register gdth_cmd_str *cmdp;
2805 struct scatterlist *sl;
2806 ulong32 cnt, blockcnt;
2807 ulong64 no, blockno;
2808 dma_addr_t phys_addr;
2809 int i, cmd_index, read_write, sgcnt, mode64;
2810 struct page *page;
2811 ulong offset;
2812
2813 ha = HADATA(gdth_ctr_tab[hanum]);
2814 cmdp = ha->pccb;
2815 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2816 scp->cmnd[0],scp->cmd_len,hdrive));
2817
2818 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2819 return 0;
2820
2821 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2822 /* test for READ_16, WRITE_16 if !mode64 ? ---
2823 not required, should not occur due to error return on
2824 READ_CAPACITY_16 */
2825
2826 cmdp->Service = CACHESERVICE;
2827 cmdp->RequestBuffer = scp;
2828 /* search free command index */
2829 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2830 TRACE(("GDT: No free command index found\n"));
2831 return 0;
2832 }
2833 /* if it's the first command, set command semaphore */
2834 if (ha->cmd_cnt == 0)
2835 gdth_set_sema0(hanum);
2836
2837 /* fill command */
2838 read_write = 0;
2839 if (scp->SCp.sent_command != -1)
2840 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2841 else if (scp->cmnd[0] == RESERVE)
2842 cmdp->OpCode = GDT_RESERVE_DRV;
2843 else if (scp->cmnd[0] == RELEASE)
2844 cmdp->OpCode = GDT_RELEASE_DRV;
2845 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2846 if (scp->cmnd[4] & 1) /* prevent ? */
2847 cmdp->OpCode = GDT_MOUNT;
2848 else if (scp->cmnd[3] & 1) /* removable drive ? */
2849 cmdp->OpCode = GDT_UNMOUNT;
2850 else
2851 cmdp->OpCode = GDT_FLUSH;
2852 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2853 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2854 ) {
2855 read_write = 1;
2856 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2857 (ha->cache_feat & GDT_WR_THROUGH)))
2858 cmdp->OpCode = GDT_WRITE_THR;
2859 else
2860 cmdp->OpCode = GDT_WRITE;
2861 } else {
2862 read_write = 2;
2863 cmdp->OpCode = GDT_READ;
2864 }
2865
2866 cmdp->BoardNode = LOCALBOARD;
2867 if (mode64) {
2868 cmdp->u.cache64.DeviceNo = hdrive;
2869 cmdp->u.cache64.BlockNo = 1;
2870 cmdp->u.cache64.sg_canz = 0;
2871 } else {
2872 cmdp->u.cache.DeviceNo = hdrive;
2873 cmdp->u.cache.BlockNo = 1;
2874 cmdp->u.cache.sg_canz = 0;
2875 }
2876
2877 if (read_write) {
2878 if (scp->cmd_len == 16) {
2879 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2880 blockno = be64_to_cpu(no);
2881 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2882 blockcnt = be32_to_cpu(cnt);
2883 } else if (scp->cmd_len == 10) {
2884 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2885 blockno = be32_to_cpu(no);
2886 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2887 blockcnt = be16_to_cpu(cnt);
2888 } else {
2889 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2890 blockno = be32_to_cpu(no) & 0x001fffffUL;
2891 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2892 }
2893 if (mode64) {
2894 cmdp->u.cache64.BlockNo = blockno;
2895 cmdp->u.cache64.BlockCnt = blockcnt;
2896 } else {
2897 cmdp->u.cache.BlockNo = (ulong32)blockno;
2898 cmdp->u.cache.BlockCnt = blockcnt;
2899 }
2900
2901 if (scp->use_sg) {
2902 sl = (struct scatterlist *)scp->request_buffer;
2903 sgcnt = scp->use_sg;
2904 scp->SCp.Status = GDTH_MAP_SG;
2905 scp->SCp.Message = (read_write == 1 ?
2906 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2907 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2908 if (mode64) {
2909 cmdp->u.cache64.DestAddr= (ulong64)-1;
2910 cmdp->u.cache64.sg_canz = sgcnt;
2911 for (i=0; i<sgcnt; ++i,++sl) {
2912 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2913 #ifdef GDTH_DMA_STATISTICS
2914 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2915 ha->dma64_cnt++;
2916 else
2917 ha->dma32_cnt++;
2918 #endif
2919 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2920 }
2921 } else {
2922 cmdp->u.cache.DestAddr= 0xffffffff;
2923 cmdp->u.cache.sg_canz = sgcnt;
2924 for (i=0; i<sgcnt; ++i,++sl) {
2925 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2926 #ifdef GDTH_DMA_STATISTICS
2927 ha->dma32_cnt++;
2928 #endif
2929 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2930 }
2931 }
2932
2933 #ifdef GDTH_STATISTICS
2934 if (max_sg < (ulong32)sgcnt) {
2935 max_sg = (ulong32)sgcnt;
2936 TRACE3(("GDT: max_sg = %d\n",max_sg));
2937 }
2938 #endif
2939
2940 } else if (scp->request_bufflen) {
2941 scp->SCp.Status = GDTH_MAP_SINGLE;
2942 scp->SCp.Message = (read_write == 1 ?
2943 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2944 page = virt_to_page(scp->request_buffer);
2945 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2946 phys_addr = pci_map_page(ha->pdev,page,offset,
2947 scp->request_bufflen,scp->SCp.Message);
2948 scp->SCp.dma_handle = phys_addr;
2949 if (mode64) {
2950 if (ha->cache_feat & SCATTER_GATHER) {
2951 cmdp->u.cache64.DestAddr = (ulong64)-1;
2952 cmdp->u.cache64.sg_canz = 1;
2953 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2954 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2955 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2956 } else {
2957 cmdp->u.cache64.DestAddr = phys_addr;
2958 cmdp->u.cache64.sg_canz= 0;
2959 }
2960 } else {
2961 if (ha->cache_feat & SCATTER_GATHER) {
2962 cmdp->u.cache.DestAddr = 0xffffffff;
2963 cmdp->u.cache.sg_canz = 1;
2964 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2965 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2966 cmdp->u.cache.sg_lst[1].sg_len = 0;
2967 } else {
2968 cmdp->u.cache.DestAddr = phys_addr;
2969 cmdp->u.cache.sg_canz= 0;
2970 }
2971 }
2972 }
2973 }
2974 /* evaluate command size, check space */
2975 if (mode64) {
2976 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2977 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2978 cmdp->u.cache64.sg_lst[0].sg_ptr,
2979 cmdp->u.cache64.sg_lst[0].sg_len));
2980 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2981 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2982 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2983 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2984 } else {
2985 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2986 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2987 cmdp->u.cache.sg_lst[0].sg_ptr,
2988 cmdp->u.cache.sg_lst[0].sg_len));
2989 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2990 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2991 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2992 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2993 }
2994 if (ha->cmd_len & 3)
2995 ha->cmd_len += (4 - (ha->cmd_len & 3));
2996
2997 if (ha->cmd_cnt > 0) {
2998 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2999 ha->ic_all_size) {
3000 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
3001 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3002 return 0;
3003 }
3004 }
3005
3006 /* copy command */
3007 gdth_copy_command(hanum);
3008 return cmd_index;
3009 }
3010
3011 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
3012 {
3013 register gdth_ha_str *ha;
3014 register gdth_cmd_str *cmdp;
3015 struct scatterlist *sl;
3016 ushort i;
3017 dma_addr_t phys_addr, sense_paddr;
3018 int cmd_index, sgcnt, mode64;
3019 unchar t,l;
3020 struct page *page;
3021 ulong offset;
3022
3023 ha = HADATA(gdth_ctr_tab[hanum]);
3024 t = scp->device->id;
3025 l = scp->device->lun;
3026 cmdp = ha->pccb;
3027 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
3028 scp->cmnd[0],b,t,l));
3029
3030 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3031 return 0;
3032
3033 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
3034
3035 cmdp->Service = SCSIRAWSERVICE;
3036 cmdp->RequestBuffer = scp;
3037 /* search free command index */
3038 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3039 TRACE(("GDT: No free command index found\n"));
3040 return 0;
3041 }
3042 /* if it's the first command, set command semaphore */
3043 if (ha->cmd_cnt == 0)
3044 gdth_set_sema0(hanum);
3045
3046 /* fill command */
3047 if (scp->SCp.sent_command != -1) {
3048 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
3049 cmdp->BoardNode = LOCALBOARD;
3050 if (mode64) {
3051 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
3052 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3053 cmdp->OpCode, cmdp->u.raw64.direction));
3054 /* evaluate command size */
3055 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
3056 } else {
3057 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
3058 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3059 cmdp->OpCode, cmdp->u.raw.direction));
3060 /* evaluate command size */
3061 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
3062 }
3063
3064 } else {
3065 page = virt_to_page(scp->sense_buffer);
3066 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
3067 sense_paddr = pci_map_page(ha->pdev,page,offset,
3068 16,PCI_DMA_FROMDEVICE);
3069 *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
3070 /* high part, if 64bit */
3071 *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
3072 cmdp->OpCode = GDT_WRITE; /* always */
3073 cmdp->BoardNode = LOCALBOARD;
3074 if (mode64) {
3075 cmdp->u.raw64.reserved = 0;
3076 cmdp->u.raw64.mdisc_time = 0;
3077 cmdp->u.raw64.mcon_time = 0;
3078 cmdp->u.raw64.clen = scp->cmd_len;
3079 cmdp->u.raw64.target = t;
3080 cmdp->u.raw64.lun = l;
3081 cmdp->u.raw64.bus = b;
3082 cmdp->u.raw64.priority = 0;
3083 cmdp->u.raw64.sdlen = scp->request_bufflen;
3084 cmdp->u.raw64.sense_len = 16;
3085 cmdp->u.raw64.sense_data = sense_paddr;
3086 cmdp->u.raw64.direction =
3087 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3088 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
3089 cmdp->u.raw64.sg_ranz = 0;
3090 } else {
3091 cmdp->u.raw.reserved = 0;
3092 cmdp->u.raw.mdisc_time = 0;
3093 cmdp->u.raw.mcon_time = 0;
3094 cmdp->u.raw.clen = scp->cmd_len;
3095 cmdp->u.raw.target = t;
3096 cmdp->u.raw.lun = l;
3097 cmdp->u.raw.bus = b;
3098 cmdp->u.raw.priority = 0;
3099 cmdp->u.raw.link_p = 0;
3100 cmdp->u.raw.sdlen = scp->request_bufflen;
3101 cmdp->u.raw.sense_len = 16;
3102 cmdp->u.raw.sense_data = sense_paddr;
3103 cmdp->u.raw.direction =
3104 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3105 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
3106 cmdp->u.raw.sg_ranz = 0;
3107 }
3108
3109 if (scp->use_sg) {
3110 sl = (struct scatterlist *)scp->request_buffer;
3111 sgcnt = scp->use_sg;
3112 scp->SCp.Status = GDTH_MAP_SG;
3113 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3114 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
3115 if (mode64) {
3116 cmdp->u.raw64.sdata = (ulong64)-1;
3117 cmdp->u.raw64.sg_ranz = sgcnt;
3118 for (i=0; i<sgcnt; ++i,++sl) {
3119 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
3120 #ifdef GDTH_DMA_STATISTICS
3121 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
3122 ha->dma64_cnt++;
3123 else
3124 ha->dma32_cnt++;
3125 #endif
3126 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
3127 }
3128 } else {
3129 cmdp->u.raw.sdata = 0xffffffff;
3130 cmdp->u.raw.sg_ranz = sgcnt;
3131 for (i=0; i<sgcnt; ++i,++sl) {
3132 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
3133 #ifdef GDTH_DMA_STATISTICS
3134 ha->dma32_cnt++;
3135 #endif
3136 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
3137 }
3138 }
3139
3140 #ifdef GDTH_STATISTICS
3141 if (max_sg < sgcnt) {
3142 max_sg = sgcnt;
3143 TRACE3(("GDT: max_sg = %d\n",sgcnt));
3144 }
3145 #endif
3146
3147 } else if (scp->request_bufflen) {
3148 scp->SCp.Status = GDTH_MAP_SINGLE;
3149 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3150 page = virt_to_page(scp->request_buffer);
3151 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
3152 phys_addr = pci_map_page(ha->pdev,page,offset,
3153 scp->request_bufflen,scp->SCp.Message);
3154 scp->SCp.dma_handle = phys_addr;
3155
3156 if (mode64) {
3157 if (ha->raw_feat & SCATTER_GATHER) {
3158 cmdp->u.raw64.sdata = (ulong64)-1;
3159 cmdp->u.raw64.sg_ranz= 1;
3160 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
3161 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
3162 cmdp->u.raw64.sg_lst[1].sg_len = 0;
3163 } else {
3164 cmdp->u.raw64.sdata = phys_addr;
3165 cmdp->u.raw64.sg_ranz= 0;
3166 }
3167 } else {
3168 if (ha->raw_feat & SCATTER_GATHER) {
3169 cmdp->u.raw.sdata = 0xffffffff;
3170 cmdp->u.raw.sg_ranz= 1;
3171 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
3172 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
3173 cmdp->u.raw.sg_lst[1].sg_len = 0;
3174 } else {
3175 cmdp->u.raw.sdata = phys_addr;
3176 cmdp->u.raw.sg_ranz= 0;
3177 }
3178 }
3179 }
3180 if (mode64) {
3181 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3182 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
3183 cmdp->u.raw64.sg_lst[0].sg_ptr,
3184 cmdp->u.raw64.sg_lst[0].sg_len));
3185 /* evaluate command size */
3186 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
3187 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
3188 } else {
3189 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3190 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
3191 cmdp->u.raw.sg_lst[0].sg_ptr,
3192 cmdp->u.raw.sg_lst[0].sg_len));
3193 /* evaluate command size */
3194 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
3195 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
3196 }
3197 }
3198 /* check space */
3199 if (ha->cmd_len & 3)
3200 ha->cmd_len += (4 - (ha->cmd_len & 3));
3201
3202 if (ha->cmd_cnt > 0) {
3203 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3204 ha->ic_all_size) {
3205 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
3206 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3207 return 0;
3208 }
3209 }
3210
3211 /* copy command */
3212 gdth_copy_command(hanum);
3213 return cmd_index;
3214 }
3215
3216 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
3217 {
3218 register gdth_ha_str *ha;
3219 register gdth_cmd_str *cmdp;
3220 int cmd_index;
3221
3222 ha = HADATA(gdth_ctr_tab[hanum]);
3223 cmdp= ha->pccb;
3224 TRACE2(("gdth_special_cmd(): "));
3225
3226 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3227 return 0;
3228
3229 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
3230 cmdp->RequestBuffer = scp;
3231
3232 /* search free command index */
3233 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3234 TRACE(("GDT: No free command index found\n"));
3235 return 0;
3236 }
3237
3238 /* if it's the first command, set command semaphore */
3239 if (ha->cmd_cnt == 0)
3240 gdth_set_sema0(hanum);
3241
3242 /* evaluate command size, check space */
3243 if (cmdp->OpCode == GDT_IOCTL) {
3244 TRACE2(("IOCTL\n"));
3245 ha->cmd_len =
3246 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
3247 } else if (cmdp->Service == CACHESERVICE) {
3248 TRACE2(("cache command %d\n",cmdp->OpCode));
3249 if (ha->cache_feat & GDT_64BIT)
3250 ha->cmd_len =
3251 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
3252 else
3253 ha->cmd_len =
3254 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
3255 } else if (cmdp->Service == SCSIRAWSERVICE) {
3256 TRACE2(("raw command %d\n",cmdp->OpCode));
3257 if (ha->raw_feat & GDT_64BIT)
3258 ha->cmd_len =
3259 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
3260 else
3261 ha->cmd_len =
3262 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
3263 }
3264
3265 if (ha->cmd_len & 3)
3266 ha->cmd_len += (4 - (ha->cmd_len & 3));
3267
3268 if (ha->cmd_cnt > 0) {
3269 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3270 ha->ic_all_size) {
3271 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
3272 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3273 return 0;
3274 }
3275 }
3276
3277 /* copy command */
3278 gdth_copy_command(hanum);
3279 return cmd_index;
3280 }
3281
3282
3283 /* Controller event handling functions */
3284 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
3285 ushort idx, gdth_evt_data *evt)
3286 {
3287 gdth_evt_str *e;
3288 struct timeval tv;
3289
3290 /* no GDTH_LOCK_HA() ! */
3291 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
3292 if (source == 0) /* no source -> no event */
3293 return NULL;
3294
3295 if (ebuffer[elastidx].event_source == source &&
3296 ebuffer[elastidx].event_idx == idx &&
3297 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
3298 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
3299 (char *)&evt->eu, evt->size)) ||
3300 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
3301 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
3302 (char *)&evt->event_string)))) {
3303 e = &ebuffer[elastidx];
3304 do_gettimeofday(&tv);
3305 e->last_stamp = tv.tv_sec;
3306 ++e->same_count;
3307 } else {
3308 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
3309 ++elastidx;
3310 if (elastidx == MAX_EVENTS)
3311 elastidx = 0;
3312 if (elastidx == eoldidx) { /* reached mark ? */
3313 ++eoldidx;
3314 if (eoldidx == MAX_EVENTS)
3315 eoldidx = 0;
3316 }
3317 }
3318 e = &ebuffer[elastidx];
3319 e->event_source = source;
3320 e->event_idx = idx;
3321 do_gettimeofday(&tv);
3322 e->first_stamp = e->last_stamp = tv.tv_sec;
3323 e->same_count = 1;
3324 e->event_data = *evt;
3325 e->application = 0;
3326 }
3327 return e;
3328 }
3329
3330 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
3331 {
3332 gdth_evt_str *e;
3333 int eindex;
3334 ulong flags;
3335
3336 TRACE2(("gdth_read_event() handle %d\n", handle));
3337 spin_lock_irqsave(&ha->smp_lock, flags);
3338 if (handle == -1)
3339 eindex = eoldidx;
3340 else
3341 eindex = handle;
3342 estr->event_source = 0;
3343
3344 if (eindex >= MAX_EVENTS) {
3345 spin_unlock_irqrestore(&ha->smp_lock, flags);
3346 return eindex;
3347 }
3348 e = &ebuffer[eindex];
3349 if (e->event_source != 0) {
3350 if (eindex != elastidx) {
3351 if (++eindex == MAX_EVENTS)
3352 eindex = 0;
3353 } else {
3354 eindex = -1;
3355 }
3356 memcpy(estr, e, sizeof(gdth_evt_str));
3357 }
3358 spin_unlock_irqrestore(&ha->smp_lock, flags);
3359 return eindex;
3360 }
3361
3362 static void gdth_readapp_event(gdth_ha_str *ha,
3363 unchar application, gdth_evt_str *estr)
3364 {
3365 gdth_evt_str *e;
3366 int eindex;
3367 ulong flags;
3368 unchar found = FALSE;
3369
3370 TRACE2(("gdth_readapp_event() app. %d\n", application));
3371 spin_lock_irqsave(&ha->smp_lock, flags);
3372 eindex = eoldidx;
3373 for (;;) {
3374 e = &ebuffer[eindex];
3375 if (e->event_source == 0)
3376 break;
3377 if ((e->application & application) == 0) {
3378 e->application |= application;
3379 found = TRUE;
3380 break;
3381 }
3382 if (eindex == elastidx)
3383 break;
3384 if (++eindex == MAX_EVENTS)
3385 eindex = 0;
3386 }
3387 if (found)
3388 memcpy(estr, e, sizeof(gdth_evt_str));
3389 else
3390 estr->event_source = 0;
3391 spin_unlock_irqrestore(&ha->smp_lock, flags);
3392 }
3393
3394 static void gdth_clear_events(void)
3395 {
3396 TRACE(("gdth_clear_events()"));
3397
3398 eoldidx = elastidx = 0;
3399 ebuffer[0].event_source = 0;
3400 }
3401
3402
3403 /* SCSI interface functions */
3404
3405 static irqreturn_t gdth_interrupt(int irq,void *dev_id)
3406 {
3407 gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
3408 register gdth_ha_str *ha;
3409 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3410 gdt6_dpram_str __iomem *dp6_ptr;
3411 gdt2_dpram_str __iomem *dp2_ptr;
3412 Scsi_Cmnd *scp;
3413 int hanum, rval, i;
3414 unchar IStatus;
3415 ushort Service;
3416 ulong flags = 0;
3417 #ifdef INT_COAL
3418 int coalesced = FALSE;
3419 int next = FALSE;
3420 gdth_coal_status *pcs = NULL;
3421 int act_int_coal = 0;
3422 #endif
3423
3424 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3425
3426 /* if polling and not from gdth_wait() -> return */
3427 if (gdth_polling) {
3428 if (!gdth_from_wait) {
3429 return IRQ_HANDLED;
3430 }
3431 }
3432
3433 if (!gdth_polling)
3434 spin_lock_irqsave(&ha2->smp_lock, flags);
3435 wait_index = 0;
3436
3437 /* search controller */
3438 if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
3439 /* spurious interrupt */
3440 if (!gdth_polling)
3441 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3442 return IRQ_HANDLED;
3443 }
3444 ha = HADATA(gdth_ctr_tab[hanum]);
3445
3446 #ifdef GDTH_STATISTICS
3447 ++act_ints;
3448 #endif
3449
3450 #ifdef INT_COAL
3451 /* See if the fw is returning coalesced status */
3452 if (IStatus == COALINDEX) {
3453 /* Coalesced status. Setup the initial status
3454 buffer pointer and flags */
3455 pcs = ha->coal_stat;
3456 coalesced = TRUE;
3457 next = TRUE;
3458 }
3459
3460 do {
3461 if (coalesced) {
3462 /* For coalesced requests all status
3463 information is found in the status buffer */
3464 IStatus = (unchar)(pcs->status & 0xff);
3465 }
3466 #endif
3467
3468 if (ha->type == GDT_EISA) {
3469 if (IStatus & 0x80) { /* error flag */
3470 IStatus &= ~0x80;
3471 ha->status = inw(ha->bmic + MAILBOXREG+8);
3472 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3473 } else /* no error */
3474 ha->status = S_OK;
3475 ha->info = inl(ha->bmic + MAILBOXREG+12);
3476 ha->service = inw(ha->bmic + MAILBOXREG+10);
3477 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3478
3479 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3480 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3481 } else if (ha->type == GDT_ISA) {
3482 dp2_ptr = ha->brd;
3483 if (IStatus & 0x80) { /* error flag */
3484 IStatus &= ~0x80;
3485 ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
3486 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3487 } else /* no error */
3488 ha->status = S_OK;
3489 ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
3490 ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
3491 ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
3492
3493 gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3494 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3495 gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3496 } else if (ha->type == GDT_PCI) {
3497 dp6_ptr = ha->brd;
3498 if (IStatus & 0x80) { /* error flag */
3499 IStatus &= ~0x80;
3500 ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
3501 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3502 } else /* no error */
3503 ha->status = S_OK;
3504 ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
3505 ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
3506 ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
3507
3508 gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3509 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3510 gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3511 } else if (ha->type == GDT_PCINEW) {
3512 if (IStatus & 0x80) { /* error flag */
3513 IStatus &= ~0x80;
3514 ha->status = inw(PTR2USHORT(&ha->plx->status));
3515 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3516 } else
3517 ha->status = S_OK;
3518 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3519 ha->service = inw(PTR2USHORT(&ha->plx->service));
3520 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3521
3522 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3523 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3524 } else if (ha->type == GDT_PCIMPR) {
3525 dp6m_ptr = ha->brd;
3526 if (IStatus & 0x80) { /* error flag */
3527 IStatus &= ~0x80;
3528 #ifdef INT_COAL
3529 if (coalesced)
3530 ha->status = pcs->ext_status & 0xffff;
3531 else
3532 #endif
3533 ha->status = gdth_readw(&dp6m_ptr->i960r.status);
3534 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3535 } else /* no error */
3536 ha->status = S_OK;
3537 #ifdef INT_COAL
3538 /* get information */
3539 if (coalesced) {
3540 ha->info = pcs->info0;
3541 ha->info2 = pcs->info1;
3542 ha->service = (pcs->ext_status >> 16) & 0xffff;
3543 } else
3544 #endif
3545 {
3546 ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
3547 ha->service = gdth_readw(&dp6m_ptr->i960r.service);
3548 ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
3549 }
3550 /* event string */
3551 if (IStatus == ASYNCINDEX) {
3552 if (ha->service != SCREENSERVICE &&
3553 (ha->fw_vers & 0xff) >= 0x1a) {
3554 ha->dvr.severity = gdth_readb
3555 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3556 for (i = 0; i < 256; ++i) {
3557 ha->dvr.event_string[i] = gdth_readb
3558 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3559 if (ha->dvr.event_string[i] == 0)
3560 break;
3561 }
3562 }
3563 }
3564 #ifdef INT_COAL
3565 /* Make sure that non coalesced interrupts get cleared
3566 before being handled by gdth_async_event/gdth_sync_event */
3567 if (!coalesced)
3568 #endif
3569 {
3570 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3571 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3572 }
3573 } else {
3574 TRACE2(("gdth_interrupt() unknown controller type\n"));
3575 if (!gdth_polling)
3576 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3577 return IRQ_HANDLED;
3578 }
3579
3580 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3581 IStatus,ha->status,ha->info));
3582
3583 if (gdth_from_wait) {
3584 wait_hanum = hanum;
3585 wait_index = (int)IStatus;
3586 }
3587
3588 if (IStatus == ASYNCINDEX) {
3589 TRACE2(("gdth_interrupt() async. event\n"));
3590 gdth_async_event(hanum);
3591 if (!gdth_polling)
3592 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3593 gdth_next(hanum);
3594 return IRQ_HANDLED;
3595 }
3596
3597 if (IStatus == SPEZINDEX) {
3598 TRACE2(("Service unknown or not initialized !\n"));
3599 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3600 ha->dvr.eu.driver.ionode = hanum;
3601 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3602 if (!gdth_polling)
3603 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3604 return IRQ_HANDLED;
3605 }
3606 scp = ha->cmd_tab[IStatus-2].cmnd;
3607 Service = ha->cmd_tab[IStatus-2].service;
3608 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3609 if (scp == UNUSED_CMND) {
3610 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3611 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3612 ha->dvr.eu.driver.ionode = hanum;
3613 ha->dvr.eu.driver.index = IStatus;
3614 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3615 if (!gdth_polling)
3616 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3617 return IRQ_HANDLED;
3618 }
3619 if (scp == INTERNAL_CMND) {
3620 TRACE(("gdth_interrupt() answer to internal command\n"));
3621 if (!gdth_polling)
3622 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3623 return IRQ_HANDLED;
3624 }
3625
3626 TRACE(("gdth_interrupt() sync. status\n"));
3627 rval = gdth_sync_event(hanum,Service,IStatus,scp);
3628 if (!gdth_polling)
3629 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3630 if (rval == 2) {
3631 gdth_putq(hanum,scp,scp->SCp.this_residual);
3632 } else if (rval == 1) {
3633 scp->scsi_done(scp);
3634 }
3635
3636 #ifdef INT_COAL
3637 if (coalesced) {
3638 /* go to the next status in the status buffer */
3639 ++pcs;
3640 #ifdef GDTH_STATISTICS
3641 ++act_int_coal;
3642 if (act_int_coal > max_int_coal) {
3643 max_int_coal = act_int_coal;
3644 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3645 }
3646 #endif
3647 /* see if there is another status */
3648 if (pcs->status == 0)
3649 /* Stop the coalesce loop */
3650 next = FALSE;
3651 }
3652 } while (next);
3653
3654 /* coalescing only for new GDT_PCIMPR controllers available */
3655 if (ha->type == GDT_PCIMPR && coalesced) {
3656 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3657 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3658 }
3659 #endif
3660
3661 gdth_next(hanum);
3662 return IRQ_HANDLED;
3663 }
3664
3665 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
3666 {
3667 register gdth_ha_str *ha;
3668 gdth_msg_str *msg;
3669 gdth_cmd_str *cmdp;
3670 unchar b, t;
3671
3672 ha = HADATA(gdth_ctr_tab[hanum]);
3673 cmdp = ha->pccb;
3674 TRACE(("gdth_sync_event() serv %d status %d\n",
3675 service,ha->status));
3676
3677 if (service == SCREENSERVICE) {
3678 msg = ha->pmsg;
3679 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3680 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3681 if (msg->msg_len > MSGLEN+1)
3682 msg->msg_len = MSGLEN+1;
3683 if (msg->msg_len)
3684 if (!(msg->msg_answer && msg->msg_ext)) {
3685 msg->msg_text[msg->msg_len] = '\0';
3686 printk("%s",msg->msg_text);
3687 }
3688
3689 if (msg->msg_ext && !msg->msg_answer) {
3690 while (gdth_test_busy(hanum))
3691 gdth_delay(0);
3692 cmdp->Service = SCREENSERVICE;
3693 cmdp->RequestBuffer = SCREEN_CMND;
3694 gdth_get_cmd_index(hanum);
3695 gdth_set_sema0(hanum);
3696 cmdp->OpCode = GDT_READ;
3697 cmdp->BoardNode = LOCALBOARD;
3698 cmdp->u.screen.reserved = 0;
3699 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3700 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3701 ha->cmd_offs_dpmem = 0;
3702 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3703 + sizeof(ulong64);
3704 ha->cmd_cnt = 0;
3705 gdth_copy_command(hanum);
3706 gdth_release_event(hanum);
3707 return 0;
3708 }
3709
3710 if (msg->msg_answer && msg->msg_alen) {
3711 /* default answers (getchar() not possible) */
3712 if (msg->msg_alen == 1) {
3713 msg->msg_alen = 0;
3714 msg->msg_len = 1;
3715 msg->msg_text[0] = 0;
3716 } else {
3717 msg->msg_alen -= 2;
3718 msg->msg_len = 2;
3719 msg->msg_text[0] = 1;
3720 msg->msg_text[1] = 0;
3721 }
3722 msg->msg_ext = 0;
3723 msg->msg_answer = 0;
3724 while (gdth_test_busy(hanum))
3725 gdth_delay(0);
3726 cmdp->Service = SCREENSERVICE;
3727 cmdp->RequestBuffer = SCREEN_CMND;
3728 gdth_get_cmd_index(hanum);
3729 gdth_set_sema0(hanum);
3730 cmdp->OpCode = GDT_WRITE;
3731 cmdp->BoardNode = LOCALBOARD;
3732 cmdp->u.screen.reserved = 0;
3733 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3734 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3735 ha->cmd_offs_dpmem = 0;
3736 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3737 + sizeof(ulong64);
3738 ha->cmd_cnt = 0;
3739 gdth_copy_command(hanum);
3740 gdth_release_event(hanum);
3741 return 0;
3742 }
3743 printk("\n");
3744
3745 } else {
3746 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
3747 t = scp->device->id;
3748 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3749 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3750 }
3751 /* cache or raw service */
3752 if (ha->status == S_BSY) {
3753 TRACE2(("Controller busy -> retry !\n"));
3754 if (scp->SCp.sent_command == GDT_MOUNT)
3755 scp->SCp.sent_command = GDT_CLUST_INFO;
3756 /* retry */
3757 return 2;
3758 }
3759 if (scp->SCp.Status == GDTH_MAP_SG)
3760 pci_unmap_sg(ha->pdev,scp->request_buffer,
3761 scp->use_sg,scp->SCp.Message);
3762 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3763 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3764 scp->request_bufflen,scp->SCp.Message);
3765 if (scp->SCp.buffer) {
3766 dma_addr_t addr;
3767 addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
3768 if (scp->host_scribble)
3769 addr += (dma_addr_t)
3770 ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
3771 pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
3772 }
3773
3774 if (ha->status == S_OK) {
3775 scp->SCp.Status = S_OK;
3776 scp->SCp.Message = ha->info;
3777 if (scp->SCp.sent_command != -1) {
3778 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3779 scp->SCp.sent_command));
3780 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3781 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3782 ha->hdr[t].cluster_type = (unchar)ha->info;
3783 if (!(ha->hdr[t].cluster_type &
3784 CLUSTER_MOUNTED)) {
3785 /* NOT MOUNTED -> MOUNT */
3786 scp->SCp.sent_command = GDT_MOUNT;
3787 if (ha->hdr[t].cluster_type &
3788 CLUSTER_RESERVED) {
3789 /* cluster drive RESERVED (on the other node) */
3790 scp->SCp.phase = -2; /* reservation conflict */
3791 }
3792 } else {
3793 scp->SCp.sent_command = -1;
3794 }
3795 } else {
3796 if (scp->SCp.sent_command == GDT_MOUNT) {
3797 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3798 ha->hdr[t].media_changed = TRUE;
3799 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3800 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3801 ha->hdr[t].media_changed = TRUE;
3802 }
3803 scp->SCp.sent_command = -1;
3804 }
3805 /* retry */
3806 scp->SCp.this_residual = HIGH_PRI;
3807 return 2;
3808 } else {
3809 /* RESERVE/RELEASE ? */
3810 if (scp->cmnd[0] == RESERVE) {
3811 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3812 } else if (scp->cmnd[0] == RELEASE) {
3813 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3814 }
3815 scp->result = DID_OK << 16;
3816 scp->sense_buffer[0] = 0;
3817 }
3818 } else {
3819 scp->SCp.Status = ha->status;
3820 scp->SCp.Message = ha->info;
3821
3822 if (scp->SCp.sent_command != -1) {
3823 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3824 scp->SCp.sent_command, ha->status));
3825 if (scp->SCp.sent_command == GDT_SCAN_START ||
3826 scp->SCp.sent_command == GDT_SCAN_END) {
3827 scp->SCp.sent_command = -1;
3828 /* retry */
3829 scp->SCp.this_residual = HIGH_PRI;
3830 return 2;
3831 }
3832 memset((char*)scp->sense_buffer,0,16);
3833 scp->sense_buffer[0] = 0x70;
3834 scp->sense_buffer[2] = NOT_READY;
3835 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3836 } else if (service == CACHESERVICE) {
3837 if (ha->status == S_CACHE_UNKNOWN &&
3838 (ha->hdr[t].cluster_type &
3839 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3840 /* bus reset -> force GDT_CLUST_INFO */
3841 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3842 }
3843 memset((char*)scp->sense_buffer,0,16);
3844 if (ha->status == (ushort)S_CACHE_RESERV) {
3845 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3846 } else {
3847 scp->sense_buffer[0] = 0x70;
3848 scp->sense_buffer[2] = NOT_READY;
3849 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3850 }
3851 if (scp->done != gdth_scsi_done) {
3852 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3853 ha->dvr.eu.sync.ionode = hanum;
3854 ha->dvr.eu.sync.service = service;
3855 ha->dvr.eu.sync.status = ha->status;
3856 ha->dvr.eu.sync.info = ha->info;
3857 ha->dvr.eu.sync.hostdrive = t;
3858 if (ha->status >= 0x8000)
3859 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3860 else
3861 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3862 }
3863 } else {
3864 /* sense buffer filled from controller firmware (DMA) */
3865 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3866 scp->result = DID_BAD_TARGET << 16;
3867 } else {
3868 scp->result = (DID_OK << 16) | ha->info;
3869 }
3870 }
3871 }
3872 if (!scp->SCp.have_data_in)
3873 scp->SCp.have_data_in++;
3874 else
3875 return 1;
3876 }
3877
3878 return 0;
3879 }
3880
3881 static char *async_cache_tab[] = {
3882 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3883 "GDT HA %u, service %u, async. status %u/%lu unknown",
3884 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3885 "GDT HA %u, service %u, async. status %u/%lu unknown",
3886 /* 2*/ "\005\000\002\006\004"
3887 "GDT HA %u, Host Drive %lu not ready",
3888 /* 3*/ "\005\000\002\006\004"
3889 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3890 /* 4*/ "\005\000\002\006\004"
3891 "GDT HA %u, mirror update on Host Drive %lu failed",
3892 /* 5*/ "\005\000\002\006\004"
3893 "GDT HA %u, Mirror Drive %lu failed",
3894 /* 6*/ "\005\000\002\006\004"
3895 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3896 /* 7*/ "\005\000\002\006\004"
3897 "GDT HA %u, Host Drive %lu write protected",
3898 /* 8*/ "\005\000\002\006\004"
3899 "GDT HA %u, media changed in Host Drive %lu",
3900 /* 9*/ "\005\000\002\006\004"
3901 "GDT HA %u, Host Drive %lu is offline",
3902 /*10*/ "\005\000\002\006\004"
3903 "GDT HA %u, media change of Mirror Drive %lu",
3904 /*11*/ "\005\000\002\006\004"
3905 "GDT HA %u, Mirror Drive %lu is write protected",
3906 /*12*/ "\005\000\002\006\004"
3907 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3908 /*13*/ "\007\000\002\006\002\010\002"
3909 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3910 /*14*/ "\005\000\002\006\002"
3911 "GDT HA %u, Array Drive %u: FAIL state entered",
3912 /*15*/ "\005\000\002\006\002"
3913 "GDT HA %u, Array Drive %u: error",
3914 /*16*/ "\007\000\002\006\002\010\002"
3915 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3916 /*17*/ "\005\000\002\006\002"
3917 "GDT HA %u, Array Drive %u: parity build failed",
3918 /*18*/ "\005\000\002\006\002"
3919 "GDT HA %u, Array Drive %u: drive rebuild failed",
3920 /*19*/ "\005\000\002\010\002"
3921 "GDT HA %u, Test of Hot Fix %u failed",
3922 /*20*/ "\005\000\002\006\002"
3923 "GDT HA %u, Array Drive %u: drive build finished successfully",
3924 /*21*/ "\005\000\002\006\002"
3925 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3926 /*22*/ "\007\000\002\006\002\010\002"
3927 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3928 /*23*/ "\005\000\002\006\002"
3929 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3930 /*24*/ "\005\000\002\010\002"
3931 "GDT HA %u, mirror update on Cache Drive %u completed",
3932 /*25*/ "\005\000\002\010\002"
3933 "GDT HA %u, mirror update on Cache Drive %lu failed",
3934 /*26*/ "\005\000\002\006\002"
3935 "GDT HA %u, Array Drive %u: drive rebuild started",
3936 /*27*/ "\005\000\002\012\001"
3937 "GDT HA %u, Fault bus %u: SHELF OK detected",
3938 /*28*/ "\005\000\002\012\001"
3939 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3940 /*29*/ "\007\000\002\012\001\013\001"
3941 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3942 /*30*/ "\007\000\002\012\001\013\001"
3943 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3944 /*31*/ "\007\000\002\012\001\013\001"
3945 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3946 /*32*/ "\007\000\002\012\001\013\001"
3947 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3948 /*33*/ "\007\000\002\012\001\013\001"
3949 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3950 /*34*/ "\011\000\002\012\001\013\001\006\004"
3951 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3952 /*35*/ "\007\000\002\012\001\013\001"
3953 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3954 /*36*/ "\007\000\002\012\001\013\001"
3955 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3956 /*37*/ "\007\000\002\012\001\006\004"
3957 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3958 /*38*/ "\007\000\002\012\001\013\001"
3959 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3960 /*39*/ "\007\000\002\012\001\013\001"
3961 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3962 /*40*/ "\007\000\002\012\001\013\001"
3963 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3964 /*41*/ "\007\000\002\012\001\013\001"
3965 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3966 /*42*/ "\005\000\002\006\002"
3967 "GDT HA %u, Array Drive %u: drive build started",
3968 /*43*/ "\003\000\002"
3969 "GDT HA %u, DRAM parity error detected",
3970 /*44*/ "\005\000\002\006\002"
3971 "GDT HA %u, Mirror Drive %u: update started",
3972 /*45*/ "\007\000\002\006\002\010\002"
3973 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3974 /*46*/ "\005\000\002\006\002"
3975 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3976 /*47*/ "\005\000\002\006\002"
3977 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3978 /*48*/ "\005\000\002\006\002"
3979 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3980 /*49*/ "\005\000\002\006\002"
3981 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3982 /*50*/ "\007\000\002\012\001\013\001"
3983 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3984 /*51*/ "\005\000\002\006\002"
3985 "GDT HA %u, Array Drive %u: expand started",
3986 /*52*/ "\005\000\002\006\002"
3987 "GDT HA %u, Array Drive %u: expand finished successfully",
3988 /*53*/ "\005\000\002\006\002"
3989 "GDT HA %u, Array Drive %u: expand failed",
3990 /*54*/ "\003\000\002"
3991 "GDT HA %u, CPU temperature critical",
3992 /*55*/ "\003\000\002"
3993 "GDT HA %u, CPU temperature OK",
3994 /*56*/ "\005\000\002\006\004"
3995 "GDT HA %u, Host drive %lu created",
3996 /*57*/ "\005\000\002\006\002"
3997 "GDT HA %u, Array Drive %u: expand restarted",
3998 /*58*/ "\005\000\002\006\002"
3999 "GDT HA %u, Array Drive %u: expand stopped",
4000 /*59*/ "\005\000\002\010\002"
4001 "GDT HA %u, Mirror Drive %u: drive build quited",
4002 /*60*/ "\005\000\002\006\002"
4003 "GDT HA %u, Array Drive %u: parity build quited",
4004 /*61*/ "\005\000\002\006\002"
4005 "GDT HA %u, Array Drive %u: drive rebuild quited",
4006 /*62*/ "\005\000\002\006\002"
4007 "GDT HA %u, Array Drive %u: parity verify started",
4008 /*63*/ "\005\000\002\006\002"
4009 "GDT HA %u, Array Drive %u: parity verify done",
4010 /*64*/ "\005\000\002\006\002"
4011 "GDT HA %u, Array Drive %u: parity verify failed",
4012 /*65*/ "\005\000\002\006\002"
4013 "GDT HA %u, Array Drive %u: parity error detected",
4014 /*66*/ "\005\000\002\006\002"
4015 "GDT HA %u, Array Drive %u: parity verify quited",
4016 /*67*/ "\005\000\002\006\002"
4017 "GDT HA %u, Host Drive %u reserved",
4018 /*68*/ "\005\000\002\006\002"
4019 "GDT HA %u, Host Drive %u mounted and released",
4020 /*69*/ "\005\000\002\006\002"
4021 "GDT HA %u, Host Drive %u released",
4022 /*70*/ "\003\000\002"
4023 "GDT HA %u, DRAM error detected and corrected with ECC",
4024 /*71*/ "\003\000\002"
4025 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
4026 /*72*/ "\011\000\002\012\001\013\001\014\001"
4027 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
4028 /*73*/ "\005\000\002\006\002"
4029 "GDT HA %u, Host drive %u resetted locally",
4030 /*74*/ "\005\000\002\006\002"
4031 "GDT HA %u, Host drive %u resetted remotely",
4032 /*75*/ "\003\000\002"
4033 "GDT HA %u, async. status 75 unknown",
4034 };
4035
4036
4037 static int gdth_async_event(int hanum)
4038 {
4039 gdth_ha_str *ha;
4040 gdth_cmd_str *cmdp;
4041 int cmd_index;
4042
4043 ha = HADATA(gdth_ctr_tab[hanum]);
4044 cmdp= ha->pccb;
4045 TRACE2(("gdth_async_event() ha %d serv %d\n",
4046 hanum,ha->service));
4047
4048 if (ha->service == SCREENSERVICE) {
4049 if (ha->status == MSG_REQUEST) {
4050 while (gdth_test_busy(hanum))
4051 gdth_delay(0);
4052 cmdp->Service = SCREENSERVICE;
4053 cmdp->RequestBuffer = SCREEN_CMND;
4054 cmd_index = gdth_get_cmd_index(hanum);
4055 gdth_set_sema0(hanum);
4056 cmdp->OpCode = GDT_READ;
4057 cmdp->BoardNode = LOCALBOARD;
4058 cmdp->u.screen.reserved = 0;
4059 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
4060 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
4061 ha->cmd_offs_dpmem = 0;
4062 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
4063 + sizeof(ulong64);
4064 ha->cmd_cnt = 0;
4065 gdth_copy_command(hanum);
4066 if (ha->type == GDT_EISA)
4067 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
4068 else if (ha->type == GDT_ISA)
4069 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
4070 else
4071 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
4072 (ushort)((ha->brd_phys>>3)&0x1f));
4073 gdth_release_event(hanum);
4074 }
4075
4076 } else {
4077 if (ha->type == GDT_PCIMPR &&
4078 (ha->fw_vers & 0xff) >= 0x1a) {
4079 ha->dvr.size = 0;
4080 ha->dvr.eu.async.ionode = hanum;
4081 ha->dvr.eu.async.status = ha->status;
4082 /* severity and event_string already set! */
4083 } else {
4084 ha->dvr.size = sizeof(ha->dvr.eu.async);
4085 ha->dvr.eu.async.ionode = hanum;
4086 ha->dvr.eu.async.service = ha->service;
4087 ha->dvr.eu.async.status = ha->status;
4088 ha->dvr.eu.async.info = ha->info;
4089 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
4090 }
4091 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
4092 gdth_log_event( &ha->dvr, NULL );
4093
4094 /* new host drive from expand? */
4095 if (ha->service == CACHESERVICE && ha->status == 56) {
4096 TRACE2(("gdth_async_event(): new host drive %d created\n",
4097 (ushort)ha->info));
4098 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
4099 }
4100 }
4101 return 1;
4102 }
4103
4104 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
4105 {
4106 gdth_stackframe stack;
4107 char *f = NULL;
4108 int i,j;
4109
4110 TRACE2(("gdth_log_event()\n"));
4111 if (dvr->size == 0) {
4112 if (buffer == NULL) {
4113 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
4114 } else {
4115 sprintf(buffer,"Adapter %d: %s\n",
4116 dvr->eu.async.ionode,dvr->event_string);
4117 }
4118 } else if (dvr->eu.async.service == CACHESERVICE &&
4119 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
4120 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
4121 dvr->eu.async.status));
4122
4123 f = async_cache_tab[dvr->eu.async.status];
4124
4125 /* i: parameter to push, j: stack element to fill */
4126 for (j=0,i=1; i < f[0]; i+=2) {
4127 switch (f[i+1]) {
4128 case 4:
4129 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
4130 break;
4131 case 2:
4132 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
4133 break;
4134 case 1:
4135 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
4136 break;
4137 default:
4138 break;
4139 }
4140 }
4141
4142 if (buffer == NULL) {
4143 printk(&f[(int)f[0]],stack);
4144 printk("\n");
4145 } else {
4146 sprintf(buffer,&f[(int)f[0]],stack);
4147 }
4148
4149 } else {
4150 if (buffer == NULL) {
4151 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
4152 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4153 } else {
4154 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
4155 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4156 }
4157 }
4158 }
4159
4160 #ifdef GDTH_STATISTICS
4161 static void gdth_timeout(ulong data)
4162 {
4163 ulong32 i;
4164 Scsi_Cmnd *nscp;
4165 gdth_ha_str *ha;
4166 ulong flags;
4167 int hanum = 0;
4168
4169 ha = HADATA(gdth_ctr_tab[hanum]);
4170 spin_lock_irqsave(&ha->smp_lock, flags);
4171
4172 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
4173 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
4174 ++act_stats;
4175
4176 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
4177 ++act_rq;
4178
4179 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
4180 act_ints, act_ios, act_stats, act_rq));
4181 act_ints = act_ios = 0;
4182
4183 gdth_timer.expires = jiffies + 30 * HZ;
4184 add_timer(&gdth_timer);
4185 spin_unlock_irqrestore(&ha->smp_lock, flags);
4186 }
4187 #endif
4188
4189 static void __init internal_setup(char *str,int *ints)
4190 {
4191 int i, argc;
4192 char *cur_str, *argv;
4193
4194 TRACE2(("internal_setup() str %s ints[0] %d\n",
4195 str ? str:"NULL", ints ? ints[0]:0));
4196
4197 /* read irq[] from ints[] */
4198 if (ints) {
4199 argc = ints[0];
4200 if (argc > 0) {
4201 if (argc > MAXHA)
4202 argc = MAXHA;
4203 for (i = 0; i < argc; ++i)
4204 irq[i] = ints[i+1];
4205 }
4206 }
4207
4208 /* analyse string */
4209 argv = str;
4210 while (argv && (cur_str = strchr(argv, ':'))) {
4211 int val = 0, c = *++cur_str;
4212
4213 if (c == 'n' || c == 'N')
4214 val = 0;
4215 else if (c == 'y' || c == 'Y')
4216 val = 1;
4217 else
4218 val = (int)simple_strtoul(cur_str, NULL, 0);
4219
4220 if (!strncmp(argv, "disable:", 8))
4221 disable = val;
4222 else if (!strncmp(argv, "reserve_mode:", 13))
4223 reserve_mode = val;
4224 else if (!strncmp(argv, "reverse_scan:", 13))
4225 reverse_scan = val;
4226 else if (!strncmp(argv, "hdr_channel:", 12))
4227 hdr_channel = val;
4228 else if (!strncmp(argv, "max_ids:", 8))
4229 max_ids = val;
4230 else if (!strncmp(argv, "rescan:", 7))
4231 rescan = val;
4232 else if (!strncmp(argv, "virt_ctr:", 9))
4233 virt_ctr = val;
4234 else if (!strncmp(argv, "shared_access:", 14))
4235 shared_access = val;
4236 else if (!strncmp(argv, "probe_eisa_isa:", 15))
4237 probe_eisa_isa = val;
4238 else if (!strncmp(argv, "reserve_list:", 13)) {
4239 reserve_list[0] = val;
4240 for (i = 1; i < MAX_RES_ARGS; i++) {
4241 cur_str = strchr(cur_str, ',');
4242 if (!cur_str)
4243 break;
4244 if (!isdigit((int)*++cur_str)) {
4245 --cur_str;
4246 break;
4247 }
4248 reserve_list[i] =
4249 (int)simple_strtoul(cur_str, NULL, 0);
4250 }
4251 if (!cur_str)
4252 break;
4253 argv = ++cur_str;
4254 continue;
4255 }
4256
4257 if ((argv = strchr(argv, ',')))
4258 ++argv;
4259 }
4260 }
4261
4262 int __init option_setup(char *str)
4263 {
4264 int ints[MAXHA];
4265 char *cur = str;
4266 int i = 1;
4267
4268 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
4269
4270 while (cur && isdigit(*cur) && i <= MAXHA) {
4271 ints[i++] = simple_strtoul(cur, NULL, 0);
4272 if ((cur = strchr(cur, ',')) != NULL) cur++;
4273 }
4274
4275 ints[0] = i - 1;
4276 internal_setup(cur, ints);
4277 return 1;
4278 }
4279
4280 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4281 static int __init gdth_detect(struct scsi_host_template *shtp)
4282 #else
4283 static int __init gdth_detect(Scsi_Host_Template *shtp)
4284 #endif
4285 {
4286 struct Scsi_Host *shp;
4287 gdth_pci_str pcistr[MAXHA];
4288 gdth_ha_str *ha;
4289 ulong32 isa_bios;
4290 ushort eisa_slot;
4291 int i,hanum,cnt,ctr,err;
4292 unchar b;
4293
4294
4295 #ifdef DEBUG_GDTH
4296 printk("GDT: This driver contains debugging information !! Trace level = %d\n",
4297 DebugState);
4298 printk(" Destination of debugging information: ");
4299 #ifdef __SERIAL__
4300 #ifdef __COM2__
4301 printk("Serial port COM2\n");
4302 #else
4303 printk("Serial port COM1\n");
4304 #endif
4305 #else
4306 printk("Console\n");
4307 #endif
4308 gdth_delay(3000);
4309 #endif
4310
4311 TRACE(("gdth_detect()\n"));
4312
4313 if (disable) {
4314 printk("GDT-HA: Controller driver disabled from command line !\n");
4315 return 0;
4316 }
4317
4318 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
4319 /* initializations */
4320 gdth_polling = TRUE; b = 0;
4321 gdth_clear_events();
4322
4323 /* As default we do not probe for EISA or ISA controllers */
4324 if (probe_eisa_isa) {
4325 /* scanning for controllers, at first: ISA controller */
4326 for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
4327 dma_addr_t scratch_dma_handle;
4328 scratch_dma_handle = 0;
4329
4330 if (gdth_ctr_count >= MAXHA)
4331 break;
4332 if (gdth_search_isa(isa_bios)) { /* controller found */
4333 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4334 if (shp == NULL)
4335 continue;
4336
4337 ha = HADATA(shp);
4338 if (!gdth_init_isa(isa_bios,ha)) {
4339 scsi_unregister(shp);
4340 continue;
4341 }
4342 #ifdef __ia64__
4343 break;
4344 #else
4345 /* controller found and initialized */
4346 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4347 isa_bios,ha->irq,ha->drq);
4348
4349 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
4350 printk("GDT-ISA: Unable to allocate IRQ\n");
4351 scsi_unregister(shp);
4352 continue;
4353 }
4354 if (request_dma(ha->drq,"gdth")) {
4355 printk("GDT-ISA: Unable to allocate DMA channel\n");
4356 free_irq(ha->irq,ha);
4357 scsi_unregister(shp);
4358 continue;
4359 }
4360 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4361 enable_dma(ha->drq);
4362 shp->unchecked_isa_dma = 1;
4363 shp->irq = ha->irq;
4364 shp->dma_channel = ha->drq;
4365 hanum = gdth_ctr_count;
4366 gdth_ctr_tab[gdth_ctr_count++] = shp;
4367 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4368
4369 NUMDATA(shp)->hanum = (ushort)hanum;
4370 NUMDATA(shp)->busnum= 0;
4371
4372 ha->pccb = CMDDATA(shp);
4373 ha->ccb_phys = 0L;
4374 ha->pdev = NULL;
4375 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4376 &scratch_dma_handle);
4377 ha->scratch_phys = scratch_dma_handle;
4378 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4379 &scratch_dma_handle);
4380 ha->msg_phys = scratch_dma_handle;
4381 #ifdef INT_COAL
4382 ha->coal_stat = (gdth_coal_status *)
4383 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4384 MAXOFFSETS, &scratch_dma_handle);
4385 ha->coal_stat_phys = scratch_dma_handle;
4386 #endif
4387
4388 ha->scratch_busy = FALSE;
4389 ha->req_first = NULL;
4390 ha->tid_cnt = MAX_HDRIVES;
4391 if (max_ids > 0 && max_ids < ha->tid_cnt)
4392 ha->tid_cnt = max_ids;
4393 for (i=0; i<GDTH_MAXCMDS; ++i)
4394 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4395 ha->scan_mode = rescan ? 0x10 : 0;
4396
4397 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4398 !gdth_search_drives(hanum)) {
4399 printk("GDT-ISA: Error during device scan\n");
4400 --gdth_ctr_count;
4401 --gdth_ctr_vcount;
4402
4403 #ifdef INT_COAL
4404 if (ha->coal_stat)
4405 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4406 MAXOFFSETS, ha->coal_stat,
4407 ha->coal_stat_phys);
4408 #endif
4409 if (ha->pscratch)
4410 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4411 ha->pscratch, ha->scratch_phys);
4412 if (ha->pmsg)
4413 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4414 ha->pmsg, ha->msg_phys);
4415
4416 free_irq(ha->irq,ha);
4417 scsi_unregister(shp);
4418 continue;
4419 }
4420 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4421 hdr_channel = ha->bus_cnt;
4422 ha->virt_bus = hdr_channel;
4423
4424 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4425 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4426 shp->highmem_io = 0;
4427 #endif
4428 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4429 shp->max_cmd_len = 16;
4430
4431 shp->max_id = ha->tid_cnt;
4432 shp->max_lun = MAXLUN;
4433 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4434 if (virt_ctr) {
4435 virt_ctr = 1;
4436 /* register addit. SCSI channels as virtual controllers */
4437 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4438 shp = scsi_register(shtp,sizeof(gdth_num_str));
4439 shp->unchecked_isa_dma = 1;
4440 shp->irq = ha->irq;
4441 shp->dma_channel = ha->drq;
4442 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4443 NUMDATA(shp)->hanum = (ushort)hanum;
4444 NUMDATA(shp)->busnum = b;
4445 }
4446 }
4447
4448 spin_lock_init(&ha->smp_lock);
4449 gdth_enable_int(hanum);
4450 #endif /* !__ia64__ */
4451 }
4452 }
4453
4454 /* scanning for EISA controllers */
4455 for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
4456 dma_addr_t scratch_dma_handle;
4457 scratch_dma_handle = 0;
4458
4459 if (gdth_ctr_count >= MAXHA)
4460 break;
4461 if (gdth_search_eisa(eisa_slot)) { /* controller found */
4462 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4463 if (shp == NULL)
4464 continue;
4465
4466 ha = HADATA(shp);
4467 if (!gdth_init_eisa(eisa_slot,ha)) {
4468 scsi_unregister(shp);
4469 continue;
4470 }
4471 /* controller found and initialized */
4472 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4473 eisa_slot>>12,ha->irq);
4474
4475 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
4476 printk("GDT-EISA: Unable to allocate IRQ\n");
4477 scsi_unregister(shp);
4478 continue;
4479 }
4480 shp->unchecked_isa_dma = 0;
4481 shp->irq = ha->irq;
4482 shp->dma_channel = 0xff;
4483 hanum = gdth_ctr_count;
4484 gdth_ctr_tab[gdth_ctr_count++] = shp;
4485 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4486
4487 NUMDATA(shp)->hanum = (ushort)hanum;
4488 NUMDATA(shp)->busnum= 0;
4489 TRACE2(("EISA detect Bus 0: hanum %d\n",
4490 NUMDATA(shp)->hanum));
4491
4492 ha->pccb = CMDDATA(shp);
4493 ha->ccb_phys = 0L;
4494
4495 ha->pdev = NULL;
4496 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4497 &scratch_dma_handle);
4498 ha->scratch_phys = scratch_dma_handle;
4499 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4500 &scratch_dma_handle);
4501 ha->msg_phys = scratch_dma_handle;
4502 #ifdef INT_COAL
4503 ha->coal_stat = (gdth_coal_status *)
4504 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4505 MAXOFFSETS, &scratch_dma_handle);
4506 ha->coal_stat_phys = scratch_dma_handle;
4507 #endif
4508 ha->ccb_phys =
4509 pci_map_single(ha->pdev,ha->pccb,
4510 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4511 ha->scratch_busy = FALSE;
4512 ha->req_first = NULL;
4513 ha->tid_cnt = MAX_HDRIVES;
4514 if (max_ids > 0 && max_ids < ha->tid_cnt)
4515 ha->tid_cnt = max_ids;
4516 for (i=0; i<GDTH_MAXCMDS; ++i)
4517 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4518 ha->scan_mode = rescan ? 0x10 : 0;
4519
4520 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4521 !gdth_search_drives(hanum)) {
4522 printk("GDT-EISA: Error during device scan\n");
4523 --gdth_ctr_count;
4524 --gdth_ctr_vcount;
4525 #ifdef INT_COAL
4526 if (ha->coal_stat)
4527 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4528 MAXOFFSETS, ha->coal_stat,
4529 ha->coal_stat_phys);
4530 #endif
4531 if (ha->pscratch)
4532 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4533 ha->pscratch, ha->scratch_phys);
4534 if (ha->pmsg)
4535 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4536 ha->pmsg, ha->msg_phys);
4537 if (ha->ccb_phys)
4538 pci_unmap_single(ha->pdev,ha->ccb_phys,
4539 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4540 free_irq(ha->irq,ha);
4541 scsi_unregister(shp);
4542 continue;
4543 }
4544 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4545 hdr_channel = ha->bus_cnt;
4546 ha->virt_bus = hdr_channel;
4547
4548 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4549 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4550 shp->highmem_io = 0;
4551 #endif
4552 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4553 shp->max_cmd_len = 16;
4554
4555 shp->max_id = ha->tid_cnt;
4556 shp->max_lun = MAXLUN;
4557 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4558 if (virt_ctr) {
4559 virt_ctr = 1;
4560 /* register addit. SCSI channels as virtual controllers */
4561 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4562 shp = scsi_register(shtp,sizeof(gdth_num_str));
4563 shp->unchecked_isa_dma = 0;
4564 shp->irq = ha->irq;
4565 shp->dma_channel = 0xff;
4566 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4567 NUMDATA(shp)->hanum = (ushort)hanum;
4568 NUMDATA(shp)->busnum = b;
4569 }
4570 }
4571
4572 spin_lock_init(&ha->smp_lock);
4573 gdth_enable_int(hanum);
4574 }
4575 }
4576 }
4577
4578 /* scanning for PCI controllers */
4579 cnt = gdth_search_pci(pcistr);
4580 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
4581 gdth_sort_pci(pcistr,cnt);
4582 for (ctr = 0; ctr < cnt; ++ctr) {
4583 dma_addr_t scratch_dma_handle;
4584 scratch_dma_handle = 0;
4585
4586 if (gdth_ctr_count >= MAXHA)
4587 break;
4588 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4589 if (shp == NULL)
4590 continue;
4591
4592 ha = HADATA(shp);
4593 if (!gdth_init_pci(&pcistr[ctr],ha)) {
4594 scsi_unregister(shp);
4595 continue;
4596 }
4597 /* controller found and initialized */
4598 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4599 pcistr[ctr].pdev->bus->number,
4600 PCI_SLOT(pcistr[ctr].pdev->devfn), ha->irq);
4601
4602 if (request_irq(ha->irq, gdth_interrupt,
4603 IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
4604 {
4605 printk("GDT-PCI: Unable to allocate IRQ\n");
4606 scsi_unregister(shp);
4607 continue;
4608 }
4609 shp->unchecked_isa_dma = 0;
4610 shp->irq = ha->irq;
4611 shp->dma_channel = 0xff;
4612 hanum = gdth_ctr_count;
4613 gdth_ctr_tab[gdth_ctr_count++] = shp;
4614 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4615
4616 NUMDATA(shp)->hanum = (ushort)hanum;
4617 NUMDATA(shp)->busnum= 0;
4618
4619 ha->pccb = CMDDATA(shp);
4620 ha->ccb_phys = 0L;
4621
4622 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4623 &scratch_dma_handle);
4624 ha->scratch_phys = scratch_dma_handle;
4625 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4626 &scratch_dma_handle);
4627 ha->msg_phys = scratch_dma_handle;
4628 #ifdef INT_COAL
4629 ha->coal_stat = (gdth_coal_status *)
4630 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4631 MAXOFFSETS, &scratch_dma_handle);
4632 ha->coal_stat_phys = scratch_dma_handle;
4633 #endif
4634 ha->scratch_busy = FALSE;
4635 ha->req_first = NULL;
4636 ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
4637 if (max_ids > 0 && max_ids < ha->tid_cnt)
4638 ha->tid_cnt = max_ids;
4639 for (i=0; i<GDTH_MAXCMDS; ++i)
4640 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4641 ha->scan_mode = rescan ? 0x10 : 0;
4642
4643 err = FALSE;
4644 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4645 !gdth_search_drives(hanum)) {
4646 err = TRUE;
4647 } else {
4648 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4649 hdr_channel = ha->bus_cnt;
4650 ha->virt_bus = hdr_channel;
4651
4652
4653 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4654 scsi_set_pci_device(shp, pcistr[ctr].pdev);
4655 #endif
4656 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
4657 /* 64-bit DMA only supported from FW >= x.43 */
4658 (!ha->dma64_support)) {
4659 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
4660 printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
4661 err = TRUE;
4662 }
4663 } else {
4664 shp->max_cmd_len = 16;
4665 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
4666 printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
4667 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
4668 printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
4669 err = TRUE;
4670 }
4671 }
4672 }
4673
4674 if (err) {
4675 printk("GDT-PCI %d: Error during device scan\n", hanum);
4676 --gdth_ctr_count;
4677 --gdth_ctr_vcount;
4678 #ifdef INT_COAL
4679 if (ha->coal_stat)
4680 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4681 MAXOFFSETS, ha->coal_stat,
4682 ha->coal_stat_phys);
4683 #endif
4684 if (ha->pscratch)
4685 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4686 ha->pscratch, ha->scratch_phys);
4687 if (ha->pmsg)
4688 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4689 ha->pmsg, ha->msg_phys);
4690 free_irq(ha->irq,ha);
4691 scsi_unregister(shp);
4692 continue;
4693 }
4694
4695 shp->max_id = ha->tid_cnt;
4696 shp->max_lun = MAXLUN;
4697 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4698 if (virt_ctr) {
4699 virt_ctr = 1;
4700 /* register addit. SCSI channels as virtual controllers */
4701 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4702 shp = scsi_register(shtp,sizeof(gdth_num_str));
4703 shp->unchecked_isa_dma = 0;
4704 shp->irq = ha->irq;
4705 shp->dma_channel = 0xff;
4706 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4707 NUMDATA(shp)->hanum = (ushort)hanum;
4708 NUMDATA(shp)->busnum = b;
4709 }
4710 }
4711
4712 spin_lock_init(&ha->smp_lock);
4713 gdth_enable_int(hanum);
4714 }
4715
4716 TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
4717 if (gdth_ctr_count > 0) {
4718 #ifdef GDTH_STATISTICS
4719 TRACE2(("gdth_detect(): Initializing timer !\n"));
4720 init_timer(&gdth_timer);
4721 gdth_timer.expires = jiffies + HZ;
4722 gdth_timer.data = 0L;
4723 gdth_timer.function = gdth_timeout;
4724 add_timer(&gdth_timer);
4725 #endif
4726 major = register_chrdev(0,"gdth",&gdth_fops);
4727 notifier_disabled = 0;
4728 register_reboot_notifier(&gdth_notifier);
4729 }
4730 gdth_polling = FALSE;
4731 return gdth_ctr_vcount;
4732 }
4733
4734 static int gdth_release(struct Scsi_Host *shp)
4735 {
4736 int hanum;
4737 gdth_ha_str *ha;
4738
4739 TRACE2(("gdth_release()\n"));
4740 if (NUMDATA(shp)->busnum == 0) {
4741 hanum = NUMDATA(shp)->hanum;
4742 ha = HADATA(gdth_ctr_tab[hanum]);
4743 if (ha->sdev) {
4744 scsi_free_host_dev(ha->sdev);
4745 ha->sdev = NULL;
4746 }
4747 gdth_flush(hanum);
4748
4749 if (shp->irq) {
4750 free_irq(shp->irq,ha);
4751 }
4752 #ifndef __ia64__
4753 if (shp->dma_channel != 0xff) {
4754 free_dma(shp->dma_channel);
4755 }
4756 #endif
4757 #ifdef INT_COAL
4758 if (ha->coal_stat)
4759 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4760 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
4761 #endif
4762 if (ha->pscratch)
4763 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4764 ha->pscratch, ha->scratch_phys);
4765 if (ha->pmsg)
4766 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4767 ha->pmsg, ha->msg_phys);
4768 if (ha->ccb_phys)
4769 pci_unmap_single(ha->pdev,ha->ccb_phys,
4770 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4771 gdth_ctr_released++;
4772 TRACE2(("gdth_release(): HA %d of %d\n",
4773 gdth_ctr_released, gdth_ctr_count));
4774
4775 if (gdth_ctr_released == gdth_ctr_count) {
4776 #ifdef GDTH_STATISTICS
4777 del_timer(&gdth_timer);
4778 #endif
4779 unregister_chrdev(major,"gdth");
4780 unregister_reboot_notifier(&gdth_notifier);
4781 }
4782 }
4783
4784 scsi_unregister(shp);
4785 return 0;
4786 }
4787
4788
4789 static const char *gdth_ctr_name(int hanum)
4790 {
4791 gdth_ha_str *ha;
4792
4793 TRACE2(("gdth_ctr_name()\n"));
4794
4795 ha = HADATA(gdth_ctr_tab[hanum]);
4796
4797 if (ha->type == GDT_EISA) {
4798 switch (ha->stype) {
4799 case GDT3_ID:
4800 return("GDT3000/3020");
4801 case GDT3A_ID:
4802 return("GDT3000A/3020A/3050A");
4803 case GDT3B_ID:
4804 return("GDT3000B/3010A");
4805 }
4806 } else if (ha->type == GDT_ISA) {
4807 return("GDT2000/2020");
4808 } else if (ha->type == GDT_PCI) {
4809 switch (ha->pdev->device) {
4810 case PCI_DEVICE_ID_VORTEX_GDT60x0:
4811 return("GDT6000/6020/6050");
4812 case PCI_DEVICE_ID_VORTEX_GDT6000B:
4813 return("GDT6000B/6010");
4814 }
4815 }
4816 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
4817
4818 return("");
4819 }
4820
4821 static const char *gdth_info(struct Scsi_Host *shp)
4822 {
4823 int hanum;
4824 gdth_ha_str *ha;
4825
4826 TRACE2(("gdth_info()\n"));
4827 hanum = NUMDATA(shp)->hanum;
4828 ha = HADATA(gdth_ctr_tab[hanum]);
4829
4830 return ((const char *)ha->binfo.type_string);
4831 }
4832
4833 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
4834 {
4835 int i, hanum;
4836 gdth_ha_str *ha;
4837 ulong flags;
4838 Scsi_Cmnd *cmnd;
4839 unchar b;
4840
4841 TRACE2(("gdth_eh_bus_reset()\n"));
4842
4843 hanum = NUMDATA(scp->device->host)->hanum;
4844 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
4845 ha = HADATA(gdth_ctr_tab[hanum]);
4846
4847 /* clear command tab */
4848 spin_lock_irqsave(&ha->smp_lock, flags);
4849 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4850 cmnd = ha->cmd_tab[i].cmnd;
4851 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4852 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4853 }
4854 spin_unlock_irqrestore(&ha->smp_lock, flags);
4855
4856 if (b == ha->virt_bus) {
4857 /* host drives */
4858 for (i = 0; i < MAX_HDRIVES; ++i) {
4859 if (ha->hdr[i].present) {
4860 spin_lock_irqsave(&ha->smp_lock, flags);
4861 gdth_polling = TRUE;
4862 while (gdth_test_busy(hanum))
4863 gdth_delay(0);
4864 if (gdth_internal_cmd(hanum, CACHESERVICE,
4865 GDT_CLUST_RESET, i, 0, 0))
4866 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4867 gdth_polling = FALSE;
4868 spin_unlock_irqrestore(&ha->smp_lock, flags);
4869 }
4870 }
4871 } else {
4872 /* raw devices */
4873 spin_lock_irqsave(&ha->smp_lock, flags);
4874 for (i = 0; i < MAXID; ++i)
4875 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4876 gdth_polling = TRUE;
4877 while (gdth_test_busy(hanum))
4878 gdth_delay(0);
4879 gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
4880 BUS_L2P(ha,b), 0, 0);
4881 gdth_polling = FALSE;
4882 spin_unlock_irqrestore(&ha->smp_lock, flags);
4883 }
4884 return SUCCESS;
4885 }
4886
4887 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4888 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
4889 #else
4890 static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
4891 #endif
4892 {
4893 unchar b, t;
4894 int hanum;
4895 gdth_ha_str *ha;
4896 struct scsi_device *sd;
4897 unsigned capacity;
4898
4899 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4900 sd = sdev;
4901 capacity = cap;
4902 #else
4903 sd = disk->device;
4904 capacity = disk->capacity;
4905 #endif
4906 hanum = NUMDATA(sd->host)->hanum;
4907 b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
4908 t = sd->id;
4909 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
4910 ha = HADATA(gdth_ctr_tab[hanum]);
4911
4912 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4913 /* raw device or host drive without mapping information */
4914 TRACE2(("Evaluate mapping\n"));
4915 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4916 } else {
4917 ip[0] = ha->hdr[t].heads;
4918 ip[1] = ha->hdr[t].secs;
4919 ip[2] = capacity / ip[0] / ip[1];
4920 }
4921
4922 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4923 ip[0],ip[1],ip[2]));
4924 return 0;
4925 }
4926
4927
4928 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
4929 {
4930 int hanum;
4931 int priority;
4932
4933 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4934
4935 scp->scsi_done = (void *)done;
4936 scp->SCp.have_data_in = 1;
4937 scp->SCp.phase = -1;
4938 scp->SCp.sent_command = -1;
4939 scp->SCp.Status = GDTH_MAP_NONE;
4940 scp->SCp.buffer = (struct scatterlist *)NULL;
4941
4942 hanum = NUMDATA(scp->device->host)->hanum;
4943 #ifdef GDTH_STATISTICS
4944 ++act_ios;
4945 #endif
4946
4947 priority = DEFAULT_PRI;
4948 if (scp->done == gdth_scsi_done)
4949 priority = scp->SCp.this_residual;
4950 else
4951 gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
4952
4953 gdth_putq( hanum, scp, priority );
4954 gdth_next( hanum );
4955 return 0;
4956 }
4957
4958
4959 static int gdth_open(struct inode *inode, struct file *filep)
4960 {
4961 gdth_ha_str *ha;
4962 int i;
4963
4964 for (i = 0; i < gdth_ctr_count; i++) {
4965 ha = HADATA(gdth_ctr_tab[i]);
4966 if (!ha->sdev)
4967 ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
4968 }
4969
4970 TRACE(("gdth_open()\n"));
4971 return 0;
4972 }
4973
4974 static int gdth_close(struct inode *inode, struct file *filep)
4975 {
4976 TRACE(("gdth_close()\n"));
4977 return 0;
4978 }
4979
4980 static int ioc_event(void __user *arg)
4981 {
4982 gdth_ioctl_event evt;
4983 gdth_ha_str *ha;
4984 ulong flags;
4985
4986 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
4987 evt.ionode >= gdth_ctr_count)
4988 return -EFAULT;
4989 ha = HADATA(gdth_ctr_tab[evt.ionode]);
4990
4991 if (evt.erase == 0xff) {
4992 if (evt.event.event_source == ES_TEST)
4993 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4994 else if (evt.event.event_source == ES_DRIVER)
4995 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4996 else if (evt.event.event_source == ES_SYNC)
4997 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4998 else
4999 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
5000 spin_lock_irqsave(&ha->smp_lock, flags);
5001 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
5002 &evt.event.event_data);
5003 spin_unlock_irqrestore(&ha->smp_lock, flags);
5004 } else if (evt.erase == 0xfe) {
5005 gdth_clear_events();
5006 } else if (evt.erase == 0) {
5007 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
5008 } else {
5009 gdth_readapp_event(ha, evt.erase, &evt.event);
5010 }
5011 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
5012 return -EFAULT;
5013 return 0;
5014 }
5015
5016 static int ioc_lockdrv(void __user *arg)
5017 {
5018 gdth_ioctl_lockdrv ldrv;
5019 unchar i, j;
5020 ulong flags;
5021 gdth_ha_str *ha;
5022
5023 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
5024 ldrv.ionode >= gdth_ctr_count)
5025 return -EFAULT;
5026 ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
5027
5028 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
5029 j = ldrv.drives[i];
5030 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
5031 continue;
5032 if (ldrv.lock) {
5033 spin_lock_irqsave(&ha->smp_lock, flags);
5034 ha->hdr[j].lock = 1;
5035 spin_unlock_irqrestore(&ha->smp_lock, flags);
5036 gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
5037 gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
5038 } else {
5039 spin_lock_irqsave(&ha->smp_lock, flags);
5040 ha->hdr[j].lock = 0;
5041 spin_unlock_irqrestore(&ha->smp_lock, flags);
5042 gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
5043 gdth_next(ldrv.ionode);
5044 }
5045 }
5046 return 0;
5047 }
5048
5049 static int ioc_resetdrv(void __user *arg, char *cmnd)
5050 {
5051 gdth_ioctl_reset res;
5052 gdth_cmd_str cmd;
5053 int hanum;
5054 gdth_ha_str *ha;
5055 int rval;
5056
5057 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
5058 res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
5059 return -EFAULT;
5060 hanum = res.ionode;
5061 ha = HADATA(gdth_ctr_tab[hanum]);
5062
5063 if (!ha->hdr[res.number].present)
5064 return 0;
5065 memset(&cmd, 0, sizeof(gdth_cmd_str));
5066 cmd.Service = CACHESERVICE;
5067 cmd.OpCode = GDT_CLUST_RESET;
5068 if (ha->cache_feat & GDT_64BIT)
5069 cmd.u.cache64.DeviceNo = res.number;
5070 else
5071 cmd.u.cache.DeviceNo = res.number;
5072
5073 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
5074 if (rval < 0)
5075 return rval;
5076 res.status = rval;
5077
5078 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
5079 return -EFAULT;
5080 return 0;
5081 }
5082
5083 static int ioc_general(void __user *arg, char *cmnd)
5084 {
5085 gdth_ioctl_general gen;
5086 char *buf = NULL;
5087 ulong64 paddr;
5088 int hanum;
5089 gdth_ha_str *ha;
5090 int rval;
5091
5092 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
5093 gen.ionode >= gdth_ctr_count)
5094 return -EFAULT;
5095 hanum = gen.ionode;
5096 ha = HADATA(gdth_ctr_tab[hanum]);
5097 if (gen.data_len + gen.sense_len != 0) {
5098 if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
5099 FALSE, &paddr)))
5100 return -EFAULT;
5101 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
5102 gen.data_len + gen.sense_len)) {
5103 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5104 return -EFAULT;
5105 }
5106
5107 if (gen.command.OpCode == GDT_IOCTL) {
5108 gen.command.u.ioctl.p_param = paddr;
5109 } else if (gen.command.Service == CACHESERVICE) {
5110 if (ha->cache_feat & GDT_64BIT) {
5111 /* copy elements from 32-bit IOCTL structure */
5112 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
5113 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
5114 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
5115 /* addresses */
5116 if (ha->cache_feat & SCATTER_GATHER) {
5117 gen.command.u.cache64.DestAddr = (ulong64)-1;
5118 gen.command.u.cache64.sg_canz = 1;
5119 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
5120 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
5121 gen.command.u.cache64.sg_lst[1].sg_len = 0;
5122 } else {
5123 gen.command.u.cache64.DestAddr = paddr;
5124 gen.command.u.cache64.sg_canz = 0;
5125 }
5126 } else {
5127 if (ha->cache_feat & SCATTER_GATHER) {
5128 gen.command.u.cache.DestAddr = 0xffffffff;
5129 gen.command.u.cache.sg_canz = 1;
5130 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
5131 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
5132 gen.command.u.cache.sg_lst[1].sg_len = 0;
5133 } else {
5134 gen.command.u.cache.DestAddr = paddr;
5135 gen.command.u.cache.sg_canz = 0;
5136 }
5137 }
5138 } else if (gen.command.Service == SCSIRAWSERVICE) {
5139 if (ha->raw_feat & GDT_64BIT) {
5140 /* copy elements from 32-bit IOCTL structure */
5141 char cmd[16];
5142 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
5143 gen.command.u.raw64.bus = gen.command.u.raw.bus;
5144 gen.command.u.raw64.lun = gen.command.u.raw.lun;
5145 gen.command.u.raw64.target = gen.command.u.raw.target;
5146 memcpy(cmd, gen.command.u.raw.cmd, 16);
5147 memcpy(gen.command.u.raw64.cmd, cmd, 16);
5148 gen.command.u.raw64.clen = gen.command.u.raw.clen;
5149 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
5150 gen.command.u.raw64.direction = gen.command.u.raw.direction;
5151 /* addresses */
5152 if (ha->raw_feat & SCATTER_GATHER) {
5153 gen.command.u.raw64.sdata = (ulong64)-1;
5154 gen.command.u.raw64.sg_ranz = 1;
5155 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
5156 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
5157 gen.command.u.raw64.sg_lst[1].sg_len = 0;
5158 } else {
5159 gen.command.u.raw64.sdata = paddr;
5160 gen.command.u.raw64.sg_ranz = 0;
5161 }
5162 gen.command.u.raw64.sense_data = paddr + gen.data_len;
5163 } else {
5164 if (ha->raw_feat & SCATTER_GATHER) {
5165 gen.command.u.raw.sdata = 0xffffffff;
5166 gen.command.u.raw.sg_ranz = 1;
5167 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
5168 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
5169 gen.command.u.raw.sg_lst[1].sg_len = 0;
5170 } else {
5171 gen.command.u.raw.sdata = paddr;
5172 gen.command.u.raw.sg_ranz = 0;
5173 }
5174 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
5175 }
5176 } else {
5177 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5178 return -EFAULT;
5179 }
5180 }
5181
5182 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
5183 if (rval < 0)
5184 return rval;
5185 gen.status = rval;
5186
5187 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
5188 gen.data_len + gen.sense_len)) {
5189 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5190 return -EFAULT;
5191 }
5192 if (copy_to_user(arg, &gen,
5193 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
5194 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5195 return -EFAULT;
5196 }
5197 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5198 return 0;
5199 }
5200
5201 static int ioc_hdrlist(void __user *arg, char *cmnd)
5202 {
5203 gdth_ioctl_rescan *rsc;
5204 gdth_cmd_str *cmd;
5205 gdth_ha_str *ha;
5206 unchar i;
5207 int hanum, rc = -ENOMEM;
5208 u32 cluster_type = 0;
5209
5210 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5211 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5212 if (!rsc || !cmd)
5213 goto free_fail;
5214
5215 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5216 rsc->ionode >= gdth_ctr_count) {
5217 rc = -EFAULT;
5218 goto free_fail;
5219 }
5220 hanum = rsc->ionode;
5221 ha = HADATA(gdth_ctr_tab[hanum]);
5222 memset(cmd, 0, sizeof(gdth_cmd_str));
5223
5224 for (i = 0; i < MAX_HDRIVES; ++i) {
5225 if (!ha->hdr[i].present) {
5226 rsc->hdr_list[i].bus = 0xff;
5227 continue;
5228 }
5229 rsc->hdr_list[i].bus = ha->virt_bus;
5230 rsc->hdr_list[i].target = i;
5231 rsc->hdr_list[i].lun = 0;
5232 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5233 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
5234 cmd->Service = CACHESERVICE;
5235 cmd->OpCode = GDT_CLUST_INFO;
5236 if (ha->cache_feat & GDT_64BIT)
5237 cmd->u.cache64.DeviceNo = i;
5238 else
5239 cmd->u.cache.DeviceNo = i;
5240 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
5241 rsc->hdr_list[i].cluster_type = cluster_type;
5242 }
5243 }
5244
5245 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5246 rc = -EFAULT;
5247 else
5248 rc = 0;
5249
5250 free_fail:
5251 kfree(rsc);
5252 kfree(cmd);
5253 return rc;
5254 }
5255
5256 static int ioc_rescan(void __user *arg, char *cmnd)
5257 {
5258 gdth_ioctl_rescan *rsc;
5259 gdth_cmd_str *cmd;
5260 ushort i, status, hdr_cnt;
5261 ulong32 info;
5262 int hanum, cyls, hds, secs;
5263 int rc = -ENOMEM;
5264 ulong flags;
5265 gdth_ha_str *ha;
5266
5267 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5268 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5269 if (!cmd || !rsc)
5270 goto free_fail;
5271
5272 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5273 rsc->ionode >= gdth_ctr_count) {
5274 rc = -EFAULT;
5275 goto free_fail;
5276 }
5277 hanum = rsc->ionode;
5278 ha = HADATA(gdth_ctr_tab[hanum]);
5279 memset(cmd, 0, sizeof(gdth_cmd_str));
5280
5281 if (rsc->flag == 0) {
5282 /* old method: re-init. cache service */
5283 cmd->Service = CACHESERVICE;
5284 if (ha->cache_feat & GDT_64BIT) {
5285 cmd->OpCode = GDT_X_INIT_HOST;
5286 cmd->u.cache64.DeviceNo = LINUX_OS;
5287 } else {
5288 cmd->OpCode = GDT_INIT;
5289 cmd->u.cache.DeviceNo = LINUX_OS;
5290 }
5291
5292 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5293 i = 0;
5294 hdr_cnt = (status == S_OK ? (ushort)info : 0);
5295 } else {
5296 i = rsc->hdr_no;
5297 hdr_cnt = i + 1;
5298 }
5299
5300 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
5301 cmd->Service = CACHESERVICE;
5302 cmd->OpCode = GDT_INFO;
5303 if (ha->cache_feat & GDT_64BIT)
5304 cmd->u.cache64.DeviceNo = i;
5305 else
5306 cmd->u.cache.DeviceNo = i;
5307
5308 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5309
5310 spin_lock_irqsave(&ha->smp_lock, flags);
5311 rsc->hdr_list[i].bus = ha->virt_bus;
5312 rsc->hdr_list[i].target = i;
5313 rsc->hdr_list[i].lun = 0;
5314 if (status != S_OK) {
5315 ha->hdr[i].present = FALSE;
5316 } else {
5317 ha->hdr[i].present = TRUE;
5318 ha->hdr[i].size = info;
5319 /* evaluate mapping */
5320 ha->hdr[i].size &= ~SECS32;
5321 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
5322 ha->hdr[i].heads = hds;
5323 ha->hdr[i].secs = secs;
5324 /* round size */
5325 ha->hdr[i].size = cyls * hds * secs;
5326 }
5327 spin_unlock_irqrestore(&ha->smp_lock, flags);
5328 if (status != S_OK)
5329 continue;
5330
5331 /* extended info, if GDT_64BIT, for drives > 2 TB */
5332 /* but we need ha->info2, not yet stored in scp->SCp */
5333
5334 /* devtype, cluster info, R/W attribs */
5335 cmd->Service = CACHESERVICE;
5336 cmd->OpCode = GDT_DEVTYPE;
5337 if (ha->cache_feat & GDT_64BIT)
5338 cmd->u.cache64.DeviceNo = i;
5339 else
5340 cmd->u.cache.DeviceNo = i;
5341
5342 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5343
5344 spin_lock_irqsave(&ha->smp_lock, flags);
5345 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
5346 spin_unlock_irqrestore(&ha->smp_lock, flags);
5347
5348 cmd->Service = CACHESERVICE;
5349 cmd->OpCode = GDT_CLUST_INFO;
5350 if (ha->cache_feat & GDT_64BIT)
5351 cmd->u.cache64.DeviceNo = i;
5352 else
5353 cmd->u.cache.DeviceNo = i;
5354
5355 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5356
5357 spin_lock_irqsave(&ha->smp_lock, flags);
5358 ha->hdr[i].cluster_type =
5359 ((status == S_OK && !shared_access) ? (ushort)info : 0);
5360 spin_unlock_irqrestore(&ha->smp_lock, flags);
5361 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5362
5363 cmd->Service = CACHESERVICE;
5364 cmd->OpCode = GDT_RW_ATTRIBS;
5365 if (ha->cache_feat & GDT_64BIT)
5366 cmd->u.cache64.DeviceNo = i;
5367 else
5368 cmd->u.cache.DeviceNo = i;
5369
5370 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5371
5372 spin_lock_irqsave(&ha->smp_lock, flags);
5373 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
5374 spin_unlock_irqrestore(&ha->smp_lock, flags);
5375 }
5376
5377 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5378 rc = -EFAULT;
5379 else
5380 rc = 0;
5381
5382 free_fail:
5383 kfree(rsc);
5384 kfree(cmd);
5385 return rc;
5386 }
5387
5388 static int gdth_ioctl(struct inode *inode, struct file *filep,
5389 unsigned int cmd, unsigned long arg)
5390 {
5391 gdth_ha_str *ha;
5392 Scsi_Cmnd *scp;
5393 ulong flags;
5394 char cmnd[MAX_COMMAND_SIZE];
5395 void __user *argp = (void __user *)arg;
5396
5397 memset(cmnd, 0xff, 12);
5398
5399 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
5400
5401 switch (cmd) {
5402 case GDTIOCTL_CTRCNT:
5403 {
5404 int cnt = gdth_ctr_count;
5405 if (put_user(cnt, (int __user *)argp))
5406 return -EFAULT;
5407 break;
5408 }
5409
5410 case GDTIOCTL_DRVERS:
5411 {
5412 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
5413 if (put_user(ver, (int __user *)argp))
5414 return -EFAULT;
5415 break;
5416 }
5417
5418 case GDTIOCTL_OSVERS:
5419 {
5420 gdth_ioctl_osvers osv;
5421
5422 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
5423 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
5424 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
5425 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
5426 return -EFAULT;
5427 break;
5428 }
5429
5430 case GDTIOCTL_CTRTYPE:
5431 {
5432 gdth_ioctl_ctrtype ctrt;
5433
5434 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
5435 ctrt.ionode >= gdth_ctr_count)
5436 return -EFAULT;
5437 ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
5438 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
5439 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
5440 } else {
5441 if (ha->type != GDT_PCIMPR) {
5442 ctrt.type = (unchar)((ha->stype<<4) + 6);
5443 } else {
5444 ctrt.type =
5445 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
5446 if (ha->stype >= 0x300)
5447 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
5448 else
5449 ctrt.ext_type = 0x6000 | ha->stype;
5450 }
5451 ctrt.device_id = ha->pdev->device;
5452 ctrt.sub_device_id = ha->pdev->subsystem_device;
5453 }
5454 ctrt.info = ha->brd_phys;
5455 ctrt.oem_id = ha->oem_id;
5456 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
5457 return -EFAULT;
5458 break;
5459 }
5460
5461 case GDTIOCTL_GENERAL:
5462 return ioc_general(argp, cmnd);
5463
5464 case GDTIOCTL_EVENT:
5465 return ioc_event(argp);
5466
5467 case GDTIOCTL_LOCKDRV:
5468 return ioc_lockdrv(argp);
5469
5470 case GDTIOCTL_LOCKCHN:
5471 {
5472 gdth_ioctl_lockchn lchn;
5473 unchar i, j;
5474
5475 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
5476 lchn.ionode >= gdth_ctr_count)
5477 return -EFAULT;
5478 ha = HADATA(gdth_ctr_tab[lchn.ionode]);
5479
5480 i = lchn.channel;
5481 if (i < ha->bus_cnt) {
5482 if (lchn.lock) {
5483 spin_lock_irqsave(&ha->smp_lock, flags);
5484 ha->raw[i].lock = 1;
5485 spin_unlock_irqrestore(&ha->smp_lock, flags);
5486 for (j = 0; j < ha->tid_cnt; ++j) {
5487 gdth_wait_completion(lchn.ionode, i, j);
5488 gdth_stop_timeout(lchn.ionode, i, j);
5489 }
5490 } else {
5491 spin_lock_irqsave(&ha->smp_lock, flags);
5492 ha->raw[i].lock = 0;
5493 spin_unlock_irqrestore(&ha->smp_lock, flags);
5494 for (j = 0; j < ha->tid_cnt; ++j) {
5495 gdth_start_timeout(lchn.ionode, i, j);
5496 gdth_next(lchn.ionode);
5497 }
5498 }
5499 }
5500 break;
5501 }
5502
5503 case GDTIOCTL_RESCAN:
5504 return ioc_rescan(argp, cmnd);
5505
5506 case GDTIOCTL_HDRLIST:
5507 return ioc_hdrlist(argp, cmnd);
5508
5509 case GDTIOCTL_RESET_BUS:
5510 {
5511 gdth_ioctl_reset res;
5512 int hanum, rval;
5513
5514 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
5515 res.ionode >= gdth_ctr_count)
5516 return -EFAULT;
5517 hanum = res.ionode;
5518 ha = HADATA(gdth_ctr_tab[hanum]);
5519
5520 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5521 scp = kmalloc(sizeof(*scp), GFP_KERNEL);
5522 if (!scp)
5523 return -ENOMEM;
5524 memset(scp, 0, sizeof(*scp));
5525 scp->device = ha->sdev;
5526 scp->cmd_len = 12;
5527 scp->use_sg = 0;
5528 scp->device->channel = virt_ctr ? 0 : res.number;
5529 rval = gdth_eh_bus_reset(scp);
5530 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5531 kfree(scp);
5532 #else
5533 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5534 if (!scp)
5535 return -ENOMEM;
5536 scp->cmd_len = 12;
5537 scp->use_sg = 0;
5538 scp->channel = virt_ctr ? 0 : res.number;
5539 rval = gdth_eh_bus_reset(scp);
5540 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5541 scsi_release_command(scp);
5542 #endif
5543 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
5544 return -EFAULT;
5545 break;
5546 }
5547
5548 case GDTIOCTL_RESET_DRV:
5549 return ioc_resetdrv(argp, cmnd);
5550
5551 default:
5552 break;
5553 }
5554 return 0;
5555 }
5556
5557
5558 /* flush routine */
5559 static void gdth_flush(int hanum)
5560 {
5561 int i;
5562 gdth_ha_str *ha;
5563 gdth_cmd_str gdtcmd;
5564 char cmnd[MAX_COMMAND_SIZE];
5565 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5566
5567 TRACE2(("gdth_flush() hanum %d\n",hanum));
5568 ha = HADATA(gdth_ctr_tab[hanum]);
5569
5570 for (i = 0; i < MAX_HDRIVES; ++i) {
5571 if (ha->hdr[i].present) {
5572 gdtcmd.BoardNode = LOCALBOARD;
5573 gdtcmd.Service = CACHESERVICE;
5574 gdtcmd.OpCode = GDT_FLUSH;
5575 if (ha->cache_feat & GDT_64BIT) {
5576 gdtcmd.u.cache64.DeviceNo = i;
5577 gdtcmd.u.cache64.BlockNo = 1;
5578 gdtcmd.u.cache64.sg_canz = 0;
5579 } else {
5580 gdtcmd.u.cache.DeviceNo = i;
5581 gdtcmd.u.cache.BlockNo = 1;
5582 gdtcmd.u.cache.sg_canz = 0;
5583 }
5584 TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
5585
5586 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
5587 }
5588 }
5589 }
5590
5591 /* shutdown routine */
5592 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5593 {
5594 int hanum;
5595 #ifndef __alpha__
5596 gdth_cmd_str gdtcmd;
5597 char cmnd[MAX_COMMAND_SIZE];
5598 #endif
5599
5600 if (notifier_disabled)
5601 return NOTIFY_OK;
5602
5603 TRACE2(("gdth_halt() event %d\n",(int)event));
5604 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5605 return NOTIFY_DONE;
5606
5607 notifier_disabled = 1;
5608 printk("GDT-HA: Flushing all host drives .. ");
5609 for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
5610 gdth_flush(hanum);
5611
5612 #ifndef __alpha__
5613 /* controller reset */
5614 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5615 gdtcmd.BoardNode = LOCALBOARD;
5616 gdtcmd.Service = CACHESERVICE;
5617 gdtcmd.OpCode = GDT_RESET;
5618 TRACE2(("gdth_halt(): reset controller %d\n", hanum));
5619 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
5620 #endif
5621 }
5622 printk("Done.\n");
5623
5624 #ifdef GDTH_STATISTICS
5625 del_timer(&gdth_timer);
5626 #endif
5627 return NOTIFY_OK;
5628 }
5629
5630 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5631 /* configure lun */
5632 static int gdth_slave_configure(struct scsi_device *sdev)
5633 {
5634 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
5635 sdev->skip_ms_page_3f = 1;
5636 sdev->skip_ms_page_8 = 1;
5637 return 0;
5638 }
5639 #endif
5640
5641 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5642 static struct scsi_host_template driver_template = {
5643 #else
5644 static Scsi_Host_Template driver_template = {
5645 #endif
5646 .proc_name = "gdth",
5647 .proc_info = gdth_proc_info,
5648 .name = "GDT SCSI Disk Array Controller",
5649 .detect = gdth_detect,
5650 .release = gdth_release,
5651 .info = gdth_info,
5652 .queuecommand = gdth_queuecommand,
5653 .eh_bus_reset_handler = gdth_eh_bus_reset,
5654 .bios_param = gdth_bios_param,
5655 .can_queue = GDTH_MAXCMDS,
5656 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5657 .slave_configure = gdth_slave_configure,
5658 #endif
5659 .this_id = -1,
5660 .sg_tablesize = GDTH_MAXSG,
5661 .cmd_per_lun = GDTH_MAXC_P_L,
5662 .unchecked_isa_dma = 1,
5663 .use_clustering = ENABLE_CLUSTERING,
5664 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
5665 .use_new_eh_code = 1,
5666 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
5667 .highmem_io = 1,
5668 #endif
5669 #endif
5670 };
5671
5672 #include "scsi_module.c"
5673 #ifndef MODULE
5674 __setup("gdth=", option_setup);
5675 #endif
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