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hfsplus: use get/put_unaligned_* helpers
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / char / synclink.c
blobfadab1d9510fe513a49ac038763da0464b8f1fa0
1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #if defined(__i386__)
57 # define BREAKPOINT() asm(" int $3");
58 #else
59 # define BREAKPOINT() { }
60 #endif
61
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
65
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
81 #include <linux/mm.h>
82 #include <linux/slab.h>
83 #include <linux/delay.h>
84 #include <linux/netdevice.h>
85 #include <linux/vmalloc.h>
86 #include <linux/init.h>
87 #include <linux/ioctl.h>
88 #include <linux/synclink.h>
89
90 #include <asm/system.h>
91 #include <asm/io.h>
92 #include <asm/irq.h>
93 #include <asm/dma.h>
94 #include <linux/bitops.h>
95 #include <asm/types.h>
96 #include <linux/termios.h>
97 #include <linux/workqueue.h>
98 #include <linux/hdlc.h>
99 #include <linux/dma-mapping.h>
100
101 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
102 #define SYNCLINK_GENERIC_HDLC 1
103 #else
104 #define SYNCLINK_GENERIC_HDLC 0
105 #endif
106
107 #define GET_USER(error,value,addr) error = get_user(value,addr)
108 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
109 #define PUT_USER(error,value,addr) error = put_user(value,addr)
110 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
111
112 #include <asm/uaccess.h>
113
114 #define RCLRVALUE 0xffff
115
116 static MGSL_PARAMS default_params = {
117 MGSL_MODE_HDLC, /* unsigned long mode */
118 0, /* unsigned char loopback; */
119 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
120 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
121 0, /* unsigned long clock_speed; */
122 0xff, /* unsigned char addr_filter; */
123 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
124 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
125 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
126 9600, /* unsigned long data_rate; */
127 8, /* unsigned char data_bits; */
128 1, /* unsigned char stop_bits; */
129 ASYNC_PARITY_NONE /* unsigned char parity; */
130 };
131
132 #define SHARED_MEM_ADDRESS_SIZE 0x40000
133 #define BUFFERLISTSIZE 4096
134 #define DMABUFFERSIZE 4096
135 #define MAXRXFRAMES 7
136
137 typedef struct _DMABUFFERENTRY
138 {
139 u32 phys_addr; /* 32-bit flat physical address of data buffer */
140 volatile u16 count; /* buffer size/data count */
141 volatile u16 status; /* Control/status field */
142 volatile u16 rcc; /* character count field */
143 u16 reserved; /* padding required by 16C32 */
144 u32 link; /* 32-bit flat link to next buffer entry */
145 char *virt_addr; /* virtual address of data buffer */
146 u32 phys_entry; /* physical address of this buffer entry */
147 dma_addr_t dma_addr;
148 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
149
150 /* The queue of BH actions to be performed */
151
152 #define BH_RECEIVE 1
153 #define BH_TRANSMIT 2
154 #define BH_STATUS 4
155
156 #define IO_PIN_SHUTDOWN_LIMIT 100
157
158 struct _input_signal_events {
159 int ri_up;
160 int ri_down;
161 int dsr_up;
162 int dsr_down;
163 int dcd_up;
164 int dcd_down;
165 int cts_up;
166 int cts_down;
167 };
168
169 /* transmit holding buffer definitions*/
170 #define MAX_TX_HOLDING_BUFFERS 5
171 struct tx_holding_buffer {
172 int buffer_size;
173 unsigned char * buffer;
174 };
175
176
177 /*
178 * Device instance data structure
179 */
180
181 struct mgsl_struct {
182 int magic;
183 int flags;
184 int count; /* count of opens */
185 int line;
186 int hw_version;
187 unsigned short close_delay;
188 unsigned short closing_wait; /* time to wait before closing */
189
190 struct mgsl_icount icount;
191
192 struct tty_struct *tty;
193 int timeout;
194 int x_char; /* xon/xoff character */
195 int blocked_open; /* # of blocked opens */
196 u16 read_status_mask;
197 u16 ignore_status_mask;
198 unsigned char *xmit_buf;
199 int xmit_head;
200 int xmit_tail;
201 int xmit_cnt;
202
203 wait_queue_head_t open_wait;
204 wait_queue_head_t close_wait;
205
206 wait_queue_head_t status_event_wait_q;
207 wait_queue_head_t event_wait_q;
208 struct timer_list tx_timer; /* HDLC transmit timeout timer */
209 struct mgsl_struct *next_device; /* device list link */
210
211 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
212 struct work_struct task; /* task structure for scheduling bh */
213
214 u32 EventMask; /* event trigger mask */
215 u32 RecordedEvents; /* pending events */
216
217 u32 max_frame_size; /* as set by device config */
218
219 u32 pending_bh;
220
221 bool bh_running; /* Protection from multiple */
222 int isr_overflow;
223 bool bh_requested;
224
225 int dcd_chkcount; /* check counts to prevent */
226 int cts_chkcount; /* too many IRQs if a signal */
227 int dsr_chkcount; /* is floating */
228 int ri_chkcount;
229
230 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
231 u32 buffer_list_phys;
232 dma_addr_t buffer_list_dma_addr;
233
234 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
235 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
236 unsigned int current_rx_buffer;
237
238 int num_tx_dma_buffers; /* number of tx dma frames required */
239 int tx_dma_buffers_used;
240 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
241 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
242 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
243 int current_tx_buffer; /* next tx dma buffer to be loaded */
244
245 unsigned char *intermediate_rxbuffer;
246
247 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
248 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
249 int put_tx_holding_index; /* next tx holding buffer to store user request */
250 int tx_holding_count; /* number of tx holding buffers waiting */
251 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
252
253 bool rx_enabled;
254 bool rx_overflow;
255 bool rx_rcc_underrun;
256
257 bool tx_enabled;
258 bool tx_active;
259 u32 idle_mode;
260
261 u16 cmr_value;
262 u16 tcsr_value;
263
264 char device_name[25]; /* device instance name */
265
266 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
267 unsigned char bus; /* expansion bus number (zero based) */
268 unsigned char function; /* PCI device number */
269
270 unsigned int io_base; /* base I/O address of adapter */
271 unsigned int io_addr_size; /* size of the I/O address range */
272 bool io_addr_requested; /* true if I/O address requested */
273
274 unsigned int irq_level; /* interrupt level */
275 unsigned long irq_flags;
276 bool irq_requested; /* true if IRQ requested */
277
278 unsigned int dma_level; /* DMA channel */
279 bool dma_requested; /* true if dma channel requested */
280
281 u16 mbre_bit;
282 u16 loopback_bits;
283 u16 usc_idle_mode;
284
285 MGSL_PARAMS params; /* communications parameters */
286
287 unsigned char serial_signals; /* current serial signal states */
288
289 bool irq_occurred; /* for diagnostics use */
290 unsigned int init_error; /* Initialization startup error (DIAGS) */
291 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
292
293 u32 last_mem_alloc;
294 unsigned char* memory_base; /* shared memory address (PCI only) */
295 u32 phys_memory_base;
296 bool shared_mem_requested;
297
298 unsigned char* lcr_base; /* local config registers (PCI only) */
299 u32 phys_lcr_base;
300 u32 lcr_offset;
301 bool lcr_mem_requested;
302
303 u32 misc_ctrl_value;
304 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
305 char char_buf[MAX_ASYNC_BUFFER_SIZE];
306 bool drop_rts_on_tx_done;
307
308 bool loopmode_insert_requested;
309 bool loopmode_send_done_requested;
310
311 struct _input_signal_events input_signal_events;
312
313 /* generic HDLC device parts */
314 int netcount;
315 int dosyncppp;
316 spinlock_t netlock;
317
318 #if SYNCLINK_GENERIC_HDLC
319 struct net_device *netdev;
320 #endif
321 };
322
323 #define MGSL_MAGIC 0x5401
324
325 /*
326 * The size of the serial xmit buffer is 1 page, or 4096 bytes
327 */
328 #ifndef SERIAL_XMIT_SIZE
329 #define SERIAL_XMIT_SIZE 4096
330 #endif
331
332 /*
333 * These macros define the offsets used in calculating the
334 * I/O address of the specified USC registers.
335 */
336
337
338 #define DCPIN 2 /* Bit 1 of I/O address */
339 #define SDPIN 4 /* Bit 2 of I/O address */
340
341 #define DCAR 0 /* DMA command/address register */
342 #define CCAR SDPIN /* channel command/address register */
343 #define DATAREG DCPIN + SDPIN /* serial data register */
344 #define MSBONLY 0x41
345 #define LSBONLY 0x40
346
347 /*
348 * These macros define the register address (ordinal number)
349 * used for writing address/value pairs to the USC.
350 */
351
352 #define CMR 0x02 /* Channel mode Register */
353 #define CCSR 0x04 /* Channel Command/status Register */
354 #define CCR 0x06 /* Channel Control Register */
355 #define PSR 0x08 /* Port status Register */
356 #define PCR 0x0a /* Port Control Register */
357 #define TMDR 0x0c /* Test mode Data Register */
358 #define TMCR 0x0e /* Test mode Control Register */
359 #define CMCR 0x10 /* Clock mode Control Register */
360 #define HCR 0x12 /* Hardware Configuration Register */
361 #define IVR 0x14 /* Interrupt Vector Register */
362 #define IOCR 0x16 /* Input/Output Control Register */
363 #define ICR 0x18 /* Interrupt Control Register */
364 #define DCCR 0x1a /* Daisy Chain Control Register */
365 #define MISR 0x1c /* Misc Interrupt status Register */
366 #define SICR 0x1e /* status Interrupt Control Register */
367 #define RDR 0x20 /* Receive Data Register */
368 #define RMR 0x22 /* Receive mode Register */
369 #define RCSR 0x24 /* Receive Command/status Register */
370 #define RICR 0x26 /* Receive Interrupt Control Register */
371 #define RSR 0x28 /* Receive Sync Register */
372 #define RCLR 0x2a /* Receive count Limit Register */
373 #define RCCR 0x2c /* Receive Character count Register */
374 #define TC0R 0x2e /* Time Constant 0 Register */
375 #define TDR 0x30 /* Transmit Data Register */
376 #define TMR 0x32 /* Transmit mode Register */
377 #define TCSR 0x34 /* Transmit Command/status Register */
378 #define TICR 0x36 /* Transmit Interrupt Control Register */
379 #define TSR 0x38 /* Transmit Sync Register */
380 #define TCLR 0x3a /* Transmit count Limit Register */
381 #define TCCR 0x3c /* Transmit Character count Register */
382 #define TC1R 0x3e /* Time Constant 1 Register */
383
384
385 /*
386 * MACRO DEFINITIONS FOR DMA REGISTERS
387 */
388
389 #define DCR 0x06 /* DMA Control Register (shared) */
390 #define DACR 0x08 /* DMA Array count Register (shared) */
391 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
392 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
393 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
394 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
395 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
396
397 #define TDMR 0x02 /* Transmit DMA mode Register */
398 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
399 #define TBCR 0x2a /* Transmit Byte count Register */
400 #define TARL 0x2c /* Transmit Address Register (low) */
401 #define TARU 0x2e /* Transmit Address Register (high) */
402 #define NTBCR 0x3a /* Next Transmit Byte count Register */
403 #define NTARL 0x3c /* Next Transmit Address Register (low) */
404 #define NTARU 0x3e /* Next Transmit Address Register (high) */
405
406 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
407 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
408 #define RBCR 0xaa /* Receive Byte count Register */
409 #define RARL 0xac /* Receive Address Register (low) */
410 #define RARU 0xae /* Receive Address Register (high) */
411 #define NRBCR 0xba /* Next Receive Byte count Register */
412 #define NRARL 0xbc /* Next Receive Address Register (low) */
413 #define NRARU 0xbe /* Next Receive Address Register (high) */
414
415
416 /*
417 * MACRO DEFINITIONS FOR MODEM STATUS BITS
418 */
419
420 #define MODEMSTATUS_DTR 0x80
421 #define MODEMSTATUS_DSR 0x40
422 #define MODEMSTATUS_RTS 0x20
423 #define MODEMSTATUS_CTS 0x10
424 #define MODEMSTATUS_RI 0x04
425 #define MODEMSTATUS_DCD 0x01
426
427
428 /*
429 * Channel Command/Address Register (CCAR) Command Codes
430 */
431
432 #define RTCmd_Null 0x0000
433 #define RTCmd_ResetHighestIus 0x1000
434 #define RTCmd_TriggerChannelLoadDma 0x2000
435 #define RTCmd_TriggerRxDma 0x2800
436 #define RTCmd_TriggerTxDma 0x3000
437 #define RTCmd_TriggerRxAndTxDma 0x3800
438 #define RTCmd_PurgeRxFifo 0x4800
439 #define RTCmd_PurgeTxFifo 0x5000
440 #define RTCmd_PurgeRxAndTxFifo 0x5800
441 #define RTCmd_LoadRcc 0x6800
442 #define RTCmd_LoadTcc 0x7000
443 #define RTCmd_LoadRccAndTcc 0x7800
444 #define RTCmd_LoadTC0 0x8800
445 #define RTCmd_LoadTC1 0x9000
446 #define RTCmd_LoadTC0AndTC1 0x9800
447 #define RTCmd_SerialDataLSBFirst 0xa000
448 #define RTCmd_SerialDataMSBFirst 0xa800
449 #define RTCmd_SelectBigEndian 0xb000
450 #define RTCmd_SelectLittleEndian 0xb800
451
452
453 /*
454 * DMA Command/Address Register (DCAR) Command Codes
455 */
456
457 #define DmaCmd_Null 0x0000
458 #define DmaCmd_ResetTxChannel 0x1000
459 #define DmaCmd_ResetRxChannel 0x1200
460 #define DmaCmd_StartTxChannel 0x2000
461 #define DmaCmd_StartRxChannel 0x2200
462 #define DmaCmd_ContinueTxChannel 0x3000
463 #define DmaCmd_ContinueRxChannel 0x3200
464 #define DmaCmd_PauseTxChannel 0x4000
465 #define DmaCmd_PauseRxChannel 0x4200
466 #define DmaCmd_AbortTxChannel 0x5000
467 #define DmaCmd_AbortRxChannel 0x5200
468 #define DmaCmd_InitTxChannel 0x7000
469 #define DmaCmd_InitRxChannel 0x7200
470 #define DmaCmd_ResetHighestDmaIus 0x8000
471 #define DmaCmd_ResetAllChannels 0x9000
472 #define DmaCmd_StartAllChannels 0xa000
473 #define DmaCmd_ContinueAllChannels 0xb000
474 #define DmaCmd_PauseAllChannels 0xc000
475 #define DmaCmd_AbortAllChannels 0xd000
476 #define DmaCmd_InitAllChannels 0xf000
477
478 #define TCmd_Null 0x0000
479 #define TCmd_ClearTxCRC 0x2000
480 #define TCmd_SelectTicrTtsaData 0x4000
481 #define TCmd_SelectTicrTxFifostatus 0x5000
482 #define TCmd_SelectTicrIntLevel 0x6000
483 #define TCmd_SelectTicrdma_level 0x7000
484 #define TCmd_SendFrame 0x8000
485 #define TCmd_SendAbort 0x9000
486 #define TCmd_EnableDleInsertion 0xc000
487 #define TCmd_DisableDleInsertion 0xd000
488 #define TCmd_ClearEofEom 0xe000
489 #define TCmd_SetEofEom 0xf000
490
491 #define RCmd_Null 0x0000
492 #define RCmd_ClearRxCRC 0x2000
493 #define RCmd_EnterHuntmode 0x3000
494 #define RCmd_SelectRicrRtsaData 0x4000
495 #define RCmd_SelectRicrRxFifostatus 0x5000
496 #define RCmd_SelectRicrIntLevel 0x6000
497 #define RCmd_SelectRicrdma_level 0x7000
498
499 /*
500 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
501 */
502
503 #define RECEIVE_STATUS BIT5
504 #define RECEIVE_DATA BIT4
505 #define TRANSMIT_STATUS BIT3
506 #define TRANSMIT_DATA BIT2
507 #define IO_PIN BIT1
508 #define MISC BIT0
509
510
511 /*
512 * Receive status Bits in Receive Command/status Register RCSR
513 */
514
515 #define RXSTATUS_SHORT_FRAME BIT8
516 #define RXSTATUS_CODE_VIOLATION BIT8
517 #define RXSTATUS_EXITED_HUNT BIT7
518 #define RXSTATUS_IDLE_RECEIVED BIT6
519 #define RXSTATUS_BREAK_RECEIVED BIT5
520 #define RXSTATUS_ABORT_RECEIVED BIT5
521 #define RXSTATUS_RXBOUND BIT4
522 #define RXSTATUS_CRC_ERROR BIT3
523 #define RXSTATUS_FRAMING_ERROR BIT3
524 #define RXSTATUS_ABORT BIT2
525 #define RXSTATUS_PARITY_ERROR BIT2
526 #define RXSTATUS_OVERRUN BIT1
527 #define RXSTATUS_DATA_AVAILABLE BIT0
528 #define RXSTATUS_ALL 0x01f6
529 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
530
531 /*
532 * Values for setting transmit idle mode in
533 * Transmit Control/status Register (TCSR)
534 */
535 #define IDLEMODE_FLAGS 0x0000
536 #define IDLEMODE_ALT_ONE_ZERO 0x0100
537 #define IDLEMODE_ZERO 0x0200
538 #define IDLEMODE_ONE 0x0300
539 #define IDLEMODE_ALT_MARK_SPACE 0x0500
540 #define IDLEMODE_SPACE 0x0600
541 #define IDLEMODE_MARK 0x0700
542 #define IDLEMODE_MASK 0x0700
543
544 /*
545 * IUSC revision identifiers
546 */
547 #define IUSC_SL1660 0x4d44
548 #define IUSC_PRE_SL1660 0x4553
549
550 /*
551 * Transmit status Bits in Transmit Command/status Register (TCSR)
552 */
553
554 #define TCSR_PRESERVE 0x0F00
555
556 #define TCSR_UNDERWAIT BIT11
557 #define TXSTATUS_PREAMBLE_SENT BIT7
558 #define TXSTATUS_IDLE_SENT BIT6
559 #define TXSTATUS_ABORT_SENT BIT5
560 #define TXSTATUS_EOF_SENT BIT4
561 #define TXSTATUS_EOM_SENT BIT4
562 #define TXSTATUS_CRC_SENT BIT3
563 #define TXSTATUS_ALL_SENT BIT2
564 #define TXSTATUS_UNDERRUN BIT1
565 #define TXSTATUS_FIFO_EMPTY BIT0
566 #define TXSTATUS_ALL 0x00fa
567 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
568
569
570 #define MISCSTATUS_RXC_LATCHED BIT15
571 #define MISCSTATUS_RXC BIT14
572 #define MISCSTATUS_TXC_LATCHED BIT13
573 #define MISCSTATUS_TXC BIT12
574 #define MISCSTATUS_RI_LATCHED BIT11
575 #define MISCSTATUS_RI BIT10
576 #define MISCSTATUS_DSR_LATCHED BIT9
577 #define MISCSTATUS_DSR BIT8
578 #define MISCSTATUS_DCD_LATCHED BIT7
579 #define MISCSTATUS_DCD BIT6
580 #define MISCSTATUS_CTS_LATCHED BIT5
581 #define MISCSTATUS_CTS BIT4
582 #define MISCSTATUS_RCC_UNDERRUN BIT3
583 #define MISCSTATUS_DPLL_NO_SYNC BIT2
584 #define MISCSTATUS_BRG1_ZERO BIT1
585 #define MISCSTATUS_BRG0_ZERO BIT0
586
587 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
588 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
589
590 #define SICR_RXC_ACTIVE BIT15
591 #define SICR_RXC_INACTIVE BIT14
592 #define SICR_RXC (BIT15+BIT14)
593 #define SICR_TXC_ACTIVE BIT13
594 #define SICR_TXC_INACTIVE BIT12
595 #define SICR_TXC (BIT13+BIT12)
596 #define SICR_RI_ACTIVE BIT11
597 #define SICR_RI_INACTIVE BIT10
598 #define SICR_RI (BIT11+BIT10)
599 #define SICR_DSR_ACTIVE BIT9
600 #define SICR_DSR_INACTIVE BIT8
601 #define SICR_DSR (BIT9+BIT8)
602 #define SICR_DCD_ACTIVE BIT7
603 #define SICR_DCD_INACTIVE BIT6
604 #define SICR_DCD (BIT7+BIT6)
605 #define SICR_CTS_ACTIVE BIT5
606 #define SICR_CTS_INACTIVE BIT4
607 #define SICR_CTS (BIT5+BIT4)
608 #define SICR_RCC_UNDERFLOW BIT3
609 #define SICR_DPLL_NO_SYNC BIT2
610 #define SICR_BRG1_ZERO BIT1
611 #define SICR_BRG0_ZERO BIT0
612
613 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
614 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
615 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
616 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
617 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
618
619 #define usc_EnableInterrupts( a, b ) \
620 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
621
622 #define usc_DisableInterrupts( a, b ) \
623 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
624
625 #define usc_EnableMasterIrqBit(a) \
626 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
627
628 #define usc_DisableMasterIrqBit(a) \
629 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
630
631 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
632
633 /*
634 * Transmit status Bits in Transmit Control status Register (TCSR)
635 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
636 */
637
638 #define TXSTATUS_PREAMBLE_SENT BIT7
639 #define TXSTATUS_IDLE_SENT BIT6
640 #define TXSTATUS_ABORT_SENT BIT5
641 #define TXSTATUS_EOF BIT4
642 #define TXSTATUS_CRC_SENT BIT3
643 #define TXSTATUS_ALL_SENT BIT2
644 #define TXSTATUS_UNDERRUN BIT1
645 #define TXSTATUS_FIFO_EMPTY BIT0
646
647 #define DICR_MASTER BIT15
648 #define DICR_TRANSMIT BIT0
649 #define DICR_RECEIVE BIT1
650
651 #define usc_EnableDmaInterrupts(a,b) \
652 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
653
654 #define usc_DisableDmaInterrupts(a,b) \
655 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
656
657 #define usc_EnableStatusIrqs(a,b) \
658 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
659
660 #define usc_DisablestatusIrqs(a,b) \
661 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
662
663 /* Transmit status Bits in Transmit Control status Register (TCSR) */
664 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
665
666
667 #define DISABLE_UNCONDITIONAL 0
668 #define DISABLE_END_OF_FRAME 1
669 #define ENABLE_UNCONDITIONAL 2
670 #define ENABLE_AUTO_CTS 3
671 #define ENABLE_AUTO_DCD 3
672 #define usc_EnableTransmitter(a,b) \
673 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
674 #define usc_EnableReceiver(a,b) \
675 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
676
677 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
678 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
679 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
680
681 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
682 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
683 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
684 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
685 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
686
687 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
688 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
689
690 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
691
692 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
693 static void usc_start_receiver( struct mgsl_struct *info );
694 static void usc_stop_receiver( struct mgsl_struct *info );
695
696 static void usc_start_transmitter( struct mgsl_struct *info );
697 static void usc_stop_transmitter( struct mgsl_struct *info );
698 static void usc_set_txidle( struct mgsl_struct *info );
699 static void usc_load_txfifo( struct mgsl_struct *info );
700
701 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
702 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
703
704 static void usc_get_serial_signals( struct mgsl_struct *info );
705 static void usc_set_serial_signals( struct mgsl_struct *info );
706
707 static void usc_reset( struct mgsl_struct *info );
708
709 static void usc_set_sync_mode( struct mgsl_struct *info );
710 static void usc_set_sdlc_mode( struct mgsl_struct *info );
711 static void usc_set_async_mode( struct mgsl_struct *info );
712 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
713
714 static void usc_loopback_frame( struct mgsl_struct *info );
715
716 static void mgsl_tx_timeout(unsigned long context);
717
718
719 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
720 static void usc_loopmode_insert_request( struct mgsl_struct * info );
721 static int usc_loopmode_active( struct mgsl_struct * info);
722 static void usc_loopmode_send_done( struct mgsl_struct * info );
723
724 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
725
726 #if SYNCLINK_GENERIC_HDLC
727 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
728 static void hdlcdev_tx_done(struct mgsl_struct *info);
729 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
730 static int hdlcdev_init(struct mgsl_struct *info);
731 static void hdlcdev_exit(struct mgsl_struct *info);
732 #endif
733
734 /*
735 * Defines a BUS descriptor value for the PCI adapter
736 * local bus address ranges.
737 */
738
739 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
740 (0x00400020 + \
741 ((WrHold) << 30) + \
742 ((WrDly) << 28) + \
743 ((RdDly) << 26) + \
744 ((Nwdd) << 20) + \
745 ((Nwad) << 15) + \
746 ((Nxda) << 13) + \
747 ((Nrdd) << 11) + \
748 ((Nrad) << 6) )
749
750 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
751
752 /*
753 * Adapter diagnostic routines
754 */
755 static bool mgsl_register_test( struct mgsl_struct *info );
756 static bool mgsl_irq_test( struct mgsl_struct *info );
757 static bool mgsl_dma_test( struct mgsl_struct *info );
758 static bool mgsl_memory_test( struct mgsl_struct *info );
759 static int mgsl_adapter_test( struct mgsl_struct *info );
760
761 /*
762 * device and resource management routines
763 */
764 static int mgsl_claim_resources(struct mgsl_struct *info);
765 static void mgsl_release_resources(struct mgsl_struct *info);
766 static void mgsl_add_device(struct mgsl_struct *info);
767 static struct mgsl_struct* mgsl_allocate_device(void);
768
769 /*
770 * DMA buffer manupulation functions.
771 */
772 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
773 static bool mgsl_get_rx_frame( struct mgsl_struct *info );
774 static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
775 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
776 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
777 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
778 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
779 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
780
781 /*
782 * DMA and Shared Memory buffer allocation and formatting
783 */
784 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
785 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
786 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
787 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
788 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
789 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
790 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
791 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
792 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
793 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
794 static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
795 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
796
797 /*
798 * Bottom half interrupt handlers
799 */
800 static void mgsl_bh_handler(struct work_struct *work);
801 static void mgsl_bh_receive(struct mgsl_struct *info);
802 static void mgsl_bh_transmit(struct mgsl_struct *info);
803 static void mgsl_bh_status(struct mgsl_struct *info);
804
805 /*
806 * Interrupt handler routines and dispatch table.
807 */
808 static void mgsl_isr_null( struct mgsl_struct *info );
809 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
810 static void mgsl_isr_receive_data( struct mgsl_struct *info );
811 static void mgsl_isr_receive_status( struct mgsl_struct *info );
812 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
813 static void mgsl_isr_io_pin( struct mgsl_struct *info );
814 static void mgsl_isr_misc( struct mgsl_struct *info );
815 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
816 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
817
818 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
819
820 static isr_dispatch_func UscIsrTable[7] =
821 {
822 mgsl_isr_null,
823 mgsl_isr_misc,
824 mgsl_isr_io_pin,
825 mgsl_isr_transmit_data,
826 mgsl_isr_transmit_status,
827 mgsl_isr_receive_data,
828 mgsl_isr_receive_status
829 };
830
831 /*
832 * ioctl call handlers
833 */
834 static int tiocmget(struct tty_struct *tty, struct file *file);
835 static int tiocmset(struct tty_struct *tty, struct file *file,
836 unsigned int set, unsigned int clear);
837 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
838 __user *user_icount);
839 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
840 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
841 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
842 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
843 static int mgsl_txenable(struct mgsl_struct * info, int enable);
844 static int mgsl_txabort(struct mgsl_struct * info);
845 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
846 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
847 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
848
849 /* set non-zero on successful registration with PCI subsystem */
850 static bool pci_registered;
851
852 /*
853 * Global linked list of SyncLink devices
854 */
855 static struct mgsl_struct *mgsl_device_list;
856 static int mgsl_device_count;
857
858 /*
859 * Set this param to non-zero to load eax with the
860 * .text section address and breakpoint on module load.
861 * This is useful for use with gdb and add-symbol-file command.
862 */
863 static int break_on_load;
864
865 /*
866 * Driver major number, defaults to zero to get auto
867 * assigned major number. May be forced as module parameter.
868 */
869 static int ttymajor;
870
871 /*
872 * Array of user specified options for ISA adapters.
873 */
874 static int io[MAX_ISA_DEVICES];
875 static int irq[MAX_ISA_DEVICES];
876 static int dma[MAX_ISA_DEVICES];
877 static int debug_level;
878 static int maxframe[MAX_TOTAL_DEVICES];
879 static int dosyncppp[MAX_TOTAL_DEVICES];
880 static int txdmabufs[MAX_TOTAL_DEVICES];
881 static int txholdbufs[MAX_TOTAL_DEVICES];
882
883 module_param(break_on_load, bool, 0);
884 module_param(ttymajor, int, 0);
885 module_param_array(io, int, NULL, 0);
886 module_param_array(irq, int, NULL, 0);
887 module_param_array(dma, int, NULL, 0);
888 module_param(debug_level, int, 0);
889 module_param_array(maxframe, int, NULL, 0);
890 module_param_array(dosyncppp, int, NULL, 0);
891 module_param_array(txdmabufs, int, NULL, 0);
892 module_param_array(txholdbufs, int, NULL, 0);
893
894 static char *driver_name = "SyncLink serial driver";
895 static char *driver_version = "$Revision: 4.38 $";
896
897 static int synclink_init_one (struct pci_dev *dev,
898 const struct pci_device_id *ent);
899 static void synclink_remove_one (struct pci_dev *dev);
900
901 static struct pci_device_id synclink_pci_tbl[] = {
902 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
903 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
904 { 0, }, /* terminate list */
905 };
906 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
907
908 MODULE_LICENSE("GPL");
909
910 static struct pci_driver synclink_pci_driver = {
911 .name = "synclink",
912 .id_table = synclink_pci_tbl,
913 .probe = synclink_init_one,
914 .remove = __devexit_p(synclink_remove_one),
915 };
916
917 static struct tty_driver *serial_driver;
918
919 /* number of characters left in xmit buffer before we ask for more */
920 #define WAKEUP_CHARS 256
921
922
923 static void mgsl_change_params(struct mgsl_struct *info);
924 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
925
926 /*
927 * 1st function defined in .text section. Calling this function in
928 * init_module() followed by a breakpoint allows a remote debugger
929 * (gdb) to get the .text address for the add-symbol-file command.
930 * This allows remote debugging of dynamically loadable modules.
931 */
932 static void* mgsl_get_text_ptr(void)
933 {
934 return mgsl_get_text_ptr;
935 }
936
937 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
938 char *name, const char *routine)
939 {
940 #ifdef MGSL_PARANOIA_CHECK
941 static const char *badmagic =
942 "Warning: bad magic number for mgsl struct (%s) in %s\n";
943 static const char *badinfo =
944 "Warning: null mgsl_struct for (%s) in %s\n";
945
946 if (!info) {
947 printk(badinfo, name, routine);
948 return 1;
949 }
950 if (info->magic != MGSL_MAGIC) {
951 printk(badmagic, name, routine);
952 return 1;
953 }
954 #else
955 if (!info)
956 return 1;
957 #endif
958 return 0;
959 }
960
961 /**
962 * line discipline callback wrappers
963 *
964 * The wrappers maintain line discipline references
965 * while calling into the line discipline.
966 *
967 * ldisc_receive_buf - pass receive data to line discipline
968 */
969
970 static void ldisc_receive_buf(struct tty_struct *tty,
971 const __u8 *data, char *flags, int count)
972 {
973 struct tty_ldisc *ld;
974 if (!tty)
975 return;
976 ld = tty_ldisc_ref(tty);
977 if (ld) {
978 if (ld->receive_buf)
979 ld->receive_buf(tty, data, flags, count);
980 tty_ldisc_deref(ld);
981 }
982 }
983
984 /* mgsl_stop() throttle (stop) transmitter
985 *
986 * Arguments: tty pointer to tty info structure
987 * Return Value: None
988 */
989 static void mgsl_stop(struct tty_struct *tty)
990 {
991 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
992 unsigned long flags;
993
994 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
995 return;
996
997 if ( debug_level >= DEBUG_LEVEL_INFO )
998 printk("mgsl_stop(%s)\n",info->device_name);
999
1000 spin_lock_irqsave(&info->irq_spinlock,flags);
1001 if (info->tx_enabled)
1002 usc_stop_transmitter(info);
1003 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1004
1005 } /* end of mgsl_stop() */
1006
1007 /* mgsl_start() release (start) transmitter
1008 *
1009 * Arguments: tty pointer to tty info structure
1010 * Return Value: None
1011 */
1012 static void mgsl_start(struct tty_struct *tty)
1013 {
1014 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1015 unsigned long flags;
1016
1017 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1018 return;
1019
1020 if ( debug_level >= DEBUG_LEVEL_INFO )
1021 printk("mgsl_start(%s)\n",info->device_name);
1022
1023 spin_lock_irqsave(&info->irq_spinlock,flags);
1024 if (!info->tx_enabled)
1025 usc_start_transmitter(info);
1026 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1027
1028 } /* end of mgsl_start() */
1029
1030 /*
1031 * Bottom half work queue access functions
1032 */
1033
1034 /* mgsl_bh_action() Return next bottom half action to perform.
1035 * Return Value: BH action code or 0 if nothing to do.
1036 */
1037 static int mgsl_bh_action(struct mgsl_struct *info)
1038 {
1039 unsigned long flags;
1040 int rc = 0;
1041
1042 spin_lock_irqsave(&info->irq_spinlock,flags);
1043
1044 if (info->pending_bh & BH_RECEIVE) {
1045 info->pending_bh &= ~BH_RECEIVE;
1046 rc = BH_RECEIVE;
1047 } else if (info->pending_bh & BH_TRANSMIT) {
1048 info->pending_bh &= ~BH_TRANSMIT;
1049 rc = BH_TRANSMIT;
1050 } else if (info->pending_bh & BH_STATUS) {
1051 info->pending_bh &= ~BH_STATUS;
1052 rc = BH_STATUS;
1053 }
1054
1055 if (!rc) {
1056 /* Mark BH routine as complete */
1057 info->bh_running = false;
1058 info->bh_requested = false;
1059 }
1060
1061 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1062
1063 return rc;
1064 }
1065
1066 /*
1067 * Perform bottom half processing of work items queued by ISR.
1068 */
1069 static void mgsl_bh_handler(struct work_struct *work)
1070 {
1071 struct mgsl_struct *info =
1072 container_of(work, struct mgsl_struct, task);
1073 int action;
1074
1075 if (!info)
1076 return;
1077
1078 if ( debug_level >= DEBUG_LEVEL_BH )
1079 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1080 __FILE__,__LINE__,info->device_name);
1081
1082 info->bh_running = true;
1083
1084 while((action = mgsl_bh_action(info)) != 0) {
1085
1086 /* Process work item */
1087 if ( debug_level >= DEBUG_LEVEL_BH )
1088 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1089 __FILE__,__LINE__,action);
1090
1091 switch (action) {
1092
1093 case BH_RECEIVE:
1094 mgsl_bh_receive(info);
1095 break;
1096 case BH_TRANSMIT:
1097 mgsl_bh_transmit(info);
1098 break;
1099 case BH_STATUS:
1100 mgsl_bh_status(info);
1101 break;
1102 default:
1103 /* unknown work item ID */
1104 printk("Unknown work item ID=%08X!\n", action);
1105 break;
1106 }
1107 }
1108
1109 if ( debug_level >= DEBUG_LEVEL_BH )
1110 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1111 __FILE__,__LINE__,info->device_name);
1112 }
1113
1114 static void mgsl_bh_receive(struct mgsl_struct *info)
1115 {
1116 bool (*get_rx_frame)(struct mgsl_struct *info) =
1117 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1118
1119 if ( debug_level >= DEBUG_LEVEL_BH )
1120 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1121 __FILE__,__LINE__,info->device_name);
1122
1123 do
1124 {
1125 if (info->rx_rcc_underrun) {
1126 unsigned long flags;
1127 spin_lock_irqsave(&info->irq_spinlock,flags);
1128 usc_start_receiver(info);
1129 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1130 return;
1131 }
1132 } while(get_rx_frame(info));
1133 }
1134
1135 static void mgsl_bh_transmit(struct mgsl_struct *info)
1136 {
1137 struct tty_struct *tty = info->tty;
1138 unsigned long flags;
1139
1140 if ( debug_level >= DEBUG_LEVEL_BH )
1141 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1142 __FILE__,__LINE__,info->device_name);
1143
1144 if (tty)
1145 tty_wakeup(tty);
1146
1147 /* if transmitter idle and loopmode_send_done_requested
1148 * then start echoing RxD to TxD
1149 */
1150 spin_lock_irqsave(&info->irq_spinlock,flags);
1151 if ( !info->tx_active && info->loopmode_send_done_requested )
1152 usc_loopmode_send_done( info );
1153 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1154 }
1155
1156 static void mgsl_bh_status(struct mgsl_struct *info)
1157 {
1158 if ( debug_level >= DEBUG_LEVEL_BH )
1159 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1160 __FILE__,__LINE__,info->device_name);
1161
1162 info->ri_chkcount = 0;
1163 info->dsr_chkcount = 0;
1164 info->dcd_chkcount = 0;
1165 info->cts_chkcount = 0;
1166 }
1167
1168 /* mgsl_isr_receive_status()
1169 *
1170 * Service a receive status interrupt. The type of status
1171 * interrupt is indicated by the state of the RCSR.
1172 * This is only used for HDLC mode.
1173 *
1174 * Arguments: info pointer to device instance data
1175 * Return Value: None
1176 */
1177 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1178 {
1179 u16 status = usc_InReg( info, RCSR );
1180
1181 if ( debug_level >= DEBUG_LEVEL_ISR )
1182 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1183 __FILE__,__LINE__,status);
1184
1185 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1186 info->loopmode_insert_requested &&
1187 usc_loopmode_active(info) )
1188 {
1189 ++info->icount.rxabort;
1190 info->loopmode_insert_requested = false;
1191
1192 /* clear CMR:13 to start echoing RxD to TxD */
1193 info->cmr_value &= ~BIT13;
1194 usc_OutReg(info, CMR, info->cmr_value);
1195
1196 /* disable received abort irq (no longer required) */
1197 usc_OutReg(info, RICR,
1198 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1199 }
1200
1201 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1202 if (status & RXSTATUS_EXITED_HUNT)
1203 info->icount.exithunt++;
1204 if (status & RXSTATUS_IDLE_RECEIVED)
1205 info->icount.rxidle++;
1206 wake_up_interruptible(&info->event_wait_q);
1207 }
1208
1209 if (status & RXSTATUS_OVERRUN){
1210 info->icount.rxover++;
1211 usc_process_rxoverrun_sync( info );
1212 }
1213
1214 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1215 usc_UnlatchRxstatusBits( info, status );
1216
1217 } /* end of mgsl_isr_receive_status() */
1218
1219 /* mgsl_isr_transmit_status()
1220 *
1221 * Service a transmit status interrupt
1222 * HDLC mode :end of transmit frame
1223 * Async mode:all data is sent
1224 * transmit status is indicated by bits in the TCSR.
1225 *
1226 * Arguments: info pointer to device instance data
1227 * Return Value: None
1228 */
1229 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1230 {
1231 u16 status = usc_InReg( info, TCSR );
1232
1233 if ( debug_level >= DEBUG_LEVEL_ISR )
1234 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1235 __FILE__,__LINE__,status);
1236
1237 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1238 usc_UnlatchTxstatusBits( info, status );
1239
1240 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1241 {
1242 /* finished sending HDLC abort. This may leave */
1243 /* the TxFifo with data from the aborted frame */
1244 /* so purge the TxFifo. Also shutdown the DMA */
1245 /* channel in case there is data remaining in */
1246 /* the DMA buffer */
1247 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1248 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1249 }
1250
1251 if ( status & TXSTATUS_EOF_SENT )
1252 info->icount.txok++;
1253 else if ( status & TXSTATUS_UNDERRUN )
1254 info->icount.txunder++;
1255 else if ( status & TXSTATUS_ABORT_SENT )
1256 info->icount.txabort++;
1257 else
1258 info->icount.txunder++;
1259
1260 info->tx_active = false;
1261 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1262 del_timer(&info->tx_timer);
1263
1264 if ( info->drop_rts_on_tx_done ) {
1265 usc_get_serial_signals( info );
1266 if ( info->serial_signals & SerialSignal_RTS ) {
1267 info->serial_signals &= ~SerialSignal_RTS;
1268 usc_set_serial_signals( info );
1269 }
1270 info->drop_rts_on_tx_done = false;
1271 }
1272
1273 #if SYNCLINK_GENERIC_HDLC
1274 if (info->netcount)
1275 hdlcdev_tx_done(info);
1276 else
1277 #endif
1278 {
1279 if (info->tty->stopped || info->tty->hw_stopped) {
1280 usc_stop_transmitter(info);
1281 return;
1282 }
1283 info->pending_bh |= BH_TRANSMIT;
1284 }
1285
1286 } /* end of mgsl_isr_transmit_status() */
1287
1288 /* mgsl_isr_io_pin()
1289 *
1290 * Service an Input/Output pin interrupt. The type of
1291 * interrupt is indicated by bits in the MISR
1292 *
1293 * Arguments: info pointer to device instance data
1294 * Return Value: None
1295 */
1296 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1297 {
1298 struct mgsl_icount *icount;
1299 u16 status = usc_InReg( info, MISR );
1300
1301 if ( debug_level >= DEBUG_LEVEL_ISR )
1302 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1303 __FILE__,__LINE__,status);
1304
1305 usc_ClearIrqPendingBits( info, IO_PIN );
1306 usc_UnlatchIostatusBits( info, status );
1307
1308 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1309 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1310 icount = &info->icount;
1311 /* update input line counters */
1312 if (status & MISCSTATUS_RI_LATCHED) {
1313 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1314 usc_DisablestatusIrqs(info,SICR_RI);
1315 icount->rng++;
1316 if ( status & MISCSTATUS_RI )
1317 info->input_signal_events.ri_up++;
1318 else
1319 info->input_signal_events.ri_down++;
1320 }
1321 if (status & MISCSTATUS_DSR_LATCHED) {
1322 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1323 usc_DisablestatusIrqs(info,SICR_DSR);
1324 icount->dsr++;
1325 if ( status & MISCSTATUS_DSR )
1326 info->input_signal_events.dsr_up++;
1327 else
1328 info->input_signal_events.dsr_down++;
1329 }
1330 if (status & MISCSTATUS_DCD_LATCHED) {
1331 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1332 usc_DisablestatusIrqs(info,SICR_DCD);
1333 icount->dcd++;
1334 if (status & MISCSTATUS_DCD) {
1335 info->input_signal_events.dcd_up++;
1336 } else
1337 info->input_signal_events.dcd_down++;
1338 #if SYNCLINK_GENERIC_HDLC
1339 if (info->netcount) {
1340 if (status & MISCSTATUS_DCD)
1341 netif_carrier_on(info->netdev);
1342 else
1343 netif_carrier_off(info->netdev);
1344 }
1345 #endif
1346 }
1347 if (status & MISCSTATUS_CTS_LATCHED)
1348 {
1349 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1350 usc_DisablestatusIrqs(info,SICR_CTS);
1351 icount->cts++;
1352 if ( status & MISCSTATUS_CTS )
1353 info->input_signal_events.cts_up++;
1354 else
1355 info->input_signal_events.cts_down++;
1356 }
1357 wake_up_interruptible(&info->status_event_wait_q);
1358 wake_up_interruptible(&info->event_wait_q);
1359
1360 if ( (info->flags & ASYNC_CHECK_CD) &&
1361 (status & MISCSTATUS_DCD_LATCHED) ) {
1362 if ( debug_level >= DEBUG_LEVEL_ISR )
1363 printk("%s CD now %s...", info->device_name,
1364 (status & MISCSTATUS_DCD) ? "on" : "off");
1365 if (status & MISCSTATUS_DCD)
1366 wake_up_interruptible(&info->open_wait);
1367 else {
1368 if ( debug_level >= DEBUG_LEVEL_ISR )
1369 printk("doing serial hangup...");
1370 if (info->tty)
1371 tty_hangup(info->tty);
1372 }
1373 }
1374
1375 if ( (info->flags & ASYNC_CTS_FLOW) &&
1376 (status & MISCSTATUS_CTS_LATCHED) ) {
1377 if (info->tty->hw_stopped) {
1378 if (status & MISCSTATUS_CTS) {
1379 if ( debug_level >= DEBUG_LEVEL_ISR )
1380 printk("CTS tx start...");
1381 if (info->tty)
1382 info->tty->hw_stopped = 0;
1383 usc_start_transmitter(info);
1384 info->pending_bh |= BH_TRANSMIT;
1385 return;
1386 }
1387 } else {
1388 if (!(status & MISCSTATUS_CTS)) {
1389 if ( debug_level >= DEBUG_LEVEL_ISR )
1390 printk("CTS tx stop...");
1391 if (info->tty)
1392 info->tty->hw_stopped = 1;
1393 usc_stop_transmitter(info);
1394 }
1395 }
1396 }
1397 }
1398
1399 info->pending_bh |= BH_STATUS;
1400
1401 /* for diagnostics set IRQ flag */
1402 if ( status & MISCSTATUS_TXC_LATCHED ){
1403 usc_OutReg( info, SICR,
1404 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1405 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1406 info->irq_occurred = true;
1407 }
1408
1409 } /* end of mgsl_isr_io_pin() */
1410
1411 /* mgsl_isr_transmit_data()
1412 *
1413 * Service a transmit data interrupt (async mode only).
1414 *
1415 * Arguments: info pointer to device instance data
1416 * Return Value: None
1417 */
1418 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1419 {
1420 if ( debug_level >= DEBUG_LEVEL_ISR )
1421 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1422 __FILE__,__LINE__,info->xmit_cnt);
1423
1424 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1425
1426 if (info->tty->stopped || info->tty->hw_stopped) {
1427 usc_stop_transmitter(info);
1428 return;
1429 }
1430
1431 if ( info->xmit_cnt )
1432 usc_load_txfifo( info );
1433 else
1434 info->tx_active = false;
1435
1436 if (info->xmit_cnt < WAKEUP_CHARS)
1437 info->pending_bh |= BH_TRANSMIT;
1438
1439 } /* end of mgsl_isr_transmit_data() */
1440
1441 /* mgsl_isr_receive_data()
1442 *
1443 * Service a receive data interrupt. This occurs
1444 * when operating in asynchronous interrupt transfer mode.
1445 * The receive data FIFO is flushed to the receive data buffers.
1446 *
1447 * Arguments: info pointer to device instance data
1448 * Return Value: None
1449 */
1450 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1451 {
1452 int Fifocount;
1453 u16 status;
1454 int work = 0;
1455 unsigned char DataByte;
1456 struct tty_struct *tty = info->tty;
1457 struct mgsl_icount *icount = &info->icount;
1458
1459 if ( debug_level >= DEBUG_LEVEL_ISR )
1460 printk("%s(%d):mgsl_isr_receive_data\n",
1461 __FILE__,__LINE__);
1462
1463 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1464
1465 /* select FIFO status for RICR readback */
1466 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1467
1468 /* clear the Wordstatus bit so that status readback */
1469 /* only reflects the status of this byte */
1470 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1471
1472 /* flush the receive FIFO */
1473
1474 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1475 int flag;
1476
1477 /* read one byte from RxFIFO */
1478 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1479 info->io_base + CCAR );
1480 DataByte = inb( info->io_base + CCAR );
1481
1482 /* get the status of the received byte */
1483 status = usc_InReg(info, RCSR);
1484 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1485 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1486 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1487
1488 icount->rx++;
1489
1490 flag = 0;
1491 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1492 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1493 printk("rxerr=%04X\n",status);
1494 /* update error statistics */
1495 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1496 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1497 icount->brk++;
1498 } else if (status & RXSTATUS_PARITY_ERROR)
1499 icount->parity++;
1500 else if (status & RXSTATUS_FRAMING_ERROR)
1501 icount->frame++;
1502 else if (status & RXSTATUS_OVERRUN) {
1503 /* must issue purge fifo cmd before */
1504 /* 16C32 accepts more receive chars */
1505 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1506 icount->overrun++;
1507 }
1508
1509 /* discard char if tty control flags say so */
1510 if (status & info->ignore_status_mask)
1511 continue;
1512
1513 status &= info->read_status_mask;
1514
1515 if (status & RXSTATUS_BREAK_RECEIVED) {
1516 flag = TTY_BREAK;
1517 if (info->flags & ASYNC_SAK)
1518 do_SAK(tty);
1519 } else if (status & RXSTATUS_PARITY_ERROR)
1520 flag = TTY_PARITY;
1521 else if (status & RXSTATUS_FRAMING_ERROR)
1522 flag = TTY_FRAME;
1523 } /* end of if (error) */
1524 tty_insert_flip_char(tty, DataByte, flag);
1525 if (status & RXSTATUS_OVERRUN) {
1526 /* Overrun is special, since it's
1527 * reported immediately, and doesn't
1528 * affect the current character
1529 */
1530 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1531 }
1532 }
1533
1534 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1535 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1536 __FILE__,__LINE__,icount->rx,icount->brk,
1537 icount->parity,icount->frame,icount->overrun);
1538 }
1539
1540 if(work)
1541 tty_flip_buffer_push(tty);
1542 }
1543
1544 /* mgsl_isr_misc()
1545 *
1546 * Service a miscellaneous interrupt source.
1547 *
1548 * Arguments: info pointer to device extension (instance data)
1549 * Return Value: None
1550 */
1551 static void mgsl_isr_misc( struct mgsl_struct *info )
1552 {
1553 u16 status = usc_InReg( info, MISR );
1554
1555 if ( debug_level >= DEBUG_LEVEL_ISR )
1556 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1557 __FILE__,__LINE__,status);
1558
1559 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1560 (info->params.mode == MGSL_MODE_HDLC)) {
1561
1562 /* turn off receiver and rx DMA */
1563 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1564 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1565 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1566 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1567 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1568
1569 /* schedule BH handler to restart receiver */
1570 info->pending_bh |= BH_RECEIVE;
1571 info->rx_rcc_underrun = true;
1572 }
1573
1574 usc_ClearIrqPendingBits( info, MISC );
1575 usc_UnlatchMiscstatusBits( info, status );
1576
1577 } /* end of mgsl_isr_misc() */
1578
1579 /* mgsl_isr_null()
1580 *
1581 * Services undefined interrupt vectors from the
1582 * USC. (hence this function SHOULD never be called)
1583 *
1584 * Arguments: info pointer to device extension (instance data)
1585 * Return Value: None
1586 */
1587 static void mgsl_isr_null( struct mgsl_struct *info )
1588 {
1589
1590 } /* end of mgsl_isr_null() */
1591
1592 /* mgsl_isr_receive_dma()
1593 *
1594 * Service a receive DMA channel interrupt.
1595 * For this driver there are two sources of receive DMA interrupts
1596 * as identified in the Receive DMA mode Register (RDMR):
1597 *
1598 * BIT3 EOA/EOL End of List, all receive buffers in receive
1599 * buffer list have been filled (no more free buffers
1600 * available). The DMA controller has shut down.
1601 *
1602 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1603 * DMA buffer is terminated in response to completion
1604 * of a good frame or a frame with errors. The status
1605 * of the frame is stored in the buffer entry in the
1606 * list of receive buffer entries.
1607 *
1608 * Arguments: info pointer to device instance data
1609 * Return Value: None
1610 */
1611 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1612 {
1613 u16 status;
1614
1615 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1616 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1617
1618 /* Read the receive DMA status to identify interrupt type. */
1619 /* This also clears the status bits. */
1620 status = usc_InDmaReg( info, RDMR );
1621
1622 if ( debug_level >= DEBUG_LEVEL_ISR )
1623 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1624 __FILE__,__LINE__,info->device_name,status);
1625
1626 info->pending_bh |= BH_RECEIVE;
1627
1628 if ( status & BIT3 ) {
1629 info->rx_overflow = true;
1630 info->icount.buf_overrun++;
1631 }
1632
1633 } /* end of mgsl_isr_receive_dma() */
1634
1635 /* mgsl_isr_transmit_dma()
1636 *
1637 * This function services a transmit DMA channel interrupt.
1638 *
1639 * For this driver there is one source of transmit DMA interrupts
1640 * as identified in the Transmit DMA Mode Register (TDMR):
1641 *
1642 * BIT2 EOB End of Buffer. This interrupt occurs when a
1643 * transmit DMA buffer has been emptied.
1644 *
1645 * The driver maintains enough transmit DMA buffers to hold at least
1646 * one max frame size transmit frame. When operating in a buffered
1647 * transmit mode, there may be enough transmit DMA buffers to hold at
1648 * least two or more max frame size frames. On an EOB condition,
1649 * determine if there are any queued transmit buffers and copy into
1650 * transmit DMA buffers if we have room.
1651 *
1652 * Arguments: info pointer to device instance data
1653 * Return Value: None
1654 */
1655 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1656 {
1657 u16 status;
1658
1659 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1660 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1661
1662 /* Read the transmit DMA status to identify interrupt type. */
1663 /* This also clears the status bits. */
1664
1665 status = usc_InDmaReg( info, TDMR );
1666
1667 if ( debug_level >= DEBUG_LEVEL_ISR )
1668 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1669 __FILE__,__LINE__,info->device_name,status);
1670
1671 if ( status & BIT2 ) {
1672 --info->tx_dma_buffers_used;
1673
1674 /* if there are transmit frames queued,
1675 * try to load the next one
1676 */
1677 if ( load_next_tx_holding_buffer(info) ) {
1678 /* if call returns non-zero value, we have
1679 * at least one free tx holding buffer
1680 */
1681 info->pending_bh |= BH_TRANSMIT;
1682 }
1683 }
1684
1685 } /* end of mgsl_isr_transmit_dma() */
1686
1687 /* mgsl_interrupt()
1688 *
1689 * Interrupt service routine entry point.
1690 *
1691 * Arguments:
1692 *
1693 * irq interrupt number that caused interrupt
1694 * dev_id device ID supplied during interrupt registration
1695 *
1696 * Return Value: None
1697 */
1698 static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1699 {
1700 struct mgsl_struct *info = dev_id;
1701 u16 UscVector;
1702 u16 DmaVector;
1703
1704 if ( debug_level >= DEBUG_LEVEL_ISR )
1705 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1706 __FILE__, __LINE__, info->irq_level);
1707
1708 spin_lock(&info->irq_spinlock);
1709
1710 for(;;) {
1711 /* Read the interrupt vectors from hardware. */
1712 UscVector = usc_InReg(info, IVR) >> 9;
1713 DmaVector = usc_InDmaReg(info, DIVR);
1714
1715 if ( debug_level >= DEBUG_LEVEL_ISR )
1716 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1717 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1718
1719 if ( !UscVector && !DmaVector )
1720 break;
1721
1722 /* Dispatch interrupt vector */
1723 if ( UscVector )
1724 (*UscIsrTable[UscVector])(info);
1725 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1726 mgsl_isr_transmit_dma(info);
1727 else
1728 mgsl_isr_receive_dma(info);
1729
1730 if ( info->isr_overflow ) {
1731 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1732 __FILE__, __LINE__, info->device_name, info->irq_level);
1733 usc_DisableMasterIrqBit(info);
1734 usc_DisableDmaInterrupts(info,DICR_MASTER);
1735 break;
1736 }
1737 }
1738
1739 /* Request bottom half processing if there's something
1740 * for it to do and the bh is not already running
1741 */
1742
1743 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1744 if ( debug_level >= DEBUG_LEVEL_ISR )
1745 printk("%s(%d):%s queueing bh task.\n",
1746 __FILE__,__LINE__,info->device_name);
1747 schedule_work(&info->task);
1748 info->bh_requested = true;
1749 }
1750
1751 spin_unlock(&info->irq_spinlock);
1752
1753 if ( debug_level >= DEBUG_LEVEL_ISR )
1754 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1755 __FILE__, __LINE__, info->irq_level);
1756
1757 return IRQ_HANDLED;
1758 } /* end of mgsl_interrupt() */
1759
1760 /* startup()
1761 *
1762 * Initialize and start device.
1763 *
1764 * Arguments: info pointer to device instance data
1765 * Return Value: 0 if success, otherwise error code
1766 */
1767 static int startup(struct mgsl_struct * info)
1768 {
1769 int retval = 0;
1770
1771 if ( debug_level >= DEBUG_LEVEL_INFO )
1772 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1773
1774 if (info->flags & ASYNC_INITIALIZED)
1775 return 0;
1776
1777 if (!info->xmit_buf) {
1778 /* allocate a page of memory for a transmit buffer */
1779 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1780 if (!info->xmit_buf) {
1781 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1782 __FILE__,__LINE__,info->device_name);
1783 return -ENOMEM;
1784 }
1785 }
1786
1787 info->pending_bh = 0;
1788
1789 memset(&info->icount, 0, sizeof(info->icount));
1790
1791 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1792
1793 /* Allocate and claim adapter resources */
1794 retval = mgsl_claim_resources(info);
1795
1796 /* perform existence check and diagnostics */
1797 if ( !retval )
1798 retval = mgsl_adapter_test(info);
1799
1800 if ( retval ) {
1801 if (capable(CAP_SYS_ADMIN) && info->tty)
1802 set_bit(TTY_IO_ERROR, &info->tty->flags);
1803 mgsl_release_resources(info);
1804 return retval;
1805 }
1806
1807 /* program hardware for current parameters */
1808 mgsl_change_params(info);
1809
1810 if (info->tty)
1811 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1812
1813 info->flags |= ASYNC_INITIALIZED;
1814
1815 return 0;
1816
1817 } /* end of startup() */
1818
1819 /* shutdown()
1820 *
1821 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1822 *
1823 * Arguments: info pointer to device instance data
1824 * Return Value: None
1825 */
1826 static void shutdown(struct mgsl_struct * info)
1827 {
1828 unsigned long flags;
1829
1830 if (!(info->flags & ASYNC_INITIALIZED))
1831 return;
1832
1833 if (debug_level >= DEBUG_LEVEL_INFO)
1834 printk("%s(%d):mgsl_shutdown(%s)\n",
1835 __FILE__,__LINE__, info->device_name );
1836
1837 /* clear status wait queue because status changes */
1838 /* can't happen after shutting down the hardware */
1839 wake_up_interruptible(&info->status_event_wait_q);
1840 wake_up_interruptible(&info->event_wait_q);
1841
1842 del_timer_sync(&info->tx_timer);
1843
1844 if (info->xmit_buf) {
1845 free_page((unsigned long) info->xmit_buf);
1846 info->xmit_buf = NULL;
1847 }
1848
1849 spin_lock_irqsave(&info->irq_spinlock,flags);
1850 usc_DisableMasterIrqBit(info);
1851 usc_stop_receiver(info);
1852 usc_stop_transmitter(info);
1853 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1854 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1855 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1856
1857 /* Disable DMAEN (Port 7, Bit 14) */
1858 /* This disconnects the DMA request signal from the ISA bus */
1859 /* on the ISA adapter. This has no effect for the PCI adapter */
1860 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1861
1862 /* Disable INTEN (Port 6, Bit12) */
1863 /* This disconnects the IRQ request signal to the ISA bus */
1864 /* on the ISA adapter. This has no effect for the PCI adapter */
1865 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1866
1867 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1868 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1869 usc_set_serial_signals(info);
1870 }
1871
1872 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1873
1874 mgsl_release_resources(info);
1875
1876 if (info->tty)
1877 set_bit(TTY_IO_ERROR, &info->tty->flags);
1878
1879 info->flags &= ~ASYNC_INITIALIZED;
1880
1881 } /* end of shutdown() */
1882
1883 static void mgsl_program_hw(struct mgsl_struct *info)
1884 {
1885 unsigned long flags;
1886
1887 spin_lock_irqsave(&info->irq_spinlock,flags);
1888
1889 usc_stop_receiver(info);
1890 usc_stop_transmitter(info);
1891 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1892
1893 if (info->params.mode == MGSL_MODE_HDLC ||
1894 info->params.mode == MGSL_MODE_RAW ||
1895 info->netcount)
1896 usc_set_sync_mode(info);
1897 else
1898 usc_set_async_mode(info);
1899
1900 usc_set_serial_signals(info);
1901
1902 info->dcd_chkcount = 0;
1903 info->cts_chkcount = 0;
1904 info->ri_chkcount = 0;
1905 info->dsr_chkcount = 0;
1906
1907 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1908 usc_EnableInterrupts(info, IO_PIN);
1909 usc_get_serial_signals(info);
1910
1911 if (info->netcount || info->tty->termios->c_cflag & CREAD)
1912 usc_start_receiver(info);
1913
1914 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1915 }
1916
1917 /* Reconfigure adapter based on new parameters
1918 */
1919 static void mgsl_change_params(struct mgsl_struct *info)
1920 {
1921 unsigned cflag;
1922 int bits_per_char;
1923
1924 if (!info->tty || !info->tty->termios)
1925 return;
1926
1927 if (debug_level >= DEBUG_LEVEL_INFO)
1928 printk("%s(%d):mgsl_change_params(%s)\n",
1929 __FILE__,__LINE__, info->device_name );
1930
1931 cflag = info->tty->termios->c_cflag;
1932
1933 /* if B0 rate (hangup) specified then negate DTR and RTS */
1934 /* otherwise assert DTR and RTS */
1935 if (cflag & CBAUD)
1936 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1937 else
1938 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1939
1940 /* byte size and parity */
1941
1942 switch (cflag & CSIZE) {
1943 case CS5: info->params.data_bits = 5; break;
1944 case CS6: info->params.data_bits = 6; break;
1945 case CS7: info->params.data_bits = 7; break;
1946 case CS8: info->params.data_bits = 8; break;
1947 /* Never happens, but GCC is too dumb to figure it out */
1948 default: info->params.data_bits = 7; break;
1949 }
1950
1951 if (cflag & CSTOPB)
1952 info->params.stop_bits = 2;
1953 else
1954 info->params.stop_bits = 1;
1955
1956 info->params.parity = ASYNC_PARITY_NONE;
1957 if (cflag & PARENB) {
1958 if (cflag & PARODD)
1959 info->params.parity = ASYNC_PARITY_ODD;
1960 else
1961 info->params.parity = ASYNC_PARITY_EVEN;
1962 #ifdef CMSPAR
1963 if (cflag & CMSPAR)
1964 info->params.parity = ASYNC_PARITY_SPACE;
1965 #endif
1966 }
1967
1968 /* calculate number of jiffies to transmit a full
1969 * FIFO (32 bytes) at specified data rate
1970 */
1971 bits_per_char = info->params.data_bits +
1972 info->params.stop_bits + 1;
1973
1974 /* if port data rate is set to 460800 or less then
1975 * allow tty settings to override, otherwise keep the
1976 * current data rate.
1977 */
1978 if (info->params.data_rate <= 460800)
1979 info->params.data_rate = tty_get_baud_rate(info->tty);
1980
1981 if ( info->params.data_rate ) {
1982 info->timeout = (32*HZ*bits_per_char) /
1983 info->params.data_rate;
1984 }
1985 info->timeout += HZ/50; /* Add .02 seconds of slop */
1986
1987 if (cflag & CRTSCTS)
1988 info->flags |= ASYNC_CTS_FLOW;
1989 else
1990 info->flags &= ~ASYNC_CTS_FLOW;
1991
1992 if (cflag & CLOCAL)
1993 info->flags &= ~ASYNC_CHECK_CD;
1994 else
1995 info->flags |= ASYNC_CHECK_CD;
1996
1997 /* process tty input control flags */
1998
1999 info->read_status_mask = RXSTATUS_OVERRUN;
2000 if (I_INPCK(info->tty))
2001 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2002 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2003 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
2004
2005 if (I_IGNPAR(info->tty))
2006 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2007 if (I_IGNBRK(info->tty)) {
2008 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2009 /* If ignoring parity and break indicators, ignore
2010 * overruns too. (For real raw support).
2011 */
2012 if (I_IGNPAR(info->tty))
2013 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2014 }
2015
2016 mgsl_program_hw(info);
2017
2018 } /* end of mgsl_change_params() */
2019
2020 /* mgsl_put_char()
2021 *
2022 * Add a character to the transmit buffer.
2023 *
2024 * Arguments: tty pointer to tty information structure
2025 * ch character to add to transmit buffer
2026 *
2027 * Return Value: None
2028 */
2029 static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2030 {
2031 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2032 unsigned long flags;
2033
2034 if ( debug_level >= DEBUG_LEVEL_INFO ) {
2035 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2036 __FILE__,__LINE__,ch,info->device_name);
2037 }
2038
2039 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2040 return;
2041
2042 if (!tty || !info->xmit_buf)
2043 return;
2044
2045 spin_lock_irqsave(&info->irq_spinlock,flags);
2046
2047 if ( (info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active ) {
2048
2049 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2050 info->xmit_buf[info->xmit_head++] = ch;
2051 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2052 info->xmit_cnt++;
2053 }
2054 }
2055
2056 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2057
2058 } /* end of mgsl_put_char() */
2059
2060 /* mgsl_flush_chars()
2061 *
2062 * Enable transmitter so remaining characters in the
2063 * transmit buffer are sent.
2064 *
2065 * Arguments: tty pointer to tty information structure
2066 * Return Value: None
2067 */
2068 static void mgsl_flush_chars(struct tty_struct *tty)
2069 {
2070 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2071 unsigned long flags;
2072
2073 if ( debug_level >= DEBUG_LEVEL_INFO )
2074 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2075 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2076
2077 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2078 return;
2079
2080 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2081 !info->xmit_buf)
2082 return;
2083
2084 if ( debug_level >= DEBUG_LEVEL_INFO )
2085 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2086 __FILE__,__LINE__,info->device_name );
2087
2088 spin_lock_irqsave(&info->irq_spinlock,flags);
2089
2090 if (!info->tx_active) {
2091 if ( (info->params.mode == MGSL_MODE_HDLC ||
2092 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2093 /* operating in synchronous (frame oriented) mode */
2094 /* copy data from circular xmit_buf to */
2095 /* transmit DMA buffer. */
2096 mgsl_load_tx_dma_buffer(info,
2097 info->xmit_buf,info->xmit_cnt);
2098 }
2099 usc_start_transmitter(info);
2100 }
2101
2102 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2103
2104 } /* end of mgsl_flush_chars() */
2105
2106 /* mgsl_write()
2107 *
2108 * Send a block of data
2109 *
2110 * Arguments:
2111 *
2112 * tty pointer to tty information structure
2113 * buf pointer to buffer containing send data
2114 * count size of send data in bytes
2115 *
2116 * Return Value: number of characters written
2117 */
2118 static int mgsl_write(struct tty_struct * tty,
2119 const unsigned char *buf, int count)
2120 {
2121 int c, ret = 0;
2122 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2123 unsigned long flags;
2124
2125 if ( debug_level >= DEBUG_LEVEL_INFO )
2126 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2127 __FILE__,__LINE__,info->device_name,count);
2128
2129 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2130 goto cleanup;
2131
2132 if (!tty || !info->xmit_buf)
2133 goto cleanup;
2134
2135 if ( info->params.mode == MGSL_MODE_HDLC ||
2136 info->params.mode == MGSL_MODE_RAW ) {
2137 /* operating in synchronous (frame oriented) mode */
2138 /* operating in synchronous (frame oriented) mode */
2139 if (info->tx_active) {
2140
2141 if ( info->params.mode == MGSL_MODE_HDLC ) {
2142 ret = 0;
2143 goto cleanup;
2144 }
2145 /* transmitter is actively sending data -
2146 * if we have multiple transmit dma and
2147 * holding buffers, attempt to queue this
2148 * frame for transmission at a later time.
2149 */
2150 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2151 /* no tx holding buffers available */
2152 ret = 0;
2153 goto cleanup;
2154 }
2155
2156 /* queue transmit frame request */
2157 ret = count;
2158 save_tx_buffer_request(info,buf,count);
2159
2160 /* if we have sufficient tx dma buffers,
2161 * load the next buffered tx request
2162 */
2163 spin_lock_irqsave(&info->irq_spinlock,flags);
2164 load_next_tx_holding_buffer(info);
2165 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2166 goto cleanup;
2167 }
2168
2169 /* if operating in HDLC LoopMode and the adapter */
2170 /* has yet to be inserted into the loop, we can't */
2171 /* transmit */
2172
2173 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2174 !usc_loopmode_active(info) )
2175 {
2176 ret = 0;
2177 goto cleanup;
2178 }
2179
2180 if ( info->xmit_cnt ) {
2181 /* Send accumulated from send_char() calls */
2182 /* as frame and wait before accepting more data. */
2183 ret = 0;
2184
2185 /* copy data from circular xmit_buf to */
2186 /* transmit DMA buffer. */
2187 mgsl_load_tx_dma_buffer(info,
2188 info->xmit_buf,info->xmit_cnt);
2189 if ( debug_level >= DEBUG_LEVEL_INFO )
2190 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2191 __FILE__,__LINE__,info->device_name);
2192 } else {
2193 if ( debug_level >= DEBUG_LEVEL_INFO )
2194 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2195 __FILE__,__LINE__,info->device_name);
2196 ret = count;
2197 info->xmit_cnt = count;
2198 mgsl_load_tx_dma_buffer(info,buf,count);
2199 }
2200 } else {
2201 while (1) {
2202 spin_lock_irqsave(&info->irq_spinlock,flags);
2203 c = min_t(int, count,
2204 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2205 SERIAL_XMIT_SIZE - info->xmit_head));
2206 if (c <= 0) {
2207 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2208 break;
2209 }
2210 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2211 info->xmit_head = ((info->xmit_head + c) &
2212 (SERIAL_XMIT_SIZE-1));
2213 info->xmit_cnt += c;
2214 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2215 buf += c;
2216 count -= c;
2217 ret += c;
2218 }
2219 }
2220
2221 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2222 spin_lock_irqsave(&info->irq_spinlock,flags);
2223 if (!info->tx_active)
2224 usc_start_transmitter(info);
2225 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2226 }
2227 cleanup:
2228 if ( debug_level >= DEBUG_LEVEL_INFO )
2229 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2230 __FILE__,__LINE__,info->device_name,ret);
2231
2232 return ret;
2233
2234 } /* end of mgsl_write() */
2235
2236 /* mgsl_write_room()
2237 *
2238 * Return the count of free bytes in transmit buffer
2239 *
2240 * Arguments: tty pointer to tty info structure
2241 * Return Value: None
2242 */
2243 static int mgsl_write_room(struct tty_struct *tty)
2244 {
2245 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2246 int ret;
2247
2248 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2249 return 0;
2250 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2251 if (ret < 0)
2252 ret = 0;
2253
2254 if (debug_level >= DEBUG_LEVEL_INFO)
2255 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2256 __FILE__,__LINE__, info->device_name,ret );
2257
2258 if ( info->params.mode == MGSL_MODE_HDLC ||
2259 info->params.mode == MGSL_MODE_RAW ) {
2260 /* operating in synchronous (frame oriented) mode */
2261 if ( info->tx_active )
2262 return 0;
2263 else
2264 return HDLC_MAX_FRAME_SIZE;
2265 }
2266
2267 return ret;
2268
2269 } /* end of mgsl_write_room() */
2270
2271 /* mgsl_chars_in_buffer()
2272 *
2273 * Return the count of bytes in transmit buffer
2274 *
2275 * Arguments: tty pointer to tty info structure
2276 * Return Value: None
2277 */
2278 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2279 {
2280 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2281
2282 if (debug_level >= DEBUG_LEVEL_INFO)
2283 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2284 __FILE__,__LINE__, info->device_name );
2285
2286 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2287 return 0;
2288
2289 if (debug_level >= DEBUG_LEVEL_INFO)
2290 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2291 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2292
2293 if ( info->params.mode == MGSL_MODE_HDLC ||
2294 info->params.mode == MGSL_MODE_RAW ) {
2295 /* operating in synchronous (frame oriented) mode */
2296 if ( info->tx_active )
2297 return info->max_frame_size;
2298 else
2299 return 0;
2300 }
2301
2302 return info->xmit_cnt;
2303 } /* end of mgsl_chars_in_buffer() */
2304
2305 /* mgsl_flush_buffer()
2306 *
2307 * Discard all data in the send buffer
2308 *
2309 * Arguments: tty pointer to tty info structure
2310 * Return Value: None
2311 */
2312 static void mgsl_flush_buffer(struct tty_struct *tty)
2313 {
2314 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2315 unsigned long flags;
2316
2317 if (debug_level >= DEBUG_LEVEL_INFO)
2318 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2319 __FILE__,__LINE__, info->device_name );
2320
2321 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2322 return;
2323
2324 spin_lock_irqsave(&info->irq_spinlock,flags);
2325 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2326 del_timer(&info->tx_timer);
2327 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2328
2329 tty_wakeup(tty);
2330 }
2331
2332 /* mgsl_send_xchar()
2333 *
2334 * Send a high-priority XON/XOFF character
2335 *
2336 * Arguments: tty pointer to tty info structure
2337 * ch character to send
2338 * Return Value: None
2339 */
2340 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2341 {
2342 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2343 unsigned long flags;
2344
2345 if (debug_level >= DEBUG_LEVEL_INFO)
2346 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2347 __FILE__,__LINE__, info->device_name, ch );
2348
2349 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2350 return;
2351
2352 info->x_char = ch;
2353 if (ch) {
2354 /* Make sure transmit interrupts are on */
2355 spin_lock_irqsave(&info->irq_spinlock,flags);
2356 if (!info->tx_enabled)
2357 usc_start_transmitter(info);
2358 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2359 }
2360 } /* end of mgsl_send_xchar() */
2361
2362 /* mgsl_throttle()
2363 *
2364 * Signal remote device to throttle send data (our receive data)
2365 *
2366 * Arguments: tty pointer to tty info structure
2367 * Return Value: None
2368 */
2369 static void mgsl_throttle(struct tty_struct * tty)
2370 {
2371 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2372 unsigned long flags;
2373
2374 if (debug_level >= DEBUG_LEVEL_INFO)
2375 printk("%s(%d):mgsl_throttle(%s) entry\n",
2376 __FILE__,__LINE__, info->device_name );
2377
2378 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2379 return;
2380
2381 if (I_IXOFF(tty))
2382 mgsl_send_xchar(tty, STOP_CHAR(tty));
2383
2384 if (tty->termios->c_cflag & CRTSCTS) {
2385 spin_lock_irqsave(&info->irq_spinlock,flags);
2386 info->serial_signals &= ~SerialSignal_RTS;
2387 usc_set_serial_signals(info);
2388 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2389 }
2390 } /* end of mgsl_throttle() */
2391
2392 /* mgsl_unthrottle()
2393 *
2394 * Signal remote device to stop throttling send data (our receive data)
2395 *
2396 * Arguments: tty pointer to tty info structure
2397 * Return Value: None
2398 */
2399 static void mgsl_unthrottle(struct tty_struct * tty)
2400 {
2401 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2402 unsigned long flags;
2403
2404 if (debug_level >= DEBUG_LEVEL_INFO)
2405 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2406 __FILE__,__LINE__, info->device_name );
2407
2408 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2409 return;
2410
2411 if (I_IXOFF(tty)) {
2412 if (info->x_char)
2413 info->x_char = 0;
2414 else
2415 mgsl_send_xchar(tty, START_CHAR(tty));
2416 }
2417
2418 if (tty->termios->c_cflag & CRTSCTS) {
2419 spin_lock_irqsave(&info->irq_spinlock,flags);
2420 info->serial_signals |= SerialSignal_RTS;
2421 usc_set_serial_signals(info);
2422 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2423 }
2424
2425 } /* end of mgsl_unthrottle() */
2426
2427 /* mgsl_get_stats()
2428 *
2429 * get the current serial parameters information
2430 *
2431 * Arguments: info pointer to device instance data
2432 * user_icount pointer to buffer to hold returned stats
2433 *
2434 * Return Value: 0 if success, otherwise error code
2435 */
2436 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2437 {
2438 int err;
2439
2440 if (debug_level >= DEBUG_LEVEL_INFO)
2441 printk("%s(%d):mgsl_get_params(%s)\n",
2442 __FILE__,__LINE__, info->device_name);
2443
2444 if (!user_icount) {
2445 memset(&info->icount, 0, sizeof(info->icount));
2446 } else {
2447 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2448 if (err)
2449 return -EFAULT;
2450 }
2451
2452 return 0;
2453
2454 } /* end of mgsl_get_stats() */
2455
2456 /* mgsl_get_params()
2457 *
2458 * get the current serial parameters information
2459 *
2460 * Arguments: info pointer to device instance data
2461 * user_params pointer to buffer to hold returned params
2462 *
2463 * Return Value: 0 if success, otherwise error code
2464 */
2465 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2466 {
2467 int err;
2468 if (debug_level >= DEBUG_LEVEL_INFO)
2469 printk("%s(%d):mgsl_get_params(%s)\n",
2470 __FILE__,__LINE__, info->device_name);
2471
2472 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2473 if (err) {
2474 if ( debug_level >= DEBUG_LEVEL_INFO )
2475 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2476 __FILE__,__LINE__,info->device_name);
2477 return -EFAULT;
2478 }
2479
2480 return 0;
2481
2482 } /* end of mgsl_get_params() */
2483
2484 /* mgsl_set_params()
2485 *
2486 * set the serial parameters
2487 *
2488 * Arguments:
2489 *
2490 * info pointer to device instance data
2491 * new_params user buffer containing new serial params
2492 *
2493 * Return Value: 0 if success, otherwise error code
2494 */
2495 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2496 {
2497 unsigned long flags;
2498 MGSL_PARAMS tmp_params;
2499 int err;
2500
2501 if (debug_level >= DEBUG_LEVEL_INFO)
2502 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2503 info->device_name );
2504 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2505 if (err) {
2506 if ( debug_level >= DEBUG_LEVEL_INFO )
2507 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2508 __FILE__,__LINE__,info->device_name);
2509 return -EFAULT;
2510 }
2511
2512 spin_lock_irqsave(&info->irq_spinlock,flags);
2513 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2514 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2515
2516 mgsl_change_params(info);
2517
2518 return 0;
2519
2520 } /* end of mgsl_set_params() */
2521
2522 /* mgsl_get_txidle()
2523 *
2524 * get the current transmit idle mode
2525 *
2526 * Arguments: info pointer to device instance data
2527 * idle_mode pointer to buffer to hold returned idle mode
2528 *
2529 * Return Value: 0 if success, otherwise error code
2530 */
2531 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2532 {
2533 int err;
2534
2535 if (debug_level >= DEBUG_LEVEL_INFO)
2536 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2537 __FILE__,__LINE__, info->device_name, info->idle_mode);
2538
2539 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2540 if (err) {
2541 if ( debug_level >= DEBUG_LEVEL_INFO )
2542 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2543 __FILE__,__LINE__,info->device_name);
2544 return -EFAULT;
2545 }
2546
2547 return 0;
2548
2549 } /* end of mgsl_get_txidle() */
2550
2551 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2552 *
2553 * Arguments: info pointer to device instance data
2554 * idle_mode new idle mode
2555 *
2556 * Return Value: 0 if success, otherwise error code
2557 */
2558 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2559 {
2560 unsigned long flags;
2561
2562 if (debug_level >= DEBUG_LEVEL_INFO)
2563 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2564 info->device_name, idle_mode );
2565
2566 spin_lock_irqsave(&info->irq_spinlock,flags);
2567 info->idle_mode = idle_mode;
2568 usc_set_txidle( info );
2569 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2570 return 0;
2571
2572 } /* end of mgsl_set_txidle() */
2573
2574 /* mgsl_txenable()
2575 *
2576 * enable or disable the transmitter
2577 *
2578 * Arguments:
2579 *
2580 * info pointer to device instance data
2581 * enable 1 = enable, 0 = disable
2582 *
2583 * Return Value: 0 if success, otherwise error code
2584 */
2585 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2586 {
2587 unsigned long flags;
2588
2589 if (debug_level >= DEBUG_LEVEL_INFO)
2590 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2591 info->device_name, enable);
2592
2593 spin_lock_irqsave(&info->irq_spinlock,flags);
2594 if ( enable ) {
2595 if ( !info->tx_enabled ) {
2596
2597 usc_start_transmitter(info);
2598 /*--------------------------------------------------
2599 * if HDLC/SDLC Loop mode, attempt to insert the
2600 * station in the 'loop' by setting CMR:13. Upon
2601 * receipt of the next GoAhead (RxAbort) sequence,
2602 * the OnLoop indicator (CCSR:7) should go active
2603 * to indicate that we are on the loop
2604 *--------------------------------------------------*/
2605 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2606 usc_loopmode_insert_request( info );
2607 }
2608 } else {
2609 if ( info->tx_enabled )
2610 usc_stop_transmitter(info);
2611 }
2612 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2613 return 0;
2614
2615 } /* end of mgsl_txenable() */
2616
2617 /* mgsl_txabort() abort send HDLC frame
2618 *
2619 * Arguments: info pointer to device instance data
2620 * Return Value: 0 if success, otherwise error code
2621 */
2622 static int mgsl_txabort(struct mgsl_struct * info)
2623 {
2624 unsigned long flags;
2625
2626 if (debug_level >= DEBUG_LEVEL_INFO)
2627 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2628 info->device_name);
2629
2630 spin_lock_irqsave(&info->irq_spinlock,flags);
2631 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2632 {
2633 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2634 usc_loopmode_cancel_transmit( info );
2635 else
2636 usc_TCmd(info,TCmd_SendAbort);
2637 }
2638 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2639 return 0;
2640
2641 } /* end of mgsl_txabort() */
2642
2643 /* mgsl_rxenable() enable or disable the receiver
2644 *
2645 * Arguments: info pointer to device instance data
2646 * enable 1 = enable, 0 = disable
2647 * Return Value: 0 if success, otherwise error code
2648 */
2649 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2650 {
2651 unsigned long flags;
2652
2653 if (debug_level >= DEBUG_LEVEL_INFO)
2654 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2655 info->device_name, enable);
2656
2657 spin_lock_irqsave(&info->irq_spinlock,flags);
2658 if ( enable ) {
2659 if ( !info->rx_enabled )
2660 usc_start_receiver(info);
2661 } else {
2662 if ( info->rx_enabled )
2663 usc_stop_receiver(info);
2664 }
2665 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2666 return 0;
2667
2668 } /* end of mgsl_rxenable() */
2669
2670 /* mgsl_wait_event() wait for specified event to occur
2671 *
2672 * Arguments: info pointer to device instance data
2673 * mask pointer to bitmask of events to wait for
2674 * Return Value: 0 if successful and bit mask updated with
2675 * of events triggerred,
2676 * otherwise error code
2677 */
2678 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2679 {
2680 unsigned long flags;
2681 int s;
2682 int rc=0;
2683 struct mgsl_icount cprev, cnow;
2684 int events;
2685 int mask;
2686 struct _input_signal_events oldsigs, newsigs;
2687 DECLARE_WAITQUEUE(wait, current);
2688
2689 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2690 if (rc) {
2691 return -EFAULT;
2692 }
2693
2694 if (debug_level >= DEBUG_LEVEL_INFO)
2695 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2696 info->device_name, mask);
2697
2698 spin_lock_irqsave(&info->irq_spinlock,flags);
2699
2700 /* return immediately if state matches requested events */
2701 usc_get_serial_signals(info);
2702 s = info->serial_signals;
2703 events = mask &
2704 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2705 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2706 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2707 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2708 if (events) {
2709 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2710 goto exit;
2711 }
2712
2713 /* save current irq counts */
2714 cprev = info->icount;
2715 oldsigs = info->input_signal_events;
2716
2717 /* enable hunt and idle irqs if needed */
2718 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2719 u16 oldreg = usc_InReg(info,RICR);
2720 u16 newreg = oldreg +
2721 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2722 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2723 if (oldreg != newreg)
2724 usc_OutReg(info, RICR, newreg);
2725 }
2726
2727 set_current_state(TASK_INTERRUPTIBLE);
2728 add_wait_queue(&info->event_wait_q, &wait);
2729
2730 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2731
2732
2733 for(;;) {
2734 schedule();
2735 if (signal_pending(current)) {
2736 rc = -ERESTARTSYS;
2737 break;
2738 }
2739
2740 /* get current irq counts */
2741 spin_lock_irqsave(&info->irq_spinlock,flags);
2742 cnow = info->icount;
2743 newsigs = info->input_signal_events;
2744 set_current_state(TASK_INTERRUPTIBLE);
2745 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2746
2747 /* if no change, wait aborted for some reason */
2748 if (newsigs.dsr_up == oldsigs.dsr_up &&
2749 newsigs.dsr_down == oldsigs.dsr_down &&
2750 newsigs.dcd_up == oldsigs.dcd_up &&
2751 newsigs.dcd_down == oldsigs.dcd_down &&
2752 newsigs.cts_up == oldsigs.cts_up &&
2753 newsigs.cts_down == oldsigs.cts_down &&
2754 newsigs.ri_up == oldsigs.ri_up &&
2755 newsigs.ri_down == oldsigs.ri_down &&
2756 cnow.exithunt == cprev.exithunt &&
2757 cnow.rxidle == cprev.rxidle) {
2758 rc = -EIO;
2759 break;
2760 }
2761
2762 events = mask &
2763 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2764 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2765 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2766 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2767 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2768 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2769 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2770 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2771 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2772 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2773 if (events)
2774 break;
2775
2776 cprev = cnow;
2777 oldsigs = newsigs;
2778 }
2779
2780 remove_wait_queue(&info->event_wait_q, &wait);
2781 set_current_state(TASK_RUNNING);
2782
2783 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2784 spin_lock_irqsave(&info->irq_spinlock,flags);
2785 if (!waitqueue_active(&info->event_wait_q)) {
2786 /* disable enable exit hunt mode/idle rcvd IRQs */
2787 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2788 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2789 }
2790 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2791 }
2792 exit:
2793 if ( rc == 0 )
2794 PUT_USER(rc, events, mask_ptr);
2795
2796 return rc;
2797
2798 } /* end of mgsl_wait_event() */
2799
2800 static int modem_input_wait(struct mgsl_struct *info,int arg)
2801 {
2802 unsigned long flags;
2803 int rc;
2804 struct mgsl_icount cprev, cnow;
2805 DECLARE_WAITQUEUE(wait, current);
2806
2807 /* save current irq counts */
2808 spin_lock_irqsave(&info->irq_spinlock,flags);
2809 cprev = info->icount;
2810 add_wait_queue(&info->status_event_wait_q, &wait);
2811 set_current_state(TASK_INTERRUPTIBLE);
2812 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2813
2814 for(;;) {
2815 schedule();
2816 if (signal_pending(current)) {
2817 rc = -ERESTARTSYS;
2818 break;
2819 }
2820
2821 /* get new irq counts */
2822 spin_lock_irqsave(&info->irq_spinlock,flags);
2823 cnow = info->icount;
2824 set_current_state(TASK_INTERRUPTIBLE);
2825 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2826
2827 /* if no change, wait aborted for some reason */
2828 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2829 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2830 rc = -EIO;
2831 break;
2832 }
2833
2834 /* check for change in caller specified modem input */
2835 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2836 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2837 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2838 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2839 rc = 0;
2840 break;
2841 }
2842
2843 cprev = cnow;
2844 }
2845 remove_wait_queue(&info->status_event_wait_q, &wait);
2846 set_current_state(TASK_RUNNING);
2847 return rc;
2848 }
2849
2850 /* return the state of the serial control and status signals
2851 */
2852 static int tiocmget(struct tty_struct *tty, struct file *file)
2853 {
2854 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2855 unsigned int result;
2856 unsigned long flags;
2857
2858 spin_lock_irqsave(&info->irq_spinlock,flags);
2859 usc_get_serial_signals(info);
2860 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2861
2862 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2863 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2864 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2865 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2866 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2867 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2868
2869 if (debug_level >= DEBUG_LEVEL_INFO)
2870 printk("%s(%d):%s tiocmget() value=%08X\n",
2871 __FILE__,__LINE__, info->device_name, result );
2872 return result;
2873 }
2874
2875 /* set modem control signals (DTR/RTS)
2876 */
2877 static int tiocmset(struct tty_struct *tty, struct file *file,
2878 unsigned int set, unsigned int clear)
2879 {
2880 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2881 unsigned long flags;
2882
2883 if (debug_level >= DEBUG_LEVEL_INFO)
2884 printk("%s(%d):%s tiocmset(%x,%x)\n",
2885 __FILE__,__LINE__,info->device_name, set, clear);
2886
2887 if (set & TIOCM_RTS)
2888 info->serial_signals |= SerialSignal_RTS;
2889 if (set & TIOCM_DTR)
2890 info->serial_signals |= SerialSignal_DTR;
2891 if (clear & TIOCM_RTS)
2892 info->serial_signals &= ~SerialSignal_RTS;
2893 if (clear & TIOCM_DTR)
2894 info->serial_signals &= ~SerialSignal_DTR;
2895
2896 spin_lock_irqsave(&info->irq_spinlock,flags);
2897 usc_set_serial_signals(info);
2898 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2899
2900 return 0;
2901 }
2902
2903 /* mgsl_break() Set or clear transmit break condition
2904 *
2905 * Arguments: tty pointer to tty instance data
2906 * break_state -1=set break condition, 0=clear
2907 * Return Value: None
2908 */
2909 static void mgsl_break(struct tty_struct *tty, int break_state)
2910 {
2911 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2912 unsigned long flags;
2913
2914 if (debug_level >= DEBUG_LEVEL_INFO)
2915 printk("%s(%d):mgsl_break(%s,%d)\n",
2916 __FILE__,__LINE__, info->device_name, break_state);
2917
2918 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2919 return;
2920
2921 spin_lock_irqsave(&info->irq_spinlock,flags);
2922 if (break_state == -1)
2923 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2924 else
2925 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2926 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2927
2928 } /* end of mgsl_break() */
2929
2930 /* mgsl_ioctl() Service an IOCTL request
2931 *
2932 * Arguments:
2933 *
2934 * tty pointer to tty instance data
2935 * file pointer to associated file object for device
2936 * cmd IOCTL command code
2937 * arg command argument/context
2938 *
2939 * Return Value: 0 if success, otherwise error code
2940 */
2941 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2942 unsigned int cmd, unsigned long arg)
2943 {
2944 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2945
2946 if (debug_level >= DEBUG_LEVEL_INFO)
2947 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2948 info->device_name, cmd );
2949
2950 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2951 return -ENODEV;
2952
2953 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2954 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2955 if (tty->flags & (1 << TTY_IO_ERROR))
2956 return -EIO;
2957 }
2958
2959 return mgsl_ioctl_common(info, cmd, arg);
2960 }
2961
2962 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2963 {
2964 int error;
2965 struct mgsl_icount cnow; /* kernel counter temps */
2966 void __user *argp = (void __user *)arg;
2967 struct serial_icounter_struct __user *p_cuser; /* user space */
2968 unsigned long flags;
2969
2970 switch (cmd) {
2971 case MGSL_IOCGPARAMS:
2972 return mgsl_get_params(info, argp);
2973 case MGSL_IOCSPARAMS:
2974 return mgsl_set_params(info, argp);
2975 case MGSL_IOCGTXIDLE:
2976 return mgsl_get_txidle(info, argp);
2977 case MGSL_IOCSTXIDLE:
2978 return mgsl_set_txidle(info,(int)arg);
2979 case MGSL_IOCTXENABLE:
2980 return mgsl_txenable(info,(int)arg);
2981 case MGSL_IOCRXENABLE:
2982 return mgsl_rxenable(info,(int)arg);
2983 case MGSL_IOCTXABORT:
2984 return mgsl_txabort(info);
2985 case MGSL_IOCGSTATS:
2986 return mgsl_get_stats(info, argp);
2987 case MGSL_IOCWAITEVENT:
2988 return mgsl_wait_event(info, argp);
2989 case MGSL_IOCLOOPTXDONE:
2990 return mgsl_loopmode_send_done(info);
2991 /* Wait for modem input (DCD,RI,DSR,CTS) change
2992 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2993 */
2994 case TIOCMIWAIT:
2995 return modem_input_wait(info,(int)arg);
2996
2997 /*
2998 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2999 * Return: write counters to the user passed counter struct
3000 * NB: both 1->0 and 0->1 transitions are counted except for
3001 * RI where only 0->1 is counted.
3002 */
3003 case TIOCGICOUNT:
3004 spin_lock_irqsave(&info->irq_spinlock,flags);
3005 cnow = info->icount;
3006 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3007 p_cuser = argp;
3008 PUT_USER(error,cnow.cts, &p_cuser->cts);
3009 if (error) return error;
3010 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3011 if (error) return error;
3012 PUT_USER(error,cnow.rng, &p_cuser->rng);
3013 if (error) return error;
3014 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3015 if (error) return error;
3016 PUT_USER(error,cnow.rx, &p_cuser->rx);
3017 if (error) return error;
3018 PUT_USER(error,cnow.tx, &p_cuser->tx);
3019 if (error) return error;
3020 PUT_USER(error,cnow.frame, &p_cuser->frame);
3021 if (error) return error;
3022 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3023 if (error) return error;
3024 PUT_USER(error,cnow.parity, &p_cuser->parity);
3025 if (error) return error;
3026 PUT_USER(error,cnow.brk, &p_cuser->brk);
3027 if (error) return error;
3028 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3029 if (error) return error;
3030 return 0;
3031 default:
3032 return -ENOIOCTLCMD;
3033 }
3034 return 0;
3035 }
3036
3037 /* mgsl_set_termios()
3038 *
3039 * Set new termios settings
3040 *
3041 * Arguments:
3042 *
3043 * tty pointer to tty structure
3044 * termios pointer to buffer to hold returned old termios
3045 *
3046 * Return Value: None
3047 */
3048 static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3049 {
3050 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3051 unsigned long flags;
3052
3053 if (debug_level >= DEBUG_LEVEL_INFO)
3054 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3055 tty->driver->name );
3056
3057 mgsl_change_params(info);
3058
3059 /* Handle transition to B0 status */
3060 if (old_termios->c_cflag & CBAUD &&
3061 !(tty->termios->c_cflag & CBAUD)) {
3062 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3063 spin_lock_irqsave(&info->irq_spinlock,flags);
3064 usc_set_serial_signals(info);
3065 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3066 }
3067
3068 /* Handle transition away from B0 status */
3069 if (!(old_termios->c_cflag & CBAUD) &&
3070 tty->termios->c_cflag & CBAUD) {
3071 info->serial_signals |= SerialSignal_DTR;
3072 if (!(tty->termios->c_cflag & CRTSCTS) ||
3073 !test_bit(TTY_THROTTLED, &tty->flags)) {
3074 info->serial_signals |= SerialSignal_RTS;
3075 }
3076 spin_lock_irqsave(&info->irq_spinlock,flags);
3077 usc_set_serial_signals(info);
3078 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3079 }
3080
3081 /* Handle turning off CRTSCTS */
3082 if (old_termios->c_cflag & CRTSCTS &&
3083 !(tty->termios->c_cflag & CRTSCTS)) {
3084 tty->hw_stopped = 0;
3085 mgsl_start(tty);
3086 }
3087
3088 } /* end of mgsl_set_termios() */
3089
3090 /* mgsl_close()
3091 *
3092 * Called when port is closed. Wait for remaining data to be
3093 * sent. Disable port and free resources.
3094 *
3095 * Arguments:
3096 *
3097 * tty pointer to open tty structure
3098 * filp pointer to open file object
3099 *
3100 * Return Value: None
3101 */
3102 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3103 {
3104 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3105
3106 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3107 return;
3108
3109 if (debug_level >= DEBUG_LEVEL_INFO)
3110 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3111 __FILE__,__LINE__, info->device_name, info->count);
3112
3113 if (!info->count)
3114 return;
3115
3116 if (tty_hung_up_p(filp))
3117 goto cleanup;
3118
3119 if ((tty->count == 1) && (info->count != 1)) {
3120 /*
3121 * tty->count is 1 and the tty structure will be freed.
3122 * info->count should be one in this case.
3123 * if it's not, correct it so that the port is shutdown.
3124 */
3125 printk("mgsl_close: bad refcount; tty->count is 1, "
3126 "info->count is %d\n", info->count);
3127 info->count = 1;
3128 }
3129
3130 info->count--;
3131
3132 /* if at least one open remaining, leave hardware active */
3133 if (info->count)
3134 goto cleanup;
3135
3136 info->flags |= ASYNC_CLOSING;
3137
3138 /* set tty->closing to notify line discipline to
3139 * only process XON/XOFF characters. Only the N_TTY
3140 * discipline appears to use this (ppp does not).
3141 */
3142 tty->closing = 1;
3143
3144 /* wait for transmit data to clear all layers */
3145
3146 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3147 if (debug_level >= DEBUG_LEVEL_INFO)
3148 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3149 __FILE__,__LINE__, info->device_name );
3150 tty_wait_until_sent(tty, info->closing_wait);
3151 }
3152
3153 if (info->flags & ASYNC_INITIALIZED)
3154 mgsl_wait_until_sent(tty, info->timeout);
3155
3156 if (tty->driver->flush_buffer)
3157 tty->driver->flush_buffer(tty);
3158
3159 tty_ldisc_flush(tty);
3160
3161 shutdown(info);
3162
3163 tty->closing = 0;
3164 info->tty = NULL;
3165
3166 if (info->blocked_open) {
3167 if (info->close_delay) {
3168 msleep_interruptible(jiffies_to_msecs(info->close_delay));
3169 }
3170 wake_up_interruptible(&info->open_wait);
3171 }
3172
3173 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3174
3175 wake_up_interruptible(&info->close_wait);
3176
3177 cleanup:
3178 if (debug_level >= DEBUG_LEVEL_INFO)
3179 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3180 tty->driver->name, info->count);
3181
3182 } /* end of mgsl_close() */
3183
3184 /* mgsl_wait_until_sent()
3185 *
3186 * Wait until the transmitter is empty.
3187 *
3188 * Arguments:
3189 *
3190 * tty pointer to tty info structure
3191 * timeout time to wait for send completion
3192 *
3193 * Return Value: None
3194 */
3195 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3196 {
3197 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3198 unsigned long orig_jiffies, char_time;
3199
3200 if (!info )
3201 return;
3202
3203 if (debug_level >= DEBUG_LEVEL_INFO)
3204 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3205 __FILE__,__LINE__, info->device_name );
3206
3207 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3208 return;
3209
3210 if (!(info->flags & ASYNC_INITIALIZED))
3211 goto exit;
3212
3213 orig_jiffies = jiffies;
3214
3215 /* Set check interval to 1/5 of estimated time to
3216 * send a character, and make it at least 1. The check
3217 * interval should also be less than the timeout.
3218 * Note: use tight timings here to satisfy the NIST-PCTS.
3219 */
3220
3221 if ( info->params.data_rate ) {
3222 char_time = info->timeout/(32 * 5);
3223 if (!char_time)
3224 char_time++;
3225 } else
3226 char_time = 1;
3227
3228 if (timeout)
3229 char_time = min_t(unsigned long, char_time, timeout);
3230
3231 if ( info->params.mode == MGSL_MODE_HDLC ||
3232 info->params.mode == MGSL_MODE_RAW ) {
3233 while (info->tx_active) {
3234 msleep_interruptible(jiffies_to_msecs(char_time));
3235 if (signal_pending(current))
3236 break;
3237 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3238 break;
3239 }
3240 } else {
3241 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3242 info->tx_enabled) {
3243 msleep_interruptible(jiffies_to_msecs(char_time));
3244 if (signal_pending(current))
3245 break;
3246 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3247 break;
3248 }
3249 }
3250
3251 exit:
3252 if (debug_level >= DEBUG_LEVEL_INFO)
3253 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3254 __FILE__,__LINE__, info->device_name );
3255
3256 } /* end of mgsl_wait_until_sent() */
3257
3258 /* mgsl_hangup()
3259 *
3260 * Called by tty_hangup() when a hangup is signaled.
3261 * This is the same as to closing all open files for the port.
3262 *
3263 * Arguments: tty pointer to associated tty object
3264 * Return Value: None
3265 */
3266 static void mgsl_hangup(struct tty_struct *tty)
3267 {
3268 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3269
3270 if (debug_level >= DEBUG_LEVEL_INFO)
3271 printk("%s(%d):mgsl_hangup(%s)\n",
3272 __FILE__,__LINE__, info->device_name );
3273
3274 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3275 return;
3276
3277 mgsl_flush_buffer(tty);
3278 shutdown(info);
3279
3280 info->count = 0;
3281 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3282 info->tty = NULL;
3283
3284 wake_up_interruptible(&info->open_wait);
3285
3286 } /* end of mgsl_hangup() */
3287
3288 /* block_til_ready()
3289 *
3290 * Block the current process until the specified port
3291 * is ready to be opened.
3292 *
3293 * Arguments:
3294 *
3295 * tty pointer to tty info structure
3296 * filp pointer to open file object
3297 * info pointer to device instance data
3298 *
3299 * Return Value: 0 if success, otherwise error code
3300 */
3301 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3302 struct mgsl_struct *info)
3303 {
3304 DECLARE_WAITQUEUE(wait, current);
3305 int retval;
3306 bool do_clocal = false;
3307 bool extra_count = false;
3308 unsigned long flags;
3309
3310 if (debug_level >= DEBUG_LEVEL_INFO)
3311 printk("%s(%d):block_til_ready on %s\n",
3312 __FILE__,__LINE__, tty->driver->name );
3313
3314 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3315 /* nonblock mode is set or port is not enabled */
3316 info->flags |= ASYNC_NORMAL_ACTIVE;
3317 return 0;
3318 }
3319
3320 if (tty->termios->c_cflag & CLOCAL)
3321 do_clocal = true;
3322
3323 /* Wait for carrier detect and the line to become
3324 * free (i.e., not in use by the callout). While we are in
3325 * this loop, info->count is dropped by one, so that
3326 * mgsl_close() knows when to free things. We restore it upon
3327 * exit, either normal or abnormal.
3328 */
3329
3330 retval = 0;
3331 add_wait_queue(&info->open_wait, &wait);
3332
3333 if (debug_level >= DEBUG_LEVEL_INFO)
3334 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3335 __FILE__,__LINE__, tty->driver->name, info->count );
3336
3337 spin_lock_irqsave(&info->irq_spinlock, flags);
3338 if (!tty_hung_up_p(filp)) {
3339 extra_count = true;
3340 info->count--;
3341 }
3342 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3343 info->blocked_open++;
3344
3345 while (1) {
3346 if (tty->termios->c_cflag & CBAUD) {
3347 spin_lock_irqsave(&info->irq_spinlock,flags);
3348 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3349 usc_set_serial_signals(info);
3350 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3351 }
3352
3353 set_current_state(TASK_INTERRUPTIBLE);
3354
3355 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3356 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3357 -EAGAIN : -ERESTARTSYS;
3358 break;
3359 }
3360
3361 spin_lock_irqsave(&info->irq_spinlock,flags);
3362 usc_get_serial_signals(info);
3363 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3364
3365 if (!(info->flags & ASYNC_CLOSING) &&
3366 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3367 break;
3368 }
3369
3370 if (signal_pending(current)) {
3371 retval = -ERESTARTSYS;
3372 break;
3373 }
3374
3375 if (debug_level >= DEBUG_LEVEL_INFO)
3376 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3377 __FILE__,__LINE__, tty->driver->name, info->count );
3378
3379 schedule();
3380 }
3381
3382 set_current_state(TASK_RUNNING);
3383 remove_wait_queue(&info->open_wait, &wait);
3384
3385 if (extra_count)
3386 info->count++;
3387 info->blocked_open--;
3388
3389 if (debug_level >= DEBUG_LEVEL_INFO)
3390 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3391 __FILE__,__LINE__, tty->driver->name, info->count );
3392
3393 if (!retval)
3394 info->flags |= ASYNC_NORMAL_ACTIVE;
3395
3396 return retval;
3397
3398 } /* end of block_til_ready() */
3399
3400 /* mgsl_open()
3401 *
3402 * Called when a port is opened. Init and enable port.
3403 * Perform serial-specific initialization for the tty structure.
3404 *
3405 * Arguments: tty pointer to tty info structure
3406 * filp associated file pointer
3407 *
3408 * Return Value: 0 if success, otherwise error code
3409 */
3410 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3411 {
3412 struct mgsl_struct *info;
3413 int retval, line;
3414 unsigned long flags;
3415
3416 /* verify range of specified line number */
3417 line = tty->index;
3418 if ((line < 0) || (line >= mgsl_device_count)) {
3419 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3420 __FILE__,__LINE__,line);
3421 return -ENODEV;
3422 }
3423
3424 /* find the info structure for the specified line */
3425 info = mgsl_device_list;
3426 while(info && info->line != line)
3427 info = info->next_device;
3428 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3429 return -ENODEV;
3430
3431 tty->driver_data = info;
3432 info->tty = tty;
3433
3434 if (debug_level >= DEBUG_LEVEL_INFO)
3435 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3436 __FILE__,__LINE__,tty->driver->name, info->count);
3437
3438 /* If port is closing, signal caller to try again */
3439 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
3440 if (info->flags & ASYNC_CLOSING)
3441 interruptible_sleep_on(&info->close_wait);
3442 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
3443 -EAGAIN : -ERESTARTSYS);
3444 goto cleanup;
3445 }
3446
3447 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3448
3449 spin_lock_irqsave(&info->netlock, flags);
3450 if (info->netcount) {
3451 retval = -EBUSY;
3452 spin_unlock_irqrestore(&info->netlock, flags);
3453 goto cleanup;
3454 }
3455 info->count++;
3456 spin_unlock_irqrestore(&info->netlock, flags);
3457
3458 if (info->count == 1) {
3459 /* 1st open on this device, init hardware */
3460 retval = startup(info);
3461 if (retval < 0)
3462 goto cleanup;
3463 }
3464
3465 retval = block_til_ready(tty, filp, info);
3466 if (retval) {
3467 if (debug_level >= DEBUG_LEVEL_INFO)
3468 printk("%s(%d):block_til_ready(%s) returned %d\n",
3469 __FILE__,__LINE__, info->device_name, retval);
3470 goto cleanup;
3471 }
3472
3473 if (debug_level >= DEBUG_LEVEL_INFO)
3474 printk("%s(%d):mgsl_open(%s) success\n",
3475 __FILE__,__LINE__, info->device_name);
3476 retval = 0;
3477
3478 cleanup:
3479 if (retval) {
3480 if (tty->count == 1)
3481 info->tty = NULL; /* tty layer will release tty struct */
3482 if(info->count)
3483 info->count--;
3484 }
3485
3486 return retval;
3487
3488 } /* end of mgsl_open() */
3489
3490 /*
3491 * /proc fs routines....
3492 */
3493
3494 static inline int line_info(char *buf, struct mgsl_struct *info)
3495 {
3496 char stat_buf[30];
3497 int ret;
3498 unsigned long flags;
3499
3500 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3501 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3502 info->device_name, info->io_base, info->irq_level,
3503 info->phys_memory_base, info->phys_lcr_base);
3504 } else {
3505 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3506 info->device_name, info->io_base,
3507 info->irq_level, info->dma_level);
3508 }
3509
3510 /* output current serial signal states */
3511 spin_lock_irqsave(&info->irq_spinlock,flags);
3512 usc_get_serial_signals(info);
3513 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3514
3515 stat_buf[0] = 0;
3516 stat_buf[1] = 0;
3517 if (info->serial_signals & SerialSignal_RTS)
3518 strcat(stat_buf, "|RTS");
3519 if (info->serial_signals & SerialSignal_CTS)
3520 strcat(stat_buf, "|CTS");
3521 if (info->serial_signals & SerialSignal_DTR)
3522 strcat(stat_buf, "|DTR");
3523 if (info->serial_signals & SerialSignal_DSR)
3524 strcat(stat_buf, "|DSR");
3525 if (info->serial_signals & SerialSignal_DCD)
3526 strcat(stat_buf, "|CD");
3527 if (info->serial_signals & SerialSignal_RI)
3528 strcat(stat_buf, "|RI");
3529
3530 if (info->params.mode == MGSL_MODE_HDLC ||
3531 info->params.mode == MGSL_MODE_RAW ) {
3532 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3533 info->icount.txok, info->icount.rxok);
3534 if (info->icount.txunder)
3535 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3536 if (info->icount.txabort)
3537 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3538 if (info->icount.rxshort)
3539 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3540 if (info->icount.rxlong)
3541 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3542 if (info->icount.rxover)
3543 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3544 if (info->icount.rxcrc)
3545 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
3546 } else {
3547 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3548 info->icount.tx, info->icount.rx);
3549 if (info->icount.frame)
3550 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3551 if (info->icount.parity)
3552 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3553 if (info->icount.brk)
3554 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3555 if (info->icount.overrun)
3556 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3557 }
3558
3559 /* Append serial signal status to end */
3560 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3561
3562 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3563 info->tx_active,info->bh_requested,info->bh_running,
3564 info->pending_bh);
3565
3566 spin_lock_irqsave(&info->irq_spinlock,flags);
3567 {
3568 u16 Tcsr = usc_InReg( info, TCSR );
3569 u16 Tdmr = usc_InDmaReg( info, TDMR );
3570 u16 Ticr = usc_InReg( info, TICR );
3571 u16 Rscr = usc_InReg( info, RCSR );
3572 u16 Rdmr = usc_InDmaReg( info, RDMR );
3573 u16 Ricr = usc_InReg( info, RICR );
3574 u16 Icr = usc_InReg( info, ICR );
3575 u16 Dccr = usc_InReg( info, DCCR );
3576 u16 Tmr = usc_InReg( info, TMR );
3577 u16 Tccr = usc_InReg( info, TCCR );
3578 u16 Ccar = inw( info->io_base + CCAR );
3579 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3580 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3581 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3582 }
3583 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3584
3585 return ret;
3586
3587 } /* end of line_info() */
3588
3589 /* mgsl_read_proc()
3590 *
3591 * Called to print information about devices
3592 *
3593 * Arguments:
3594 * page page of memory to hold returned info
3595 * start
3596 * off
3597 * count
3598 * eof
3599 * data
3600 *
3601 * Return Value:
3602 */
3603 static int mgsl_read_proc(char *page, char **start, off_t off, int count,
3604 int *eof, void *data)
3605 {
3606 int len = 0, l;
3607 off_t begin = 0;
3608 struct mgsl_struct *info;
3609
3610 len += sprintf(page, "synclink driver:%s\n", driver_version);
3611
3612 info = mgsl_device_list;
3613 while( info ) {
3614 l = line_info(page + len, info);
3615 len += l;
3616 if (len+begin > off+count)
3617 goto done;
3618 if (len+begin < off) {
3619 begin += len;
3620 len = 0;
3621 }
3622 info = info->next_device;
3623 }
3624
3625 *eof = 1;
3626 done:
3627 if (off >= len+begin)
3628 return 0;
3629 *start = page + (off-begin);
3630 return ((count < begin+len-off) ? count : begin+len-off);
3631
3632 } /* end of mgsl_read_proc() */
3633
3634 /* mgsl_allocate_dma_buffers()
3635 *
3636 * Allocate and format DMA buffers (ISA adapter)
3637 * or format shared memory buffers (PCI adapter).
3638 *
3639 * Arguments: info pointer to device instance data
3640 * Return Value: 0 if success, otherwise error
3641 */
3642 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3643 {
3644 unsigned short BuffersPerFrame;
3645
3646 info->last_mem_alloc = 0;
3647
3648 /* Calculate the number of DMA buffers necessary to hold the */
3649 /* largest allowable frame size. Note: If the max frame size is */
3650 /* not an even multiple of the DMA buffer size then we need to */
3651 /* round the buffer count per frame up one. */
3652
3653 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3654 if ( info->max_frame_size % DMABUFFERSIZE )
3655 BuffersPerFrame++;
3656
3657 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3658 /*
3659 * The PCI adapter has 256KBytes of shared memory to use.
3660 * This is 64 PAGE_SIZE buffers.
3661 *
3662 * The first page is used for padding at this time so the
3663 * buffer list does not begin at offset 0 of the PCI
3664 * adapter's shared memory.
3665 *
3666 * The 2nd page is used for the buffer list. A 4K buffer
3667 * list can hold 128 DMA_BUFFER structures at 32 bytes
3668 * each.
3669 *
3670 * This leaves 62 4K pages.
3671 *
3672 * The next N pages are used for transmit frame(s). We
3673 * reserve enough 4K page blocks to hold the required
3674 * number of transmit dma buffers (num_tx_dma_buffers),
3675 * each of MaxFrameSize size.
3676 *
3677 * Of the remaining pages (62-N), determine how many can
3678 * be used to receive full MaxFrameSize inbound frames
3679 */
3680 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3681 info->rx_buffer_count = 62 - info->tx_buffer_count;
3682 } else {
3683 /* Calculate the number of PAGE_SIZE buffers needed for */
3684 /* receive and transmit DMA buffers. */
3685
3686
3687 /* Calculate the number of DMA buffers necessary to */
3688 /* hold 7 max size receive frames and one max size transmit frame. */
3689 /* The receive buffer count is bumped by one so we avoid an */
3690 /* End of List condition if all receive buffers are used when */
3691 /* using linked list DMA buffers. */
3692
3693 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3694 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3695
3696 /*
3697 * limit total TxBuffers & RxBuffers to 62 4K total
3698 * (ala PCI Allocation)
3699 */
3700
3701 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3702 info->rx_buffer_count = 62 - info->tx_buffer_count;
3703
3704 }
3705
3706 if ( debug_level >= DEBUG_LEVEL_INFO )
3707 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3708 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3709
3710 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3711 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3712 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3713 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3714 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3715 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3716 return -ENOMEM;
3717 }
3718
3719 mgsl_reset_rx_dma_buffers( info );
3720 mgsl_reset_tx_dma_buffers( info );
3721
3722 return 0;
3723
3724 } /* end of mgsl_allocate_dma_buffers() */
3725
3726 /*
3727 * mgsl_alloc_buffer_list_memory()
3728 *
3729 * Allocate a common DMA buffer for use as the
3730 * receive and transmit buffer lists.
3731 *
3732 * A buffer list is a set of buffer entries where each entry contains
3733 * a pointer to an actual buffer and a pointer to the next buffer entry
3734 * (plus some other info about the buffer).
3735 *
3736 * The buffer entries for a list are built to form a circular list so
3737 * that when the entire list has been traversed you start back at the
3738 * beginning.
3739 *
3740 * This function allocates memory for just the buffer entries.
3741 * The links (pointer to next entry) are filled in with the physical
3742 * address of the next entry so the adapter can navigate the list
3743 * using bus master DMA. The pointers to the actual buffers are filled
3744 * out later when the actual buffers are allocated.
3745 *
3746 * Arguments: info pointer to device instance data
3747 * Return Value: 0 if success, otherwise error
3748 */
3749 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3750 {
3751 unsigned int i;
3752
3753 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3754 /* PCI adapter uses shared memory. */
3755 info->buffer_list = info->memory_base + info->last_mem_alloc;
3756 info->buffer_list_phys = info->last_mem_alloc;
3757 info->last_mem_alloc += BUFFERLISTSIZE;
3758 } else {
3759 /* ISA adapter uses system memory. */
3760 /* The buffer lists are allocated as a common buffer that both */
3761 /* the processor and adapter can access. This allows the driver to */
3762 /* inspect portions of the buffer while other portions are being */
3763 /* updated by the adapter using Bus Master DMA. */
3764
3765 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3766 if (info->buffer_list == NULL)
3767 return -ENOMEM;
3768 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3769 }
3770
3771 /* We got the memory for the buffer entry lists. */
3772 /* Initialize the memory block to all zeros. */
3773 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3774
3775 /* Save virtual address pointers to the receive and */
3776 /* transmit buffer lists. (Receive 1st). These pointers will */
3777 /* be used by the processor to access the lists. */
3778 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3779 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3780 info->tx_buffer_list += info->rx_buffer_count;
3781
3782 /*
3783 * Build the links for the buffer entry lists such that
3784 * two circular lists are built. (Transmit and Receive).
3785 *
3786 * Note: the links are physical addresses
3787 * which are read by the adapter to determine the next
3788 * buffer entry to use.
3789 */
3790
3791 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3792 /* calculate and store physical address of this buffer entry */
3793 info->rx_buffer_list[i].phys_entry =
3794 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3795
3796 /* calculate and store physical address of */
3797 /* next entry in cirular list of entries */
3798
3799 info->rx_buffer_list[i].link = info->buffer_list_phys;
3800
3801 if ( i < info->rx_buffer_count - 1 )
3802 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3803 }
3804
3805 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3806 /* calculate and store physical address of this buffer entry */
3807 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3808 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3809
3810 /* calculate and store physical address of */
3811 /* next entry in cirular list of entries */
3812
3813 info->tx_buffer_list[i].link = info->buffer_list_phys +
3814 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3815
3816 if ( i < info->tx_buffer_count - 1 )
3817 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3818 }
3819
3820 return 0;
3821
3822 } /* end of mgsl_alloc_buffer_list_memory() */
3823
3824 /* Free DMA buffers allocated for use as the
3825 * receive and transmit buffer lists.
3826 * Warning:
3827 *
3828 * The data transfer buffers associated with the buffer list
3829 * MUST be freed before freeing the buffer list itself because
3830 * the buffer list contains the information necessary to free
3831 * the individual buffers!
3832 */
3833 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3834 {
3835 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3836 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3837
3838 info->buffer_list = NULL;
3839 info->rx_buffer_list = NULL;
3840 info->tx_buffer_list = NULL;
3841
3842 } /* end of mgsl_free_buffer_list_memory() */
3843
3844 /*
3845 * mgsl_alloc_frame_memory()
3846 *
3847 * Allocate the frame DMA buffers used by the specified buffer list.
3848 * Each DMA buffer will be one memory page in size. This is necessary
3849 * because memory can fragment enough that it may be impossible
3850 * contiguous pages.
3851 *
3852 * Arguments:
3853 *
3854 * info pointer to device instance data
3855 * BufferList pointer to list of buffer entries
3856 * Buffercount count of buffer entries in buffer list
3857 *
3858 * Return Value: 0 if success, otherwise -ENOMEM
3859 */
3860 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3861 {
3862 int i;
3863 u32 phys_addr;
3864
3865 /* Allocate page sized buffers for the receive buffer list */
3866
3867 for ( i = 0; i < Buffercount; i++ ) {
3868 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3869 /* PCI adapter uses shared memory buffers. */
3870 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3871 phys_addr = info->last_mem_alloc;
3872 info->last_mem_alloc += DMABUFFERSIZE;
3873 } else {
3874 /* ISA adapter uses system memory. */
3875 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3876 if (BufferList[i].virt_addr == NULL)
3877 return -ENOMEM;
3878 phys_addr = (u32)(BufferList[i].dma_addr);
3879 }
3880 BufferList[i].phys_addr = phys_addr;
3881 }
3882
3883 return 0;
3884
3885 } /* end of mgsl_alloc_frame_memory() */
3886
3887 /*
3888 * mgsl_free_frame_memory()
3889 *
3890 * Free the buffers associated with
3891 * each buffer entry of a buffer list.
3892 *
3893 * Arguments:
3894 *
3895 * info pointer to device instance data
3896 * BufferList pointer to list of buffer entries
3897 * Buffercount count of buffer entries in buffer list
3898 *
3899 * Return Value: None
3900 */
3901 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3902 {
3903 int i;
3904
3905 if ( BufferList ) {
3906 for ( i = 0 ; i < Buffercount ; i++ ) {
3907 if ( BufferList[i].virt_addr ) {
3908 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3909 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3910 BufferList[i].virt_addr = NULL;
3911 }
3912 }
3913 }
3914
3915 } /* end of mgsl_free_frame_memory() */
3916
3917 /* mgsl_free_dma_buffers()
3918 *
3919 * Free DMA buffers
3920 *
3921 * Arguments: info pointer to device instance data
3922 * Return Value: None
3923 */
3924 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3925 {
3926 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3927 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3928 mgsl_free_buffer_list_memory( info );
3929
3930 } /* end of mgsl_free_dma_buffers() */
3931
3932
3933 /*
3934 * mgsl_alloc_intermediate_rxbuffer_memory()
3935 *
3936 * Allocate a buffer large enough to hold max_frame_size. This buffer
3937 * is used to pass an assembled frame to the line discipline.
3938 *
3939 * Arguments:
3940 *
3941 * info pointer to device instance data
3942 *
3943 * Return Value: 0 if success, otherwise -ENOMEM
3944 */
3945 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3946 {
3947 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3948 if ( info->intermediate_rxbuffer == NULL )
3949 return -ENOMEM;
3950
3951 return 0;
3952
3953 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3954
3955 /*
3956 * mgsl_free_intermediate_rxbuffer_memory()
3957 *
3958 *
3959 * Arguments:
3960 *
3961 * info pointer to device instance data
3962 *
3963 * Return Value: None
3964 */
3965 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3966 {
3967 kfree(info->intermediate_rxbuffer);
3968 info->intermediate_rxbuffer = NULL;
3969
3970 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3971
3972 /*
3973 * mgsl_alloc_intermediate_txbuffer_memory()
3974 *
3975 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3976 * This buffer is used to load transmit frames into the adapter's dma transfer
3977 * buffers when there is sufficient space.
3978 *
3979 * Arguments:
3980 *
3981 * info pointer to device instance data
3982 *
3983 * Return Value: 0 if success, otherwise -ENOMEM
3984 */
3985 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3986 {
3987 int i;
3988
3989 if ( debug_level >= DEBUG_LEVEL_INFO )
3990 printk("%s %s(%d) allocating %d tx holding buffers\n",
3991 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3992
3993 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3994
3995 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3996 info->tx_holding_buffers[i].buffer =
3997 kmalloc(info->max_frame_size, GFP_KERNEL);
3998 if (info->tx_holding_buffers[i].buffer == NULL) {
3999 for (--i; i >= 0; i--) {
4000 kfree(info->tx_holding_buffers[i].buffer);
4001 info->tx_holding_buffers[i].buffer = NULL;
4002 }
4003 return -ENOMEM;
4004 }
4005 }
4006
4007 return 0;
4008
4009 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4010
4011 /*
4012 * mgsl_free_intermediate_txbuffer_memory()
4013 *
4014 *
4015 * Arguments:
4016 *
4017 * info pointer to device instance data
4018 *
4019 * Return Value: None
4020 */
4021 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4022 {
4023 int i;
4024
4025 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4026 kfree(info->tx_holding_buffers[i].buffer);
4027 info->tx_holding_buffers[i].buffer = NULL;
4028 }
4029
4030 info->get_tx_holding_index = 0;
4031 info->put_tx_holding_index = 0;
4032 info->tx_holding_count = 0;
4033
4034 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4035
4036
4037 /*
4038 * load_next_tx_holding_buffer()
4039 *
4040 * attempts to load the next buffered tx request into the
4041 * tx dma buffers
4042 *
4043 * Arguments:
4044 *
4045 * info pointer to device instance data
4046 *
4047 * Return Value: true if next buffered tx request loaded
4048 * into adapter's tx dma buffer,
4049 * false otherwise
4050 */
4051 static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4052 {
4053 bool ret = false;
4054
4055 if ( info->tx_holding_count ) {
4056 /* determine if we have enough tx dma buffers
4057 * to accommodate the next tx frame
4058 */
4059 struct tx_holding_buffer *ptx =
4060 &info->tx_holding_buffers[info->get_tx_holding_index];
4061 int num_free = num_free_tx_dma_buffers(info);
4062 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4063 if ( ptx->buffer_size % DMABUFFERSIZE )
4064 ++num_needed;
4065
4066 if (num_needed <= num_free) {
4067 info->xmit_cnt = ptx->buffer_size;
4068 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4069
4070 --info->tx_holding_count;
4071 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4072 info->get_tx_holding_index=0;
4073
4074 /* restart transmit timer */
4075 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4076
4077 ret = true;
4078 }
4079 }
4080
4081 return ret;
4082 }
4083
4084 /*
4085 * save_tx_buffer_request()
4086 *
4087 * attempt to store transmit frame request for later transmission
4088 *
4089 * Arguments:
4090 *
4091 * info pointer to device instance data
4092 * Buffer pointer to buffer containing frame to load
4093 * BufferSize size in bytes of frame in Buffer
4094 *
4095 * Return Value: 1 if able to store, 0 otherwise
4096 */
4097 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4098 {
4099 struct tx_holding_buffer *ptx;
4100
4101 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4102 return 0; /* all buffers in use */
4103 }
4104
4105 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4106 ptx->buffer_size = BufferSize;
4107 memcpy( ptx->buffer, Buffer, BufferSize);
4108
4109 ++info->tx_holding_count;
4110 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4111 info->put_tx_holding_index=0;
4112
4113 return 1;
4114 }
4115
4116 static int mgsl_claim_resources(struct mgsl_struct *info)
4117 {
4118 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4119 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4120 __FILE__,__LINE__,info->device_name, info->io_base);
4121 return -ENODEV;
4122 }
4123 info->io_addr_requested = true;
4124
4125 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4126 info->device_name, info ) < 0 ) {
4127 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4128 __FILE__,__LINE__,info->device_name, info->irq_level );
4129 goto errout;
4130 }
4131 info->irq_requested = true;
4132
4133 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4134 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4135 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4136 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4137 goto errout;
4138 }
4139 info->shared_mem_requested = true;
4140 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4141 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4142 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4143 goto errout;
4144 }
4145 info->lcr_mem_requested = true;
4146
4147 info->memory_base = ioremap(info->phys_memory_base,0x40000);
4148 if (!info->memory_base) {
4149 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4150 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4151 goto errout;
4152 }
4153
4154 if ( !mgsl_memory_test(info) ) {
4155 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4156 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4157 goto errout;
4158 }
4159
4160 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
4161 if (!info->lcr_base) {
4162 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4163 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4164 goto errout;
4165 }
4166
4167 } else {
4168 /* claim DMA channel */
4169
4170 if (request_dma(info->dma_level,info->device_name) < 0){
4171 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4172 __FILE__,__LINE__,info->device_name, info->dma_level );
4173 mgsl_release_resources( info );
4174 return -ENODEV;
4175 }
4176 info->dma_requested = true;
4177
4178 /* ISA adapter uses bus master DMA */
4179 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4180 enable_dma(info->dma_level);
4181 }
4182
4183 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4184 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4185 __FILE__,__LINE__,info->device_name, info->dma_level );
4186 goto errout;
4187 }
4188
4189 return 0;
4190 errout:
4191 mgsl_release_resources(info);
4192 return -ENODEV;
4193
4194 } /* end of mgsl_claim_resources() */
4195
4196 static void mgsl_release_resources(struct mgsl_struct *info)
4197 {
4198 if ( debug_level >= DEBUG_LEVEL_INFO )
4199 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4200 __FILE__,__LINE__,info->device_name );
4201
4202 if ( info->irq_requested ) {
4203 free_irq(info->irq_level, info);
4204 info->irq_requested = false;
4205 }
4206 if ( info->dma_requested ) {
4207 disable_dma(info->dma_level);
4208 free_dma(info->dma_level);
4209 info->dma_requested = false;
4210 }
4211 mgsl_free_dma_buffers(info);
4212 mgsl_free_intermediate_rxbuffer_memory(info);
4213 mgsl_free_intermediate_txbuffer_memory(info);
4214
4215 if ( info->io_addr_requested ) {
4216 release_region(info->io_base,info->io_addr_size);
4217 info->io_addr_requested = false;
4218 }
4219 if ( info->shared_mem_requested ) {
4220 release_mem_region(info->phys_memory_base,0x40000);
4221 info->shared_mem_requested = false;
4222 }
4223 if ( info->lcr_mem_requested ) {
4224 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4225 info->lcr_mem_requested = false;
4226 }
4227 if (info->memory_base){
4228 iounmap(info->memory_base);
4229 info->memory_base = NULL;
4230 }
4231 if (info->lcr_base){
4232 iounmap(info->lcr_base - info->lcr_offset);
4233 info->lcr_base = NULL;
4234 }
4235
4236 if ( debug_level >= DEBUG_LEVEL_INFO )
4237 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4238 __FILE__,__LINE__,info->device_name );
4239
4240 } /* end of mgsl_release_resources() */
4241
4242 /* mgsl_add_device()
4243 *
4244 * Add the specified device instance data structure to the
4245 * global linked list of devices and increment the device count.
4246 *
4247 * Arguments: info pointer to device instance data
4248 * Return Value: None
4249 */
4250 static void mgsl_add_device( struct mgsl_struct *info )
4251 {
4252 info->next_device = NULL;
4253 info->line = mgsl_device_count;
4254 sprintf(info->device_name,"ttySL%d",info->line);
4255
4256 if (info->line < MAX_TOTAL_DEVICES) {
4257 if (maxframe[info->line])
4258 info->max_frame_size = maxframe[info->line];
4259 info->dosyncppp = dosyncppp[info->line];
4260
4261 if (txdmabufs[info->line]) {
4262 info->num_tx_dma_buffers = txdmabufs[info->line];
4263 if (info->num_tx_dma_buffers < 1)
4264 info->num_tx_dma_buffers = 1;
4265 }
4266
4267 if (txholdbufs[info->line]) {
4268 info->num_tx_holding_buffers = txholdbufs[info->line];
4269 if (info->num_tx_holding_buffers < 1)
4270 info->num_tx_holding_buffers = 1;
4271 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4272 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4273 }
4274 }
4275
4276 mgsl_device_count++;
4277
4278 if ( !mgsl_device_list )
4279 mgsl_device_list = info;
4280 else {
4281 struct mgsl_struct *current_dev = mgsl_device_list;
4282 while( current_dev->next_device )
4283 current_dev = current_dev->next_device;
4284 current_dev->next_device = info;
4285 }
4286
4287 if ( info->max_frame_size < 4096 )
4288 info->max_frame_size = 4096;
4289 else if ( info->max_frame_size > 65535 )
4290 info->max_frame_size = 65535;
4291
4292 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4293 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4294 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4295 info->phys_memory_base, info->phys_lcr_base,
4296 info->max_frame_size );
4297 } else {
4298 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4299 info->device_name, info->io_base, info->irq_level, info->dma_level,
4300 info->max_frame_size );
4301 }
4302
4303 #if SYNCLINK_GENERIC_HDLC
4304 hdlcdev_init(info);
4305 #endif
4306
4307 } /* end of mgsl_add_device() */
4308
4309 /* mgsl_allocate_device()
4310 *
4311 * Allocate and initialize a device instance structure
4312 *
4313 * Arguments: none
4314 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4315 */
4316 static struct mgsl_struct* mgsl_allocate_device(void)
4317 {
4318 struct mgsl_struct *info;
4319
4320 info = kzalloc(sizeof(struct mgsl_struct),
4321 GFP_KERNEL);
4322
4323 if (!info) {
4324 printk("Error can't allocate device instance data\n");
4325 } else {
4326 info->magic = MGSL_MAGIC;
4327 INIT_WORK(&info->task, mgsl_bh_handler);
4328 info->max_frame_size = 4096;
4329 info->close_delay = 5*HZ/10;
4330 info->closing_wait = 30*HZ;
4331 init_waitqueue_head(&info->open_wait);
4332 init_waitqueue_head(&info->close_wait);
4333 init_waitqueue_head(&info->status_event_wait_q);
4334 init_waitqueue_head(&info->event_wait_q);
4335 spin_lock_init(&info->irq_spinlock);
4336 spin_lock_init(&info->netlock);
4337 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4338 info->idle_mode = HDLC_TXIDLE_FLAGS;
4339 info->num_tx_dma_buffers = 1;
4340 info->num_tx_holding_buffers = 0;
4341 }
4342
4343 return info;
4344
4345 } /* end of mgsl_allocate_device()*/
4346
4347 static const struct tty_operations mgsl_ops = {
4348 .open = mgsl_open,
4349 .close = mgsl_close,
4350 .write = mgsl_write,
4351 .put_char = mgsl_put_char,
4352 .flush_chars = mgsl_flush_chars,
4353 .write_room = mgsl_write_room,
4354 .chars_in_buffer = mgsl_chars_in_buffer,
4355 .flush_buffer = mgsl_flush_buffer,
4356 .ioctl = mgsl_ioctl,
4357 .throttle = mgsl_throttle,
4358 .unthrottle = mgsl_unthrottle,
4359 .send_xchar = mgsl_send_xchar,
4360 .break_ctl = mgsl_break,
4361 .wait_until_sent = mgsl_wait_until_sent,
4362 .read_proc = mgsl_read_proc,
4363 .set_termios = mgsl_set_termios,
4364 .stop = mgsl_stop,
4365 .start = mgsl_start,
4366 .hangup = mgsl_hangup,
4367 .tiocmget = tiocmget,
4368 .tiocmset = tiocmset,
4369 };
4370
4371 /*
4372 * perform tty device initialization
4373 */
4374 static int mgsl_init_tty(void)
4375 {
4376 int rc;
4377
4378 serial_driver = alloc_tty_driver(128);
4379 if (!serial_driver)
4380 return -ENOMEM;
4381
4382 serial_driver->owner = THIS_MODULE;
4383 serial_driver->driver_name = "synclink";
4384 serial_driver->name = "ttySL";
4385 serial_driver->major = ttymajor;
4386 serial_driver->minor_start = 64;
4387 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4388 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4389 serial_driver->init_termios = tty_std_termios;
4390 serial_driver->init_termios.c_cflag =
4391 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4392 serial_driver->init_termios.c_ispeed = 9600;
4393 serial_driver->init_termios.c_ospeed = 9600;
4394 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4395 tty_set_operations(serial_driver, &mgsl_ops);
4396 if ((rc = tty_register_driver(serial_driver)) < 0) {
4397 printk("%s(%d):Couldn't register serial driver\n",
4398 __FILE__,__LINE__);
4399 put_tty_driver(serial_driver);
4400 serial_driver = NULL;
4401 return rc;
4402 }
4403
4404 printk("%s %s, tty major#%d\n",
4405 driver_name, driver_version,
4406 serial_driver->major);
4407 return 0;
4408 }
4409
4410 /* enumerate user specified ISA adapters
4411 */
4412 static void mgsl_enum_isa_devices(void)
4413 {
4414 struct mgsl_struct *info;
4415 int i;
4416
4417 /* Check for user specified ISA devices */
4418
4419 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4420 if ( debug_level >= DEBUG_LEVEL_INFO )
4421 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4422 io[i], irq[i], dma[i] );
4423
4424 info = mgsl_allocate_device();
4425 if ( !info ) {
4426 /* error allocating device instance data */
4427 if ( debug_level >= DEBUG_LEVEL_ERROR )
4428 printk( "can't allocate device instance data.\n");
4429 continue;
4430 }
4431
4432 /* Copy user configuration info to device instance data */
4433 info->io_base = (unsigned int)io[i];
4434 info->irq_level = (unsigned int)irq[i];
4435 info->irq_level = irq_canonicalize(info->irq_level);
4436 info->dma_level = (unsigned int)dma[i];
4437 info->bus_type = MGSL_BUS_TYPE_ISA;
4438 info->io_addr_size = 16;
4439 info->irq_flags = 0;
4440
4441 mgsl_add_device( info );
4442 }
4443 }
4444
4445 static void synclink_cleanup(void)
4446 {
4447 int rc;
4448 struct mgsl_struct *info;
4449 struct mgsl_struct *tmp;
4450
4451 printk("Unloading %s: %s\n", driver_name, driver_version);
4452
4453 if (serial_driver) {
4454 if ((rc = tty_unregister_driver(serial_driver)))
4455 printk("%s(%d) failed to unregister tty driver err=%d\n",
4456 __FILE__,__LINE__,rc);
4457 put_tty_driver(serial_driver);
4458 }
4459
4460 info = mgsl_device_list;
4461 while(info) {
4462 #if SYNCLINK_GENERIC_HDLC
4463 hdlcdev_exit(info);
4464 #endif
4465 mgsl_release_resources(info);
4466 tmp = info;
4467 info = info->next_device;
4468 kfree(tmp);
4469 }
4470
4471 if (pci_registered)
4472 pci_unregister_driver(&synclink_pci_driver);
4473 }
4474
4475 static int __init synclink_init(void)
4476 {
4477 int rc;
4478
4479 if (break_on_load) {
4480 mgsl_get_text_ptr();
4481 BREAKPOINT();
4482 }
4483
4484 printk("%s %s\n", driver_name, driver_version);
4485
4486 mgsl_enum_isa_devices();
4487 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4488 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4489 else
4490 pci_registered = true;
4491
4492 if ((rc = mgsl_init_tty()) < 0)
4493 goto error;
4494
4495 return 0;
4496
4497 error:
4498 synclink_cleanup();
4499 return rc;
4500 }
4501
4502 static void __exit synclink_exit(void)
4503 {
4504 synclink_cleanup();
4505 }
4506
4507 module_init(synclink_init);
4508 module_exit(synclink_exit);
4509
4510 /*
4511 * usc_RTCmd()
4512 *
4513 * Issue a USC Receive/Transmit command to the
4514 * Channel Command/Address Register (CCAR).
4515 *
4516 * Notes:
4517 *
4518 * The command is encoded in the most significant 5 bits <15..11>
4519 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4520 * and Bits <6..0> must be written as zeros.
4521 *
4522 * Arguments:
4523 *
4524 * info pointer to device information structure
4525 * Cmd command mask (use symbolic macros)
4526 *
4527 * Return Value:
4528 *
4529 * None
4530 */
4531 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4532 {
4533 /* output command to CCAR in bits <15..11> */
4534 /* preserve bits <10..7>, bits <6..0> must be zero */
4535
4536 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4537
4538 /* Read to flush write to CCAR */
4539 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4540 inw( info->io_base + CCAR );
4541
4542 } /* end of usc_RTCmd() */
4543
4544 /*
4545 * usc_DmaCmd()
4546 *
4547 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4548 *
4549 * Arguments:
4550 *
4551 * info pointer to device information structure
4552 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4553 *
4554 * Return Value:
4555 *
4556 * None
4557 */
4558 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4559 {
4560 /* write command mask to DCAR */
4561 outw( Cmd + info->mbre_bit, info->io_base );
4562
4563 /* Read to flush write to DCAR */
4564 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4565 inw( info->io_base );
4566
4567 } /* end of usc_DmaCmd() */
4568
4569 /*
4570 * usc_OutDmaReg()
4571 *
4572 * Write a 16-bit value to a USC DMA register
4573 *
4574 * Arguments:
4575 *
4576 * info pointer to device info structure
4577 * RegAddr register address (number) for write
4578 * RegValue 16-bit value to write to register
4579 *
4580 * Return Value:
4581 *
4582 * None
4583 *
4584 */
4585 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4586 {
4587 /* Note: The DCAR is located at the adapter base address */
4588 /* Note: must preserve state of BIT8 in DCAR */
4589
4590 outw( RegAddr + info->mbre_bit, info->io_base );
4591 outw( RegValue, info->io_base );
4592
4593 /* Read to flush write to DCAR */
4594 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4595 inw( info->io_base );
4596
4597 } /* end of usc_OutDmaReg() */
4598
4599 /*
4600 * usc_InDmaReg()
4601 *
4602 * Read a 16-bit value from a DMA register
4603 *
4604 * Arguments:
4605 *
4606 * info pointer to device info structure
4607 * RegAddr register address (number) to read from
4608 *
4609 * Return Value:
4610 *
4611 * The 16-bit value read from register
4612 *
4613 */
4614 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4615 {
4616 /* Note: The DCAR is located at the adapter base address */
4617 /* Note: must preserve state of BIT8 in DCAR */
4618
4619 outw( RegAddr + info->mbre_bit, info->io_base );
4620 return inw( info->io_base );
4621
4622 } /* end of usc_InDmaReg() */
4623
4624 /*
4625 *
4626 * usc_OutReg()
4627 *
4628 * Write a 16-bit value to a USC serial channel register
4629 *
4630 * Arguments:
4631 *
4632 * info pointer to device info structure
4633 * RegAddr register address (number) to write to
4634 * RegValue 16-bit value to write to register
4635 *
4636 * Return Value:
4637 *
4638 * None
4639 *
4640 */
4641 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4642 {
4643 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4644 outw( RegValue, info->io_base + CCAR );
4645
4646 /* Read to flush write to CCAR */
4647 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4648 inw( info->io_base + CCAR );
4649
4650 } /* end of usc_OutReg() */
4651
4652 /*
4653 * usc_InReg()
4654 *
4655 * Reads a 16-bit value from a USC serial channel register
4656 *
4657 * Arguments:
4658 *
4659 * info pointer to device extension
4660 * RegAddr register address (number) to read from
4661 *
4662 * Return Value:
4663 *
4664 * 16-bit value read from register
4665 */
4666 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4667 {
4668 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4669 return inw( info->io_base + CCAR );
4670
4671 } /* end of usc_InReg() */
4672
4673 /* usc_set_sdlc_mode()
4674 *
4675 * Set up the adapter for SDLC DMA communications.
4676 *
4677 * Arguments: info pointer to device instance data
4678 * Return Value: NONE
4679 */
4680 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4681 {
4682 u16 RegValue;
4683 bool PreSL1660;
4684
4685 /*
4686 * determine if the IUSC on the adapter is pre-SL1660. If
4687 * not, take advantage of the UnderWait feature of more
4688 * modern chips. If an underrun occurs and this bit is set,
4689 * the transmitter will idle the programmed idle pattern
4690 * until the driver has time to service the underrun. Otherwise,
4691 * the dma controller may get the cycles previously requested
4692 * and begin transmitting queued tx data.
4693 */
4694 usc_OutReg(info,TMCR,0x1f);
4695 RegValue=usc_InReg(info,TMDR);
4696 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4697
4698 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4699 {
4700 /*
4701 ** Channel Mode Register (CMR)
4702 **
4703 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4704 ** <13> 0 0 = Transmit Disabled (initially)
4705 ** <12> 0 1 = Consecutive Idles share common 0
4706 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4707 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4708 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4709 **
4710 ** 1000 1110 0000 0110 = 0x8e06
4711 */
4712 RegValue = 0x8e06;
4713
4714 /*--------------------------------------------------
4715 * ignore user options for UnderRun Actions and
4716 * preambles
4717 *--------------------------------------------------*/
4718 }
4719 else
4720 {
4721 /* Channel mode Register (CMR)
4722 *
4723 * <15..14> 00 Tx Sub modes, Underrun Action
4724 * <13> 0 1 = Send Preamble before opening flag
4725 * <12> 0 1 = Consecutive Idles share common 0
4726 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4727 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4728 * <3..0> 0110 Receiver mode = HDLC/SDLC
4729 *
4730 * 0000 0110 0000 0110 = 0x0606
4731 */
4732 if (info->params.mode == MGSL_MODE_RAW) {
4733 RegValue = 0x0001; /* Set Receive mode = external sync */
4734
4735 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4736 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4737
4738 /*
4739 * TxSubMode:
4740 * CMR <15> 0 Don't send CRC on Tx Underrun
4741 * CMR <14> x undefined
4742 * CMR <13> 0 Send preamble before openning sync
4743 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4744 *
4745 * TxMode:
4746 * CMR <11-8) 0100 MonoSync
4747 *
4748 * 0x00 0100 xxxx xxxx 04xx
4749 */
4750 RegValue |= 0x0400;
4751 }
4752 else {
4753
4754 RegValue = 0x0606;
4755
4756 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4757 RegValue |= BIT14;
4758 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4759 RegValue |= BIT15;
4760 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4761 RegValue |= BIT15 + BIT14;
4762 }
4763
4764 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4765 RegValue |= BIT13;
4766 }
4767
4768 if ( info->params.mode == MGSL_MODE_HDLC &&
4769 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4770 RegValue |= BIT12;
4771
4772 if ( info->params.addr_filter != 0xff )
4773 {
4774 /* set up receive address filtering */
4775 usc_OutReg( info, RSR, info->params.addr_filter );
4776 RegValue |= BIT4;
4777 }
4778
4779 usc_OutReg( info, CMR, RegValue );
4780 info->cmr_value = RegValue;
4781
4782 /* Receiver mode Register (RMR)
4783 *
4784 * <15..13> 000 encoding
4785 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4786 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4787 * <9> 0 1 = Include Receive chars in CRC
4788 * <8> 1 1 = Use Abort/PE bit as abort indicator
4789 * <7..6> 00 Even parity
4790 * <5> 0 parity disabled
4791 * <4..2> 000 Receive Char Length = 8 bits
4792 * <1..0> 00 Disable Receiver
4793 *
4794 * 0000 0101 0000 0000 = 0x0500
4795 */
4796
4797 RegValue = 0x0500;
4798
4799 switch ( info->params.encoding ) {
4800 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4801 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4802 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4803 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4804 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4805 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4806 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4807 }
4808
4809 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4810 RegValue |= BIT9;
4811 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4812 RegValue |= ( BIT12 | BIT10 | BIT9 );
4813
4814 usc_OutReg( info, RMR, RegValue );
4815
4816 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4817 /* When an opening flag of an SDLC frame is recognized the */
4818 /* Receive Character count (RCC) is loaded with the value in */
4819 /* RCLR. The RCC is decremented for each received byte. The */
4820 /* value of RCC is stored after the closing flag of the frame */
4821 /* allowing the frame size to be computed. */
4822
4823 usc_OutReg( info, RCLR, RCLRVALUE );
4824
4825 usc_RCmd( info, RCmd_SelectRicrdma_level );
4826
4827 /* Receive Interrupt Control Register (RICR)
4828 *
4829 * <15..8> ? RxFIFO DMA Request Level
4830 * <7> 0 Exited Hunt IA (Interrupt Arm)
4831 * <6> 0 Idle Received IA
4832 * <5> 0 Break/Abort IA
4833 * <4> 0 Rx Bound IA
4834 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4835 * <2> 0 Abort/PE IA
4836 * <1> 1 Rx Overrun IA
4837 * <0> 0 Select TC0 value for readback
4838 *
4839 * 0000 0000 0000 1000 = 0x000a
4840 */
4841
4842 /* Carry over the Exit Hunt and Idle Received bits */
4843 /* in case they have been armed by usc_ArmEvents. */
4844
4845 RegValue = usc_InReg( info, RICR ) & 0xc0;
4846
4847 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4848 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4849 else
4850 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4851
4852 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4853
4854 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4855 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4856
4857 /* Transmit mode Register (TMR)
4858 *
4859 * <15..13> 000 encoding
4860 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4861 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4862 * <9> 0 1 = Tx CRC Enabled
4863 * <8> 0 1 = Append CRC to end of transmit frame
4864 * <7..6> 00 Transmit parity Even
4865 * <5> 0 Transmit parity Disabled
4866 * <4..2> 000 Tx Char Length = 8 bits
4867 * <1..0> 00 Disable Transmitter
4868 *
4869 * 0000 0100 0000 0000 = 0x0400
4870 */
4871
4872 RegValue = 0x0400;
4873
4874 switch ( info->params.encoding ) {
4875 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4876 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4877 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4878 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4879 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4880 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4881 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4882 }
4883
4884 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4885 RegValue |= BIT9 + BIT8;
4886 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4887 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4888
4889 usc_OutReg( info, TMR, RegValue );
4890
4891 usc_set_txidle( info );
4892
4893
4894 usc_TCmd( info, TCmd_SelectTicrdma_level );
4895
4896 /* Transmit Interrupt Control Register (TICR)
4897 *
4898 * <15..8> ? Transmit FIFO DMA Level
4899 * <7> 0 Present IA (Interrupt Arm)
4900 * <6> 0 Idle Sent IA
4901 * <5> 1 Abort Sent IA
4902 * <4> 1 EOF/EOM Sent IA
4903 * <3> 0 CRC Sent IA
4904 * <2> 1 1 = Wait for SW Trigger to Start Frame
4905 * <1> 1 Tx Underrun IA
4906 * <0> 0 TC0 constant on read back
4907 *
4908 * 0000 0000 0011 0110 = 0x0036
4909 */
4910
4911 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4912 usc_OutReg( info, TICR, 0x0736 );
4913 else
4914 usc_OutReg( info, TICR, 0x1436 );
4915
4916 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4917 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4918
4919 /*
4920 ** Transmit Command/Status Register (TCSR)
4921 **
4922 ** <15..12> 0000 TCmd
4923 ** <11> 0/1 UnderWait
4924 ** <10..08> 000 TxIdle
4925 ** <7> x PreSent
4926 ** <6> x IdleSent
4927 ** <5> x AbortSent
4928 ** <4> x EOF/EOM Sent
4929 ** <3> x CRC Sent
4930 ** <2> x All Sent
4931 ** <1> x TxUnder
4932 ** <0> x TxEmpty
4933 **
4934 ** 0000 0000 0000 0000 = 0x0000
4935 */
4936 info->tcsr_value = 0;
4937
4938 if ( !PreSL1660 )
4939 info->tcsr_value |= TCSR_UNDERWAIT;
4940
4941 usc_OutReg( info, TCSR, info->tcsr_value );
4942
4943 /* Clock mode Control Register (CMCR)
4944 *
4945 * <15..14> 00 counter 1 Source = Disabled
4946 * <13..12> 00 counter 0 Source = Disabled
4947 * <11..10> 11 BRG1 Input is TxC Pin
4948 * <9..8> 11 BRG0 Input is TxC Pin
4949 * <7..6> 01 DPLL Input is BRG1 Output
4950 * <5..3> XXX TxCLK comes from Port 0
4951 * <2..0> XXX RxCLK comes from Port 1
4952 *
4953 * 0000 1111 0111 0111 = 0x0f77
4954 */
4955
4956 RegValue = 0x0f40;
4957
4958 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4959 RegValue |= 0x0003; /* RxCLK from DPLL */
4960 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4961 RegValue |= 0x0004; /* RxCLK from BRG0 */
4962 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4963 RegValue |= 0x0006; /* RxCLK from TXC Input */
4964 else
4965 RegValue |= 0x0007; /* RxCLK from Port1 */
4966
4967 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4968 RegValue |= 0x0018; /* TxCLK from DPLL */
4969 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4970 RegValue |= 0x0020; /* TxCLK from BRG0 */
4971 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4972 RegValue |= 0x0038; /* RxCLK from TXC Input */
4973 else
4974 RegValue |= 0x0030; /* TxCLK from Port0 */
4975
4976 usc_OutReg( info, CMCR, RegValue );
4977
4978
4979 /* Hardware Configuration Register (HCR)
4980 *
4981 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4982 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4983 * <12> 0 CVOK:0=report code violation in biphase
4984 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4985 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4986 * <7..6> 00 reserved
4987 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4988 * <4> X BRG1 Enable
4989 * <3..2> 00 reserved
4990 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4991 * <0> 0 BRG0 Enable
4992 */
4993
4994 RegValue = 0x0000;
4995
4996 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4997 u32 XtalSpeed;
4998 u32 DpllDivisor;
4999 u16 Tc;
5000
5001 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5002 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5003
5004 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5005 XtalSpeed = 11059200;
5006 else
5007 XtalSpeed = 14745600;
5008
5009 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5010 DpllDivisor = 16;
5011 RegValue |= BIT10;
5012 }
5013 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5014 DpllDivisor = 8;
5015 RegValue |= BIT11;
5016 }
5017 else
5018 DpllDivisor = 32;
5019
5020 /* Tc = (Xtal/Speed) - 1 */
5021 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5022 /* then rounding up gives a more precise time constant. Instead */
5023 /* of rounding up and then subtracting 1 we just don't subtract */
5024 /* the one in this case. */
5025
5026 /*--------------------------------------------------
5027 * ejz: for DPLL mode, application should use the
5028 * same clock speed as the partner system, even
5029 * though clocking is derived from the input RxData.
5030 * In case the user uses a 0 for the clock speed,
5031 * default to 0xffffffff and don't try to divide by
5032 * zero
5033 *--------------------------------------------------*/
5034 if ( info->params.clock_speed )
5035 {
5036 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5037 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5038 / info->params.clock_speed) )
5039 Tc--;
5040 }
5041 else
5042 Tc = -1;
5043
5044
5045 /* Write 16-bit Time Constant for BRG1 */
5046 usc_OutReg( info, TC1R, Tc );
5047
5048 RegValue |= BIT4; /* enable BRG1 */
5049
5050 switch ( info->params.encoding ) {
5051 case HDLC_ENCODING_NRZ:
5052 case HDLC_ENCODING_NRZB:
5053 case HDLC_ENCODING_NRZI_MARK:
5054 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5055 case HDLC_ENCODING_BIPHASE_MARK:
5056 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5057 case HDLC_ENCODING_BIPHASE_LEVEL:
5058 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5059 }
5060 }
5061
5062 usc_OutReg( info, HCR, RegValue );
5063
5064
5065 /* Channel Control/status Register (CCSR)
5066 *
5067 * <15> X RCC FIFO Overflow status (RO)
5068 * <14> X RCC FIFO Not Empty status (RO)
5069 * <13> 0 1 = Clear RCC FIFO (WO)
5070 * <12> X DPLL Sync (RW)
5071 * <11> X DPLL 2 Missed Clocks status (RO)
5072 * <10> X DPLL 1 Missed Clock status (RO)
5073 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5074 * <7> X SDLC Loop On status (RO)
5075 * <6> X SDLC Loop Send status (RO)
5076 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5077 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5078 * <1..0> 00 reserved
5079 *
5080 * 0000 0000 0010 0000 = 0x0020
5081 */
5082
5083 usc_OutReg( info, CCSR, 0x1020 );
5084
5085
5086 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5087 usc_OutReg( info, SICR,
5088 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5089 }
5090
5091
5092 /* enable Master Interrupt Enable bit (MIE) */
5093 usc_EnableMasterIrqBit( info );
5094
5095 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5096 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5097
5098 /* arm RCC underflow interrupt */
5099 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5100 usc_EnableInterrupts(info, MISC);
5101
5102 info->mbre_bit = 0;
5103 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5104 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5105 info->mbre_bit = BIT8;
5106 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5107
5108 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5109 /* Enable DMAEN (Port 7, Bit 14) */
5110 /* This connects the DMA request signal to the ISA bus */
5111 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5112 }
5113
5114 /* DMA Control Register (DCR)
5115 *
5116 * <15..14> 10 Priority mode = Alternating Tx/Rx
5117 * 01 Rx has priority
5118 * 00 Tx has priority
5119 *
5120 * <13> 1 Enable Priority Preempt per DCR<15..14>
5121 * (WARNING DCR<11..10> must be 00 when this is 1)
5122 * 0 Choose activate channel per DCR<11..10>
5123 *
5124 * <12> 0 Little Endian for Array/List
5125 * <11..10> 00 Both Channels can use each bus grant
5126 * <9..6> 0000 reserved
5127 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5128 * <4> 0 1 = drive D/C and S/D pins
5129 * <3> 1 1 = Add one wait state to all DMA cycles.
5130 * <2> 0 1 = Strobe /UAS on every transfer.
5131 * <1..0> 11 Addr incrementing only affects LS24 bits
5132 *
5133 * 0110 0000 0000 1011 = 0x600b
5134 */
5135
5136 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5137 /* PCI adapter does not need DMA wait state */
5138 usc_OutDmaReg( info, DCR, 0xa00b );
5139 }
5140 else
5141 usc_OutDmaReg( info, DCR, 0x800b );
5142
5143
5144 /* Receive DMA mode Register (RDMR)
5145 *
5146 * <15..14> 11 DMA mode = Linked List Buffer mode
5147 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5148 * <12> 1 Clear count of List Entry after fetching
5149 * <11..10> 00 Address mode = Increment
5150 * <9> 1 Terminate Buffer on RxBound
5151 * <8> 0 Bus Width = 16bits
5152 * <7..0> ? status Bits (write as 0s)
5153 *
5154 * 1111 0010 0000 0000 = 0xf200
5155 */
5156
5157 usc_OutDmaReg( info, RDMR, 0xf200 );
5158
5159
5160 /* Transmit DMA mode Register (TDMR)
5161 *
5162 * <15..14> 11 DMA mode = Linked List Buffer mode
5163 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5164 * <12> 1 Clear count of List Entry after fetching
5165 * <11..10> 00 Address mode = Increment
5166 * <9> 1 Terminate Buffer on end of frame
5167 * <8> 0 Bus Width = 16bits
5168 * <7..0> ? status Bits (Read Only so write as 0)
5169 *
5170 * 1111 0010 0000 0000 = 0xf200
5171 */
5172
5173 usc_OutDmaReg( info, TDMR, 0xf200 );
5174
5175
5176 /* DMA Interrupt Control Register (DICR)
5177 *
5178 * <15> 1 DMA Interrupt Enable
5179 * <14> 0 1 = Disable IEO from USC
5180 * <13> 0 1 = Don't provide vector during IntAck
5181 * <12> 1 1 = Include status in Vector
5182 * <10..2> 0 reserved, Must be 0s
5183 * <1> 0 1 = Rx DMA Interrupt Enabled
5184 * <0> 0 1 = Tx DMA Interrupt Enabled
5185 *
5186 * 1001 0000 0000 0000 = 0x9000
5187 */
5188
5189 usc_OutDmaReg( info, DICR, 0x9000 );
5190
5191 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5192 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5193 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5194
5195 /* Channel Control Register (CCR)
5196 *
5197 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5198 * <13> 0 Trigger Tx on SW Command Disabled
5199 * <12> 0 Flag Preamble Disabled
5200 * <11..10> 00 Preamble Length
5201 * <9..8> 00 Preamble Pattern
5202 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5203 * <5> 0 Trigger Rx on SW Command Disabled
5204 * <4..0> 0 reserved
5205 *
5206 * 1000 0000 1000 0000 = 0x8080
5207 */
5208
5209 RegValue = 0x8080;
5210
5211 switch ( info->params.preamble_length ) {
5212 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5213 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5214 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5215 }
5216
5217 switch ( info->params.preamble ) {
5218 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5219 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5220 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5221 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5222 }
5223
5224 usc_OutReg( info, CCR, RegValue );
5225
5226
5227 /*
5228 * Burst/Dwell Control Register
5229 *
5230 * <15..8> 0x20 Maximum number of transfers per bus grant
5231 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5232 */
5233
5234 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5235 /* don't limit bus occupancy on PCI adapter */
5236 usc_OutDmaReg( info, BDCR, 0x0000 );
5237 }
5238 else
5239 usc_OutDmaReg( info, BDCR, 0x2000 );
5240
5241 usc_stop_transmitter(info);
5242 usc_stop_receiver(info);
5243
5244 } /* end of usc_set_sdlc_mode() */
5245
5246 /* usc_enable_loopback()
5247 *
5248 * Set the 16C32 for internal loopback mode.
5249 * The TxCLK and RxCLK signals are generated from the BRG0 and
5250 * the TxD is looped back to the RxD internally.
5251 *
5252 * Arguments: info pointer to device instance data
5253 * enable 1 = enable loopback, 0 = disable
5254 * Return Value: None
5255 */
5256 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5257 {
5258 if (enable) {
5259 /* blank external TXD output */
5260 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5261
5262 /* Clock mode Control Register (CMCR)
5263 *
5264 * <15..14> 00 counter 1 Disabled
5265 * <13..12> 00 counter 0 Disabled
5266 * <11..10> 11 BRG1 Input is TxC Pin
5267 * <9..8> 11 BRG0 Input is TxC Pin
5268 * <7..6> 01 DPLL Input is BRG1 Output
5269 * <5..3> 100 TxCLK comes from BRG0
5270 * <2..0> 100 RxCLK comes from BRG0
5271 *
5272 * 0000 1111 0110 0100 = 0x0f64
5273 */
5274
5275 usc_OutReg( info, CMCR, 0x0f64 );
5276
5277 /* Write 16-bit Time Constant for BRG0 */
5278 /* use clock speed if available, otherwise use 8 for diagnostics */
5279 if (info->params.clock_speed) {
5280 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5281 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5282 else
5283 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5284 } else
5285 usc_OutReg(info, TC0R, (u16)8);
5286
5287 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5288 mode = Continuous Set Bit 0 to enable BRG0. */
5289 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5290
5291 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5292 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5293
5294 /* set Internal Data loopback mode */
5295 info->loopback_bits = 0x300;
5296 outw( 0x0300, info->io_base + CCAR );
5297 } else {
5298 /* enable external TXD output */
5299 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5300
5301 /* clear Internal Data loopback mode */
5302 info->loopback_bits = 0;
5303 outw( 0,info->io_base + CCAR );
5304 }
5305
5306 } /* end of usc_enable_loopback() */
5307
5308 /* usc_enable_aux_clock()
5309 *
5310 * Enabled the AUX clock output at the specified frequency.
5311 *
5312 * Arguments:
5313 *
5314 * info pointer to device extension
5315 * data_rate data rate of clock in bits per second
5316 * A data rate of 0 disables the AUX clock.
5317 *
5318 * Return Value: None
5319 */
5320 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5321 {
5322 u32 XtalSpeed;
5323 u16 Tc;
5324
5325 if ( data_rate ) {
5326 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5327 XtalSpeed = 11059200;
5328 else
5329 XtalSpeed = 14745600;
5330
5331
5332 /* Tc = (Xtal/Speed) - 1 */
5333 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5334 /* then rounding up gives a more precise time constant. Instead */
5335 /* of rounding up and then subtracting 1 we just don't subtract */
5336 /* the one in this case. */
5337
5338
5339 Tc = (u16)(XtalSpeed/data_rate);
5340 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5341 Tc--;
5342
5343 /* Write 16-bit Time Constant for BRG0 */
5344 usc_OutReg( info, TC0R, Tc );
5345
5346 /*
5347 * Hardware Configuration Register (HCR)
5348 * Clear Bit 1, BRG0 mode = Continuous
5349 * Set Bit 0 to enable BRG0.
5350 */
5351
5352 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5353
5354 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5355 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5356 } else {
5357 /* data rate == 0 so turn off BRG0 */
5358 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5359 }
5360
5361 } /* end of usc_enable_aux_clock() */
5362
5363 /*
5364 *
5365 * usc_process_rxoverrun_sync()
5366 *
5367 * This function processes a receive overrun by resetting the
5368 * receive DMA buffers and issuing a Purge Rx FIFO command
5369 * to allow the receiver to continue receiving.
5370 *
5371 * Arguments:
5372 *
5373 * info pointer to device extension
5374 *
5375 * Return Value: None
5376 */
5377 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5378 {
5379 int start_index;
5380 int end_index;
5381 int frame_start_index;
5382 bool start_of_frame_found = false;
5383 bool end_of_frame_found = false;
5384 bool reprogram_dma = false;
5385
5386 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5387 u32 phys_addr;
5388
5389 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5390 usc_RCmd( info, RCmd_EnterHuntmode );
5391 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5392
5393 /* CurrentRxBuffer points to the 1st buffer of the next */
5394 /* possibly available receive frame. */
5395
5396 frame_start_index = start_index = end_index = info->current_rx_buffer;
5397
5398 /* Search for an unfinished string of buffers. This means */
5399 /* that a receive frame started (at least one buffer with */
5400 /* count set to zero) but there is no terminiting buffer */
5401 /* (status set to non-zero). */
5402
5403 while( !buffer_list[end_index].count )
5404 {
5405 /* Count field has been reset to zero by 16C32. */
5406 /* This buffer is currently in use. */
5407
5408 if ( !start_of_frame_found )
5409 {
5410 start_of_frame_found = true;
5411 frame_start_index = end_index;
5412 end_of_frame_found = false;
5413 }
5414
5415 if ( buffer_list[end_index].status )
5416 {
5417 /* Status field has been set by 16C32. */
5418 /* This is the last buffer of a received frame. */
5419
5420 /* We want to leave the buffers for this frame intact. */
5421 /* Move on to next possible frame. */
5422
5423 start_of_frame_found = false;
5424 end_of_frame_found = true;
5425 }
5426
5427 /* advance to next buffer entry in linked list */
5428 end_index++;
5429 if ( end_index == info->rx_buffer_count )
5430 end_index = 0;
5431
5432 if ( start_index == end_index )
5433 {
5434 /* The entire list has been searched with all Counts == 0 and */
5435 /* all Status == 0. The receive buffers are */
5436 /* completely screwed, reset all receive buffers! */
5437 mgsl_reset_rx_dma_buffers( info );
5438 frame_start_index = 0;
5439 start_of_frame_found = false;
5440 reprogram_dma = true;
5441 break;
5442 }
5443 }
5444
5445 if ( start_of_frame_found && !end_of_frame_found )
5446 {
5447 /* There is an unfinished string of receive DMA buffers */
5448 /* as a result of the receiver overrun. */
5449
5450 /* Reset the buffers for the unfinished frame */
5451 /* and reprogram the receive DMA controller to start */
5452 /* at the 1st buffer of unfinished frame. */
5453
5454 start_index = frame_start_index;
5455
5456 do
5457 {
5458 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5459
5460 /* Adjust index for wrap around. */
5461 if ( start_index == info->rx_buffer_count )
5462 start_index = 0;
5463
5464 } while( start_index != end_index );
5465
5466 reprogram_dma = true;
5467 }
5468
5469 if ( reprogram_dma )
5470 {
5471 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5472 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5473 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5474
5475 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5476
5477 /* This empties the receive FIFO and loads the RCC with RCLR */
5478 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5479
5480 /* program 16C32 with physical address of 1st DMA buffer entry */
5481 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5482 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5483 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5484
5485 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5486 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5487 usc_EnableInterrupts( info, RECEIVE_STATUS );
5488
5489 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5490 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5491
5492 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5493 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5494 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5495 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5496 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5497 else
5498 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5499 }
5500 else
5501 {
5502 /* This empties the receive FIFO and loads the RCC with RCLR */
5503 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5504 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5505 }
5506
5507 } /* end of usc_process_rxoverrun_sync() */
5508
5509 /* usc_stop_receiver()
5510 *
5511 * Disable USC receiver
5512 *
5513 * Arguments: info pointer to device instance data
5514 * Return Value: None
5515 */
5516 static void usc_stop_receiver( struct mgsl_struct *info )
5517 {
5518 if (debug_level >= DEBUG_LEVEL_ISR)
5519 printk("%s(%d):usc_stop_receiver(%s)\n",
5520 __FILE__,__LINE__, info->device_name );
5521
5522 /* Disable receive DMA channel. */
5523 /* This also disables receive DMA channel interrupts */
5524 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5525
5526 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5527 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5528 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5529
5530 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5531
5532 /* This empties the receive FIFO and loads the RCC with RCLR */
5533 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5534 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5535
5536 info->rx_enabled = false;
5537 info->rx_overflow = false;
5538 info->rx_rcc_underrun = false;
5539
5540 } /* end of stop_receiver() */
5541
5542 /* usc_start_receiver()
5543 *
5544 * Enable the USC receiver
5545 *
5546 * Arguments: info pointer to device instance data
5547 * Return Value: None
5548 */
5549 static void usc_start_receiver( struct mgsl_struct *info )
5550 {
5551 u32 phys_addr;
5552
5553 if (debug_level >= DEBUG_LEVEL_ISR)
5554 printk("%s(%d):usc_start_receiver(%s)\n",
5555 __FILE__,__LINE__, info->device_name );
5556
5557 mgsl_reset_rx_dma_buffers( info );
5558 usc_stop_receiver( info );
5559
5560 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5561 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5562
5563 if ( info->params.mode == MGSL_MODE_HDLC ||
5564 info->params.mode == MGSL_MODE_RAW ) {
5565 /* DMA mode Transfers */
5566 /* Program the DMA controller. */
5567 /* Enable the DMA controller end of buffer interrupt. */
5568
5569 /* program 16C32 with physical address of 1st DMA buffer entry */
5570 phys_addr = info->rx_buffer_list[0].phys_entry;
5571 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5572 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5573
5574 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5575 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5576 usc_EnableInterrupts( info, RECEIVE_STATUS );
5577
5578 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5579 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5580
5581 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5582 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5583 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5584 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5585 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5586 else
5587 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5588 } else {
5589 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5590 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5591 usc_EnableInterrupts(info, RECEIVE_DATA);
5592
5593 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5594 usc_RCmd( info, RCmd_EnterHuntmode );
5595
5596 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5597 }
5598
5599 usc_OutReg( info, CCSR, 0x1020 );
5600
5601 info->rx_enabled = true;
5602
5603 } /* end of usc_start_receiver() */
5604
5605 /* usc_start_transmitter()
5606 *
5607 * Enable the USC transmitter and send a transmit frame if
5608 * one is loaded in the DMA buffers.
5609 *
5610 * Arguments: info pointer to device instance data
5611 * Return Value: None
5612 */
5613 static void usc_start_transmitter( struct mgsl_struct *info )
5614 {
5615 u32 phys_addr;
5616 unsigned int FrameSize;
5617
5618 if (debug_level >= DEBUG_LEVEL_ISR)
5619 printk("%s(%d):usc_start_transmitter(%s)\n",
5620 __FILE__,__LINE__, info->device_name );
5621
5622 if ( info->xmit_cnt ) {
5623
5624 /* If auto RTS enabled and RTS is inactive, then assert */
5625 /* RTS and set a flag indicating that the driver should */
5626 /* negate RTS when the transmission completes. */
5627
5628 info->drop_rts_on_tx_done = false;
5629
5630 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5631 usc_get_serial_signals( info );
5632 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5633 info->serial_signals |= SerialSignal_RTS;
5634 usc_set_serial_signals( info );
5635 info->drop_rts_on_tx_done = true;
5636 }
5637 }
5638
5639
5640 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5641 if ( !info->tx_active ) {
5642 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5643 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5644 usc_EnableInterrupts(info, TRANSMIT_DATA);
5645 usc_load_txfifo(info);
5646 }
5647 } else {
5648 /* Disable transmit DMA controller while programming. */
5649 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5650
5651 /* Transmit DMA buffer is loaded, so program USC */
5652 /* to send the frame contained in the buffers. */
5653
5654 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5655
5656 /* if operating in Raw sync mode, reset the rcc component
5657 * of the tx dma buffer entry, otherwise, the serial controller
5658 * will send a closing sync char after this count.
5659 */
5660 if ( info->params.mode == MGSL_MODE_RAW )
5661 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5662
5663 /* Program the Transmit Character Length Register (TCLR) */
5664 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5665 usc_OutReg( info, TCLR, (u16)FrameSize );
5666
5667 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5668
5669 /* Program the address of the 1st DMA Buffer Entry in linked list */
5670 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5671 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5672 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5673
5674 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5675 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5676 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5677
5678 if ( info->params.mode == MGSL_MODE_RAW &&
5679 info->num_tx_dma_buffers > 1 ) {
5680 /* When running external sync mode, attempt to 'stream' transmit */
5681 /* by filling tx dma buffers as they become available. To do this */
5682 /* we need to enable Tx DMA EOB Status interrupts : */
5683 /* */
5684 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5685 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5686
5687 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5688 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5689 }
5690
5691 /* Initialize Transmit DMA Channel */
5692 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5693
5694 usc_TCmd( info, TCmd_SendFrame );
5695
5696 mod_timer(&info->tx_timer, jiffies +
5697 msecs_to_jiffies(5000));
5698 }
5699 info->tx_active = true;
5700 }
5701
5702 if ( !info->tx_enabled ) {
5703 info->tx_enabled = true;
5704 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5705 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5706 else
5707 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5708 }
5709
5710 } /* end of usc_start_transmitter() */
5711
5712 /* usc_stop_transmitter()
5713 *
5714 * Stops the transmitter and DMA
5715 *
5716 * Arguments: info pointer to device isntance data
5717 * Return Value: None
5718 */
5719 static void usc_stop_transmitter( struct mgsl_struct *info )
5720 {
5721 if (debug_level >= DEBUG_LEVEL_ISR)
5722 printk("%s(%d):usc_stop_transmitter(%s)\n",
5723 __FILE__,__LINE__, info->device_name );
5724
5725 del_timer(&info->tx_timer);
5726
5727 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5728 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5729 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5730
5731 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5732 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5733 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5734
5735 info->tx_enabled = false;
5736 info->tx_active = false;
5737
5738 } /* end of usc_stop_transmitter() */
5739
5740 /* usc_load_txfifo()
5741 *
5742 * Fill the transmit FIFO until the FIFO is full or
5743 * there is no more data to load.
5744 *
5745 * Arguments: info pointer to device extension (instance data)
5746 * Return Value: None
5747 */
5748 static void usc_load_txfifo( struct mgsl_struct *info )
5749 {
5750 int Fifocount;
5751 u8 TwoBytes[2];
5752
5753 if ( !info->xmit_cnt && !info->x_char )
5754 return;
5755
5756 /* Select transmit FIFO status readback in TICR */
5757 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5758
5759 /* load the Transmit FIFO until FIFOs full or all data sent */
5760
5761 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5762 /* there is more space in the transmit FIFO and */
5763 /* there is more data in transmit buffer */
5764
5765 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5766 /* write a 16-bit word from transmit buffer to 16C32 */
5767
5768 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5769 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5770 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5771 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5772
5773 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5774
5775 info->xmit_cnt -= 2;
5776 info->icount.tx += 2;
5777 } else {
5778 /* only 1 byte left to transmit or 1 FIFO slot left */
5779
5780 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5781 info->io_base + CCAR );
5782
5783 if (info->x_char) {
5784 /* transmit pending high priority char */
5785 outw( info->x_char,info->io_base + CCAR );
5786 info->x_char = 0;
5787 } else {
5788 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5789 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5790 info->xmit_cnt--;
5791 }
5792 info->icount.tx++;
5793 }
5794 }
5795
5796 } /* end of usc_load_txfifo() */
5797
5798 /* usc_reset()
5799 *
5800 * Reset the adapter to a known state and prepare it for further use.
5801 *
5802 * Arguments: info pointer to device instance data
5803 * Return Value: None
5804 */
5805 static void usc_reset( struct mgsl_struct *info )
5806 {
5807 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5808 int i;
5809 u32 readval;
5810
5811 /* Set BIT30 of Misc Control Register */
5812 /* (Local Control Register 0x50) to force reset of USC. */
5813
5814 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5815 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5816
5817 info->misc_ctrl_value |= BIT30;
5818 *MiscCtrl = info->misc_ctrl_value;
5819
5820 /*
5821 * Force at least 170ns delay before clearing
5822 * reset bit. Each read from LCR takes at least
5823 * 30ns so 10 times for 300ns to be safe.
5824 */
5825 for(i=0;i<10;i++)
5826 readval = *MiscCtrl;
5827
5828 info->misc_ctrl_value &= ~BIT30;
5829 *MiscCtrl = info->misc_ctrl_value;
5830
5831 *LCR0BRDR = BUS_DESCRIPTOR(
5832 1, // Write Strobe Hold (0-3)
5833 2, // Write Strobe Delay (0-3)
5834 2, // Read Strobe Delay (0-3)
5835 0, // NWDD (Write data-data) (0-3)
5836 4, // NWAD (Write Addr-data) (0-31)
5837 0, // NXDA (Read/Write Data-Addr) (0-3)
5838 0, // NRDD (Read Data-Data) (0-3)
5839 5 // NRAD (Read Addr-Data) (0-31)
5840 );
5841 } else {
5842 /* do HW reset */
5843 outb( 0,info->io_base + 8 );
5844 }
5845
5846 info->mbre_bit = 0;
5847 info->loopback_bits = 0;
5848 info->usc_idle_mode = 0;
5849
5850 /*
5851 * Program the Bus Configuration Register (BCR)
5852 *
5853 * <15> 0 Don't use separate address
5854 * <14..6> 0 reserved
5855 * <5..4> 00 IAckmode = Default, don't care
5856 * <3> 1 Bus Request Totem Pole output
5857 * <2> 1 Use 16 Bit data bus
5858 * <1> 0 IRQ Totem Pole output
5859 * <0> 0 Don't Shift Right Addr
5860 *
5861 * 0000 0000 0000 1100 = 0x000c
5862 *
5863 * By writing to io_base + SDPIN the Wait/Ack pin is
5864 * programmed to work as a Wait pin.
5865 */
5866
5867 outw( 0x000c,info->io_base + SDPIN );
5868
5869
5870 outw( 0,info->io_base );
5871 outw( 0,info->io_base + CCAR );
5872
5873 /* select little endian byte ordering */
5874 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5875
5876
5877 /* Port Control Register (PCR)
5878 *
5879 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5880 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5881 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5882 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5883 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5884 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5885 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5886 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5887 *
5888 * 1111 0000 1111 0101 = 0xf0f5
5889 */
5890
5891 usc_OutReg( info, PCR, 0xf0f5 );
5892
5893
5894 /*
5895 * Input/Output Control Register
5896 *
5897 * <15..14> 00 CTS is active low input
5898 * <13..12> 00 DCD is active low input
5899 * <11..10> 00 TxREQ pin is input (DSR)
5900 * <9..8> 00 RxREQ pin is input (RI)
5901 * <7..6> 00 TxD is output (Transmit Data)
5902 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5903 * <2..0> 100 RxC is Output (drive with BRG0)
5904 *
5905 * 0000 0000 0000 0100 = 0x0004
5906 */
5907
5908 usc_OutReg( info, IOCR, 0x0004 );
5909
5910 } /* end of usc_reset() */
5911
5912 /* usc_set_async_mode()
5913 *
5914 * Program adapter for asynchronous communications.
5915 *
5916 * Arguments: info pointer to device instance data
5917 * Return Value: None
5918 */
5919 static void usc_set_async_mode( struct mgsl_struct *info )
5920 {
5921 u16 RegValue;
5922
5923 /* disable interrupts while programming USC */
5924 usc_DisableMasterIrqBit( info );
5925
5926 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5927 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5928
5929 usc_loopback_frame( info );
5930
5931 /* Channel mode Register (CMR)
5932 *
5933 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5934 * <13..12> 00 00 = 16X Clock
5935 * <11..8> 0000 Transmitter mode = Asynchronous
5936 * <7..6> 00 reserved?
5937 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5938 * <3..0> 0000 Receiver mode = Asynchronous
5939 *
5940 * 0000 0000 0000 0000 = 0x0
5941 */
5942
5943 RegValue = 0;
5944 if ( info->params.stop_bits != 1 )
5945 RegValue |= BIT14;
5946 usc_OutReg( info, CMR, RegValue );
5947
5948
5949 /* Receiver mode Register (RMR)
5950 *
5951 * <15..13> 000 encoding = None
5952 * <12..08> 00000 reserved (Sync Only)
5953 * <7..6> 00 Even parity
5954 * <5> 0 parity disabled
5955 * <4..2> 000 Receive Char Length = 8 bits
5956 * <1..0> 00 Disable Receiver
5957 *
5958 * 0000 0000 0000 0000 = 0x0
5959 */
5960
5961 RegValue = 0;
5962
5963 if ( info->params.data_bits != 8 )
5964 RegValue |= BIT4+BIT3+BIT2;
5965
5966 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5967 RegValue |= BIT5;
5968 if ( info->params.parity != ASYNC_PARITY_ODD )
5969 RegValue |= BIT6;
5970 }
5971
5972 usc_OutReg( info, RMR, RegValue );
5973
5974
5975 /* Set IRQ trigger level */
5976
5977 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5978
5979
5980 /* Receive Interrupt Control Register (RICR)
5981 *
5982 * <15..8> ? RxFIFO IRQ Request Level
5983 *
5984 * Note: For async mode the receive FIFO level must be set
5985 * to 0 to avoid the situation where the FIFO contains fewer bytes
5986 * than the trigger level and no more data is expected.
5987 *
5988 * <7> 0 Exited Hunt IA (Interrupt Arm)
5989 * <6> 0 Idle Received IA
5990 * <5> 0 Break/Abort IA
5991 * <4> 0 Rx Bound IA
5992 * <3> 0 Queued status reflects oldest byte in FIFO
5993 * <2> 0 Abort/PE IA
5994 * <1> 0 Rx Overrun IA
5995 * <0> 0 Select TC0 value for readback
5996 *
5997 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5998 */
5999
6000 usc_OutReg( info, RICR, 0x0000 );
6001
6002 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
6003 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6004
6005
6006 /* Transmit mode Register (TMR)
6007 *
6008 * <15..13> 000 encoding = None
6009 * <12..08> 00000 reserved (Sync Only)
6010 * <7..6> 00 Transmit parity Even
6011 * <5> 0 Transmit parity Disabled
6012 * <4..2> 000 Tx Char Length = 8 bits
6013 * <1..0> 00 Disable Transmitter
6014 *
6015 * 0000 0000 0000 0000 = 0x0
6016 */
6017
6018 RegValue = 0;
6019
6020 if ( info->params.data_bits != 8 )
6021 RegValue |= BIT4+BIT3+BIT2;
6022
6023 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6024 RegValue |= BIT5;
6025 if ( info->params.parity != ASYNC_PARITY_ODD )
6026 RegValue |= BIT6;
6027 }
6028
6029 usc_OutReg( info, TMR, RegValue );
6030
6031 usc_set_txidle( info );
6032
6033
6034 /* Set IRQ trigger level */
6035
6036 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6037
6038
6039 /* Transmit Interrupt Control Register (TICR)
6040 *
6041 * <15..8> ? Transmit FIFO IRQ Level
6042 * <7> 0 Present IA (Interrupt Arm)
6043 * <6> 1 Idle Sent IA
6044 * <5> 0 Abort Sent IA
6045 * <4> 0 EOF/EOM Sent IA
6046 * <3> 0 CRC Sent IA
6047 * <2> 0 1 = Wait for SW Trigger to Start Frame
6048 * <1> 0 Tx Underrun IA
6049 * <0> 0 TC0 constant on read back
6050 *
6051 * 0000 0000 0100 0000 = 0x0040
6052 */
6053
6054 usc_OutReg( info, TICR, 0x1f40 );
6055
6056 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6057 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6058
6059 usc_enable_async_clock( info, info->params.data_rate );
6060
6061
6062 /* Channel Control/status Register (CCSR)
6063 *
6064 * <15> X RCC FIFO Overflow status (RO)
6065 * <14> X RCC FIFO Not Empty status (RO)
6066 * <13> 0 1 = Clear RCC FIFO (WO)
6067 * <12> X DPLL in Sync status (RO)
6068 * <11> X DPLL 2 Missed Clocks status (RO)
6069 * <10> X DPLL 1 Missed Clock status (RO)
6070 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6071 * <7> X SDLC Loop On status (RO)
6072 * <6> X SDLC Loop Send status (RO)
6073 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6074 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6075 * <1..0> 00 reserved
6076 *
6077 * 0000 0000 0010 0000 = 0x0020
6078 */
6079
6080 usc_OutReg( info, CCSR, 0x0020 );
6081
6082 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6083 RECEIVE_DATA + RECEIVE_STATUS );
6084
6085 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6086 RECEIVE_DATA + RECEIVE_STATUS );
6087
6088 usc_EnableMasterIrqBit( info );
6089
6090 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6091 /* Enable INTEN (Port 6, Bit12) */
6092 /* This connects the IRQ request signal to the ISA bus */
6093 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6094 }
6095
6096 if (info->params.loopback) {
6097 info->loopback_bits = 0x300;
6098 outw(0x0300, info->io_base + CCAR);
6099 }
6100
6101 } /* end of usc_set_async_mode() */
6102
6103 /* usc_loopback_frame()
6104 *
6105 * Loop back a small (2 byte) dummy SDLC frame.
6106 * Interrupts and DMA are NOT used. The purpose of this is to
6107 * clear any 'stale' status info left over from running in async mode.
6108 *
6109 * The 16C32 shows the strange behaviour of marking the 1st
6110 * received SDLC frame with a CRC error even when there is no
6111 * CRC error. To get around this a small dummy from of 2 bytes
6112 * is looped back when switching from async to sync mode.
6113 *
6114 * Arguments: info pointer to device instance data
6115 * Return Value: None
6116 */
6117 static void usc_loopback_frame( struct mgsl_struct *info )
6118 {
6119 int i;
6120 unsigned long oldmode = info->params.mode;
6121
6122 info->params.mode = MGSL_MODE_HDLC;
6123
6124 usc_DisableMasterIrqBit( info );
6125
6126 usc_set_sdlc_mode( info );
6127 usc_enable_loopback( info, 1 );
6128
6129 /* Write 16-bit Time Constant for BRG0 */
6130 usc_OutReg( info, TC0R, 0 );
6131
6132 /* Channel Control Register (CCR)
6133 *
6134 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6135 * <13> 0 Trigger Tx on SW Command Disabled
6136 * <12> 0 Flag Preamble Disabled
6137 * <11..10> 00 Preamble Length = 8-Bits
6138 * <9..8> 01 Preamble Pattern = flags
6139 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6140 * <5> 0 Trigger Rx on SW Command Disabled
6141 * <4..0> 0 reserved
6142 *
6143 * 0000 0001 0000 0000 = 0x0100
6144 */
6145
6146 usc_OutReg( info, CCR, 0x0100 );
6147
6148 /* SETUP RECEIVER */
6149 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6150 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6151
6152 /* SETUP TRANSMITTER */
6153 /* Program the Transmit Character Length Register (TCLR) */
6154 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6155 usc_OutReg( info, TCLR, 2 );
6156 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6157
6158 /* unlatch Tx status bits, and start transmit channel. */
6159 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6160 outw(0,info->io_base + DATAREG);
6161
6162 /* ENABLE TRANSMITTER */
6163 usc_TCmd( info, TCmd_SendFrame );
6164 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6165
6166 /* WAIT FOR RECEIVE COMPLETE */
6167 for (i=0 ; i<1000 ; i++)
6168 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6169 break;
6170
6171 /* clear Internal Data loopback mode */
6172 usc_enable_loopback(info, 0);
6173
6174 usc_EnableMasterIrqBit(info);
6175
6176 info->params.mode = oldmode;
6177
6178 } /* end of usc_loopback_frame() */
6179
6180 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6181 *
6182 * Arguments: info pointer to adapter info structure
6183 * Return Value: None
6184 */
6185 static void usc_set_sync_mode( struct mgsl_struct *info )
6186 {
6187 usc_loopback_frame( info );
6188 usc_set_sdlc_mode( info );
6189
6190 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6191 /* Enable INTEN (Port 6, Bit12) */
6192 /* This connects the IRQ request signal to the ISA bus */
6193 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6194 }
6195
6196 usc_enable_aux_clock(info, info->params.clock_speed);
6197
6198 if (info->params.loopback)
6199 usc_enable_loopback(info,1);
6200
6201 } /* end of mgsl_set_sync_mode() */
6202
6203 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6204 *
6205 * Arguments: info pointer to device instance data
6206 * Return Value: None
6207 */
6208 static void usc_set_txidle( struct mgsl_struct *info )
6209 {
6210 u16 usc_idle_mode = IDLEMODE_FLAGS;
6211
6212 /* Map API idle mode to USC register bits */
6213
6214 switch( info->idle_mode ){
6215 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6216 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6217 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6218 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6219 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6220 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6221 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6222 }
6223
6224 info->usc_idle_mode = usc_idle_mode;
6225 //usc_OutReg(info, TCSR, usc_idle_mode);
6226 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6227 info->tcsr_value += usc_idle_mode;
6228 usc_OutReg(info, TCSR, info->tcsr_value);
6229
6230 /*
6231 * if SyncLink WAN adapter is running in external sync mode, the
6232 * transmitter has been set to Monosync in order to try to mimic
6233 * a true raw outbound bit stream. Monosync still sends an open/close
6234 * sync char at the start/end of a frame. Try to match those sync
6235 * patterns to the idle mode set here
6236 */
6237 if ( info->params.mode == MGSL_MODE_RAW ) {
6238 unsigned char syncpat = 0;
6239 switch( info->idle_mode ) {
6240 case HDLC_TXIDLE_FLAGS:
6241 syncpat = 0x7e;
6242 break;
6243 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6244 syncpat = 0x55;
6245 break;
6246 case HDLC_TXIDLE_ZEROS:
6247 case HDLC_TXIDLE_SPACE:
6248 syncpat = 0x00;
6249 break;
6250 case HDLC_TXIDLE_ONES:
6251 case HDLC_TXIDLE_MARK:
6252 syncpat = 0xff;
6253 break;
6254 case HDLC_TXIDLE_ALT_MARK_SPACE:
6255 syncpat = 0xaa;
6256 break;
6257 }
6258
6259 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6260 }
6261
6262 } /* end of usc_set_txidle() */
6263
6264 /* usc_get_serial_signals()
6265 *
6266 * Query the adapter for the state of the V24 status (input) signals.
6267 *
6268 * Arguments: info pointer to device instance data
6269 * Return Value: None
6270 */
6271 static void usc_get_serial_signals( struct mgsl_struct *info )
6272 {
6273 u16 status;
6274
6275 /* clear all serial signals except DTR and RTS */
6276 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6277
6278 /* Read the Misc Interrupt status Register (MISR) to get */
6279 /* the V24 status signals. */
6280
6281 status = usc_InReg( info, MISR );
6282
6283 /* set serial signal bits to reflect MISR */
6284
6285 if ( status & MISCSTATUS_CTS )
6286 info->serial_signals |= SerialSignal_CTS;
6287
6288 if ( status & MISCSTATUS_DCD )
6289 info->serial_signals |= SerialSignal_DCD;
6290
6291 if ( status & MISCSTATUS_RI )
6292 info->serial_signals |= SerialSignal_RI;
6293
6294 if ( status & MISCSTATUS_DSR )
6295 info->serial_signals |= SerialSignal_DSR;
6296
6297 } /* end of usc_get_serial_signals() */
6298
6299 /* usc_set_serial_signals()
6300 *
6301 * Set the state of DTR and RTS based on contents of
6302 * serial_signals member of device extension.
6303 *
6304 * Arguments: info pointer to device instance data
6305 * Return Value: None
6306 */
6307 static void usc_set_serial_signals( struct mgsl_struct *info )
6308 {
6309 u16 Control;
6310 unsigned char V24Out = info->serial_signals;
6311
6312 /* get the current value of the Port Control Register (PCR) */
6313
6314 Control = usc_InReg( info, PCR );
6315
6316 if ( V24Out & SerialSignal_RTS )
6317 Control &= ~(BIT6);
6318 else
6319 Control |= BIT6;
6320
6321 if ( V24Out & SerialSignal_DTR )
6322 Control &= ~(BIT4);
6323 else
6324 Control |= BIT4;
6325
6326 usc_OutReg( info, PCR, Control );
6327
6328 } /* end of usc_set_serial_signals() */
6329
6330 /* usc_enable_async_clock()
6331 *
6332 * Enable the async clock at the specified frequency.
6333 *
6334 * Arguments: info pointer to device instance data
6335 * data_rate data rate of clock in bps
6336 * 0 disables the AUX clock.
6337 * Return Value: None
6338 */
6339 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6340 {
6341 if ( data_rate ) {
6342 /*
6343 * Clock mode Control Register (CMCR)
6344 *
6345 * <15..14> 00 counter 1 Disabled
6346 * <13..12> 00 counter 0 Disabled
6347 * <11..10> 11 BRG1 Input is TxC Pin
6348 * <9..8> 11 BRG0 Input is TxC Pin
6349 * <7..6> 01 DPLL Input is BRG1 Output
6350 * <5..3> 100 TxCLK comes from BRG0
6351 * <2..0> 100 RxCLK comes from BRG0
6352 *
6353 * 0000 1111 0110 0100 = 0x0f64
6354 */
6355
6356 usc_OutReg( info, CMCR, 0x0f64 );
6357
6358
6359 /*
6360 * Write 16-bit Time Constant for BRG0
6361 * Time Constant = (ClkSpeed / data_rate) - 1
6362 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6363 */
6364
6365 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6366 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6367 else
6368 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6369
6370
6371 /*
6372 * Hardware Configuration Register (HCR)
6373 * Clear Bit 1, BRG0 mode = Continuous
6374 * Set Bit 0 to enable BRG0.
6375 */
6376
6377 usc_OutReg( info, HCR,
6378 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6379
6380
6381 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6382
6383 usc_OutReg( info, IOCR,
6384 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6385 } else {
6386 /* data rate == 0 so turn off BRG0 */
6387 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6388 }
6389
6390 } /* end of usc_enable_async_clock() */
6391
6392 /*
6393 * Buffer Structures:
6394 *
6395 * Normal memory access uses virtual addresses that can make discontiguous
6396 * physical memory pages appear to be contiguous in the virtual address
6397 * space (the processors memory mapping handles the conversions).
6398 *
6399 * DMA transfers require physically contiguous memory. This is because
6400 * the DMA system controller and DMA bus masters deal with memory using
6401 * only physical addresses.
6402 *
6403 * This causes a problem under Windows NT when large DMA buffers are
6404 * needed. Fragmentation of the nonpaged pool prevents allocations of
6405 * physically contiguous buffers larger than the PAGE_SIZE.
6406 *
6407 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6408 * allows DMA transfers to physically discontiguous buffers. Information
6409 * about each data transfer buffer is contained in a memory structure
6410 * called a 'buffer entry'. A list of buffer entries is maintained
6411 * to track and control the use of the data transfer buffers.
6412 *
6413 * To support this strategy we will allocate sufficient PAGE_SIZE
6414 * contiguous memory buffers to allow for the total required buffer
6415 * space.
6416 *
6417 * The 16C32 accesses the list of buffer entries using Bus Master
6418 * DMA. Control information is read from the buffer entries by the
6419 * 16C32 to control data transfers. status information is written to
6420 * the buffer entries by the 16C32 to indicate the status of completed
6421 * transfers.
6422 *
6423 * The CPU writes control information to the buffer entries to control
6424 * the 16C32 and reads status information from the buffer entries to
6425 * determine information about received and transmitted frames.
6426 *
6427 * Because the CPU and 16C32 (adapter) both need simultaneous access
6428 * to the buffer entries, the buffer entry memory is allocated with
6429 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6430 * entry list to PAGE_SIZE.
6431 *
6432 * The actual data buffers on the other hand will only be accessed
6433 * by the CPU or the adapter but not by both simultaneously. This allows
6434 * Scatter/Gather packet based DMA procedures for using physically
6435 * discontiguous pages.
6436 */
6437
6438 /*
6439 * mgsl_reset_tx_dma_buffers()
6440 *
6441 * Set the count for all transmit buffers to 0 to indicate the
6442 * buffer is available for use and set the current buffer to the
6443 * first buffer. This effectively makes all buffers free and
6444 * discards any data in buffers.
6445 *
6446 * Arguments: info pointer to device instance data
6447 * Return Value: None
6448 */
6449 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6450 {
6451 unsigned int i;
6452
6453 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6454 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6455 }
6456
6457 info->current_tx_buffer = 0;
6458 info->start_tx_dma_buffer = 0;
6459 info->tx_dma_buffers_used = 0;
6460
6461 info->get_tx_holding_index = 0;
6462 info->put_tx_holding_index = 0;
6463 info->tx_holding_count = 0;
6464
6465 } /* end of mgsl_reset_tx_dma_buffers() */
6466
6467 /*
6468 * num_free_tx_dma_buffers()
6469 *
6470 * returns the number of free tx dma buffers available
6471 *
6472 * Arguments: info pointer to device instance data
6473 * Return Value: number of free tx dma buffers
6474 */
6475 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6476 {
6477 return info->tx_buffer_count - info->tx_dma_buffers_used;
6478 }
6479
6480 /*
6481 * mgsl_reset_rx_dma_buffers()
6482 *
6483 * Set the count for all receive buffers to DMABUFFERSIZE
6484 * and set the current buffer to the first buffer. This effectively
6485 * makes all buffers free and discards any data in buffers.
6486 *
6487 * Arguments: info pointer to device instance data
6488 * Return Value: None
6489 */
6490 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6491 {
6492 unsigned int i;
6493
6494 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6495 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6496 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6497 // info->rx_buffer_list[i].status = 0;
6498 }
6499
6500 info->current_rx_buffer = 0;
6501
6502 } /* end of mgsl_reset_rx_dma_buffers() */
6503
6504 /*
6505 * mgsl_free_rx_frame_buffers()
6506 *
6507 * Free the receive buffers used by a received SDLC
6508 * frame such that the buffers can be reused.
6509 *
6510 * Arguments:
6511 *
6512 * info pointer to device instance data
6513 * StartIndex index of 1st receive buffer of frame
6514 * EndIndex index of last receive buffer of frame
6515 *
6516 * Return Value: None
6517 */
6518 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6519 {
6520 bool Done = false;
6521 DMABUFFERENTRY *pBufEntry;
6522 unsigned int Index;
6523
6524 /* Starting with 1st buffer entry of the frame clear the status */
6525 /* field and set the count field to DMA Buffer Size. */
6526
6527 Index = StartIndex;
6528
6529 while( !Done ) {
6530 pBufEntry = &(info->rx_buffer_list[Index]);
6531
6532 if ( Index == EndIndex ) {
6533 /* This is the last buffer of the frame! */
6534 Done = true;
6535 }
6536
6537 /* reset current buffer for reuse */
6538 // pBufEntry->status = 0;
6539 // pBufEntry->count = DMABUFFERSIZE;
6540 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6541
6542 /* advance to next buffer entry in linked list */
6543 Index++;
6544 if ( Index == info->rx_buffer_count )
6545 Index = 0;
6546 }
6547
6548 /* set current buffer to next buffer after last buffer of frame */
6549 info->current_rx_buffer = Index;
6550
6551 } /* end of free_rx_frame_buffers() */
6552
6553 /* mgsl_get_rx_frame()
6554 *
6555 * This function attempts to return a received SDLC frame from the
6556 * receive DMA buffers. Only frames received without errors are returned.
6557 *
6558 * Arguments: info pointer to device extension
6559 * Return Value: true if frame returned, otherwise false
6560 */
6561 static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6562 {
6563 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6564 unsigned short status;
6565 DMABUFFERENTRY *pBufEntry;
6566 unsigned int framesize = 0;
6567 bool ReturnCode = false;
6568 unsigned long flags;
6569 struct tty_struct *tty = info->tty;
6570 bool return_frame = false;
6571
6572 /*
6573 * current_rx_buffer points to the 1st buffer of the next available
6574 * receive frame. To find the last buffer of the frame look for
6575 * a non-zero status field in the buffer entries. (The status
6576 * field is set by the 16C32 after completing a receive frame.
6577 */
6578
6579 StartIndex = EndIndex = info->current_rx_buffer;
6580
6581 while( !info->rx_buffer_list[EndIndex].status ) {
6582 /*
6583 * If the count field of the buffer entry is non-zero then
6584 * this buffer has not been used. (The 16C32 clears the count
6585 * field when it starts using the buffer.) If an unused buffer
6586 * is encountered then there are no frames available.
6587 */
6588
6589 if ( info->rx_buffer_list[EndIndex].count )
6590 goto Cleanup;
6591
6592 /* advance to next buffer entry in linked list */
6593 EndIndex++;
6594 if ( EndIndex == info->rx_buffer_count )
6595 EndIndex = 0;
6596
6597 /* if entire list searched then no frame available */
6598 if ( EndIndex == StartIndex ) {
6599 /* If this occurs then something bad happened,
6600 * all buffers have been 'used' but none mark
6601 * the end of a frame. Reset buffers and receiver.
6602 */
6603
6604 if ( info->rx_enabled ){
6605 spin_lock_irqsave(&info->irq_spinlock,flags);
6606 usc_start_receiver(info);
6607 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6608 }
6609 goto Cleanup;
6610 }
6611 }
6612
6613
6614 /* check status of receive frame */
6615
6616 status = info->rx_buffer_list[EndIndex].status;
6617
6618 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6619 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6620 if ( status & RXSTATUS_SHORT_FRAME )
6621 info->icount.rxshort++;
6622 else if ( status & RXSTATUS_ABORT )
6623 info->icount.rxabort++;
6624 else if ( status & RXSTATUS_OVERRUN )
6625 info->icount.rxover++;
6626 else {
6627 info->icount.rxcrc++;
6628 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6629 return_frame = true;
6630 }
6631 framesize = 0;
6632 #if SYNCLINK_GENERIC_HDLC
6633 {
6634 struct net_device_stats *stats = hdlc_stats(info->netdev);
6635 stats->rx_errors++;
6636 stats->rx_frame_errors++;
6637 }
6638 #endif
6639 } else
6640 return_frame = true;
6641
6642 if ( return_frame ) {
6643 /* receive frame has no errors, get frame size.
6644 * The frame size is the starting value of the RCC (which was
6645 * set to 0xffff) minus the ending value of the RCC (decremented
6646 * once for each receive character) minus 2 for the 16-bit CRC.
6647 */
6648
6649 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6650
6651 /* adjust frame size for CRC if any */
6652 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6653 framesize -= 2;
6654 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6655 framesize -= 4;
6656 }
6657
6658 if ( debug_level >= DEBUG_LEVEL_BH )
6659 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6660 __FILE__,__LINE__,info->device_name,status,framesize);
6661
6662 if ( debug_level >= DEBUG_LEVEL_DATA )
6663 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6664 min_t(int, framesize, DMABUFFERSIZE),0);
6665
6666 if (framesize) {
6667 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6668 ((framesize+1) > info->max_frame_size) ) ||
6669 (framesize > info->max_frame_size) )
6670 info->icount.rxlong++;
6671 else {
6672 /* copy dma buffer(s) to contiguous intermediate buffer */
6673 int copy_count = framesize;
6674 int index = StartIndex;
6675 unsigned char *ptmp = info->intermediate_rxbuffer;
6676
6677 if ( !(status & RXSTATUS_CRC_ERROR))
6678 info->icount.rxok++;
6679
6680 while(copy_count) {
6681 int partial_count;
6682 if ( copy_count > DMABUFFERSIZE )
6683 partial_count = DMABUFFERSIZE;
6684 else
6685 partial_count = copy_count;
6686
6687 pBufEntry = &(info->rx_buffer_list[index]);
6688 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6689 ptmp += partial_count;
6690 copy_count -= partial_count;
6691
6692 if ( ++index == info->rx_buffer_count )
6693 index = 0;
6694 }
6695
6696 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6697 ++framesize;
6698 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6699 RX_CRC_ERROR :
6700 RX_OK);
6701
6702 if ( debug_level >= DEBUG_LEVEL_DATA )
6703 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6704 __FILE__,__LINE__,info->device_name,
6705 *ptmp);
6706 }
6707
6708 #if SYNCLINK_GENERIC_HDLC
6709 if (info->netcount)
6710 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6711 else
6712 #endif
6713 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6714 }
6715 }
6716 /* Free the buffers used by this frame. */
6717 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6718
6719 ReturnCode = true;
6720
6721 Cleanup:
6722
6723 if ( info->rx_enabled && info->rx_overflow ) {
6724 /* The receiver needs to restarted because of
6725 * a receive overflow (buffer or FIFO). If the
6726 * receive buffers are now empty, then restart receiver.
6727 */
6728
6729 if ( !info->rx_buffer_list[EndIndex].status &&
6730 info->rx_buffer_list[EndIndex].count ) {
6731 spin_lock_irqsave(&info->irq_spinlock,flags);
6732 usc_start_receiver(info);
6733 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6734 }
6735 }
6736
6737 return ReturnCode;
6738
6739 } /* end of mgsl_get_rx_frame() */
6740
6741 /* mgsl_get_raw_rx_frame()
6742 *
6743 * This function attempts to return a received frame from the
6744 * receive DMA buffers when running in external loop mode. In this mode,
6745 * we will return at most one DMABUFFERSIZE frame to the application.
6746 * The USC receiver is triggering off of DCD going active to start a new
6747 * frame, and DCD going inactive to terminate the frame (similar to
6748 * processing a closing flag character).
6749 *
6750 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6751 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6752 * status field and the RCC field will indicate the length of the
6753 * entire received frame. We take this RCC field and get the modulus
6754 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6755 * last Rx DMA buffer and return that last portion of the frame.
6756 *
6757 * Arguments: info pointer to device extension
6758 * Return Value: true if frame returned, otherwise false
6759 */
6760 static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6761 {
6762 unsigned int CurrentIndex, NextIndex;
6763 unsigned short status;
6764 DMABUFFERENTRY *pBufEntry;
6765 unsigned int framesize = 0;
6766 bool ReturnCode = false;
6767 unsigned long flags;
6768 struct tty_struct *tty = info->tty;
6769
6770 /*
6771 * current_rx_buffer points to the 1st buffer of the next available
6772 * receive frame. The status field is set by the 16C32 after
6773 * completing a receive frame. If the status field of this buffer
6774 * is zero, either the USC is still filling this buffer or this
6775 * is one of a series of buffers making up a received frame.
6776 *
6777 * If the count field of this buffer is zero, the USC is either
6778 * using this buffer or has used this buffer. Look at the count
6779 * field of the next buffer. If that next buffer's count is
6780 * non-zero, the USC is still actively using the current buffer.
6781 * Otherwise, if the next buffer's count field is zero, the
6782 * current buffer is complete and the USC is using the next
6783 * buffer.
6784 */
6785 CurrentIndex = NextIndex = info->current_rx_buffer;
6786 ++NextIndex;
6787 if ( NextIndex == info->rx_buffer_count )
6788 NextIndex = 0;
6789
6790 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6791 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6792 info->rx_buffer_list[NextIndex].count == 0)) {
6793 /*
6794 * Either the status field of this dma buffer is non-zero
6795 * (indicating the last buffer of a receive frame) or the next
6796 * buffer is marked as in use -- implying this buffer is complete
6797 * and an intermediate buffer for this received frame.
6798 */
6799
6800 status = info->rx_buffer_list[CurrentIndex].status;
6801
6802 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6803 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6804 if ( status & RXSTATUS_SHORT_FRAME )
6805 info->icount.rxshort++;
6806 else if ( status & RXSTATUS_ABORT )
6807 info->icount.rxabort++;
6808 else if ( status & RXSTATUS_OVERRUN )
6809 info->icount.rxover++;
6810 else
6811 info->icount.rxcrc++;
6812 framesize = 0;
6813 } else {
6814 /*
6815 * A receive frame is available, get frame size and status.
6816 *
6817 * The frame size is the starting value of the RCC (which was
6818 * set to 0xffff) minus the ending value of the RCC (decremented
6819 * once for each receive character) minus 2 or 4 for the 16-bit
6820 * or 32-bit CRC.
6821 *
6822 * If the status field is zero, this is an intermediate buffer.
6823 * It's size is 4K.
6824 *
6825 * If the DMA Buffer Entry's Status field is non-zero, the
6826 * receive operation completed normally (ie: DCD dropped). The
6827 * RCC field is valid and holds the received frame size.
6828 * It is possible that the RCC field will be zero on a DMA buffer
6829 * entry with a non-zero status. This can occur if the total
6830 * frame size (number of bytes between the time DCD goes active
6831 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6832 * case the 16C32 has underrun on the RCC count and appears to
6833 * stop updating this counter to let us know the actual received
6834 * frame size. If this happens (non-zero status and zero RCC),
6835 * simply return the entire RxDMA Buffer
6836 */
6837 if ( status ) {
6838 /*
6839 * In the event that the final RxDMA Buffer is
6840 * terminated with a non-zero status and the RCC
6841 * field is zero, we interpret this as the RCC
6842 * having underflowed (received frame > 65535 bytes).
6843 *
6844 * Signal the event to the user by passing back
6845 * a status of RxStatus_CrcError returning the full
6846 * buffer and let the app figure out what data is
6847 * actually valid
6848 */
6849 if ( info->rx_buffer_list[CurrentIndex].rcc )
6850 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6851 else
6852 framesize = DMABUFFERSIZE;
6853 }
6854 else
6855 framesize = DMABUFFERSIZE;
6856 }
6857
6858 if ( framesize > DMABUFFERSIZE ) {
6859 /*
6860 * if running in raw sync mode, ISR handler for
6861 * End Of Buffer events terminates all buffers at 4K.
6862 * If this frame size is said to be >4K, get the
6863 * actual number of bytes of the frame in this buffer.
6864 */
6865 framesize = framesize % DMABUFFERSIZE;
6866 }
6867
6868
6869 if ( debug_level >= DEBUG_LEVEL_BH )
6870 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6871 __FILE__,__LINE__,info->device_name,status,framesize);
6872
6873 if ( debug_level >= DEBUG_LEVEL_DATA )
6874 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6875 min_t(int, framesize, DMABUFFERSIZE),0);
6876
6877 if (framesize) {
6878 /* copy dma buffer(s) to contiguous intermediate buffer */
6879 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6880
6881 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6882 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6883 info->icount.rxok++;
6884
6885 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6886 }
6887
6888 /* Free the buffers used by this frame. */
6889 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6890
6891 ReturnCode = true;
6892 }
6893
6894
6895 if ( info->rx_enabled && info->rx_overflow ) {
6896 /* The receiver needs to restarted because of
6897 * a receive overflow (buffer or FIFO). If the
6898 * receive buffers are now empty, then restart receiver.
6899 */
6900
6901 if ( !info->rx_buffer_list[CurrentIndex].status &&
6902 info->rx_buffer_list[CurrentIndex].count ) {
6903 spin_lock_irqsave(&info->irq_spinlock,flags);
6904 usc_start_receiver(info);
6905 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6906 }
6907 }
6908
6909 return ReturnCode;
6910
6911 } /* end of mgsl_get_raw_rx_frame() */
6912
6913 /* mgsl_load_tx_dma_buffer()
6914 *
6915 * Load the transmit DMA buffer with the specified data.
6916 *
6917 * Arguments:
6918 *
6919 * info pointer to device extension
6920 * Buffer pointer to buffer containing frame to load
6921 * BufferSize size in bytes of frame in Buffer
6922 *
6923 * Return Value: None
6924 */
6925 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6926 const char *Buffer, unsigned int BufferSize)
6927 {
6928 unsigned short Copycount;
6929 unsigned int i = 0;
6930 DMABUFFERENTRY *pBufEntry;
6931
6932 if ( debug_level >= DEBUG_LEVEL_DATA )
6933 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6934
6935 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6936 /* set CMR:13 to start transmit when
6937 * next GoAhead (abort) is received
6938 */
6939 info->cmr_value |= BIT13;
6940 }
6941
6942 /* begin loading the frame in the next available tx dma
6943 * buffer, remember it's starting location for setting
6944 * up tx dma operation
6945 */
6946 i = info->current_tx_buffer;
6947 info->start_tx_dma_buffer = i;
6948
6949 /* Setup the status and RCC (Frame Size) fields of the 1st */
6950 /* buffer entry in the transmit DMA buffer list. */
6951
6952 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6953 info->tx_buffer_list[i].rcc = BufferSize;
6954 info->tx_buffer_list[i].count = BufferSize;
6955
6956 /* Copy frame data from 1st source buffer to the DMA buffers. */
6957 /* The frame data may span multiple DMA buffers. */
6958
6959 while( BufferSize ){
6960 /* Get a pointer to next DMA buffer entry. */
6961 pBufEntry = &info->tx_buffer_list[i++];
6962
6963 if ( i == info->tx_buffer_count )
6964 i=0;
6965
6966 /* Calculate the number of bytes that can be copied from */
6967 /* the source buffer to this DMA buffer. */
6968 if ( BufferSize > DMABUFFERSIZE )
6969 Copycount = DMABUFFERSIZE;
6970 else
6971 Copycount = BufferSize;
6972
6973 /* Actually copy data from source buffer to DMA buffer. */
6974 /* Also set the data count for this individual DMA buffer. */
6975 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6976 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6977 else
6978 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6979
6980 pBufEntry->count = Copycount;
6981
6982 /* Advance source pointer and reduce remaining data count. */
6983 Buffer += Copycount;
6984 BufferSize -= Copycount;
6985
6986 ++info->tx_dma_buffers_used;
6987 }
6988
6989 /* remember next available tx dma buffer */
6990 info->current_tx_buffer = i;
6991
6992 } /* end of mgsl_load_tx_dma_buffer() */
6993
6994 /*
6995 * mgsl_register_test()
6996 *
6997 * Performs a register test of the 16C32.
6998 *
6999 * Arguments: info pointer to device instance data
7000 * Return Value: true if test passed, otherwise false
7001 */
7002 static bool mgsl_register_test( struct mgsl_struct *info )
7003 {
7004 static unsigned short BitPatterns[] =
7005 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7006 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
7007 unsigned int i;
7008 bool rc = true;
7009 unsigned long flags;
7010
7011 spin_lock_irqsave(&info->irq_spinlock,flags);
7012 usc_reset(info);
7013
7014 /* Verify the reset state of some registers. */
7015
7016 if ( (usc_InReg( info, SICR ) != 0) ||
7017 (usc_InReg( info, IVR ) != 0) ||
7018 (usc_InDmaReg( info, DIVR ) != 0) ){
7019 rc = false;
7020 }
7021
7022 if ( rc ){
7023 /* Write bit patterns to various registers but do it out of */
7024 /* sync, then read back and verify values. */
7025
7026 for ( i = 0 ; i < Patterncount ; i++ ) {
7027 usc_OutReg( info, TC0R, BitPatterns[i] );
7028 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7029 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7030 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7031 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
7032 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7033
7034 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7035 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7036 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7037 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7038 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7039 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7040 rc = false;
7041 break;
7042 }
7043 }
7044 }
7045
7046 usc_reset(info);
7047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7048
7049 return rc;
7050
7051 } /* end of mgsl_register_test() */
7052
7053 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7054 *
7055 * Arguments: info pointer to device instance data
7056 * Return Value: true if test passed, otherwise false
7057 */
7058 static bool mgsl_irq_test( struct mgsl_struct *info )
7059 {
7060 unsigned long EndTime;
7061 unsigned long flags;
7062
7063 spin_lock_irqsave(&info->irq_spinlock,flags);
7064 usc_reset(info);
7065
7066 /*
7067 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7068 * The ISR sets irq_occurred to true.
7069 */
7070
7071 info->irq_occurred = false;
7072
7073 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7074 /* Enable INTEN (Port 6, Bit12) */
7075 /* This connects the IRQ request signal to the ISA bus */
7076 /* on the ISA adapter. This has no effect for the PCI adapter */
7077 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7078
7079 usc_EnableMasterIrqBit(info);
7080 usc_EnableInterrupts(info, IO_PIN);
7081 usc_ClearIrqPendingBits(info, IO_PIN);
7082
7083 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7084 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7085
7086 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7087
7088 EndTime=100;
7089 while( EndTime-- && !info->irq_occurred ) {
7090 msleep_interruptible(10);
7091 }
7092
7093 spin_lock_irqsave(&info->irq_spinlock,flags);
7094 usc_reset(info);
7095 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7096
7097 return info->irq_occurred;
7098
7099 } /* end of mgsl_irq_test() */
7100
7101 /* mgsl_dma_test()
7102 *
7103 * Perform a DMA test of the 16C32. A small frame is
7104 * transmitted via DMA from a transmit buffer to a receive buffer
7105 * using single buffer DMA mode.
7106 *
7107 * Arguments: info pointer to device instance data
7108 * Return Value: true if test passed, otherwise false
7109 */
7110 static bool mgsl_dma_test( struct mgsl_struct *info )
7111 {
7112 unsigned short FifoLevel;
7113 unsigned long phys_addr;
7114 unsigned int FrameSize;
7115 unsigned int i;
7116 char *TmpPtr;
7117 bool rc = true;
7118 unsigned short status=0;
7119 unsigned long EndTime;
7120 unsigned long flags;
7121 MGSL_PARAMS tmp_params;
7122
7123 /* save current port options */
7124 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7125 /* load default port options */
7126 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7127
7128 #define TESTFRAMESIZE 40
7129
7130 spin_lock_irqsave(&info->irq_spinlock,flags);
7131
7132 /* setup 16C32 for SDLC DMA transfer mode */
7133
7134 usc_reset(info);
7135 usc_set_sdlc_mode(info);
7136 usc_enable_loopback(info,1);
7137
7138 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7139 * field of the buffer entry after fetching buffer address. This
7140 * way we can detect a DMA failure for a DMA read (which should be
7141 * non-destructive to system memory) before we try and write to
7142 * memory (where a failure could corrupt system memory).
7143 */
7144
7145 /* Receive DMA mode Register (RDMR)
7146 *
7147 * <15..14> 11 DMA mode = Linked List Buffer mode
7148 * <13> 1 RSBinA/L = store Rx status Block in List entry
7149 * <12> 0 1 = Clear count of List Entry after fetching
7150 * <11..10> 00 Address mode = Increment
7151 * <9> 1 Terminate Buffer on RxBound
7152 * <8> 0 Bus Width = 16bits
7153 * <7..0> ? status Bits (write as 0s)
7154 *
7155 * 1110 0010 0000 0000 = 0xe200
7156 */
7157
7158 usc_OutDmaReg( info, RDMR, 0xe200 );
7159
7160 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7161
7162
7163 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7164
7165 FrameSize = TESTFRAMESIZE;
7166
7167 /* setup 1st transmit buffer entry: */
7168 /* with frame size and transmit control word */
7169
7170 info->tx_buffer_list[0].count = FrameSize;
7171 info->tx_buffer_list[0].rcc = FrameSize;
7172 info->tx_buffer_list[0].status = 0x4000;
7173
7174 /* build a transmit frame in 1st transmit DMA buffer */
7175
7176 TmpPtr = info->tx_buffer_list[0].virt_addr;
7177 for (i = 0; i < FrameSize; i++ )
7178 *TmpPtr++ = i;
7179
7180 /* setup 1st receive buffer entry: */
7181 /* clear status, set max receive buffer size */
7182
7183 info->rx_buffer_list[0].status = 0;
7184 info->rx_buffer_list[0].count = FrameSize + 4;
7185
7186 /* zero out the 1st receive buffer */
7187
7188 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7189
7190 /* Set count field of next buffer entries to prevent */
7191 /* 16C32 from using buffers after the 1st one. */
7192
7193 info->tx_buffer_list[1].count = 0;
7194 info->rx_buffer_list[1].count = 0;
7195
7196
7197 /***************************/
7198 /* Program 16C32 receiver. */
7199 /***************************/
7200
7201 spin_lock_irqsave(&info->irq_spinlock,flags);
7202
7203 /* setup DMA transfers */
7204 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7205
7206 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7207 phys_addr = info->rx_buffer_list[0].phys_entry;
7208 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7209 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7210
7211 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7212 usc_InDmaReg( info, RDMR );
7213 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7214
7215 /* Enable Receiver (RMR <1..0> = 10) */
7216 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7217
7218 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7219
7220
7221 /*************************************************************/
7222 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7223 /*************************************************************/
7224
7225 /* Wait 100ms for interrupt. */
7226 EndTime = jiffies + msecs_to_jiffies(100);
7227
7228 for(;;) {
7229 if (time_after(jiffies, EndTime)) {
7230 rc = false;
7231 break;
7232 }
7233
7234 spin_lock_irqsave(&info->irq_spinlock,flags);
7235 status = usc_InDmaReg( info, RDMR );
7236 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7237
7238 if ( !(status & BIT4) && (status & BIT5) ) {
7239 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7240 /* BUSY (BIT 5) is active (channel still active). */
7241 /* This means the buffer entry read has completed. */
7242 break;
7243 }
7244 }
7245
7246
7247 /******************************/
7248 /* Program 16C32 transmitter. */
7249 /******************************/
7250
7251 spin_lock_irqsave(&info->irq_spinlock,flags);
7252
7253 /* Program the Transmit Character Length Register (TCLR) */
7254 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7255
7256 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7257 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7258
7259 /* Program the address of the 1st DMA Buffer Entry in linked list */
7260
7261 phys_addr = info->tx_buffer_list[0].phys_entry;
7262 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7263 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7264
7265 /* unlatch Tx status bits, and start transmit channel. */
7266
7267 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7268 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7269
7270 /* wait for DMA controller to fill transmit FIFO */
7271
7272 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7273
7274 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7275
7276
7277 /**********************************/
7278 /* WAIT FOR TRANSMIT FIFO TO FILL */
7279 /**********************************/
7280
7281 /* Wait 100ms */
7282 EndTime = jiffies + msecs_to_jiffies(100);
7283
7284 for(;;) {
7285 if (time_after(jiffies, EndTime)) {
7286 rc = false;
7287 break;
7288 }
7289
7290 spin_lock_irqsave(&info->irq_spinlock,flags);
7291 FifoLevel = usc_InReg(info, TICR) >> 8;
7292 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7293
7294 if ( FifoLevel < 16 )
7295 break;
7296 else
7297 if ( FrameSize < 32 ) {
7298 /* This frame is smaller than the entire transmit FIFO */
7299 /* so wait for the entire frame to be loaded. */
7300 if ( FifoLevel <= (32 - FrameSize) )
7301 break;
7302 }
7303 }
7304
7305
7306 if ( rc )
7307 {
7308 /* Enable 16C32 transmitter. */
7309
7310 spin_lock_irqsave(&info->irq_spinlock,flags);
7311
7312 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7313 usc_TCmd( info, TCmd_SendFrame );
7314 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7315
7316 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7317
7318
7319 /******************************/
7320 /* WAIT FOR TRANSMIT COMPLETE */
7321 /******************************/
7322
7323 /* Wait 100ms */
7324 EndTime = jiffies + msecs_to_jiffies(100);
7325
7326 /* While timer not expired wait for transmit complete */
7327
7328 spin_lock_irqsave(&info->irq_spinlock,flags);
7329 status = usc_InReg( info, TCSR );
7330 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7331
7332 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7333 if (time_after(jiffies, EndTime)) {
7334 rc = false;
7335 break;
7336 }
7337
7338 spin_lock_irqsave(&info->irq_spinlock,flags);
7339 status = usc_InReg( info, TCSR );
7340 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7341 }
7342 }
7343
7344
7345 if ( rc ){
7346 /* CHECK FOR TRANSMIT ERRORS */
7347 if ( status & (BIT5 + BIT1) )
7348 rc = false;
7349 }
7350
7351 if ( rc ) {
7352 /* WAIT FOR RECEIVE COMPLETE */
7353
7354 /* Wait 100ms */
7355 EndTime = jiffies + msecs_to_jiffies(100);
7356
7357 /* Wait for 16C32 to write receive status to buffer entry. */
7358 status=info->rx_buffer_list[0].status;
7359 while ( status == 0 ) {
7360 if (time_after(jiffies, EndTime)) {
7361 rc = false;
7362 break;
7363 }
7364 status=info->rx_buffer_list[0].status;
7365 }
7366 }
7367
7368
7369 if ( rc ) {
7370 /* CHECK FOR RECEIVE ERRORS */
7371 status = info->rx_buffer_list[0].status;
7372
7373 if ( status & (BIT8 + BIT3 + BIT1) ) {
7374 /* receive error has occurred */
7375 rc = false;
7376 } else {
7377 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7378 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7379 rc = false;
7380 }
7381 }
7382 }
7383
7384 spin_lock_irqsave(&info->irq_spinlock,flags);
7385 usc_reset( info );
7386 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7387
7388 /* restore current port options */
7389 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7390
7391 return rc;
7392
7393 } /* end of mgsl_dma_test() */
7394
7395 /* mgsl_adapter_test()
7396 *
7397 * Perform the register, IRQ, and DMA tests for the 16C32.
7398 *
7399 * Arguments: info pointer to device instance data
7400 * Return Value: 0 if success, otherwise -ENODEV
7401 */
7402 static int mgsl_adapter_test( struct mgsl_struct *info )
7403 {
7404 if ( debug_level >= DEBUG_LEVEL_INFO )
7405 printk( "%s(%d):Testing device %s\n",
7406 __FILE__,__LINE__,info->device_name );
7407
7408 if ( !mgsl_register_test( info ) ) {
7409 info->init_error = DiagStatus_AddressFailure;
7410 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7411 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7412 return -ENODEV;
7413 }
7414
7415 if ( !mgsl_irq_test( info ) ) {
7416 info->init_error = DiagStatus_IrqFailure;
7417 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7418 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7419 return -ENODEV;
7420 }
7421
7422 if ( !mgsl_dma_test( info ) ) {
7423 info->init_error = DiagStatus_DmaFailure;
7424 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7425 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7426 return -ENODEV;
7427 }
7428
7429 if ( debug_level >= DEBUG_LEVEL_INFO )
7430 printk( "%s(%d):device %s passed diagnostics\n",
7431 __FILE__,__LINE__,info->device_name );
7432
7433 return 0;
7434
7435 } /* end of mgsl_adapter_test() */
7436
7437 /* mgsl_memory_test()
7438 *
7439 * Test the shared memory on a PCI adapter.
7440 *
7441 * Arguments: info pointer to device instance data
7442 * Return Value: true if test passed, otherwise false
7443 */
7444 static bool mgsl_memory_test( struct mgsl_struct *info )
7445 {
7446 static unsigned long BitPatterns[] =
7447 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7448 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7449 unsigned long i;
7450 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7451 unsigned long * TestAddr;
7452
7453 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7454 return true;
7455
7456 TestAddr = (unsigned long *)info->memory_base;
7457
7458 /* Test data lines with test pattern at one location. */
7459
7460 for ( i = 0 ; i < Patterncount ; i++ ) {
7461 *TestAddr = BitPatterns[i];
7462 if ( *TestAddr != BitPatterns[i] )
7463 return false;
7464 }
7465
7466 /* Test address lines with incrementing pattern over */
7467 /* entire address range. */
7468
7469 for ( i = 0 ; i < TestLimit ; i++ ) {
7470 *TestAddr = i * 4;
7471 TestAddr++;
7472 }
7473
7474 TestAddr = (unsigned long *)info->memory_base;
7475
7476 for ( i = 0 ; i < TestLimit ; i++ ) {
7477 if ( *TestAddr != i * 4 )
7478 return false;
7479 TestAddr++;
7480 }
7481
7482 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7483
7484 return true;
7485
7486 } /* End Of mgsl_memory_test() */
7487
7488
7489 /* mgsl_load_pci_memory()
7490 *
7491 * Load a large block of data into the PCI shared memory.
7492 * Use this instead of memcpy() or memmove() to move data
7493 * into the PCI shared memory.
7494 *
7495 * Notes:
7496 *
7497 * This function prevents the PCI9050 interface chip from hogging
7498 * the adapter local bus, which can starve the 16C32 by preventing
7499 * 16C32 bus master cycles.
7500 *
7501 * The PCI9050 documentation says that the 9050 will always release
7502 * control of the local bus after completing the current read
7503 * or write operation.
7504 *
7505 * It appears that as long as the PCI9050 write FIFO is full, the
7506 * PCI9050 treats all of the writes as a single burst transaction
7507 * and will not release the bus. This causes DMA latency problems
7508 * at high speeds when copying large data blocks to the shared
7509 * memory.
7510 *
7511 * This function in effect, breaks the a large shared memory write
7512 * into multiple transations by interleaving a shared memory read
7513 * which will flush the write FIFO and 'complete' the write
7514 * transation. This allows any pending DMA request to gain control
7515 * of the local bus in a timely fasion.
7516 *
7517 * Arguments:
7518 *
7519 * TargetPtr pointer to target address in PCI shared memory
7520 * SourcePtr pointer to source buffer for data
7521 * count count in bytes of data to copy
7522 *
7523 * Return Value: None
7524 */
7525 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7526 unsigned short count )
7527 {
7528 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7529 #define PCI_LOAD_INTERVAL 64
7530
7531 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7532 unsigned short Index;
7533 unsigned long Dummy;
7534
7535 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7536 {
7537 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7538 Dummy = *((volatile unsigned long *)TargetPtr);
7539 TargetPtr += PCI_LOAD_INTERVAL;
7540 SourcePtr += PCI_LOAD_INTERVAL;
7541 }
7542
7543 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7544
7545 } /* End Of mgsl_load_pci_memory() */
7546
7547 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7548 {
7549 int i;
7550 int linecount;
7551 if (xmit)
7552 printk("%s tx data:\n",info->device_name);
7553 else
7554 printk("%s rx data:\n",info->device_name);
7555
7556 while(count) {
7557 if (count > 16)
7558 linecount = 16;
7559 else
7560 linecount = count;
7561
7562 for(i=0;i<linecount;i++)
7563 printk("%02X ",(unsigned char)data[i]);
7564 for(;i<17;i++)
7565 printk(" ");
7566 for(i=0;i<linecount;i++) {
7567 if (data[i]>=040 && data[i]<=0176)
7568 printk("%c",data[i]);
7569 else
7570 printk(".");
7571 }
7572 printk("\n");
7573
7574 data += linecount;
7575 count -= linecount;
7576 }
7577 } /* end of mgsl_trace_block() */
7578
7579 /* mgsl_tx_timeout()
7580 *
7581 * called when HDLC frame times out
7582 * update stats and do tx completion processing
7583 *
7584 * Arguments: context pointer to device instance data
7585 * Return Value: None
7586 */
7587 static void mgsl_tx_timeout(unsigned long context)
7588 {
7589 struct mgsl_struct *info = (struct mgsl_struct*)context;
7590 unsigned long flags;
7591
7592 if ( debug_level >= DEBUG_LEVEL_INFO )
7593 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7594 __FILE__,__LINE__,info->device_name);
7595 if(info->tx_active &&
7596 (info->params.mode == MGSL_MODE_HDLC ||
7597 info->params.mode == MGSL_MODE_RAW) ) {
7598 info->icount.txtimeout++;
7599 }
7600 spin_lock_irqsave(&info->irq_spinlock,flags);
7601 info->tx_active = false;
7602 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7603
7604 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7605 usc_loopmode_cancel_transmit( info );
7606
7607 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7608
7609 #if SYNCLINK_GENERIC_HDLC
7610 if (info->netcount)
7611 hdlcdev_tx_done(info);
7612 else
7613 #endif
7614 mgsl_bh_transmit(info);
7615
7616 } /* end of mgsl_tx_timeout() */
7617
7618 /* signal that there are no more frames to send, so that
7619 * line is 'released' by echoing RxD to TxD when current
7620 * transmission is complete (or immediately if no tx in progress).
7621 */
7622 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7623 {
7624 unsigned long flags;
7625
7626 spin_lock_irqsave(&info->irq_spinlock,flags);
7627 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7628 if (info->tx_active)
7629 info->loopmode_send_done_requested = true;
7630 else
7631 usc_loopmode_send_done(info);
7632 }
7633 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7634
7635 return 0;
7636 }
7637
7638 /* release the line by echoing RxD to TxD
7639 * upon completion of a transmit frame
7640 */
7641 static void usc_loopmode_send_done( struct mgsl_struct * info )
7642 {
7643 info->loopmode_send_done_requested = false;
7644 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7645 info->cmr_value &= ~BIT13;
7646 usc_OutReg(info, CMR, info->cmr_value);
7647 }
7648
7649 /* abort a transmit in progress while in HDLC LoopMode
7650 */
7651 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7652 {
7653 /* reset tx dma channel and purge TxFifo */
7654 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7655 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7656 usc_loopmode_send_done( info );
7657 }
7658
7659 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7660 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7661 * we must clear CMR:13 to begin repeating TxData to RxData
7662 */
7663 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7664 {
7665 info->loopmode_insert_requested = true;
7666
7667 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7668 * begin repeating TxData on RxData (complete insertion)
7669 */
7670 usc_OutReg( info, RICR,
7671 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7672
7673 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7674 info->cmr_value |= BIT13;
7675 usc_OutReg(info, CMR, info->cmr_value);
7676 }
7677
7678 /* return 1 if station is inserted into the loop, otherwise 0
7679 */
7680 static int usc_loopmode_active( struct mgsl_struct * info)
7681 {
7682 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7683 }
7684
7685 #if SYNCLINK_GENERIC_HDLC
7686
7687 /**
7688 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7689 * set encoding and frame check sequence (FCS) options
7690 *
7691 * dev pointer to network device structure
7692 * encoding serial encoding setting
7693 * parity FCS setting
7694 *
7695 * returns 0 if success, otherwise error code
7696 */
7697 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7698 unsigned short parity)
7699 {
7700 struct mgsl_struct *info = dev_to_port(dev);
7701 unsigned char new_encoding;
7702 unsigned short new_crctype;
7703
7704 /* return error if TTY interface open */
7705 if (info->count)
7706 return -EBUSY;
7707
7708 switch (encoding)
7709 {
7710 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7711 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7712 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7713 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7714 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7715 default: return -EINVAL;
7716 }
7717
7718 switch (parity)
7719 {
7720 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7721 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7722 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7723 default: return -EINVAL;
7724 }
7725
7726 info->params.encoding = new_encoding;
7727 info->params.crc_type = new_crctype;
7728
7729 /* if network interface up, reprogram hardware */
7730 if (info->netcount)
7731 mgsl_program_hw(info);
7732
7733 return 0;
7734 }
7735
7736 /**
7737 * called by generic HDLC layer to send frame
7738 *
7739 * skb socket buffer containing HDLC frame
7740 * dev pointer to network device structure
7741 *
7742 * returns 0 if success, otherwise error code
7743 */
7744 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7745 {
7746 struct mgsl_struct *info = dev_to_port(dev);
7747 struct net_device_stats *stats = hdlc_stats(dev);
7748 unsigned long flags;
7749
7750 if (debug_level >= DEBUG_LEVEL_INFO)
7751 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7752
7753 /* stop sending until this frame completes */
7754 netif_stop_queue(dev);
7755
7756 /* copy data to device buffers */
7757 info->xmit_cnt = skb->len;
7758 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7759
7760 /* update network statistics */
7761 stats->tx_packets++;
7762 stats->tx_bytes += skb->len;
7763
7764 /* done with socket buffer, so free it */
7765 dev_kfree_skb(skb);
7766
7767 /* save start time for transmit timeout detection */
7768 dev->trans_start = jiffies;
7769
7770 /* start hardware transmitter if necessary */
7771 spin_lock_irqsave(&info->irq_spinlock,flags);
7772 if (!info->tx_active)
7773 usc_start_transmitter(info);
7774 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7775
7776 return 0;
7777 }
7778
7779 /**
7780 * called by network layer when interface enabled
7781 * claim resources and initialize hardware
7782 *
7783 * dev pointer to network device structure
7784 *
7785 * returns 0 if success, otherwise error code
7786 */
7787 static int hdlcdev_open(struct net_device *dev)
7788 {
7789 struct mgsl_struct *info = dev_to_port(dev);
7790 int rc;
7791 unsigned long flags;
7792
7793 if (debug_level >= DEBUG_LEVEL_INFO)
7794 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7795
7796 /* generic HDLC layer open processing */
7797 if ((rc = hdlc_open(dev)))
7798 return rc;
7799
7800 /* arbitrate between network and tty opens */
7801 spin_lock_irqsave(&info->netlock, flags);
7802 if (info->count != 0 || info->netcount != 0) {
7803 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7804 spin_unlock_irqrestore(&info->netlock, flags);
7805 return -EBUSY;
7806 }
7807 info->netcount=1;
7808 spin_unlock_irqrestore(&info->netlock, flags);
7809
7810 /* claim resources and init adapter */
7811 if ((rc = startup(info)) != 0) {
7812 spin_lock_irqsave(&info->netlock, flags);
7813 info->netcount=0;
7814 spin_unlock_irqrestore(&info->netlock, flags);
7815 return rc;
7816 }
7817
7818 /* assert DTR and RTS, apply hardware settings */
7819 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7820 mgsl_program_hw(info);
7821
7822 /* enable network layer transmit */
7823 dev->trans_start = jiffies;
7824 netif_start_queue(dev);
7825
7826 /* inform generic HDLC layer of current DCD status */
7827 spin_lock_irqsave(&info->irq_spinlock, flags);
7828 usc_get_serial_signals(info);
7829 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7830 if (info->serial_signals & SerialSignal_DCD)
7831 netif_carrier_on(dev);
7832 else
7833 netif_carrier_off(dev);
7834 return 0;
7835 }
7836
7837 /**
7838 * called by network layer when interface is disabled
7839 * shutdown hardware and release resources
7840 *
7841 * dev pointer to network device structure
7842 *
7843 * returns 0 if success, otherwise error code
7844 */
7845 static int hdlcdev_close(struct net_device *dev)
7846 {
7847 struct mgsl_struct *info = dev_to_port(dev);
7848 unsigned long flags;
7849
7850 if (debug_level >= DEBUG_LEVEL_INFO)
7851 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7852
7853 netif_stop_queue(dev);
7854
7855 /* shutdown adapter and release resources */
7856 shutdown(info);
7857
7858 hdlc_close(dev);
7859
7860 spin_lock_irqsave(&info->netlock, flags);
7861 info->netcount=0;
7862 spin_unlock_irqrestore(&info->netlock, flags);
7863
7864 return 0;
7865 }
7866
7867 /**
7868 * called by network layer to process IOCTL call to network device
7869 *
7870 * dev pointer to network device structure
7871 * ifr pointer to network interface request structure
7872 * cmd IOCTL command code
7873 *
7874 * returns 0 if success, otherwise error code
7875 */
7876 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7877 {
7878 const size_t size = sizeof(sync_serial_settings);
7879 sync_serial_settings new_line;
7880 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7881 struct mgsl_struct *info = dev_to_port(dev);
7882 unsigned int flags;
7883
7884 if (debug_level >= DEBUG_LEVEL_INFO)
7885 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7886
7887 /* return error if TTY interface open */
7888 if (info->count)
7889 return -EBUSY;
7890
7891 if (cmd != SIOCWANDEV)
7892 return hdlc_ioctl(dev, ifr, cmd);
7893
7894 switch(ifr->ifr_settings.type) {
7895 case IF_GET_IFACE: /* return current sync_serial_settings */
7896
7897 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7898 if (ifr->ifr_settings.size < size) {
7899 ifr->ifr_settings.size = size; /* data size wanted */
7900 return -ENOBUFS;
7901 }
7902
7903 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7904 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7905 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7906 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7907
7908 switch (flags){
7909 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7910 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7911 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7912 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7913 default: new_line.clock_type = CLOCK_DEFAULT;
7914 }
7915
7916 new_line.clock_rate = info->params.clock_speed;
7917 new_line.loopback = info->params.loopback ? 1:0;
7918
7919 if (copy_to_user(line, &new_line, size))
7920 return -EFAULT;
7921 return 0;
7922
7923 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7924
7925 if(!capable(CAP_NET_ADMIN))
7926 return -EPERM;
7927 if (copy_from_user(&new_line, line, size))
7928 return -EFAULT;
7929
7930 switch (new_line.clock_type)
7931 {
7932 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7933 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7934 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7935 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7936 case CLOCK_DEFAULT: flags = info->params.flags &
7937 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7938 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7939 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7940 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7941 default: return -EINVAL;
7942 }
7943
7944 if (new_line.loopback != 0 && new_line.loopback != 1)
7945 return -EINVAL;
7946
7947 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7948 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7949 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7950 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7951 info->params.flags |= flags;
7952
7953 info->params.loopback = new_line.loopback;
7954
7955 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7956 info->params.clock_speed = new_line.clock_rate;
7957 else
7958 info->params.clock_speed = 0;
7959
7960 /* if network interface up, reprogram hardware */
7961 if (info->netcount)
7962 mgsl_program_hw(info);
7963 return 0;
7964
7965 default:
7966 return hdlc_ioctl(dev, ifr, cmd);
7967 }
7968 }
7969
7970 /**
7971 * called by network layer when transmit timeout is detected
7972 *
7973 * dev pointer to network device structure
7974 */
7975 static void hdlcdev_tx_timeout(struct net_device *dev)
7976 {
7977 struct mgsl_struct *info = dev_to_port(dev);
7978 struct net_device_stats *stats = hdlc_stats(dev);
7979 unsigned long flags;
7980
7981 if (debug_level >= DEBUG_LEVEL_INFO)
7982 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7983
7984 stats->tx_errors++;
7985 stats->tx_aborted_errors++;
7986
7987 spin_lock_irqsave(&info->irq_spinlock,flags);
7988 usc_stop_transmitter(info);
7989 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7990
7991 netif_wake_queue(dev);
7992 }
7993
7994 /**
7995 * called by device driver when transmit completes
7996 * reenable network layer transmit if stopped
7997 *
7998 * info pointer to device instance information
7999 */
8000 static void hdlcdev_tx_done(struct mgsl_struct *info)
8001 {
8002 if (netif_queue_stopped(info->netdev))
8003 netif_wake_queue(info->netdev);
8004 }
8005
8006 /**
8007 * called by device driver when frame received
8008 * pass frame to network layer
8009 *
8010 * info pointer to device instance information
8011 * buf pointer to buffer contianing frame data
8012 * size count of data bytes in buf
8013 */
8014 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
8015 {
8016 struct sk_buff *skb = dev_alloc_skb(size);
8017 struct net_device *dev = info->netdev;
8018 struct net_device_stats *stats = hdlc_stats(dev);
8019
8020 if (debug_level >= DEBUG_LEVEL_INFO)
8021 printk("hdlcdev_rx(%s)\n",dev->name);
8022
8023 if (skb == NULL) {
8024 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
8025 stats->rx_dropped++;
8026 return;
8027 }
8028
8029 memcpy(skb_put(skb, size),buf,size);
8030
8031 skb->protocol = hdlc_type_trans(skb, info->netdev);
8032
8033 stats->rx_packets++;
8034 stats->rx_bytes += size;
8035
8036 netif_rx(skb);
8037
8038 info->netdev->last_rx = jiffies;
8039 }
8040
8041 /**
8042 * called by device driver when adding device instance
8043 * do generic HDLC initialization
8044 *
8045 * info pointer to device instance information
8046 *
8047 * returns 0 if success, otherwise error code
8048 */
8049 static int hdlcdev_init(struct mgsl_struct *info)
8050 {
8051 int rc;
8052 struct net_device *dev;
8053 hdlc_device *hdlc;
8054
8055 /* allocate and initialize network and HDLC layer objects */
8056
8057 if (!(dev = alloc_hdlcdev(info))) {
8058 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8059 return -ENOMEM;
8060 }
8061
8062 /* for network layer reporting purposes only */
8063 dev->base_addr = info->io_base;
8064 dev->irq = info->irq_level;
8065 dev->dma = info->dma_level;
8066
8067 /* network layer callbacks and settings */
8068 dev->do_ioctl = hdlcdev_ioctl;
8069 dev->open = hdlcdev_open;
8070 dev->stop = hdlcdev_close;
8071 dev->tx_timeout = hdlcdev_tx_timeout;
8072 dev->watchdog_timeo = 10*HZ;
8073 dev->tx_queue_len = 50;
8074
8075 /* generic HDLC layer callbacks and settings */
8076 hdlc = dev_to_hdlc(dev);
8077 hdlc->attach = hdlcdev_attach;
8078 hdlc->xmit = hdlcdev_xmit;
8079
8080 /* register objects with HDLC layer */
8081 if ((rc = register_hdlc_device(dev))) {
8082 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8083 free_netdev(dev);
8084 return rc;
8085 }
8086
8087 info->netdev = dev;
8088 return 0;
8089 }
8090
8091 /**
8092 * called by device driver when removing device instance
8093 * do generic HDLC cleanup
8094 *
8095 * info pointer to device instance information
8096 */
8097 static void hdlcdev_exit(struct mgsl_struct *info)
8098 {
8099 unregister_hdlc_device(info->netdev);
8100 free_netdev(info->netdev);
8101 info->netdev = NULL;
8102 }
8103
8104 #endif /* CONFIG_HDLC */
8105
8106
8107 static int __devinit synclink_init_one (struct pci_dev *dev,
8108 const struct pci_device_id *ent)
8109 {
8110 struct mgsl_struct *info;
8111
8112 if (pci_enable_device(dev)) {
8113 printk("error enabling pci device %p\n", dev);
8114 return -EIO;
8115 }
8116
8117 if (!(info = mgsl_allocate_device())) {
8118 printk("can't allocate device instance data.\n");
8119 return -EIO;
8120 }
8121
8122 /* Copy user configuration info to device instance data */
8123
8124 info->io_base = pci_resource_start(dev, 2);
8125 info->irq_level = dev->irq;
8126 info->phys_memory_base = pci_resource_start(dev, 3);
8127
8128 /* Because veremap only works on page boundaries we must map
8129 * a larger area than is actually implemented for the LCR
8130 * memory range. We map a full page starting at the page boundary.
8131 */
8132 info->phys_lcr_base = pci_resource_start(dev, 0);
8133 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8134 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8135
8136 info->bus_type = MGSL_BUS_TYPE_PCI;
8137 info->io_addr_size = 8;
8138 info->irq_flags = IRQF_SHARED;
8139
8140 if (dev->device == 0x0210) {
8141 /* Version 1 PCI9030 based universal PCI adapter */
8142 info->misc_ctrl_value = 0x007c4080;
8143 info->hw_version = 1;
8144 } else {
8145 /* Version 0 PCI9050 based 5V PCI adapter
8146 * A PCI9050 bug prevents reading LCR registers if
8147 * LCR base address bit 7 is set. Maintain shadow
8148 * value so we can write to LCR misc control reg.
8149 */
8150 info->misc_ctrl_value = 0x087e4546;
8151 info->hw_version = 0;
8152 }
8153
8154 mgsl_add_device(info);
8155
8156 return 0;
8157 }
8158
8159 static void __devexit synclink_remove_one (struct pci_dev *dev)
8160 {
8161 }
8162
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