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drivers/net/netxen/: cleanups
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / video / tdfxfb.c
blob057bdd593800c9c9f3b22fc5066ed7ba6fd20def
1 /*
2 *
3 * tdfxfb.c
4 *
5 * Author: Hannu Mallat <hmallat@cc.hut.fi>
6 *
7 * Copyright © 1999 Hannu Mallat
8 * All rights reserved
9 *
10 * Created : Thu Sep 23 18:17:43 1999, hmallat
11 * Last modified: Tue Nov 2 21:19:47 1999, hmallat
12 *
13 * Lots of the information here comes from the Daryll Strauss' Banshee
14 * patches to the XF86 server, and the rest comes from the 3dfx
15 * Banshee specification. I'm very much indebted to Daryll for his
16 * work on the X server.
17 *
18 * Voodoo3 support was contributed Harold Oga. Lots of additions
19 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
20 * Kesmarki. Thanks guys!
21 *
22 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
23 * behave very differently from the Voodoo3/4/5. For anyone wanting to
24 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
25 * located at http://www.sourceforge.net/projects/sstfb).
26 *
27 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
28 * I do wish the next version is a bit more complete. Without the XF86
29 * patches I couldn't have gotten even this far... for instance, the
30 * extensions to the VGA register set go completely unmentioned in the
31 * spec! Also, lots of references are made to the 'SST core', but no
32 * spec is publicly available, AFAIK.
33 *
34 * The structure of this driver comes pretty much from the Permedia
35 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
36 *
37 * TODO:
38 * - multihead support (basically need to support an array of fb_infos)
39 * - support other architectures (PPC, Alpha); does the fact that the VGA
40 * core can be accessed only thru I/O (not memory mapped) complicate
41 * things?
42 *
43 * Version history:
44 *
45 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
46 *
47 * 0.1.3 (released 1999-11-02) added Attila's panning support, code
48 * reorg, hwcursor address page size alignment
49 * (for mmaping both frame buffer and regs),
50 * and my changes to get rid of hardcoded
51 * VGA i/o register locations (uses PCI
52 * configuration info now)
53 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
54 * improvements
55 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
56 * 0.1.0 (released 1999-10-06) initial version
57 *
58 */
59
60 #include <linux/module.h>
61 #include <linux/kernel.h>
62 #include <linux/errno.h>
63 #include <linux/string.h>
64 #include <linux/mm.h>
65 #include <linux/slab.h>
66 #include <linux/fb.h>
67 #include <linux/init.h>
68 #include <linux/pci.h>
69 #include <asm/io.h>
70
71 #include <video/tdfx.h>
72
73 #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __FUNCTION__ , ## b)
74
75 #ifdef CONFIG_MTRR
76 #include <asm/mtrr.h>
77 #else
78 /* duplicate asm/mtrr.h defines to work on archs without mtrr */
79 #define MTRR_TYPE_WRCOMB 1
80
81 static inline int mtrr_add(unsigned long base, unsigned long size,
82 unsigned int type, char increment)
83 {
84 return -ENODEV;
85 }
86 static inline int mtrr_del(int reg, unsigned long base,
87 unsigned long size)
88 {
89 return -ENODEV;
90 }
91 #endif
92
93 #define BANSHEE_MAX_PIXCLOCK 270000
94 #define VOODOO3_MAX_PIXCLOCK 300000
95 #define VOODOO5_MAX_PIXCLOCK 350000
96
97 static struct fb_fix_screeninfo tdfx_fix __devinitdata = {
98 .id = "3Dfx",
99 .type = FB_TYPE_PACKED_PIXELS,
100 .visual = FB_VISUAL_PSEUDOCOLOR,
101 .ypanstep = 1,
102 .ywrapstep = 1,
103 .accel = FB_ACCEL_3DFX_BANSHEE
104 };
105
106 static struct fb_var_screeninfo tdfx_var __devinitdata = {
107 /* "640x480, 8 bpp @ 60 Hz */
108 .xres = 640,
109 .yres = 480,
110 .xres_virtual = 640,
111 .yres_virtual = 1024,
112 .bits_per_pixel = 8,
113 .red = {0, 8, 0},
114 .blue = {0, 8, 0},
115 .green = {0, 8, 0},
116 .activate = FB_ACTIVATE_NOW,
117 .height = -1,
118 .width = -1,
119 .accel_flags = FB_ACCELF_TEXT,
120 .pixclock = 39722,
121 .left_margin = 40,
122 .right_margin = 24,
123 .upper_margin = 32,
124 .lower_margin = 11,
125 .hsync_len = 96,
126 .vsync_len = 2,
127 .vmode = FB_VMODE_NONINTERLACED
128 };
129
130 /*
131 * PCI driver prototypes
132 */
133 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
134 const struct pci_device_id *id);
135 static void __devexit tdfxfb_remove(struct pci_dev *pdev);
136
137 static struct pci_device_id tdfxfb_id_table[] = {
138 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
140 0xff0000, 0 },
141 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
143 0xff0000, 0 },
144 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
146 0xff0000, 0 },
147 { 0, }
148 };
149
150 static struct pci_driver tdfxfb_driver = {
151 .name = "tdfxfb",
152 .id_table = tdfxfb_id_table,
153 .probe = tdfxfb_probe,
154 .remove = __devexit_p(tdfxfb_remove),
155 };
156
157 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
158
159 /*
160 * Driver data
161 */
162 static int nopan;
163 static int nowrap = 1; /* not implemented (yet) */
164 static int hwcursor = 1;
165 static char *mode_option __devinitdata;
166 /* mtrr option */
167 static int nomtrr __devinitdata;
168
169 /* -------------------------------------------------------------------------
170 * Hardware-specific funcions
171 * ------------------------------------------------------------------------- */
172
173 static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
174 {
175 return inb(par->iobase + reg - 0x300);
176 }
177
178 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
179 {
180 outb(val, par->iobase + reg - 0x300);
181 }
182
183 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
184 {
185 vga_outb(par, GRA_I, idx);
186 wmb();
187 vga_outb(par, GRA_D, val);
188 wmb();
189 }
190
191 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
192 {
193 vga_outb(par, SEQ_I, idx);
194 wmb();
195 vga_outb(par, SEQ_D, val);
196 wmb();
197 }
198
199 static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
200 {
201 vga_outb(par, SEQ_I, idx);
202 mb();
203 return vga_inb(par, SEQ_D);
204 }
205
206 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
207 {
208 vga_outb(par, CRT_I, idx);
209 wmb();
210 vga_outb(par, CRT_D, val);
211 wmb();
212 }
213
214 static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
215 {
216 vga_outb(par, CRT_I, idx);
217 mb();
218 return vga_inb(par, CRT_D);
219 }
220
221 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
222 {
223 unsigned char tmp;
224
225 tmp = vga_inb(par, IS1_R);
226 vga_outb(par, ATT_IW, idx);
227 vga_outb(par, ATT_IW, val);
228 }
229
230 static inline void vga_disable_video(struct tdfx_par *par)
231 {
232 unsigned char s;
233
234 s = seq_inb(par, 0x01) | 0x20;
235 seq_outb(par, 0x00, 0x01);
236 seq_outb(par, 0x01, s);
237 seq_outb(par, 0x00, 0x03);
238 }
239
240 static inline void vga_enable_video(struct tdfx_par *par)
241 {
242 unsigned char s;
243
244 s = seq_inb(par, 0x01) & 0xdf;
245 seq_outb(par, 0x00, 0x01);
246 seq_outb(par, 0x01, s);
247 seq_outb(par, 0x00, 0x03);
248 }
249
250 static inline void vga_enable_palette(struct tdfx_par *par)
251 {
252 vga_inb(par, IS1_R);
253 mb();
254 vga_outb(par, ATT_IW, 0x20);
255 }
256
257 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
258 {
259 return readl(par->regbase_virt + reg);
260 }
261
262 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
263 {
264 writel(val, par->regbase_virt + reg);
265 }
266
267 static inline void banshee_make_room(struct tdfx_par *par, int size)
268 {
269 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
270 * won't quit if you ask for more. */
271 while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
272 cpu_relax();
273 }
274
275 static int banshee_wait_idle(struct fb_info *info)
276 {
277 struct tdfx_par *par = info->par;
278 int i = 0;
279
280 banshee_make_room(par, 1);
281 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
282
283 do {
284 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
285 i++;
286 } while (i < 3);
287
288 return 0;
289 }
290
291 /*
292 * Set the color of a palette entry in 8bpp mode
293 */
294 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
295 {
296 banshee_make_room(par, 2);
297 tdfx_outl(par, DACADDR, regno);
298 /* read after write makes it working */
299 tdfx_inl(par, DACADDR);
300 tdfx_outl(par, DACDATA, c);
301 }
302
303 static u32 do_calc_pll(int freq, int *freq_out)
304 {
305 int m, n, k, best_m, best_n, best_k, best_error;
306 int fref = 14318;
307
308 best_error = freq;
309 best_n = best_m = best_k = 0;
310
311 for (k = 3; k >= 0; k--) {
312 for (m = 63; m >= 0; m--) {
313 /*
314 * Estimate value of n that produces target frequency
315 * with current m and k
316 */
317 int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
318
319 /* Search neighborhood of estimated n */
320 for (n = max(0, n_estimated);
321 n <= min(255, n_estimated + 1);
322 n++) {
323 /*
324 * Calculate PLL freqency with current m, k and
325 * estimated n
326 */
327 int f = (fref * (n + 2) / (m + 2)) >> k;
328 int error = abs(f - freq);
329
330 /*
331 * If this is the closest we've come to the
332 * target frequency then remember n, m and k
333 */
334 if (error < best_error) {
335 best_error = error;
336 best_n = n;
337 best_m = m;
338 best_k = k;
339 }
340 }
341 }
342 }
343
344 n = best_n;
345 m = best_m;
346 k = best_k;
347 *freq_out = (fref * (n + 2) / (m + 2)) >> k;
348
349 return (n << 8) | (m << 2) | k;
350 }
351
352 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
353 {
354 struct tdfx_par *par = info->par;
355 int i;
356
357 banshee_wait_idle(info);
358
359 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
360
361 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
362
363 banshee_make_room(par, 3);
364 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
365 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
366 #if 0
367 tdfx_outl(par, PLLCTRL1, reg->mempll);
368 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
369 #endif
370 tdfx_outl(par, PLLCTRL0, reg->vidpll);
371
372 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
373
374 for (i = 0; i < 5; i++)
375 seq_outb(par, i, reg->seq[i]);
376
377 for (i = 0; i < 25; i++)
378 crt_outb(par, i, reg->crt[i]);
379
380 for (i = 0; i < 9; i++)
381 gra_outb(par, i, reg->gra[i]);
382
383 for (i = 0; i < 21; i++)
384 att_outb(par, i, reg->att[i]);
385
386 crt_outb(par, 0x1a, reg->ext[0]);
387 crt_outb(par, 0x1b, reg->ext[1]);
388
389 vga_enable_palette(par);
390 vga_enable_video(par);
391
392 banshee_make_room(par, 9);
393 tdfx_outl(par, VGAINIT0, reg->vgainit0);
394 tdfx_outl(par, DACMODE, reg->dacmode);
395 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
396 tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
397
398 tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
399 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
400 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
401 tdfx_outl(par, VGAINIT1, reg->vgainit1);
402 tdfx_outl(par, MISCINIT0, reg->miscinit0);
403
404 banshee_make_room(par, 8);
405 tdfx_outl(par, SRCBASE, reg->startaddr);
406 tdfx_outl(par, DSTBASE, reg->startaddr);
407 tdfx_outl(par, COMMANDEXTRA_2D, 0);
408 tdfx_outl(par, CLIP0MIN, 0);
409 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
410 tdfx_outl(par, CLIP1MIN, 0);
411 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
412 tdfx_outl(par, SRCXY, 0);
413
414 banshee_wait_idle(info);
415 }
416
417 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
418 {
419 u32 draminit0 = tdfx_inl(par, DRAMINIT0);
420 u32 draminit1 = tdfx_inl(par, DRAMINIT1);
421 u32 miscinit1;
422 int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
423 int chip_size; /* in MB */
424 int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
425
426 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
427 /* Banshee/Voodoo3 */
428 chip_size = 2;
429 if (has_sgram && (draminit0 & DRAMINIT0_SGRAM_TYPE))
430 chip_size = 1;
431 } else {
432 /* Voodoo4/5 */
433 has_sgram = 0;
434 chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK;
435 chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT);
436 }
437
438 /* disable block writes for SDRAM */
439 miscinit1 = tdfx_inl(par, MISCINIT1);
440 miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
441 miscinit1 |= MISCINIT1_CLUT_INV;
442
443 banshee_make_room(par, 1);
444 tdfx_outl(par, MISCINIT1, miscinit1);
445 return num_chips * chip_size * 1024l * 1024;
446 }
447
448 /* ------------------------------------------------------------------------- */
449
450 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
451 {
452 struct tdfx_par *par = info->par;
453 u32 lpitch;
454
455 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
456 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
457 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
458 return -EINVAL;
459 }
460
461 if (var->xres != var->xres_virtual)
462 var->xres_virtual = var->xres;
463
464 if (var->yres > var->yres_virtual)
465 var->yres_virtual = var->yres;
466
467 if (var->xoffset) {
468 DPRINTK("xoffset not supported\n");
469 return -EINVAL;
470 }
471 var->yoffset = 0;
472
473 /*
474 * Banshee doesn't support interlace, but Voodoo4/5 and probably
475 * Voodoo3 do.
476 * no direct information about device id now?
477 * use max_pixclock for this...
478 */
479 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
480 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
481 DPRINTK("interlace not supported\n");
482 return -EINVAL;
483 }
484
485 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
486 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
487
488 if (var->xres < 320 || var->xres > 2048) {
489 DPRINTK("width not supported: %u\n", var->xres);
490 return -EINVAL;
491 }
492
493 if (var->yres < 200 || var->yres > 2048) {
494 DPRINTK("height not supported: %u\n", var->yres);
495 return -EINVAL;
496 }
497
498 if (lpitch * var->yres_virtual > info->fix.smem_len) {
499 var->yres_virtual = info->fix.smem_len / lpitch;
500 if (var->yres_virtual < var->yres) {
501 DPRINTK("no memory for screen (%ux%ux%u)\n",
502 var->xres, var->yres_virtual,
503 var->bits_per_pixel);
504 return -EINVAL;
505 }
506 }
507
508 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
509 DPRINTK("pixclock too high (%ldKHz)\n",
510 PICOS2KHZ(var->pixclock));
511 return -EINVAL;
512 }
513
514 var->transp.offset = 0;
515 var->transp.length = 0;
516 switch (var->bits_per_pixel) {
517 case 8:
518 var->red.length = 8;
519 var->red.offset = 0;
520 var->green = var->red;
521 var->blue = var->red;
522 break;
523 case 16:
524 var->red.offset = 11;
525 var->red.length = 5;
526 var->green.offset = 5;
527 var->green.length = 6;
528 var->blue.offset = 0;
529 var->blue.length = 5;
530 break;
531 case 32:
532 var->transp.offset = 24;
533 var->transp.length = 8;
534 case 24:
535 var->red.offset = 16;
536 var->green.offset = 8;
537 var->blue.offset = 0;
538 var->red.length = var->green.length = var->blue.length = 8;
539 break;
540 }
541 var->width = -1;
542 var->height = -1;
543
544 var->accel_flags = FB_ACCELF_TEXT;
545
546 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
547 var->xres, var->yres, var->bits_per_pixel);
548 return 0;
549 }
550
551 static int tdfxfb_set_par(struct fb_info *info)
552 {
553 struct tdfx_par *par = info->par;
554 u32 hdispend = info->var.xres;
555 u32 hsyncsta = hdispend + info->var.right_margin;
556 u32 hsyncend = hsyncsta + info->var.hsync_len;
557 u32 htotal = hsyncend + info->var.left_margin;
558 u32 hd, hs, he, ht, hbs, hbe;
559 u32 vd, vs, ve, vt, vbs, vbe;
560 struct banshee_reg reg;
561 int fout, freq;
562 u32 wd;
563 u32 cpp = (info->var.bits_per_pixel + 7) >> 3;
564
565 memset(&reg, 0, sizeof(reg));
566
567 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
568 VIDCFG_CURS_X11 |
569 ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) |
570 (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
571
572 /* PLL settings */
573 freq = PICOS2KHZ(info->var.pixclock);
574
575 reg.vidcfg &= ~VIDCFG_2X;
576
577 if (freq > par->max_pixclock / 2) {
578 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
579 reg.dacmode |= DACMODE_2X;
580 reg.vidcfg |= VIDCFG_2X;
581 hdispend >>= 1;
582 hsyncsta >>= 1;
583 hsyncend >>= 1;
584 htotal >>= 1;
585 }
586
587 wd = (hdispend >> 3) - 1;
588 hd = wd;
589 hs = (hsyncsta >> 3) - 1;
590 he = (hsyncend >> 3) - 1;
591 ht = (htotal >> 3) - 1;
592 hbs = hd;
593 hbe = ht;
594
595 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
596 vd = (info->var.yres << 1) - 1;
597 vs = vd + (info->var.lower_margin << 1);
598 ve = vs + (info->var.vsync_len << 1);
599 vt = ve + (info->var.upper_margin << 1) - 1;
600 reg.screensize = info->var.xres | (info->var.yres << 13);
601 reg.vidcfg |= VIDCFG_HALF_MODE;
602 reg.crt[0x09] = 0x80;
603 } else {
604 vd = info->var.yres - 1;
605 vs = vd + info->var.lower_margin;
606 ve = vs + info->var.vsync_len;
607 vt = ve + info->var.upper_margin - 1;
608 reg.screensize = info->var.xres | (info->var.yres << 12);
609 reg.vidcfg &= ~VIDCFG_HALF_MODE;
610 }
611 vbs = vd;
612 vbe = vt;
613
614 /* this is all pretty standard VGA register stuffing */
615 reg.misc[0x00] = 0x0f |
616 (info->var.xres < 400 ? 0xa0 :
617 info->var.xres < 480 ? 0x60 :
618 info->var.xres < 768 ? 0xe0 : 0x20);
619
620 reg.gra[0x05] = 0x40;
621 reg.gra[0x06] = 0x05;
622 reg.gra[0x07] = 0x0f;
623 reg.gra[0x08] = 0xff;
624
625 reg.att[0x00] = 0x00;
626 reg.att[0x01] = 0x01;
627 reg.att[0x02] = 0x02;
628 reg.att[0x03] = 0x03;
629 reg.att[0x04] = 0x04;
630 reg.att[0x05] = 0x05;
631 reg.att[0x06] = 0x06;
632 reg.att[0x07] = 0x07;
633 reg.att[0x08] = 0x08;
634 reg.att[0x09] = 0x09;
635 reg.att[0x0a] = 0x0a;
636 reg.att[0x0b] = 0x0b;
637 reg.att[0x0c] = 0x0c;
638 reg.att[0x0d] = 0x0d;
639 reg.att[0x0e] = 0x0e;
640 reg.att[0x0f] = 0x0f;
641 reg.att[0x10] = 0x41;
642 reg.att[0x12] = 0x0f;
643
644 reg.seq[0x00] = 0x03;
645 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
646 reg.seq[0x02] = 0x0f;
647 reg.seq[0x03] = 0x00;
648 reg.seq[0x04] = 0x0e;
649
650 reg.crt[0x00] = ht - 4;
651 reg.crt[0x01] = hd;
652 reg.crt[0x02] = hbs;
653 reg.crt[0x03] = 0x80 | (hbe & 0x1f);
654 reg.crt[0x04] = hs;
655 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
656 reg.crt[0x06] = vt;
657 reg.crt[0x07] = ((vs & 0x200) >> 2) |
658 ((vd & 0x200) >> 3) |
659 ((vt & 0x200) >> 4) | 0x10 |
660 ((vbs & 0x100) >> 5) |
661 ((vs & 0x100) >> 6) |
662 ((vd & 0x100) >> 7) |
663 ((vt & 0x100) >> 8);
664 reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
665 reg.crt[0x10] = vs;
666 reg.crt[0x11] = (ve & 0x0f) | 0x20;
667 reg.crt[0x12] = vd;
668 reg.crt[0x13] = wd;
669 reg.crt[0x15] = vbs;
670 reg.crt[0x16] = vbe + 1;
671 reg.crt[0x17] = 0xc3;
672 reg.crt[0x18] = 0xff;
673
674 /* Banshee's nonvga stuff */
675 reg.ext[0x00] = (((ht & 0x100) >> 8) |
676 ((hd & 0x100) >> 6) |
677 ((hbs & 0x100) >> 4) |
678 ((hbe & 0x40) >> 1) |
679 ((hs & 0x100) >> 2) |
680 ((he & 0x20) << 2));
681 reg.ext[0x01] = (((vt & 0x400) >> 10) |
682 ((vd & 0x400) >> 8) |
683 ((vbs & 0x400) >> 6) |
684 ((vbe & 0x400) >> 4));
685
686 reg.vgainit0 = VGAINIT0_8BIT_DAC |
687 VGAINIT0_EXT_ENABLE |
688 VGAINIT0_WAKEUP_3C3 |
689 VGAINIT0_ALT_READBACK |
690 VGAINIT0_EXTSHIFTOUT;
691 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
692
693 if (hwcursor)
694 reg.curspataddr = info->fix.smem_len;
695
696 reg.cursloc = 0;
697
698 reg.cursc0 = 0;
699 reg.cursc1 = 0xffffff;
700
701 reg.stride = info->var.xres * cpp;
702 reg.startaddr = info->var.yoffset * reg.stride
703 + info->var.xoffset * cpp;
704
705 reg.vidpll = do_calc_pll(freq, &fout);
706 #if 0
707 reg.mempll = do_calc_pll(..., &fout);
708 reg.gfxpll = do_calc_pll(..., &fout);
709 #endif
710
711 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
712 reg.vidcfg |= VIDCFG_INTERLACE;
713 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
714
715 #if defined(__BIG_ENDIAN)
716 switch (info->var.bits_per_pixel) {
717 case 8:
718 case 24:
719 reg.miscinit0 &= ~(1 << 30);
720 reg.miscinit0 &= ~(1 << 31);
721 break;
722 case 16:
723 reg.miscinit0 |= (1 << 30);
724 reg.miscinit0 |= (1 << 31);
725 break;
726 case 32:
727 reg.miscinit0 |= (1 << 30);
728 reg.miscinit0 &= ~(1 << 31);
729 break;
730 }
731 #endif
732 do_write_regs(info, &reg);
733
734 /* Now change fb_fix_screeninfo according to changes in par */
735 info->fix.line_length = reg.stride;
736 info->fix.visual = (info->var.bits_per_pixel == 8)
737 ? FB_VISUAL_PSEUDOCOLOR
738 : FB_VISUAL_TRUECOLOR;
739 DPRINTK("Graphics mode is now set at %dx%d depth %d\n",
740 info->var.xres, info->var.yres, info->var.bits_per_pixel);
741 return 0;
742 }
743
744 /* A handy macro shamelessly pinched from matroxfb */
745 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
746
747 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
748 unsigned blue, unsigned transp,
749 struct fb_info *info)
750 {
751 struct tdfx_par *par = info->par;
752 u32 rgbcol;
753
754 if (regno >= info->cmap.len || regno > 255)
755 return 1;
756
757 /* grayscale works only partially under directcolor */
758 if (info->var.grayscale) {
759 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
760 blue = (red * 77 + green * 151 + blue * 28) >> 8;
761 green = blue;
762 red = blue;
763 }
764
765 switch (info->fix.visual) {
766 case FB_VISUAL_PSEUDOCOLOR:
767 rgbcol = (((u32)red & 0xff00) << 8) |
768 (((u32)green & 0xff00) << 0) |
769 (((u32)blue & 0xff00) >> 8);
770 do_setpalentry(par, regno, rgbcol);
771 break;
772 /* Truecolor has no hardware color palettes. */
773 case FB_VISUAL_TRUECOLOR:
774 if (regno < 16) {
775 rgbcol = (CNVT_TOHW(red, info->var.red.length) <<
776 info->var.red.offset) |
777 (CNVT_TOHW(green, info->var.green.length) <<
778 info->var.green.offset) |
779 (CNVT_TOHW(blue, info->var.blue.length) <<
780 info->var.blue.offset) |
781 (CNVT_TOHW(transp, info->var.transp.length) <<
782 info->var.transp.offset);
783 par->palette[regno] = rgbcol;
784 }
785
786 break;
787 default:
788 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
789 break;
790 }
791
792 return 0;
793 }
794
795 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
796 static int tdfxfb_blank(int blank, struct fb_info *info)
797 {
798 struct tdfx_par *par = info->par;
799 int vgablank = 1;
800 u32 dacmode = tdfx_inl(par, DACMODE);
801
802 dacmode &= ~(BIT(1) | BIT(3));
803
804 switch (blank) {
805 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
806 vgablank = 0;
807 break;
808 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
809 break;
810 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
811 dacmode |= BIT(3);
812 break;
813 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
814 dacmode |= BIT(1);
815 break;
816 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
817 dacmode |= BIT(1) | BIT(3);
818 break;
819 }
820
821 banshee_make_room(par, 1);
822 tdfx_outl(par, DACMODE, dacmode);
823 if (vgablank)
824 vga_disable_video(par);
825 else
826 vga_enable_video(par);
827 return 0;
828 }
829
830 /*
831 * Set the starting position of the visible screen to var->yoffset
832 */
833 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
834 struct fb_info *info)
835 {
836 struct tdfx_par *par = info->par;
837 u32 addr = var->yoffset * info->fix.line_length;
838
839 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
840 return -EINVAL;
841 if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
842 return -EINVAL;
843
844 banshee_make_room(par, 1);
845 tdfx_outl(par, VIDDESKSTART, addr);
846
847 info->var.xoffset = var->xoffset;
848 info->var.yoffset = var->yoffset;
849 return 0;
850 }
851
852 #ifdef CONFIG_FB_3DFX_ACCEL
853 /*
854 * FillRect 2D command (solidfill or invert (via ROP_XOR))
855 */
856 static void tdfxfb_fillrect(struct fb_info *info,
857 const struct fb_fillrect *rect)
858 {
859 struct tdfx_par *par = info->par;
860 u32 bpp = info->var.bits_per_pixel;
861 u32 stride = info->fix.line_length;
862 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
863 int tdfx_rop;
864 u32 dx = rect->dx;
865 u32 dy = rect->dy;
866 u32 dstbase = 0;
867
868 if (rect->rop == ROP_COPY)
869 tdfx_rop = TDFX_ROP_COPY;
870 else
871 tdfx_rop = TDFX_ROP_XOR;
872
873 /* asume always rect->height < 4096 */
874 if (dy + rect->height > 4095) {
875 dstbase = stride * dy;
876 dy = 0;
877 }
878 /* asume always rect->width < 4096 */
879 if (dx + rect->width > 4095) {
880 dstbase += dx * bpp >> 3;
881 dx = 0;
882 }
883 banshee_make_room(par, 6);
884 tdfx_outl(par, DSTFORMAT, fmt);
885 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
886 tdfx_outl(par, COLORFORE, rect->color);
887 } else { /* FB_VISUAL_TRUECOLOR */
888 tdfx_outl(par, COLORFORE, par->palette[rect->color]);
889 }
890 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
891 tdfx_outl(par, DSTBASE, dstbase);
892 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
893 tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
894 }
895
896 /*
897 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
898 */
899 static void tdfxfb_copyarea(struct fb_info *info,
900 const struct fb_copyarea *area)
901 {
902 struct tdfx_par *par = info->par;
903 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
904 u32 bpp = info->var.bits_per_pixel;
905 u32 stride = info->fix.line_length;
906 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
907 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
908 u32 dstbase = 0;
909 u32 srcbase = 0;
910
911 /* asume always area->height < 4096 */
912 if (sy + area->height > 4095) {
913 srcbase = stride * sy;
914 sy = 0;
915 }
916 /* asume always area->width < 4096 */
917 if (sx + area->width > 4095) {
918 srcbase += sx * bpp >> 3;
919 sx = 0;
920 }
921 /* asume always area->height < 4096 */
922 if (dy + area->height > 4095) {
923 dstbase = stride * dy;
924 dy = 0;
925 }
926 /* asume always area->width < 4096 */
927 if (dx + area->width > 4095) {
928 dstbase += dx * bpp >> 3;
929 dx = 0;
930 }
931
932 if (area->sx <= area->dx) {
933 /* -X */
934 blitcmd |= BIT(14);
935 sx += area->width - 1;
936 dx += area->width - 1;
937 }
938 if (area->sy <= area->dy) {
939 /* -Y */
940 blitcmd |= BIT(15);
941 sy += area->height - 1;
942 dy += area->height - 1;
943 }
944
945 banshee_make_room(par, 8);
946
947 tdfx_outl(par, SRCFORMAT, fmt);
948 tdfx_outl(par, DSTFORMAT, fmt);
949 tdfx_outl(par, COMMAND_2D, blitcmd);
950 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
951 tdfx_outl(par, DSTXY, dx | (dy << 16));
952 tdfx_outl(par, SRCBASE, srcbase);
953 tdfx_outl(par, DSTBASE, dstbase);
954 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
955 }
956
957 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
958 {
959 struct tdfx_par *par = info->par;
960 int size = image->height * ((image->width * image->depth + 7) >> 3);
961 int fifo_free;
962 int i, stride = info->fix.line_length;
963 u32 bpp = info->var.bits_per_pixel;
964 u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
965 u8 *chardata = (u8 *) image->data;
966 u32 srcfmt;
967 u32 dx = image->dx;
968 u32 dy = image->dy;
969 u32 dstbase = 0;
970
971 if (image->depth != 1) {
972 #ifdef BROKEN_CODE
973 banshee_make_room(par, 6 + ((size + 3) >> 2));
974 srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) |
975 0x400000;
976 #else
977 cfb_imageblit(info, image);
978 #endif
979 return;
980 }
981 banshee_make_room(par, 9);
982 switch (info->fix.visual) {
983 case FB_VISUAL_PSEUDOCOLOR:
984 tdfx_outl(par, COLORFORE, image->fg_color);
985 tdfx_outl(par, COLORBACK, image->bg_color);
986 break;
987 case FB_VISUAL_TRUECOLOR:
988 default:
989 tdfx_outl(par, COLORFORE,
990 par->palette[image->fg_color]);
991 tdfx_outl(par, COLORBACK,
992 par->palette[image->bg_color]);
993 }
994 #ifdef __BIG_ENDIAN
995 srcfmt = 0x400000 | BIT(20);
996 #else
997 srcfmt = 0x400000;
998 #endif
999 /* asume always image->height < 4096 */
1000 if (dy + image->height > 4095) {
1001 dstbase = stride * dy;
1002 dy = 0;
1003 }
1004 /* asume always image->width < 4096 */
1005 if (dx + image->width > 4095) {
1006 dstbase += dx * bpp >> 3;
1007 dx = 0;
1008 }
1009
1010 tdfx_outl(par, DSTBASE, dstbase);
1011 tdfx_outl(par, SRCXY, 0);
1012 tdfx_outl(par, DSTXY, dx | (dy << 16));
1013 tdfx_outl(par, COMMAND_2D,
1014 COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
1015 tdfx_outl(par, SRCFORMAT, srcfmt);
1016 tdfx_outl(par, DSTFORMAT, dstfmt);
1017 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
1018
1019 /* A count of how many free FIFO entries we've requested.
1020 * When this goes negative, we need to request more. */
1021 fifo_free = 0;
1022
1023 /* Send four bytes at a time of data */
1024 for (i = (size >> 2); i > 0; i--) {
1025 if (--fifo_free < 0) {
1026 fifo_free = 31;
1027 banshee_make_room(par, fifo_free);
1028 }
1029 tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
1030 chardata += 4;
1031 }
1032
1033 /* Send the leftovers now */
1034 banshee_make_room(par, 3);
1035 switch (size % 4) {
1036 case 0:
1037 break;
1038 case 1:
1039 tdfx_outl(par, LAUNCH_2D, *chardata);
1040 break;
1041 case 2:
1042 tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
1043 break;
1044 case 3:
1045 tdfx_outl(par, LAUNCH_2D,
1046 *(u16 *)chardata | (chardata[3] << 24));
1047 break;
1048 }
1049 }
1050 #endif /* CONFIG_FB_3DFX_ACCEL */
1051
1052 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1053 {
1054 struct tdfx_par *par = info->par;
1055 u32 vidcfg;
1056
1057 if (!hwcursor)
1058 return -EINVAL; /* just to force soft_cursor() call */
1059
1060 /* Too large of a cursor or wrong bpp :-( */
1061 if (cursor->image.width > 64 ||
1062 cursor->image.height > 64 ||
1063 cursor->image.depth > 1)
1064 return -EINVAL;
1065
1066 vidcfg = tdfx_inl(par, VIDPROCCFG);
1067 if (cursor->enable)
1068 tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
1069 else
1070 tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
1071
1072 /*
1073 * If the cursor is not be changed this means either we want the
1074 * current cursor state (if enable is set) or we want to query what
1075 * we can do with the cursor (if enable is not set)
1076 */
1077 if (!cursor->set)
1078 return 0;
1079
1080 /* fix cursor color - XFree86 forgets to restore it properly */
1081 if (cursor->set & FB_CUR_SETCMAP) {
1082 struct fb_cmap cmap = info->cmap;
1083 u32 bg_idx = cursor->image.bg_color;
1084 u32 fg_idx = cursor->image.fg_color;
1085 unsigned long bg_color, fg_color;
1086
1087 fg_color = (((u32)cmap.red[fg_idx] & 0xff00) << 8) |
1088 (((u32)cmap.green[fg_idx] & 0xff00) << 0) |
1089 (((u32)cmap.blue[fg_idx] & 0xff00) >> 8);
1090 bg_color = (((u32)cmap.red[bg_idx] & 0xff00) << 8) |
1091 (((u32)cmap.green[bg_idx] & 0xff00) << 0) |
1092 (((u32)cmap.blue[bg_idx] & 0xff00) >> 8);
1093 banshee_make_room(par, 2);
1094 tdfx_outl(par, HWCURC0, bg_color);
1095 tdfx_outl(par, HWCURC1, fg_color);
1096 }
1097
1098 if (cursor->set & FB_CUR_SETPOS) {
1099 int x = cursor->image.dx;
1100 int y = cursor->image.dy - info->var.yoffset;
1101
1102 x += 63;
1103 y += 63;
1104 banshee_make_room(par, 1);
1105 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1106 }
1107 if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
1108 /*
1109 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1110 * The reason is so the card can fetch 8 words at a time
1111 * and are stored on chip for use for the next 8 scanlines.
1112 * This reduces the number of times for access to draw the
1113 * cursor for each screen refresh.
1114 * Each pattern is a bitmap of 64 bit wide and 64 bit high
1115 * (total of 8192 bits or 1024 bytes). The two patterns are
1116 * stored in such a way that pattern 0 always resides in the
1117 * lower half (least significant 64 bits) of a 128 bit word
1118 * and pattern 1 the upper half. If you examine the data of
1119 * the cursor image the graphics card uses then from the
1120 * begining you see line one of pattern 0, line one of
1121 * pattern 1, line two of pattern 0, line two of pattern 1,
1122 * etc etc. The linear stride for the cursor is always 16 bytes
1123 * (128 bits) which is the maximum cursor width times two for
1124 * the two monochrome patterns.
1125 */
1126 u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len;
1127 u8 *bitmap = (u8 *)cursor->image.data;
1128 u8 *mask = (u8 *)cursor->mask;
1129 int i;
1130
1131 fb_memset(cursorbase, 0, 1024);
1132
1133 for (i = 0; i < cursor->image.height; i++) {
1134 int h = 0;
1135 int j = (cursor->image.width + 7) >> 3;
1136
1137 for (; j > 0; j--) {
1138 u8 data = *mask ^ *bitmap;
1139 if (cursor->rop == ROP_COPY)
1140 data = *mask & *bitmap;
1141 /* Pattern 0. Copy the cursor mask to it */
1142 fb_writeb(*mask, cursorbase + h);
1143 mask++;
1144 /* Pattern 1. Copy the cursor bitmap to it */
1145 fb_writeb(data, cursorbase + h + 8);
1146 bitmap++;
1147 h++;
1148 }
1149 cursorbase += 16;
1150 }
1151 }
1152 return 0;
1153 }
1154
1155 static struct fb_ops tdfxfb_ops = {
1156 .owner = THIS_MODULE,
1157 .fb_check_var = tdfxfb_check_var,
1158 .fb_set_par = tdfxfb_set_par,
1159 .fb_setcolreg = tdfxfb_setcolreg,
1160 .fb_blank = tdfxfb_blank,
1161 .fb_pan_display = tdfxfb_pan_display,
1162 .fb_sync = banshee_wait_idle,
1163 .fb_cursor = tdfxfb_cursor,
1164 #ifdef CONFIG_FB_3DFX_ACCEL
1165 .fb_fillrect = tdfxfb_fillrect,
1166 .fb_copyarea = tdfxfb_copyarea,
1167 .fb_imageblit = tdfxfb_imageblit,
1168 #else
1169 .fb_fillrect = cfb_fillrect,
1170 .fb_copyarea = cfb_copyarea,
1171 .fb_imageblit = cfb_imageblit,
1172 #endif
1173 };
1174
1175 /**
1176 * tdfxfb_probe - Device Initializiation
1177 *
1178 * @pdev: PCI Device to initialize
1179 * @id: PCI Device ID
1180 *
1181 * Initializes and allocates resources for PCI device @pdev.
1182 *
1183 */
1184 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1185 const struct pci_device_id *id)
1186 {
1187 struct tdfx_par *default_par;
1188 struct fb_info *info;
1189 int err, lpitch;
1190
1191 err = pci_enable_device(pdev);
1192 if (err) {
1193 printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err);
1194 return err;
1195 }
1196
1197 info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
1198
1199 if (!info)
1200 return -ENOMEM;
1201
1202 default_par = info->par;
1203
1204 /* Configure the default fb_fix_screeninfo first */
1205 switch (pdev->device) {
1206 case PCI_DEVICE_ID_3DFX_BANSHEE:
1207 strcat(tdfx_fix.id, " Banshee");
1208 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1209 break;
1210 case PCI_DEVICE_ID_3DFX_VOODOO3:
1211 strcat(tdfx_fix.id, " Voodoo3");
1212 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1213 break;
1214 case PCI_DEVICE_ID_3DFX_VOODOO5:
1215 strcat(tdfx_fix.id, " Voodoo5");
1216 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1217 break;
1218 }
1219
1220 tdfx_fix.mmio_start = pci_resource_start(pdev, 0);
1221 tdfx_fix.mmio_len = pci_resource_len(pdev, 0);
1222 if (!request_mem_region(tdfx_fix.mmio_start, tdfx_fix.mmio_len,
1223 "tdfx regbase")) {
1224 printk(KERN_ERR "tdfxfb: Can't reserve regbase\n");
1225 goto out_err;
1226 }
1227
1228 default_par->regbase_virt =
1229 ioremap_nocache(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
1230 if (!default_par->regbase_virt) {
1231 printk(KERN_ERR "fb: Can't remap %s register area.\n",
1232 tdfx_fix.id);
1233 goto out_err_regbase;
1234 }
1235
1236 tdfx_fix.smem_start = pci_resource_start(pdev, 1);
1237 tdfx_fix.smem_len = do_lfb_size(default_par, pdev->device);
1238 if (!tdfx_fix.smem_len) {
1239 printk(KERN_ERR "fb: Can't count %s memory.\n", tdfx_fix.id);
1240 goto out_err_regbase;
1241 }
1242
1243 if (!request_mem_region(tdfx_fix.smem_start,
1244 pci_resource_len(pdev, 1), "tdfx smem")) {
1245 printk(KERN_ERR "tdfxfb: Can't reserve smem\n");
1246 goto out_err_regbase;
1247 }
1248
1249 info->screen_base = ioremap_nocache(tdfx_fix.smem_start,
1250 tdfx_fix.smem_len);
1251 if (!info->screen_base) {
1252 printk(KERN_ERR "fb: Can't remap %s framebuffer.\n",
1253 tdfx_fix.id);
1254 goto out_err_screenbase;
1255 }
1256
1257 default_par->iobase = pci_resource_start(pdev, 2);
1258
1259 if (!request_region(pci_resource_start(pdev, 2),
1260 pci_resource_len(pdev, 2), "tdfx iobase")) {
1261 printk(KERN_ERR "tdfxfb: Can't reserve iobase\n");
1262 goto out_err_screenbase;
1263 }
1264
1265 printk(KERN_INFO "fb: %s memory = %dK\n", tdfx_fix.id,
1266 tdfx_fix.smem_len >> 10);
1267
1268 default_par->mtrr_handle = -1;
1269 if (!nomtrr)
1270 default_par->mtrr_handle =
1271 mtrr_add(tdfx_fix.smem_start, tdfx_fix.smem_len,
1272 MTRR_TYPE_WRCOMB, 1);
1273
1274 tdfx_fix.ypanstep = nopan ? 0 : 1;
1275 tdfx_fix.ywrapstep = nowrap ? 0 : 1;
1276
1277 info->fbops = &tdfxfb_ops;
1278 info->fix = tdfx_fix;
1279 info->pseudo_palette = default_par->palette;
1280 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1281 #ifdef CONFIG_FB_3DFX_ACCEL
1282 info->flags |= FBINFO_HWACCEL_FILLRECT |
1283 FBINFO_HWACCEL_COPYAREA |
1284 FBINFO_HWACCEL_IMAGEBLIT |
1285 FBINFO_READS_FAST;
1286 #endif
1287 /* reserve 8192 bits for cursor */
1288 /* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */
1289 if (hwcursor)
1290 info->fix.smem_len = (info->fix.smem_len - 1024) &
1291 (PAGE_MASK << 1);
1292
1293 if (!mode_option)
1294 mode_option = "640x480@60";
1295
1296 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1297 if (!err || err == 4)
1298 info->var = tdfx_var;
1299
1300 /* maximize virtual vertical length */
1301 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1302 info->var.yres_virtual = info->fix.smem_len / lpitch;
1303 if (info->var.yres_virtual < info->var.yres)
1304 goto out_err_iobase;
1305
1306 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1307 printk(KERN_ERR "tdfxfb: Can't allocate color map\n");
1308 goto out_err_iobase;
1309 }
1310
1311 if (register_framebuffer(info) < 0) {
1312 printk(KERN_ERR "tdfxfb: can't register framebuffer\n");
1313 fb_dealloc_cmap(&info->cmap);
1314 goto out_err_iobase;
1315 }
1316 /*
1317 * Our driver data
1318 */
1319 pci_set_drvdata(pdev, info);
1320 return 0;
1321
1322 out_err_iobase:
1323 if (default_par->mtrr_handle >= 0)
1324 mtrr_del(default_par->mtrr_handle, info->fix.smem_start,
1325 info->fix.smem_len);
1326 release_mem_region(pci_resource_start(pdev, 2),
1327 pci_resource_len(pdev, 2));
1328 out_err_screenbase:
1329 if (info->screen_base)
1330 iounmap(info->screen_base);
1331 release_mem_region(tdfx_fix.smem_start, pci_resource_len(pdev, 1));
1332 out_err_regbase:
1333 /*
1334 * Cleanup after anything that was remapped/allocated.
1335 */
1336 if (default_par->regbase_virt)
1337 iounmap(default_par->regbase_virt);
1338 release_mem_region(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
1339 out_err:
1340 framebuffer_release(info);
1341 return -ENXIO;
1342 }
1343
1344 #ifndef MODULE
1345 static void tdfxfb_setup(char *options)
1346 {
1347 char *this_opt;
1348
1349 if (!options || !*options)
1350 return;
1351
1352 while ((this_opt = strsep(&options, ",")) != NULL) {
1353 if (!*this_opt)
1354 continue;
1355 if (!strcmp(this_opt, "nopan")) {
1356 nopan = 1;
1357 } else if (!strcmp(this_opt, "nowrap")) {
1358 nowrap = 1;
1359 } else if (!strncmp(this_opt, "hwcursor=", 9)) {
1360 hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1361 #ifdef CONFIG_MTRR
1362 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1363 nomtrr = 1;
1364 #endif
1365 } else {
1366 mode_option = this_opt;
1367 }
1368 }
1369 }
1370 #endif
1371
1372 /**
1373 * tdfxfb_remove - Device removal
1374 *
1375 * @pdev: PCI Device to cleanup
1376 *
1377 * Releases all resources allocated during the course of the driver's
1378 * lifetime for the PCI device @pdev.
1379 *
1380 */
1381 static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1382 {
1383 struct fb_info *info = pci_get_drvdata(pdev);
1384 struct tdfx_par *par = info->par;
1385
1386 unregister_framebuffer(info);
1387 if (par->mtrr_handle >= 0)
1388 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1389 info->fix.smem_len);
1390 iounmap(par->regbase_virt);
1391 iounmap(info->screen_base);
1392
1393 /* Clean up after reserved regions */
1394 release_region(pci_resource_start(pdev, 2),
1395 pci_resource_len(pdev, 2));
1396 release_mem_region(pci_resource_start(pdev, 1),
1397 pci_resource_len(pdev, 1));
1398 release_mem_region(pci_resource_start(pdev, 0),
1399 pci_resource_len(pdev, 0));
1400 pci_set_drvdata(pdev, NULL);
1401 framebuffer_release(info);
1402 }
1403
1404 static int __init tdfxfb_init(void)
1405 {
1406 #ifndef MODULE
1407 char *option = NULL;
1408
1409 if (fb_get_options("tdfxfb", &option))
1410 return -ENODEV;
1411
1412 tdfxfb_setup(option);
1413 #endif
1414 return pci_register_driver(&tdfxfb_driver);
1415 }
1416
1417 static void __exit tdfxfb_exit(void)
1418 {
1419 pci_unregister_driver(&tdfxfb_driver);
1420 }
1421
1422 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1423 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1424 MODULE_LICENSE("GPL");
1425
1426 module_param(hwcursor, int, 0644);
1427 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1428 "(1=enable, 0=disable, default=1)");
1429 #ifdef CONFIG_MTRR
1430 module_param(nomtrr, bool, 0);
1431 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)");
1432 #endif
1433
1434 module_init(tdfxfb_init);
1435 module_exit(tdfxfb_exit);
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