2 * drivers/video/aty/radeon_base.c
4 * framebuffer driver for ATI Radeon chipset video boards
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
11 * Special thanks to ATI DevRel team for their hardware donations.
13 * ...Insert GPL boilerplate here...
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
21 * All Rights Reserved.
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
44 * XFree86 driver authors:
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
53 #define RADEON_VERSION "0.2.0"
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/errno.h>
59 #include <linux/string.h>
61 #include <linux/slab.h>
62 #include <linux/delay.h>
63 #include <linux/time.h>
65 #include <linux/ioport.h>
66 #include <linux/init.h>
67 #include <linux/pci.h>
68 #include <linux/vmalloc.h>
69 #include <linux/device.h>
72 #include <linux/uaccess.h>
76 #include <asm/pci-bridge.h>
77 #include "../macmodes.h"
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
83 #endif /* CONFIG_PPC_OF */
89 #include <video/radeon.h>
90 #include <linux/radeonfb.h>
92 #include "../edid.h" // MOVE THAT TO include/video
96 #define MAX_MAPPED_VRAM (2048*2048*4)
97 #define MIN_MAPPED_VRAM (1024*768*1)
99 #define CHIP_DEF(id, family, flags) \
100 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
102 static struct pci_device_id radeonfb_pci_table
[] = {
103 /* Radeon Xpress 200m */
104 CHIP_DEF(PCI_CHIP_RS480_5955
, RS480
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
| CHIP_IS_MOBILITY
),
105 CHIP_DEF(PCI_CHIP_RS482_5975
, RS480
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
| CHIP_IS_MOBILITY
),
107 CHIP_DEF(PCI_CHIP_RADEON_LY
, RV100
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
108 CHIP_DEF(PCI_CHIP_RADEON_LZ
, RV100
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
110 CHIP_DEF(PCI_CHIP_RV100_QY
, RV100
, CHIP_HAS_CRTC2
),
111 CHIP_DEF(PCI_CHIP_RV100_QZ
, RV100
, CHIP_HAS_CRTC2
),
112 CHIP_DEF(PCI_CHIP_RN50
, RV100
, CHIP_HAS_CRTC2
),
113 /* Radeon IGP320M (U1) */
114 CHIP_DEF(PCI_CHIP_RS100_4336
, RS100
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
| CHIP_IS_MOBILITY
),
115 /* Radeon IGP320 (A3) */
116 CHIP_DEF(PCI_CHIP_RS100_4136
, RS100
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
),
117 /* IGP330M/340M/350M (U2) */
118 CHIP_DEF(PCI_CHIP_RS200_4337
, RS200
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
| CHIP_IS_MOBILITY
),
119 /* IGP330/340/350 (A4) */
120 CHIP_DEF(PCI_CHIP_RS200_4137
, RS200
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
),
121 /* Mobility 7000 IGP */
122 CHIP_DEF(PCI_CHIP_RS250_4437
, RS200
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
| CHIP_IS_MOBILITY
),
124 CHIP_DEF(PCI_CHIP_RS250_4237
, RS200
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
),
126 CHIP_DEF(PCI_CHIP_R200_BB
, R200
, CHIP_HAS_CRTC2
),
127 CHIP_DEF(PCI_CHIP_R200_BC
, R200
, CHIP_HAS_CRTC2
),
129 CHIP_DEF(PCI_CHIP_R200_QH
, R200
, CHIP_HAS_CRTC2
),
131 CHIP_DEF(PCI_CHIP_R200_QL
, R200
, CHIP_HAS_CRTC2
),
133 CHIP_DEF(PCI_CHIP_R200_QM
, R200
, CHIP_HAS_CRTC2
),
135 CHIP_DEF(PCI_CHIP_RADEON_LW
, RV200
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
136 CHIP_DEF(PCI_CHIP_RADEON_LX
, RV200
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
138 CHIP_DEF(PCI_CHIP_RV200_QW
, RV200
, CHIP_HAS_CRTC2
),
139 CHIP_DEF(PCI_CHIP_RV200_QX
, RV200
, CHIP_HAS_CRTC2
),
141 CHIP_DEF(PCI_CHIP_RV250_Ld
, RV250
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
142 CHIP_DEF(PCI_CHIP_RV250_Le
, RV250
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
143 CHIP_DEF(PCI_CHIP_RV250_Lf
, RV250
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
144 CHIP_DEF(PCI_CHIP_RV250_Lg
, RV250
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
146 CHIP_DEF(PCI_CHIP_RV250_If
, RV250
, CHIP_HAS_CRTC2
),
147 CHIP_DEF(PCI_CHIP_RV250_Ig
, RV250
, CHIP_HAS_CRTC2
),
149 CHIP_DEF(PCI_CHIP_RC410_5A62
, RC410
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
| CHIP_IS_MOBILITY
),
150 /* Mobility 9100 IGP (U3) */
151 CHIP_DEF(PCI_CHIP_RS300_5835
, RS300
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
| CHIP_IS_MOBILITY
),
152 CHIP_DEF(PCI_CHIP_RS350_7835
, RS300
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
| CHIP_IS_MOBILITY
),
154 CHIP_DEF(PCI_CHIP_RS300_5834
, RS300
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
),
155 CHIP_DEF(PCI_CHIP_RS350_7834
, RS300
, CHIP_HAS_CRTC2
| CHIP_IS_IGP
),
156 /* Mobility 9200 (M9+) */
157 CHIP_DEF(PCI_CHIP_RV280_5C61
, RV280
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
158 CHIP_DEF(PCI_CHIP_RV280_5C63
, RV280
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
160 CHIP_DEF(PCI_CHIP_RV280_5960
, RV280
, CHIP_HAS_CRTC2
),
161 CHIP_DEF(PCI_CHIP_RV280_5961
, RV280
, CHIP_HAS_CRTC2
),
162 CHIP_DEF(PCI_CHIP_RV280_5962
, RV280
, CHIP_HAS_CRTC2
),
163 CHIP_DEF(PCI_CHIP_RV280_5964
, RV280
, CHIP_HAS_CRTC2
),
165 CHIP_DEF(PCI_CHIP_R300_AD
, R300
, CHIP_HAS_CRTC2
),
166 CHIP_DEF(PCI_CHIP_R300_AE
, R300
, CHIP_HAS_CRTC2
),
167 /* 9600TX / FireGL Z1 */
168 CHIP_DEF(PCI_CHIP_R300_AF
, R300
, CHIP_HAS_CRTC2
),
169 CHIP_DEF(PCI_CHIP_R300_AG
, R300
, CHIP_HAS_CRTC2
),
170 /* 9700/9500/Pro/FireGL X1 */
171 CHIP_DEF(PCI_CHIP_R300_ND
, R300
, CHIP_HAS_CRTC2
),
172 CHIP_DEF(PCI_CHIP_R300_NE
, R300
, CHIP_HAS_CRTC2
),
173 CHIP_DEF(PCI_CHIP_R300_NF
, R300
, CHIP_HAS_CRTC2
),
174 CHIP_DEF(PCI_CHIP_R300_NG
, R300
, CHIP_HAS_CRTC2
),
175 /* Mobility M10/M11 */
176 CHIP_DEF(PCI_CHIP_RV350_NP
, RV350
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
177 CHIP_DEF(PCI_CHIP_RV350_NQ
, RV350
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
178 CHIP_DEF(PCI_CHIP_RV350_NR
, RV350
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
179 CHIP_DEF(PCI_CHIP_RV350_NS
, RV350
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
180 CHIP_DEF(PCI_CHIP_RV350_NT
, RV350
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
181 CHIP_DEF(PCI_CHIP_RV350_NV
, RV350
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
183 CHIP_DEF(PCI_CHIP_RV350_AP
, RV350
, CHIP_HAS_CRTC2
),
184 CHIP_DEF(PCI_CHIP_RV350_AQ
, RV350
, CHIP_HAS_CRTC2
),
185 CHIP_DEF(PCI_CHIP_RV360_AR
, RV350
, CHIP_HAS_CRTC2
),
186 CHIP_DEF(PCI_CHIP_RV350_AS
, RV350
, CHIP_HAS_CRTC2
),
187 CHIP_DEF(PCI_CHIP_RV350_AT
, RV350
, CHIP_HAS_CRTC2
),
188 CHIP_DEF(PCI_CHIP_RV350_AV
, RV350
, CHIP_HAS_CRTC2
),
189 /* 9800/Pro/FileGL X2 */
190 CHIP_DEF(PCI_CHIP_R350_AH
, R350
, CHIP_HAS_CRTC2
),
191 CHIP_DEF(PCI_CHIP_R350_AI
, R350
, CHIP_HAS_CRTC2
),
192 CHIP_DEF(PCI_CHIP_R350_AJ
, R350
, CHIP_HAS_CRTC2
),
193 CHIP_DEF(PCI_CHIP_R350_AK
, R350
, CHIP_HAS_CRTC2
),
194 CHIP_DEF(PCI_CHIP_R350_NH
, R350
, CHIP_HAS_CRTC2
),
195 CHIP_DEF(PCI_CHIP_R350_NI
, R350
, CHIP_HAS_CRTC2
),
196 CHIP_DEF(PCI_CHIP_R360_NJ
, R350
, CHIP_HAS_CRTC2
),
197 CHIP_DEF(PCI_CHIP_R350_NK
, R350
, CHIP_HAS_CRTC2
),
199 CHIP_DEF(PCI_CHIP_RV380_3E50
, RV380
, CHIP_HAS_CRTC2
),
200 CHIP_DEF(PCI_CHIP_RV380_3E54
, RV380
, CHIP_HAS_CRTC2
),
201 CHIP_DEF(PCI_CHIP_RV380_3150
, RV380
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
202 CHIP_DEF(PCI_CHIP_RV380_3154
, RV380
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
203 CHIP_DEF(PCI_CHIP_RV370_5B60
, RV380
, CHIP_HAS_CRTC2
),
204 CHIP_DEF(PCI_CHIP_RV370_5B62
, RV380
, CHIP_HAS_CRTC2
),
205 CHIP_DEF(PCI_CHIP_RV370_5B63
, RV380
, CHIP_HAS_CRTC2
),
206 CHIP_DEF(PCI_CHIP_RV370_5B64
, RV380
, CHIP_HAS_CRTC2
),
207 CHIP_DEF(PCI_CHIP_RV370_5B65
, RV380
, CHIP_HAS_CRTC2
),
208 CHIP_DEF(PCI_CHIP_RV370_5460
, RV380
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
209 CHIP_DEF(PCI_CHIP_RV370_5464
, RV380
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
210 CHIP_DEF(PCI_CHIP_R420_JH
, R420
, CHIP_HAS_CRTC2
),
211 CHIP_DEF(PCI_CHIP_R420_JI
, R420
, CHIP_HAS_CRTC2
),
212 CHIP_DEF(PCI_CHIP_R420_JJ
, R420
, CHIP_HAS_CRTC2
),
213 CHIP_DEF(PCI_CHIP_R420_JK
, R420
, CHIP_HAS_CRTC2
),
214 CHIP_DEF(PCI_CHIP_R420_JL
, R420
, CHIP_HAS_CRTC2
),
215 CHIP_DEF(PCI_CHIP_R420_JM
, R420
, CHIP_HAS_CRTC2
),
216 CHIP_DEF(PCI_CHIP_R420_JN
, R420
, CHIP_HAS_CRTC2
| CHIP_IS_MOBILITY
),
217 CHIP_DEF(PCI_CHIP_R420_JP
, R420
, CHIP_HAS_CRTC2
),
218 CHIP_DEF(PCI_CHIP_R423_UH
, R420
, CHIP_HAS_CRTC2
),
219 CHIP_DEF(PCI_CHIP_R423_UI
, R420
, CHIP_HAS_CRTC2
),
220 CHIP_DEF(PCI_CHIP_R423_UJ
, R420
, CHIP_HAS_CRTC2
),
221 CHIP_DEF(PCI_CHIP_R423_UK
, R420
, CHIP_HAS_CRTC2
),
222 CHIP_DEF(PCI_CHIP_R423_UQ
, R420
, CHIP_HAS_CRTC2
),
223 CHIP_DEF(PCI_CHIP_R423_UR
, R420
, CHIP_HAS_CRTC2
),
224 CHIP_DEF(PCI_CHIP_R423_UT
, R420
, CHIP_HAS_CRTC2
),
225 CHIP_DEF(PCI_CHIP_R423_5D57
, R420
, CHIP_HAS_CRTC2
),
226 /* Original Radeon/7200 */
227 CHIP_DEF(PCI_CHIP_RADEON_QD
, RADEON
, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QE
, RADEON
, 0),
229 CHIP_DEF(PCI_CHIP_RADEON_QF
, RADEON
, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QG
, RADEON
, 0),
233 MODULE_DEVICE_TABLE(pci
, radeonfb_pci_table
);
242 /* these common regs are cleared before mode setting so they do not
243 * interfere with anything
245 static reg_val common_regs
[] = {
247 { OVR_WID_LEFT_RIGHT
, 0 },
248 { OVR_WID_TOP_BOTTOM
, 0 },
249 { OV0_SCALE_CNTL
, 0 },
254 { CAP0_TRIG_CNTL
, 0 },
255 { CAP1_TRIG_CNTL
, 0 },
262 static char *mode_option
;
263 static char *monitor_layout
;
264 static int noaccel
= 0;
265 static int default_dynclk
= -2;
266 static int nomodeset
= 0;
267 static int ignore_edid
= 0;
268 static int mirror
= 0;
269 static int panel_yres
= 0;
270 static int force_dfp
= 0;
271 static int force_measure_pll
= 0;
273 static int nomtrr
= 0;
275 static int force_sleep
;
276 static int ignore_devlist
;
277 #ifdef CONFIG_PMAC_BACKLIGHT
278 static int backlight
= 1;
280 static int backlight
= 0;
287 static void radeon_unmap_ROM(struct radeonfb_info
*rinfo
, struct pci_dev
*dev
)
289 if (!rinfo
->bios_seg
)
291 pci_unmap_rom(dev
, rinfo
->bios_seg
);
294 static int __devinit
radeon_map_ROM(struct radeonfb_info
*rinfo
, struct pci_dev
*dev
)
301 /* If this is a primary card, there is a shadow copy of the
302 * ROM somewhere in the first meg. We will just ignore the copy
303 * and use the ROM directly.
306 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
308 temp
= INREG(MPP_TB_CONFIG
);
311 OUTREG(MPP_TB_CONFIG
, temp
);
312 temp
= INREG(MPP_TB_CONFIG
);
314 rom
= pci_map_rom(dev
, &rom_size
);
316 printk(KERN_ERR
"radeonfb (%s): ROM failed to map\n",
317 pci_name(rinfo
->pdev
));
321 rinfo
->bios_seg
= rom
;
323 /* Very simple test to make sure it appeared */
324 if (BIOS_IN16(0) != 0xaa55) {
325 printk(KERN_DEBUG
"radeonfb (%s): Invalid ROM signature %x "
326 "should be 0xaa55\n",
327 pci_name(rinfo
->pdev
), BIOS_IN16(0));
330 /* Look for the PCI data to check the ROM type */
331 dptr
= BIOS_IN16(0x18);
333 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
334 * for now, until I've verified this works everywhere. The goal here is more
335 * to phase out Open Firmware images.
337 * Currently, we only look at the first PCI data, we could iteratre and deal with
338 * them all, and we should use fb_bios_start relative to start of image and not
339 * relative start of ROM, but so far, I never found a dual-image ATI card
342 * u32 signature; + 0x00
345 * u16 reserved_1; + 0x08
347 * u8 drevision; + 0x0c
348 * u8 class_hi; + 0x0d
349 * u16 class_lo; + 0x0e
351 * u16 irevision; + 0x12
353 * u8 indicator; + 0x15
354 * u16 reserved_2; + 0x16
357 if (BIOS_IN32(dptr
) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
358 printk(KERN_WARNING
"radeonfb (%s): PCI DATA signature in ROM"
359 "incorrect: %08x\n", pci_name(rinfo
->pdev
), BIOS_IN32(dptr
));
362 rom_type
= BIOS_IN8(dptr
+ 0x14);
365 printk(KERN_INFO
"radeonfb: Found Intel x86 BIOS ROM Image\n");
368 printk(KERN_INFO
"radeonfb: Found Open Firmware ROM Image\n");
371 printk(KERN_INFO
"radeonfb: Found HP PA-RISC ROM Image\n");
374 printk(KERN_INFO
"radeonfb: Found unknown type %d ROM Image\n", rom_type
);
378 /* Locate the flat panel infos, do some sanity checking !!! */
379 rinfo
->fp_bios_start
= BIOS_IN16(0x48);
383 rinfo
->bios_seg
= NULL
;
384 radeon_unmap_ROM(rinfo
, dev
);
389 static int __devinit
radeon_find_mem_vbios(struct radeonfb_info
*rinfo
)
391 /* I simplified this code as we used to miss the signatures in
392 * a lot of case. It's now closer to XFree, we just don't check
393 * for signatures at all... Something better will have to be done
394 * if we end up having conflicts
397 void __iomem
*rom_base
= NULL
;
399 for(segstart
=0x000c0000; segstart
<0x000f0000; segstart
+=0x00001000) {
400 rom_base
= ioremap(segstart
, 0x10000);
401 if (rom_base
== NULL
)
403 if (readb(rom_base
) == 0x55 && readb(rom_base
+ 1) == 0xaa)
408 if (rom_base
== NULL
)
411 /* Locate the flat panel infos, do some sanity checking !!! */
412 rinfo
->bios_seg
= rom_base
;
413 rinfo
->fp_bios_start
= BIOS_IN16(0x48);
419 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
421 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
422 * tree. Hopefully, ATI OF driver is kind enough to fill these
424 static int __devinit
radeon_read_xtal_OF (struct radeonfb_info
*rinfo
)
426 struct device_node
*dp
= rinfo
->of_node
;
431 val
= of_get_property(dp
, "ATY,RefCLK", NULL
);
433 printk(KERN_WARNING
"radeonfb: No ATY,RefCLK property !\n");
437 rinfo
->pll
.ref_clk
= (*val
) / 10;
439 val
= of_get_property(dp
, "ATY,SCLK", NULL
);
441 rinfo
->pll
.sclk
= (*val
) / 10;
443 val
= of_get_property(dp
, "ATY,MCLK", NULL
);
445 rinfo
->pll
.mclk
= (*val
) / 10;
449 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
452 * Read PLL infos from chip registers
454 static int __devinit
radeon_probe_pll_params(struct radeonfb_info
*rinfo
)
456 unsigned char ppll_div_sel
;
458 unsigned sclk
, mclk
, tmp
, ref_div
;
459 int hTotal
, vTotal
, num
, denom
, m
, n
;
460 unsigned long long hz
, vclk
;
462 struct timeval start_tv
, stop_tv
;
463 long total_secs
, total_usecs
;
466 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
470 /* Flush PCI buffers ? */
471 tmp
= INREG16(DEVICE_ID
);
475 for(i
=0; i
<1000000; i
++)
476 if (((INREG(CRTC_VLINE_CRNT_VLINE
) >> 16) & 0x3ff) == 0)
479 do_gettimeofday(&start_tv
);
481 for(i
=0; i
<1000000; i
++)
482 if (((INREG(CRTC_VLINE_CRNT_VLINE
) >> 16) & 0x3ff) != 0)
485 for(i
=0; i
<1000000; i
++)
486 if (((INREG(CRTC_VLINE_CRNT_VLINE
) >> 16) & 0x3ff) == 0)
489 do_gettimeofday(&stop_tv
);
493 total_secs
= stop_tv
.tv_sec
- start_tv
.tv_sec
;
496 total_usecs
= stop_tv
.tv_usec
- start_tv
.tv_usec
;
497 total_usecs
+= total_secs
* 1000000;
499 total_usecs
= -total_usecs
;
500 hz
= 1000000/total_usecs
;
502 hTotal
= ((INREG(CRTC_H_TOTAL_DISP
) & 0x1ff) + 1) * 8;
503 vTotal
= ((INREG(CRTC_V_TOTAL_DISP
) & 0x3ff) + 1);
504 vclk
= (long long)hTotal
* (long long)vTotal
* hz
;
506 switch((INPLL(PPLL_REF_DIV
) & 0x30000) >> 16) {
513 n
= ((INPLL(M_SPLL_REF_FB_DIV
) >> 16) & 0xff);
514 m
= (INPLL(M_SPLL_REF_FB_DIV
) & 0xff);
519 n
= ((INPLL(M_SPLL_REF_FB_DIV
) >> 8) & 0xff);
520 m
= (INPLL(M_SPLL_REF_FB_DIV
) & 0xff);
526 ppll_div_sel
= INREG8(CLOCK_CNTL_INDEX
+ 1) & 0x3;
527 radeon_pll_errata_after_index(rinfo
);
529 n
= (INPLL(PPLL_DIV_0
+ ppll_div_sel
) & 0x7ff);
530 m
= (INPLL(PPLL_REF_DIV
) & 0x3ff);
535 switch ((INPLL(PPLL_DIV_0
+ ppll_div_sel
) >> 16) & 0x7) {
557 do_div(vclk
, 1000 * num
);
560 if ((xtal
> 26900) && (xtal
< 27100))
562 else if ((xtal
> 14200) && (xtal
< 14400))
564 else if ((xtal
> 29400) && (xtal
< 29600))
567 printk(KERN_WARNING
"xtal calculation failed: %ld\n", xtal
);
571 tmp
= INPLL(M_SPLL_REF_FB_DIV
);
572 ref_div
= INPLL(PPLL_REF_DIV
) & 0x3ff;
574 Ns
= (tmp
& 0xff0000) >> 16;
575 Nm
= (tmp
& 0xff00) >> 8;
577 sclk
= round_div((2 * Ns
* xtal
), (2 * M
));
578 mclk
= round_div((2 * Nm
* xtal
), (2 * M
));
580 /* we're done, hopefully these are sane values */
581 rinfo
->pll
.ref_clk
= xtal
;
582 rinfo
->pll
.ref_div
= ref_div
;
583 rinfo
->pll
.sclk
= sclk
;
584 rinfo
->pll
.mclk
= mclk
;
590 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
592 static void __devinit
radeon_get_pllinfo(struct radeonfb_info
*rinfo
)
595 * In the case nothing works, these are defaults; they are mostly
596 * incomplete, however. It does provide ppll_max and _min values
597 * even for most other methods, however.
599 switch (rinfo
->chipset
) {
600 case PCI_DEVICE_ID_ATI_RADEON_QW
:
601 case PCI_DEVICE_ID_ATI_RADEON_QX
:
602 rinfo
->pll
.ppll_max
= 35000;
603 rinfo
->pll
.ppll_min
= 12000;
604 rinfo
->pll
.mclk
= 23000;
605 rinfo
->pll
.sclk
= 23000;
606 rinfo
->pll
.ref_clk
= 2700;
608 case PCI_DEVICE_ID_ATI_RADEON_QL
:
609 case PCI_DEVICE_ID_ATI_RADEON_QN
:
610 case PCI_DEVICE_ID_ATI_RADEON_QO
:
611 case PCI_DEVICE_ID_ATI_RADEON_Ql
:
612 case PCI_DEVICE_ID_ATI_RADEON_BB
:
613 rinfo
->pll
.ppll_max
= 35000;
614 rinfo
->pll
.ppll_min
= 12000;
615 rinfo
->pll
.mclk
= 27500;
616 rinfo
->pll
.sclk
= 27500;
617 rinfo
->pll
.ref_clk
= 2700;
619 case PCI_DEVICE_ID_ATI_RADEON_Id
:
620 case PCI_DEVICE_ID_ATI_RADEON_Ie
:
621 case PCI_DEVICE_ID_ATI_RADEON_If
:
622 case PCI_DEVICE_ID_ATI_RADEON_Ig
:
623 rinfo
->pll
.ppll_max
= 35000;
624 rinfo
->pll
.ppll_min
= 12000;
625 rinfo
->pll
.mclk
= 25000;
626 rinfo
->pll
.sclk
= 25000;
627 rinfo
->pll
.ref_clk
= 2700;
629 case PCI_DEVICE_ID_ATI_RADEON_ND
:
630 case PCI_DEVICE_ID_ATI_RADEON_NE
:
631 case PCI_DEVICE_ID_ATI_RADEON_NF
:
632 case PCI_DEVICE_ID_ATI_RADEON_NG
:
633 rinfo
->pll
.ppll_max
= 40000;
634 rinfo
->pll
.ppll_min
= 20000;
635 rinfo
->pll
.mclk
= 27000;
636 rinfo
->pll
.sclk
= 27000;
637 rinfo
->pll
.ref_clk
= 2700;
639 case PCI_DEVICE_ID_ATI_RADEON_QD
:
640 case PCI_DEVICE_ID_ATI_RADEON_QE
:
641 case PCI_DEVICE_ID_ATI_RADEON_QF
:
642 case PCI_DEVICE_ID_ATI_RADEON_QG
:
644 rinfo
->pll
.ppll_max
= 35000;
645 rinfo
->pll
.ppll_min
= 12000;
646 rinfo
->pll
.mclk
= 16600;
647 rinfo
->pll
.sclk
= 16600;
648 rinfo
->pll
.ref_clk
= 2700;
651 rinfo
->pll
.ref_div
= INPLL(PPLL_REF_DIV
) & PPLL_REF_DIV_MASK
;
654 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
656 * Retrieve PLL infos from Open Firmware first
658 if (!force_measure_pll
&& radeon_read_xtal_OF(rinfo
) == 0) {
659 printk(KERN_INFO
"radeonfb: Retrieved PLL infos from Open Firmware\n");
662 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
665 * Check out if we have an X86 which gave us some PLL informations
666 * and if yes, retrieve them
668 if (!force_measure_pll
&& rinfo
->bios_seg
) {
669 u16 pll_info_block
= BIOS_IN16(rinfo
->fp_bios_start
+ 0x30);
671 rinfo
->pll
.sclk
= BIOS_IN16(pll_info_block
+ 0x08);
672 rinfo
->pll
.mclk
= BIOS_IN16(pll_info_block
+ 0x0a);
673 rinfo
->pll
.ref_clk
= BIOS_IN16(pll_info_block
+ 0x0e);
674 rinfo
->pll
.ref_div
= BIOS_IN16(pll_info_block
+ 0x10);
675 rinfo
->pll
.ppll_min
= BIOS_IN32(pll_info_block
+ 0x12);
676 rinfo
->pll
.ppll_max
= BIOS_IN32(pll_info_block
+ 0x16);
678 printk(KERN_INFO
"radeonfb: Retrieved PLL infos from BIOS\n");
683 * We didn't get PLL parameters from either OF or BIOS, we try to
686 if (radeon_probe_pll_params(rinfo
) == 0) {
687 printk(KERN_INFO
"radeonfb: Retrieved PLL infos from registers\n");
692 * Fall back to already-set defaults...
694 printk(KERN_INFO
"radeonfb: Used default PLL infos\n");
698 * Some methods fail to retrieve SCLK and MCLK values, we apply default
699 * settings in this case (200Mhz). If that really happne often, we could
700 * fetch from registers instead...
702 if (rinfo
->pll
.mclk
== 0)
703 rinfo
->pll
.mclk
= 20000;
704 if (rinfo
->pll
.sclk
== 0)
705 rinfo
->pll
.sclk
= 20000;
707 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
708 rinfo
->pll
.ref_clk
/ 100, rinfo
->pll
.ref_clk
% 100,
710 rinfo
->pll
.mclk
/ 100, rinfo
->pll
.mclk
% 100,
711 rinfo
->pll
.sclk
/ 100, rinfo
->pll
.sclk
% 100);
712 printk("radeonfb: PLL min %d max %d\n", rinfo
->pll
.ppll_min
, rinfo
->pll
.ppll_max
);
715 static int radeonfb_check_var (struct fb_var_screeninfo
*var
, struct fb_info
*info
)
717 struct radeonfb_info
*rinfo
= info
->par
;
718 struct fb_var_screeninfo v
;
722 if (radeon_match_mode(rinfo
, &v
, var
))
725 switch (v
.bits_per_pixel
) {
727 v
.bits_per_pixel
= 8;
730 v
.bits_per_pixel
= 16;
733 #if 0 /* Doesn't seem to work */
734 v
.bits_per_pixel
= 24;
739 v
.bits_per_pixel
= 32;
745 switch (var_to_depth(&v
)) {
748 v
.red
.offset
= v
.green
.offset
= v
.blue
.offset
= 0;
749 v
.red
.length
= v
.green
.length
= v
.blue
.length
= 8;
750 v
.transp
.offset
= v
.transp
.length
= 0;
758 v
.red
.length
= v
.green
.length
= v
.blue
.length
= 5;
759 v
.transp
.offset
= v
.transp
.length
= 0;
770 v
.transp
.offset
= v
.transp
.length
= 0;
778 v
.red
.length
= v
.blue
.length
= v
.green
.length
= 8;
779 v
.transp
.offset
= v
.transp
.length
= 0;
787 v
.red
.length
= v
.blue
.length
= v
.green
.length
= 8;
788 v
.transp
.offset
= 24;
792 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
793 var
->xres
, var
->yres
, var
->bits_per_pixel
);
797 if (v
.yres_virtual
< v
.yres
)
798 v
.yres_virtual
= v
.yres
;
799 if (v
.xres_virtual
< v
.xres
)
800 v
.xres_virtual
= v
.xres
;
803 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
804 * with some panels, though I don't quite like this solution
806 if (rinfo
->info
->flags
& FBINFO_HWACCEL_DISABLED
) {
807 v
.xres_virtual
= v
.xres_virtual
& ~7ul;
809 pitch
= ((v
.xres_virtual
* ((v
.bits_per_pixel
+ 1) / 8) + 0x3f)
811 v
.xres_virtual
= (pitch
<< 6) / ((v
.bits_per_pixel
+ 1) / 8);
814 if (((v
.xres_virtual
* v
.yres_virtual
* nom
) / den
) > rinfo
->mapped_vram
)
817 if (v
.xres_virtual
< v
.xres
)
818 v
.xres
= v
.xres_virtual
;
825 if (v
.xoffset
> v
.xres_virtual
- v
.xres
)
826 v
.xoffset
= v
.xres_virtual
- v
.xres
- 1;
828 if (v
.yoffset
> v
.yres_virtual
- v
.yres
)
829 v
.yoffset
= v
.yres_virtual
- v
.yres
- 1;
831 v
.red
.msb_right
= v
.green
.msb_right
= v
.blue
.msb_right
=
832 v
.transp
.offset
= v
.transp
.length
=
833 v
.transp
.msb_right
= 0;
835 memcpy(var
, &v
, sizeof(v
));
841 static int radeonfb_pan_display (struct fb_var_screeninfo
*var
,
842 struct fb_info
*info
)
844 struct radeonfb_info
*rinfo
= info
->par
;
846 if ((var
->xoffset
+ var
->xres
> var
->xres_virtual
)
847 || (var
->yoffset
+ var
->yres
> var
->yres_virtual
))
854 OUTREG(CRTC_OFFSET
, ((var
->yoffset
* var
->xres_virtual
+ var
->xoffset
)
855 * var
->bits_per_pixel
/ 8) & ~7);
860 static int radeonfb_ioctl (struct fb_info
*info
, unsigned int cmd
,
863 struct radeonfb_info
*rinfo
= info
->par
;
870 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
871 * and do something better using 2nd CRTC instead of just hackish
872 * routing to second output
874 case FBIO_RADEON_SET_MIRROR
:
875 if (!rinfo
->is_mobility
)
878 rc
= get_user(value
, (__u32 __user
*)arg
);
885 tmp
= INREG(LVDS_GEN_CNTL
);
887 tmp
|= (LVDS_ON
| LVDS_BLON
);
889 tmp
= INREG(LVDS_GEN_CNTL
);
891 tmp
&= ~(LVDS_ON
| LVDS_BLON
);
894 OUTREG(LVDS_GEN_CNTL
, tmp
);
897 tmp
= INREG(CRTC_EXT_CNTL
);
902 tmp
= INREG(CRTC_EXT_CNTL
);
908 OUTREG(CRTC_EXT_CNTL
, tmp
);
911 case FBIO_RADEON_GET_MIRROR
:
912 if (!rinfo
->is_mobility
)
915 tmp
= INREG(LVDS_GEN_CNTL
);
916 if ((LVDS_ON
| LVDS_BLON
) & tmp
)
919 tmp
= INREG(CRTC_EXT_CNTL
);
920 if (CRTC_CRT_ON
& tmp
)
923 return put_user(value
, (__u32 __user
*)arg
);
932 int radeon_screen_blank(struct radeonfb_info
*rinfo
, int blank
, int mode_switch
)
938 if (rinfo
->lock_blank
)
941 radeon_engine_idle();
943 val
= INREG(CRTC_EXT_CNTL
);
944 val
&= ~(CRTC_DISPLAY_DIS
| CRTC_HSYNC_DIS
|
947 case FB_BLANK_VSYNC_SUSPEND
:
948 val
|= (CRTC_DISPLAY_DIS
| CRTC_VSYNC_DIS
);
950 case FB_BLANK_HSYNC_SUSPEND
:
951 val
|= (CRTC_DISPLAY_DIS
| CRTC_HSYNC_DIS
);
953 case FB_BLANK_POWERDOWN
:
954 val
|= (CRTC_DISPLAY_DIS
| CRTC_VSYNC_DIS
|
957 case FB_BLANK_NORMAL
:
958 val
|= CRTC_DISPLAY_DIS
;
960 case FB_BLANK_UNBLANK
:
964 OUTREG(CRTC_EXT_CNTL
, val
);
967 switch (rinfo
->mon1_type
) {
970 OUTREGP(FP_GEN_CNTL
, (FP_FPON
| FP_TMDS_EN
),
971 ~(FP_FPON
| FP_TMDS_EN
));
973 if (mode_switch
|| blank
== FB_BLANK_NORMAL
)
975 OUTREGP(FP_GEN_CNTL
, 0, ~(FP_FPON
| FP_TMDS_EN
));
979 del_timer_sync(&rinfo
->lvds_timer
);
980 val
= INREG(LVDS_GEN_CNTL
);
982 u32 target_val
= (val
& ~LVDS_DISPLAY_DIS
) | LVDS_BLON
| LVDS_ON
983 | LVDS_EN
| (rinfo
->init_state
.lvds_gen_cntl
984 & (LVDS_DIGON
| LVDS_BL_MOD_EN
));
985 if ((val
^ target_val
) == LVDS_DISPLAY_DIS
)
986 OUTREG(LVDS_GEN_CNTL
, target_val
);
987 else if ((val
^ target_val
) != 0) {
988 OUTREG(LVDS_GEN_CNTL
, target_val
989 & ~(LVDS_ON
| LVDS_BL_MOD_EN
));
990 rinfo
->init_state
.lvds_gen_cntl
&= ~LVDS_STATE_MASK
;
991 rinfo
->init_state
.lvds_gen_cntl
|=
992 target_val
& LVDS_STATE_MASK
;
994 radeon_msleep(rinfo
->panel_info
.pwr_delay
);
995 OUTREG(LVDS_GEN_CNTL
, target_val
);
998 rinfo
->pending_lvds_gen_cntl
= target_val
;
999 mod_timer(&rinfo
->lvds_timer
,
1001 msecs_to_jiffies(rinfo
->panel_info
.pwr_delay
));
1005 val
|= LVDS_DISPLAY_DIS
;
1006 OUTREG(LVDS_GEN_CNTL
, val
);
1008 /* We don't do a full switch-off on a simple mode switch */
1009 if (mode_switch
|| blank
== FB_BLANK_NORMAL
)
1012 /* Asic bug, when turning off LVDS_ON, we have to make sure
1013 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1015 tmp_pix_clks
= INPLL(PIXCLKS_CNTL
);
1016 if (rinfo
->is_mobility
|| rinfo
->is_IGP
)
1017 OUTPLLP(PIXCLKS_CNTL
, 0, ~PIXCLK_LVDS_ALWAYS_ONb
);
1018 val
&= ~(LVDS_BL_MOD_EN
);
1019 OUTREG(LVDS_GEN_CNTL
, val
);
1021 val
&= ~(LVDS_ON
| LVDS_EN
);
1022 OUTREG(LVDS_GEN_CNTL
, val
);
1024 rinfo
->pending_lvds_gen_cntl
= val
;
1025 mod_timer(&rinfo
->lvds_timer
,
1027 msecs_to_jiffies(rinfo
->panel_info
.pwr_delay
));
1028 rinfo
->init_state
.lvds_gen_cntl
&= ~LVDS_STATE_MASK
;
1029 rinfo
->init_state
.lvds_gen_cntl
|= val
& LVDS_STATE_MASK
;
1030 if (rinfo
->is_mobility
|| rinfo
->is_IGP
)
1031 OUTPLL(PIXCLKS_CNTL
, tmp_pix_clks
);
1035 // todo: powerdown DAC
1043 static int radeonfb_blank (int blank
, struct fb_info
*info
)
1045 struct radeonfb_info
*rinfo
= info
->par
;
1050 return radeon_screen_blank(rinfo
, blank
, 0);
1053 static int radeon_setcolreg (unsigned regno
, unsigned red
, unsigned green
,
1054 unsigned blue
, unsigned transp
,
1055 struct radeonfb_info
*rinfo
)
1067 rinfo
->palette
[regno
].red
= red
;
1068 rinfo
->palette
[regno
].green
= green
;
1069 rinfo
->palette
[regno
].blue
= blue
;
1074 if (!rinfo
->asleep
) {
1075 radeon_fifo_wait(9);
1077 if (rinfo
->bpp
== 16) {
1080 if (rinfo
->depth
== 16 && regno
> 63)
1082 if (rinfo
->depth
== 15 && regno
> 31)
1085 /* For 565, the green component is mixed one order
1088 if (rinfo
->depth
== 16) {
1089 OUTREG(PALETTE_INDEX
, pindex
>>1);
1090 OUTREG(PALETTE_DATA
,
1091 (rinfo
->palette
[regno
>>1].red
<< 16) |
1093 (rinfo
->palette
[regno
>>1].blue
));
1094 green
= rinfo
->palette
[regno
<<1].green
;
1098 if (rinfo
->depth
!= 16 || regno
< 32) {
1099 OUTREG(PALETTE_INDEX
, pindex
);
1100 OUTREG(PALETTE_DATA
, (red
<< 16) |
1101 (green
<< 8) | blue
);
1105 u32
*pal
= rinfo
->info
->pseudo_palette
;
1106 switch (rinfo
->depth
) {
1108 pal
[regno
] = (regno
<< 10) | (regno
<< 5) | regno
;
1111 pal
[regno
] = (regno
<< 11) | (regno
<< 5) | regno
;
1114 pal
[regno
] = (regno
<< 16) | (regno
<< 8) | regno
;
1117 i
= (regno
<< 8) | regno
;
1118 pal
[regno
] = (i
<< 16) | i
;
1125 static int radeonfb_setcolreg (unsigned regno
, unsigned red
, unsigned green
,
1126 unsigned blue
, unsigned transp
,
1127 struct fb_info
*info
)
1129 struct radeonfb_info
*rinfo
= info
->par
;
1130 u32 dac_cntl2
, vclk_cntl
= 0;
1133 if (!rinfo
->asleep
) {
1134 if (rinfo
->is_mobility
) {
1135 vclk_cntl
= INPLL(VCLK_ECP_CNTL
);
1136 OUTPLL(VCLK_ECP_CNTL
,
1137 vclk_cntl
& ~PIXCLK_DAC_ALWAYS_ONb
);
1140 /* Make sure we are on first palette */
1141 if (rinfo
->has_CRTC2
) {
1142 dac_cntl2
= INREG(DAC_CNTL2
);
1143 dac_cntl2
&= ~DAC2_PALETTE_ACCESS_CNTL
;
1144 OUTREG(DAC_CNTL2
, dac_cntl2
);
1148 rc
= radeon_setcolreg (regno
, red
, green
, blue
, transp
, rinfo
);
1150 if (!rinfo
->asleep
&& rinfo
->is_mobility
)
1151 OUTPLL(VCLK_ECP_CNTL
, vclk_cntl
);
1156 static int radeonfb_setcmap(struct fb_cmap
*cmap
, struct fb_info
*info
)
1158 struct radeonfb_info
*rinfo
= info
->par
;
1159 u16
*red
, *green
, *blue
, *transp
;
1160 u32 dac_cntl2
, vclk_cntl
= 0;
1161 int i
, start
, rc
= 0;
1163 if (!rinfo
->asleep
) {
1164 if (rinfo
->is_mobility
) {
1165 vclk_cntl
= INPLL(VCLK_ECP_CNTL
);
1166 OUTPLL(VCLK_ECP_CNTL
,
1167 vclk_cntl
& ~PIXCLK_DAC_ALWAYS_ONb
);
1170 /* Make sure we are on first palette */
1171 if (rinfo
->has_CRTC2
) {
1172 dac_cntl2
= INREG(DAC_CNTL2
);
1173 dac_cntl2
&= ~DAC2_PALETTE_ACCESS_CNTL
;
1174 OUTREG(DAC_CNTL2
, dac_cntl2
);
1179 green
= cmap
->green
;
1181 transp
= cmap
->transp
;
1182 start
= cmap
->start
;
1184 for (i
= 0; i
< cmap
->len
; i
++) {
1185 u_int hred
, hgreen
, hblue
, htransp
= 0xffff;
1191 htransp
= *transp
++;
1192 rc
= radeon_setcolreg (start
++, hred
, hgreen
, hblue
, htransp
,
1198 if (!rinfo
->asleep
&& rinfo
->is_mobility
)
1199 OUTPLL(VCLK_ECP_CNTL
, vclk_cntl
);
1204 static void radeon_save_state (struct radeonfb_info
*rinfo
,
1205 struct radeon_regs
*save
)
1208 save
->crtc_gen_cntl
= INREG(CRTC_GEN_CNTL
);
1209 save
->crtc_ext_cntl
= INREG(CRTC_EXT_CNTL
);
1210 save
->crtc_more_cntl
= INREG(CRTC_MORE_CNTL
);
1211 save
->dac_cntl
= INREG(DAC_CNTL
);
1212 save
->crtc_h_total_disp
= INREG(CRTC_H_TOTAL_DISP
);
1213 save
->crtc_h_sync_strt_wid
= INREG(CRTC_H_SYNC_STRT_WID
);
1214 save
->crtc_v_total_disp
= INREG(CRTC_V_TOTAL_DISP
);
1215 save
->crtc_v_sync_strt_wid
= INREG(CRTC_V_SYNC_STRT_WID
);
1216 save
->crtc_pitch
= INREG(CRTC_PITCH
);
1217 save
->surface_cntl
= INREG(SURFACE_CNTL
);
1220 save
->fp_crtc_h_total_disp
= INREG(FP_CRTC_H_TOTAL_DISP
);
1221 save
->fp_crtc_v_total_disp
= INREG(FP_CRTC_V_TOTAL_DISP
);
1222 save
->fp_gen_cntl
= INREG(FP_GEN_CNTL
);
1223 save
->fp_h_sync_strt_wid
= INREG(FP_H_SYNC_STRT_WID
);
1224 save
->fp_horz_stretch
= INREG(FP_HORZ_STRETCH
);
1225 save
->fp_v_sync_strt_wid
= INREG(FP_V_SYNC_STRT_WID
);
1226 save
->fp_vert_stretch
= INREG(FP_VERT_STRETCH
);
1227 save
->lvds_gen_cntl
= INREG(LVDS_GEN_CNTL
);
1228 save
->lvds_pll_cntl
= INREG(LVDS_PLL_CNTL
);
1229 save
->tmds_crc
= INREG(TMDS_CRC
);
1230 save
->tmds_transmitter_cntl
= INREG(TMDS_TRANSMITTER_CNTL
);
1231 save
->vclk_ecp_cntl
= INPLL(VCLK_ECP_CNTL
);
1234 save
->clk_cntl_index
= INREG(CLOCK_CNTL_INDEX
) & ~0x3f;
1235 radeon_pll_errata_after_index(rinfo
);
1236 save
->ppll_div_3
= INPLL(PPLL_DIV_3
);
1237 save
->ppll_ref_div
= INPLL(PPLL_REF_DIV
);
1241 static void radeon_write_pll_regs(struct radeonfb_info
*rinfo
, struct radeon_regs
*mode
)
1245 radeon_fifo_wait(20);
1247 /* Workaround from XFree */
1248 if (rinfo
->is_mobility
) {
1249 /* A temporal workaround for the occational blanking on certain laptop
1250 * panels. This appears to related to the PLL divider registers
1251 * (fail to lock?). It occurs even when all dividers are the same
1252 * with their old settings. In this case we really don't need to
1253 * fiddle with PLL registers. By doing this we can avoid the blanking
1254 * problem with some panels.
1256 if ((mode
->ppll_ref_div
== (INPLL(PPLL_REF_DIV
) & PPLL_REF_DIV_MASK
)) &&
1257 (mode
->ppll_div_3
== (INPLL(PPLL_DIV_3
) &
1258 (PPLL_POST3_DIV_MASK
| PPLL_FB3_DIV_MASK
)))) {
1259 /* We still have to force a switch to selected PPLL div thanks to
1260 * an XFree86 driver bug which will switch it away in some cases
1261 * even when using UseFDev */
1262 OUTREGP(CLOCK_CNTL_INDEX
,
1263 mode
->clk_cntl_index
& PPLL_DIV_SEL_MASK
,
1264 ~PPLL_DIV_SEL_MASK
);
1265 radeon_pll_errata_after_index(rinfo
);
1266 radeon_pll_errata_after_data(rinfo
);
1271 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1272 OUTPLLP(VCLK_ECP_CNTL
, VCLK_SRC_SEL_CPUCLK
, ~VCLK_SRC_SEL_MASK
);
1274 /* Reset PPLL & enable atomic update */
1276 PPLL_RESET
| PPLL_ATOMIC_UPDATE_EN
| PPLL_VGA_ATOMIC_UPDATE_EN
,
1277 ~(PPLL_RESET
| PPLL_ATOMIC_UPDATE_EN
| PPLL_VGA_ATOMIC_UPDATE_EN
));
1279 /* Switch to selected PPLL divider */
1280 OUTREGP(CLOCK_CNTL_INDEX
,
1281 mode
->clk_cntl_index
& PPLL_DIV_SEL_MASK
,
1282 ~PPLL_DIV_SEL_MASK
);
1283 radeon_pll_errata_after_index(rinfo
);
1284 radeon_pll_errata_after_data(rinfo
);
1286 /* Set PPLL ref. div */
1287 if (rinfo
->family
== CHIP_FAMILY_R300
||
1288 rinfo
->family
== CHIP_FAMILY_RS300
||
1289 rinfo
->family
== CHIP_FAMILY_R350
||
1290 rinfo
->family
== CHIP_FAMILY_RV350
||
1291 rinfo
->family
== CHIP_FAMILY_RV380
) {
1292 if (mode
->ppll_ref_div
& R300_PPLL_REF_DIV_ACC_MASK
) {
1293 /* When restoring console mode, use saved PPLL_REF_DIV
1296 OUTPLLP(PPLL_REF_DIV
, mode
->ppll_ref_div
, 0);
1298 /* R300 uses ref_div_acc field as real ref divider */
1299 OUTPLLP(PPLL_REF_DIV
,
1300 (mode
->ppll_ref_div
<< R300_PPLL_REF_DIV_ACC_SHIFT
),
1301 ~R300_PPLL_REF_DIV_ACC_MASK
);
1304 OUTPLLP(PPLL_REF_DIV
, mode
->ppll_ref_div
, ~PPLL_REF_DIV_MASK
);
1306 /* Set PPLL divider 3 & post divider*/
1307 OUTPLLP(PPLL_DIV_3
, mode
->ppll_div_3
, ~PPLL_FB3_DIV_MASK
);
1308 OUTPLLP(PPLL_DIV_3
, mode
->ppll_div_3
, ~PPLL_POST3_DIV_MASK
);
1311 while (INPLL(PPLL_REF_DIV
) & PPLL_ATOMIC_UPDATE_R
)
1313 OUTPLLP(PPLL_REF_DIV
, PPLL_ATOMIC_UPDATE_W
, ~PPLL_ATOMIC_UPDATE_W
);
1315 /* Wait read update complete */
1316 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1317 the cause yet, but this workaround will mask the problem for now.
1318 Other chips usually will pass at the very first test, so the
1319 workaround shouldn't have any effect on them. */
1320 for (i
= 0; (i
< 10000 && INPLL(PPLL_REF_DIV
) & PPLL_ATOMIC_UPDATE_R
); i
++)
1323 OUTPLL(HTOTAL_CNTL
, 0);
1325 /* Clear reset & atomic update */
1326 OUTPLLP(PPLL_CNTL
, 0,
1327 ~(PPLL_RESET
| PPLL_SLEEP
| PPLL_ATOMIC_UPDATE_EN
| PPLL_VGA_ATOMIC_UPDATE_EN
));
1329 /* We may want some locking ... oh well */
1332 /* Switch back VCLK source to PPLL */
1333 OUTPLLP(VCLK_ECP_CNTL
, VCLK_SRC_SEL_PPLLCLK
, ~VCLK_SRC_SEL_MASK
);
1337 * Timer function for delayed LVDS panel power up/down
1339 static void radeon_lvds_timer_func(unsigned long data
)
1341 struct radeonfb_info
*rinfo
= (struct radeonfb_info
*)data
;
1343 radeon_engine_idle();
1345 OUTREG(LVDS_GEN_CNTL
, rinfo
->pending_lvds_gen_cntl
);
1349 * Apply a video mode. This will apply the whole register set, including
1350 * the PLL registers, to the card
1352 void radeon_write_mode (struct radeonfb_info
*rinfo
, struct radeon_regs
*mode
,
1356 int primary_mon
= PRIMARY_MONITOR(rinfo
);
1362 radeon_screen_blank(rinfo
, FB_BLANK_NORMAL
, 0);
1364 radeon_fifo_wait(31);
1365 for (i
=0; i
<10; i
++)
1366 OUTREG(common_regs
[i
].reg
, common_regs
[i
].val
);
1368 /* Apply surface registers */
1369 for (i
=0; i
<8; i
++) {
1370 OUTREG(SURFACE0_LOWER_BOUND
+ 0x10*i
, mode
->surf_lower_bound
[i
]);
1371 OUTREG(SURFACE0_UPPER_BOUND
+ 0x10*i
, mode
->surf_upper_bound
[i
]);
1372 OUTREG(SURFACE0_INFO
+ 0x10*i
, mode
->surf_info
[i
]);
1375 OUTREG(CRTC_GEN_CNTL
, mode
->crtc_gen_cntl
);
1376 OUTREGP(CRTC_EXT_CNTL
, mode
->crtc_ext_cntl
,
1377 ~(CRTC_HSYNC_DIS
| CRTC_VSYNC_DIS
| CRTC_DISPLAY_DIS
));
1378 OUTREG(CRTC_MORE_CNTL
, mode
->crtc_more_cntl
);
1379 OUTREGP(DAC_CNTL
, mode
->dac_cntl
, DAC_RANGE_CNTL
| DAC_BLANKING
);
1380 OUTREG(CRTC_H_TOTAL_DISP
, mode
->crtc_h_total_disp
);
1381 OUTREG(CRTC_H_SYNC_STRT_WID
, mode
->crtc_h_sync_strt_wid
);
1382 OUTREG(CRTC_V_TOTAL_DISP
, mode
->crtc_v_total_disp
);
1383 OUTREG(CRTC_V_SYNC_STRT_WID
, mode
->crtc_v_sync_strt_wid
);
1384 OUTREG(CRTC_OFFSET
, 0);
1385 OUTREG(CRTC_OFFSET_CNTL
, 0);
1386 OUTREG(CRTC_PITCH
, mode
->crtc_pitch
);
1387 OUTREG(SURFACE_CNTL
, mode
->surface_cntl
);
1389 radeon_write_pll_regs(rinfo
, mode
);
1391 if ((primary_mon
== MT_DFP
) || (primary_mon
== MT_LCD
)) {
1392 radeon_fifo_wait(10);
1393 OUTREG(FP_CRTC_H_TOTAL_DISP
, mode
->fp_crtc_h_total_disp
);
1394 OUTREG(FP_CRTC_V_TOTAL_DISP
, mode
->fp_crtc_v_total_disp
);
1395 OUTREG(FP_H_SYNC_STRT_WID
, mode
->fp_h_sync_strt_wid
);
1396 OUTREG(FP_V_SYNC_STRT_WID
, mode
->fp_v_sync_strt_wid
);
1397 OUTREG(FP_HORZ_STRETCH
, mode
->fp_horz_stretch
);
1398 OUTREG(FP_VERT_STRETCH
, mode
->fp_vert_stretch
);
1399 OUTREG(FP_GEN_CNTL
, mode
->fp_gen_cntl
);
1400 OUTREG(TMDS_CRC
, mode
->tmds_crc
);
1401 OUTREG(TMDS_TRANSMITTER_CNTL
, mode
->tmds_transmitter_cntl
);
1405 radeon_screen_blank(rinfo
, FB_BLANK_UNBLANK
, 0);
1407 radeon_fifo_wait(2);
1408 OUTPLL(VCLK_ECP_CNTL
, mode
->vclk_ecp_cntl
);
1414 * Calculate the PLL values for a given mode
1416 static void radeon_calc_pll_regs(struct radeonfb_info
*rinfo
, struct radeon_regs
*regs
,
1434 int fb_div
, pll_output_freq
= 0;
1437 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1438 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1439 * recent than an r(v)100...
1442 /* XXX I had reports of flicker happening with the cinema display
1443 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1444 * this case. This could just be a bandwidth calculation issue, I
1445 * haven't implemented the bandwidth code yet, but in the meantime,
1446 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1447 * I haven't seen a case were were absolutely needed an odd PLL
1448 * divider. I'll find a better fix once I have more infos on the
1449 * real cause of the problem.
1451 while (rinfo
->has_CRTC2
) {
1452 u32 fp2_gen_cntl
= INREG(FP2_GEN_CNTL
);
1453 u32 disp_output_cntl
;
1456 /* FP2 path not enabled */
1457 if ((fp2_gen_cntl
& FP2_ON
) == 0)
1459 /* Not all chip revs have the same format for this register,
1460 * extract the source selection
1462 if (rinfo
->family
== CHIP_FAMILY_R200
||
1463 rinfo
->family
== CHIP_FAMILY_R300
||
1464 rinfo
->family
== CHIP_FAMILY_R350
||
1465 rinfo
->family
== CHIP_FAMILY_RV350
) {
1466 source
= (fp2_gen_cntl
>> 10) & 0x3;
1467 /* sourced from transform unit, check for transform unit
1471 disp_output_cntl
= INREG(DISP_OUTPUT_CNTL
);
1472 source
= (disp_output_cntl
>> 12) & 0x3;
1475 source
= (fp2_gen_cntl
>> 13) & 0x1;
1476 /* sourced from CRTC2 -> exit */
1480 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1487 if (freq
> rinfo
->pll
.ppll_max
)
1488 freq
= rinfo
->pll
.ppll_max
;
1489 if (freq
*12 < rinfo
->pll
.ppll_min
)
1490 freq
= rinfo
->pll
.ppll_min
/ 12;
1491 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1492 freq
, rinfo
->pll
.ppll_min
, rinfo
->pll
.ppll_max
);
1494 for (post_div
= &post_divs
[0]; post_div
->divider
; ++post_div
) {
1495 pll_output_freq
= post_div
->divider
* freq
;
1496 /* If we output to the DVO port (external TMDS), we don't allow an
1497 * odd PLL divider as those aren't supported on this path
1499 if (uses_dvo
&& (post_div
->divider
& 1))
1501 if (pll_output_freq
>= rinfo
->pll
.ppll_min
&&
1502 pll_output_freq
<= rinfo
->pll
.ppll_max
)
1506 /* If we fall through the bottom, try the "default value"
1507 given by the terminal post_div->bitvalue */
1508 if ( !post_div
->divider
) {
1509 post_div
= &post_divs
[post_div
->bitvalue
];
1510 pll_output_freq
= post_div
->divider
* freq
;
1512 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1513 rinfo
->pll
.ref_div
, rinfo
->pll
.ref_clk
,
1516 /* If we fall through the bottom, try the "default value"
1517 given by the terminal post_div->bitvalue */
1518 if ( !post_div
->divider
) {
1519 post_div
= &post_divs
[post_div
->bitvalue
];
1520 pll_output_freq
= post_div
->divider
* freq
;
1522 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1523 rinfo
->pll
.ref_div
, rinfo
->pll
.ref_clk
,
1526 fb_div
= round_div(rinfo
->pll
.ref_div
*pll_output_freq
,
1527 rinfo
->pll
.ref_clk
);
1528 regs
->ppll_ref_div
= rinfo
->pll
.ref_div
;
1529 regs
->ppll_div_3
= fb_div
| (post_div
->bitvalue
<< 16);
1531 RTRACE("post div = 0x%x\n", post_div
->bitvalue
);
1532 RTRACE("fb_div = 0x%x\n", fb_div
);
1533 RTRACE("ppll_div_3 = 0x%x\n", regs
->ppll_div_3
);
1536 static int radeonfb_set_par(struct fb_info
*info
)
1538 struct radeonfb_info
*rinfo
= info
->par
;
1539 struct fb_var_screeninfo
*mode
= &info
->var
;
1540 struct radeon_regs
*newmode
;
1541 int hTotal
, vTotal
, hSyncStart
, hSyncEnd
,
1542 hSyncPol
, vSyncStart
, vSyncEnd
, vSyncPol
, cSync
;
1543 u8 hsync_adj_tab
[] = {0, 0x12, 9, 9, 6, 5};
1544 u8 hsync_fudge_fp
[] = {2, 2, 0, 0, 5, 5};
1545 u32 sync
, h_sync_pol
, v_sync_pol
, dotClock
, pixClock
;
1549 int hsync_start
, hsync_fudge
, bytpp
, hsync_wid
, vsync_wid
;
1550 int primary_mon
= PRIMARY_MONITOR(rinfo
);
1551 int depth
= var_to_depth(mode
);
1554 newmode
= kmalloc(sizeof(struct radeon_regs
), GFP_KERNEL
);
1558 /* We always want engine to be idle on a mode switch, even
1559 * if we won't actually change the mode
1561 radeon_engine_idle();
1563 hSyncStart
= mode
->xres
+ mode
->right_margin
;
1564 hSyncEnd
= hSyncStart
+ mode
->hsync_len
;
1565 hTotal
= hSyncEnd
+ mode
->left_margin
;
1567 vSyncStart
= mode
->yres
+ mode
->lower_margin
;
1568 vSyncEnd
= vSyncStart
+ mode
->vsync_len
;
1569 vTotal
= vSyncEnd
+ mode
->upper_margin
;
1570 pixClock
= mode
->pixclock
;
1573 h_sync_pol
= sync
& FB_SYNC_HOR_HIGH_ACT
? 0 : 1;
1574 v_sync_pol
= sync
& FB_SYNC_VERT_HIGH_ACT
? 0 : 1;
1576 if (primary_mon
== MT_DFP
|| primary_mon
== MT_LCD
) {
1577 if (rinfo
->panel_info
.xres
< mode
->xres
)
1578 mode
->xres
= rinfo
->panel_info
.xres
;
1579 if (rinfo
->panel_info
.yres
< mode
->yres
)
1580 mode
->yres
= rinfo
->panel_info
.yres
;
1582 hTotal
= mode
->xres
+ rinfo
->panel_info
.hblank
;
1583 hSyncStart
= mode
->xres
+ rinfo
->panel_info
.hOver_plus
;
1584 hSyncEnd
= hSyncStart
+ rinfo
->panel_info
.hSync_width
;
1586 vTotal
= mode
->yres
+ rinfo
->panel_info
.vblank
;
1587 vSyncStart
= mode
->yres
+ rinfo
->panel_info
.vOver_plus
;
1588 vSyncEnd
= vSyncStart
+ rinfo
->panel_info
.vSync_width
;
1590 h_sync_pol
= !rinfo
->panel_info
.hAct_high
;
1591 v_sync_pol
= !rinfo
->panel_info
.vAct_high
;
1593 pixClock
= 100000000 / rinfo
->panel_info
.clock
;
1595 if (rinfo
->panel_info
.use_bios_dividers
) {
1597 newmode
->ppll_div_3
= rinfo
->panel_info
.fbk_divider
|
1598 (rinfo
->panel_info
.post_divider
<< 16);
1599 newmode
->ppll_ref_div
= rinfo
->panel_info
.ref_divider
;
1602 dotClock
= 1000000000 / pixClock
;
1603 freq
= dotClock
/ 10; /* x100 */
1605 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1606 hSyncStart
, hSyncEnd
, hTotal
);
1607 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1608 vSyncStart
, vSyncEnd
, vTotal
);
1610 hsync_wid
= (hSyncEnd
- hSyncStart
) / 8;
1611 vsync_wid
= vSyncEnd
- vSyncStart
;
1614 else if (hsync_wid
> 0x3f) /* max */
1619 else if (vsync_wid
> 0x1f) /* max */
1622 hSyncPol
= mode
->sync
& FB_SYNC_HOR_HIGH_ACT
? 0 : 1;
1623 vSyncPol
= mode
->sync
& FB_SYNC_VERT_HIGH_ACT
? 0 : 1;
1625 cSync
= mode
->sync
& FB_SYNC_COMP_HIGH_ACT
? (1 << 4) : 0;
1627 format
= radeon_get_dstbpp(depth
);
1628 bytpp
= mode
->bits_per_pixel
>> 3;
1630 if ((primary_mon
== MT_DFP
) || (primary_mon
== MT_LCD
))
1631 hsync_fudge
= hsync_fudge_fp
[format
-1];
1633 hsync_fudge
= hsync_adj_tab
[format
-1];
1635 hsync_start
= hSyncStart
- 8 + hsync_fudge
;
1637 newmode
->crtc_gen_cntl
= CRTC_EXT_DISP_EN
| CRTC_EN
|
1640 /* Clear auto-center etc... */
1641 newmode
->crtc_more_cntl
= rinfo
->init_state
.crtc_more_cntl
;
1642 newmode
->crtc_more_cntl
&= 0xfffffff0;
1644 if ((primary_mon
== MT_DFP
) || (primary_mon
== MT_LCD
)) {
1645 newmode
->crtc_ext_cntl
= VGA_ATI_LINEAR
| XCRT_CNT_EN
;
1647 newmode
->crtc_ext_cntl
|= CRTC_CRT_ON
;
1649 newmode
->crtc_gen_cntl
&= ~(CRTC_DBL_SCAN_EN
|
1652 newmode
->crtc_ext_cntl
= VGA_ATI_LINEAR
| XCRT_CNT_EN
|
1656 newmode
->dac_cntl
= /* INREG(DAC_CNTL) | */ DAC_MASK_ALL
| DAC_VGA_ADR_EN
|
1659 newmode
->crtc_h_total_disp
= ((((hTotal
/ 8) - 1) & 0x3ff) |
1660 (((mode
->xres
/ 8) - 1) << 16));
1662 newmode
->crtc_h_sync_strt_wid
= ((hsync_start
& 0x1fff) |
1663 (hsync_wid
<< 16) | (h_sync_pol
<< 23));
1665 newmode
->crtc_v_total_disp
= ((vTotal
- 1) & 0xffff) |
1666 ((mode
->yres
- 1) << 16);
1668 newmode
->crtc_v_sync_strt_wid
= (((vSyncStart
- 1) & 0xfff) |
1669 (vsync_wid
<< 16) | (v_sync_pol
<< 23));
1671 if (!(info
->flags
& FBINFO_HWACCEL_DISABLED
)) {
1672 /* We first calculate the engine pitch */
1673 rinfo
->pitch
= ((mode
->xres_virtual
* ((mode
->bits_per_pixel
+ 1) / 8) + 0x3f)
1676 /* Then, re-multiply it to get the CRTC pitch */
1677 newmode
->crtc_pitch
= (rinfo
->pitch
<< 3) / ((mode
->bits_per_pixel
+ 1) / 8);
1679 newmode
->crtc_pitch
= (mode
->xres_virtual
>> 3);
1681 newmode
->crtc_pitch
|= (newmode
->crtc_pitch
<< 16);
1684 * It looks like recent chips have a problem with SURFACE_CNTL,
1685 * setting SURF_TRANSLATION_DIS completely disables the
1686 * swapper as well, so we leave it unset now.
1688 newmode
->surface_cntl
= 0;
1690 #if defined(__BIG_ENDIAN)
1692 /* Setup swapping on both apertures, though we currently
1693 * only use aperture 0, enabling swapper on aperture 1
1696 switch (mode
->bits_per_pixel
) {
1698 newmode
->surface_cntl
|= NONSURF_AP0_SWP_16BPP
;
1699 newmode
->surface_cntl
|= NONSURF_AP1_SWP_16BPP
;
1703 newmode
->surface_cntl
|= NONSURF_AP0_SWP_32BPP
;
1704 newmode
->surface_cntl
|= NONSURF_AP1_SWP_32BPP
;
1709 /* Clear surface registers */
1710 for (i
=0; i
<8; i
++) {
1711 newmode
->surf_lower_bound
[i
] = 0;
1712 newmode
->surf_upper_bound
[i
] = 0x1f;
1713 newmode
->surf_info
[i
] = 0;
1716 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1717 newmode
->crtc_h_total_disp
, newmode
->crtc_h_sync_strt_wid
);
1718 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1719 newmode
->crtc_v_total_disp
, newmode
->crtc_v_sync_strt_wid
);
1721 rinfo
->bpp
= mode
->bits_per_pixel
;
1722 rinfo
->depth
= depth
;
1724 RTRACE("pixclock = %lu\n", (unsigned long)pixClock
);
1725 RTRACE("freq = %lu\n", (unsigned long)freq
);
1727 /* We use PPLL_DIV_3 */
1728 newmode
->clk_cntl_index
= 0x300;
1730 /* Calculate PPLL value if necessary */
1732 radeon_calc_pll_regs(rinfo
, newmode
, freq
);
1734 newmode
->vclk_ecp_cntl
= rinfo
->init_state
.vclk_ecp_cntl
;
1736 if ((primary_mon
== MT_DFP
) || (primary_mon
== MT_LCD
)) {
1737 unsigned int hRatio
, vRatio
;
1739 if (mode
->xres
> rinfo
->panel_info
.xres
)
1740 mode
->xres
= rinfo
->panel_info
.xres
;
1741 if (mode
->yres
> rinfo
->panel_info
.yres
)
1742 mode
->yres
= rinfo
->panel_info
.yres
;
1744 newmode
->fp_horz_stretch
= (((rinfo
->panel_info
.xres
/ 8) - 1)
1745 << HORZ_PANEL_SHIFT
);
1746 newmode
->fp_vert_stretch
= ((rinfo
->panel_info
.yres
- 1)
1747 << VERT_PANEL_SHIFT
);
1749 if (mode
->xres
!= rinfo
->panel_info
.xres
) {
1750 hRatio
= round_div(mode
->xres
* HORZ_STRETCH_RATIO_MAX
,
1751 rinfo
->panel_info
.xres
);
1752 newmode
->fp_horz_stretch
= (((((unsigned long)hRatio
) & HORZ_STRETCH_RATIO_MASK
)) |
1753 (newmode
->fp_horz_stretch
&
1754 (HORZ_PANEL_SIZE
| HORZ_FP_LOOP_STRETCH
|
1755 HORZ_AUTO_RATIO_INC
)));
1756 newmode
->fp_horz_stretch
|= (HORZ_STRETCH_BLEND
|
1757 HORZ_STRETCH_ENABLE
);
1760 newmode
->fp_horz_stretch
&= ~HORZ_AUTO_RATIO
;
1762 if (mode
->yres
!= rinfo
->panel_info
.yres
) {
1763 vRatio
= round_div(mode
->yres
* VERT_STRETCH_RATIO_MAX
,
1764 rinfo
->panel_info
.yres
);
1765 newmode
->fp_vert_stretch
= (((((unsigned long)vRatio
) & VERT_STRETCH_RATIO_MASK
)) |
1766 (newmode
->fp_vert_stretch
&
1767 (VERT_PANEL_SIZE
| VERT_STRETCH_RESERVED
)));
1768 newmode
->fp_vert_stretch
|= (VERT_STRETCH_BLEND
|
1769 VERT_STRETCH_ENABLE
);
1772 newmode
->fp_vert_stretch
&= ~VERT_AUTO_RATIO_EN
;
1774 newmode
->fp_gen_cntl
= (rinfo
->init_state
.fp_gen_cntl
& (u32
)
1776 FP_RMX_HVSYNC_CONTROL_EN
|
1781 FP_CRTC_USE_SHADOW_VEND
|
1784 newmode
->fp_gen_cntl
|= (FP_CRTC_DONT_SHADOW_VPAR
|
1785 FP_CRTC_DONT_SHADOW_HEND
|
1788 if (IS_R300_VARIANT(rinfo
) ||
1789 (rinfo
->family
== CHIP_FAMILY_R200
)) {
1790 newmode
->fp_gen_cntl
&= ~R200_FP_SOURCE_SEL_MASK
;
1792 newmode
->fp_gen_cntl
|= R200_FP_SOURCE_SEL_RMX
;
1794 newmode
->fp_gen_cntl
|= R200_FP_SOURCE_SEL_CRTC1
;
1796 newmode
->fp_gen_cntl
|= FP_SEL_CRTC1
;
1798 newmode
->lvds_gen_cntl
= rinfo
->init_state
.lvds_gen_cntl
;
1799 newmode
->lvds_pll_cntl
= rinfo
->init_state
.lvds_pll_cntl
;
1800 newmode
->tmds_crc
= rinfo
->init_state
.tmds_crc
;
1801 newmode
->tmds_transmitter_cntl
= rinfo
->init_state
.tmds_transmitter_cntl
;
1803 if (primary_mon
== MT_LCD
) {
1804 newmode
->lvds_gen_cntl
|= (LVDS_ON
| LVDS_BLON
);
1805 newmode
->fp_gen_cntl
&= ~(FP_FPON
| FP_TMDS_EN
);
1808 newmode
->fp_gen_cntl
|= (FP_FPON
| FP_TMDS_EN
);
1809 newmode
->tmds_transmitter_cntl
&= ~(TMDS_PLLRST
);
1810 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1811 if (IS_R300_VARIANT(rinfo
) ||
1812 (rinfo
->family
== CHIP_FAMILY_R200
) || !rinfo
->has_CRTC2
)
1813 newmode
->tmds_transmitter_cntl
&= ~TMDS_PLL_EN
;
1815 newmode
->tmds_transmitter_cntl
|= TMDS_PLL_EN
;
1816 newmode
->crtc_ext_cntl
&= ~CRTC_CRT_ON
;
1819 newmode
->fp_crtc_h_total_disp
= (((rinfo
->panel_info
.hblank
/ 8) & 0x3ff) |
1820 (((mode
->xres
/ 8) - 1) << 16));
1821 newmode
->fp_crtc_v_total_disp
= (rinfo
->panel_info
.vblank
& 0xffff) |
1822 ((mode
->yres
- 1) << 16);
1823 newmode
->fp_h_sync_strt_wid
= ((rinfo
->panel_info
.hOver_plus
& 0x1fff) |
1824 (hsync_wid
<< 16) | (h_sync_pol
<< 23));
1825 newmode
->fp_v_sync_strt_wid
= ((rinfo
->panel_info
.vOver_plus
& 0xfff) |
1826 (vsync_wid
<< 16) | (v_sync_pol
<< 23));
1830 if (!rinfo
->asleep
) {
1831 memcpy(&rinfo
->state
, newmode
, sizeof(*newmode
));
1832 radeon_write_mode (rinfo
, newmode
, 0);
1833 /* (re)initialize the engine */
1834 if (!(info
->flags
& FBINFO_HWACCEL_DISABLED
))
1835 radeonfb_engine_init (rinfo
);
1838 if (!(info
->flags
& FBINFO_HWACCEL_DISABLED
))
1839 info
->fix
.line_length
= rinfo
->pitch
*64;
1841 info
->fix
.line_length
= mode
->xres_virtual
1842 * ((mode
->bits_per_pixel
+ 1) / 8);
1843 info
->fix
.visual
= rinfo
->depth
== 8 ? FB_VISUAL_PSEUDOCOLOR
1844 : FB_VISUAL_DIRECTCOLOR
;
1846 #ifdef CONFIG_BOOTX_TEXT
1847 /* Update debug text engine */
1848 btext_update_display(rinfo
->fb_base_phys
, mode
->xres
, mode
->yres
,
1849 rinfo
->depth
, info
->fix
.line_length
);
1857 static struct fb_ops radeonfb_ops
= {
1858 .owner
= THIS_MODULE
,
1859 .fb_check_var
= radeonfb_check_var
,
1860 .fb_set_par
= radeonfb_set_par
,
1861 .fb_setcolreg
= radeonfb_setcolreg
,
1862 .fb_setcmap
= radeonfb_setcmap
,
1863 .fb_pan_display
= radeonfb_pan_display
,
1864 .fb_blank
= radeonfb_blank
,
1865 .fb_ioctl
= radeonfb_ioctl
,
1866 .fb_sync
= radeonfb_sync
,
1867 .fb_fillrect
= radeonfb_fillrect
,
1868 .fb_copyarea
= radeonfb_copyarea
,
1869 .fb_imageblit
= radeonfb_imageblit
,
1873 static int __devinit
radeon_set_fbinfo (struct radeonfb_info
*rinfo
)
1875 struct fb_info
*info
= rinfo
->info
;
1878 info
->pseudo_palette
= rinfo
->pseudo_palette
;
1879 info
->flags
= FBINFO_DEFAULT
1880 | FBINFO_HWACCEL_COPYAREA
1881 | FBINFO_HWACCEL_FILLRECT
1882 | FBINFO_HWACCEL_XPAN
1883 | FBINFO_HWACCEL_YPAN
;
1884 info
->fbops
= &radeonfb_ops
;
1885 info
->screen_base
= rinfo
->fb_base
;
1886 info
->screen_size
= rinfo
->mapped_vram
;
1887 /* Fill fix common fields */
1888 strlcpy(info
->fix
.id
, rinfo
->name
, sizeof(info
->fix
.id
));
1889 info
->fix
.smem_start
= rinfo
->fb_base_phys
;
1890 info
->fix
.smem_len
= rinfo
->video_ram
;
1891 info
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
1892 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
1893 info
->fix
.xpanstep
= 8;
1894 info
->fix
.ypanstep
= 1;
1895 info
->fix
.ywrapstep
= 0;
1896 info
->fix
.type_aux
= 0;
1897 info
->fix
.mmio_start
= rinfo
->mmio_base_phys
;
1898 info
->fix
.mmio_len
= RADEON_REGSIZE
;
1899 info
->fix
.accel
= FB_ACCEL_ATI_RADEON
;
1901 fb_alloc_cmap(&info
->cmap
, 256, 0);
1904 info
->flags
|= FBINFO_HWACCEL_DISABLED
;
1910 * This reconfigure the card's internal memory map. In theory, we'd like
1911 * to setup the card's memory at the same address as it's PCI bus address,
1912 * and the AGP aperture right after that so that system RAM on 32 bits
1913 * machines at least, is directly accessible. However, doing so would
1914 * conflict with the current XFree drivers...
1915 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1916 * on the proper way to set this up and duplicate this here. In the meantime,
1917 * I put the card's memory at 0 in card space and AGP at some random high
1918 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1920 #ifdef CONFIG_PPC_OF
1921 #undef SET_MC_FB_FROM_APERTURE
1922 static void fixup_memory_mappings(struct radeonfb_info
*rinfo
)
1924 u32 save_crtc_gen_cntl
, save_crtc2_gen_cntl
= 0;
1925 u32 save_crtc_ext_cntl
;
1926 u32 aper_base
, aper_size
;
1929 /* First, we disable display to avoid interfering */
1930 if (rinfo
->has_CRTC2
) {
1931 save_crtc2_gen_cntl
= INREG(CRTC2_GEN_CNTL
);
1932 OUTREG(CRTC2_GEN_CNTL
, save_crtc2_gen_cntl
| CRTC2_DISP_REQ_EN_B
);
1934 save_crtc_gen_cntl
= INREG(CRTC_GEN_CNTL
);
1935 save_crtc_ext_cntl
= INREG(CRTC_EXT_CNTL
);
1937 OUTREG(CRTC_EXT_CNTL
, save_crtc_ext_cntl
| CRTC_DISPLAY_DIS
);
1938 OUTREG(CRTC_GEN_CNTL
, save_crtc_gen_cntl
| CRTC_DISP_REQ_EN_B
);
1941 aper_base
= INREG(CONFIG_APER_0_BASE
);
1942 aper_size
= INREG(CONFIG_APER_SIZE
);
1944 #ifdef SET_MC_FB_FROM_APERTURE
1945 /* Set framebuffer to be at the same address as set in PCI BAR */
1946 OUTREG(MC_FB_LOCATION
,
1947 ((aper_base
+ aper_size
- 1) & 0xffff0000) | (aper_base
>> 16));
1948 rinfo
->fb_local_base
= aper_base
;
1950 OUTREG(MC_FB_LOCATION
, 0x7fff0000);
1951 rinfo
->fb_local_base
= 0;
1953 agp_base
= aper_base
+ aper_size
;
1954 if (agp_base
& 0xf0000000)
1955 agp_base
= (aper_base
| 0x0fffffff) + 1;
1957 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1958 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1959 * always the case on PPCs afaik.
1961 #ifdef SET_MC_FB_FROM_APERTURE
1962 OUTREG(MC_AGP_LOCATION
, 0xffff0000 | (agp_base
>> 16));
1964 OUTREG(MC_AGP_LOCATION
, 0xffffe000);
1967 /* Fixup the display base addresses & engine offsets while we
1970 #ifdef SET_MC_FB_FROM_APERTURE
1971 OUTREG(DISPLAY_BASE_ADDR
, aper_base
);
1972 if (rinfo
->has_CRTC2
)
1973 OUTREG(CRTC2_DISPLAY_BASE_ADDR
, aper_base
);
1974 OUTREG(OV0_BASE_ADDR
, aper_base
);
1976 OUTREG(DISPLAY_BASE_ADDR
, 0);
1977 if (rinfo
->has_CRTC2
)
1978 OUTREG(CRTC2_DISPLAY_BASE_ADDR
, 0);
1979 OUTREG(OV0_BASE_ADDR
, 0);
1983 /* Restore display settings */
1984 OUTREG(CRTC_GEN_CNTL
, save_crtc_gen_cntl
);
1985 OUTREG(CRTC_EXT_CNTL
, save_crtc_ext_cntl
);
1986 if (rinfo
->has_CRTC2
)
1987 OUTREG(CRTC2_GEN_CNTL
, save_crtc2_gen_cntl
);
1989 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1991 ((aper_base
+ aper_size
- 1) & 0xffff0000) | (aper_base
>> 16),
1992 0xffff0000 | (agp_base
>> 16));
1994 #endif /* CONFIG_PPC_OF */
1997 static void radeon_identify_vram(struct radeonfb_info
*rinfo
)
2001 /* framebuffer size */
2002 if ((rinfo
->family
== CHIP_FAMILY_RS100
) ||
2003 (rinfo
->family
== CHIP_FAMILY_RS200
) ||
2004 (rinfo
->family
== CHIP_FAMILY_RS300
) ||
2005 (rinfo
->family
== CHIP_FAMILY_RC410
) ||
2006 (rinfo
->family
== CHIP_FAMILY_RS480
) ) {
2007 u32 tom
= INREG(NB_TOM
);
2008 tmp
= ((((tom
>> 16) - (tom
& 0xffff) + 1) << 6) * 1024);
2010 radeon_fifo_wait(6);
2011 OUTREG(MC_FB_LOCATION
, tom
);
2012 OUTREG(DISPLAY_BASE_ADDR
, (tom
& 0xffff) << 16);
2013 OUTREG(CRTC2_DISPLAY_BASE_ADDR
, (tom
& 0xffff) << 16);
2014 OUTREG(OV0_BASE_ADDR
, (tom
& 0xffff) << 16);
2016 /* This is supposed to fix the crtc2 noise problem. */
2017 OUTREG(GRPH2_BUFFER_CNTL
, INREG(GRPH2_BUFFER_CNTL
) & ~0x7f0000);
2019 if ((rinfo
->family
== CHIP_FAMILY_RS100
) ||
2020 (rinfo
->family
== CHIP_FAMILY_RS200
)) {
2021 /* This is to workaround the asic bug for RMX, some versions
2022 of BIOS dosen't have this register initialized correctly.
2024 OUTREGP(CRTC_MORE_CNTL
, CRTC_H_CUTOFF_ACTIVE_EN
,
2025 ~CRTC_H_CUTOFF_ACTIVE_EN
);
2028 tmp
= INREG(CONFIG_MEMSIZE
);
2031 /* mem size is bits [28:0], mask off the rest */
2032 rinfo
->video_ram
= tmp
& CONFIG_MEMSIZE_MASK
;
2035 * Hack to get around some busted production M6's
2038 if (rinfo
->video_ram
== 0) {
2039 switch (rinfo
->pdev
->device
) {
2040 case PCI_CHIP_RADEON_LY
:
2041 case PCI_CHIP_RADEON_LZ
:
2042 rinfo
->video_ram
= 8192 * 1024;
2051 * Now try to identify VRAM type
2053 if (rinfo
->is_IGP
|| (rinfo
->family
>= CHIP_FAMILY_R300
) ||
2054 (INREG(MEM_SDRAM_MODE_REG
) & (1<<30)))
2055 rinfo
->vram_ddr
= 1;
2057 rinfo
->vram_ddr
= 0;
2059 tmp
= INREG(MEM_CNTL
);
2060 if (IS_R300_VARIANT(rinfo
)) {
2061 tmp
&= R300_MEM_NUM_CHANNELS_MASK
;
2063 case 0: rinfo
->vram_width
= 64; break;
2064 case 1: rinfo
->vram_width
= 128; break;
2065 case 2: rinfo
->vram_width
= 256; break;
2066 default: rinfo
->vram_width
= 128; break;
2068 } else if ((rinfo
->family
== CHIP_FAMILY_RV100
) ||
2069 (rinfo
->family
== CHIP_FAMILY_RS100
) ||
2070 (rinfo
->family
== CHIP_FAMILY_RS200
)){
2071 if (tmp
& RV100_MEM_HALF_MODE
)
2072 rinfo
->vram_width
= 32;
2074 rinfo
->vram_width
= 64;
2076 if (tmp
& MEM_NUM_CHANNELS_MASK
)
2077 rinfo
->vram_width
= 128;
2079 rinfo
->vram_width
= 64;
2082 /* This may not be correct, as some cards can have half of channel disabled
2083 * ToDo: identify these cases
2086 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2087 pci_name(rinfo
->pdev
),
2088 rinfo
->video_ram
/ 1024,
2089 rinfo
->vram_ddr
? "DDR" : "SDRAM",
2097 static ssize_t
radeon_show_one_edid(char *buf
, loff_t off
, size_t count
, const u8
*edid
)
2099 if (off
> EDID_LENGTH
)
2102 if (off
+ count
> EDID_LENGTH
)
2103 count
= EDID_LENGTH
- off
;
2105 memcpy(buf
, edid
+ off
, count
);
2111 static ssize_t
radeon_show_edid1(struct kobject
*kobj
,
2112 struct bin_attribute
*bin_attr
,
2113 char *buf
, loff_t off
, size_t count
)
2115 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
2116 struct pci_dev
*pdev
= to_pci_dev(dev
);
2117 struct fb_info
*info
= pci_get_drvdata(pdev
);
2118 struct radeonfb_info
*rinfo
= info
->par
;
2120 return radeon_show_one_edid(buf
, off
, count
, rinfo
->mon1_EDID
);
2124 static ssize_t
radeon_show_edid2(struct kobject
*kobj
,
2125 struct bin_attribute
*bin_attr
,
2126 char *buf
, loff_t off
, size_t count
)
2128 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
2129 struct pci_dev
*pdev
= to_pci_dev(dev
);
2130 struct fb_info
*info
= pci_get_drvdata(pdev
);
2131 struct radeonfb_info
*rinfo
= info
->par
;
2133 return radeon_show_one_edid(buf
, off
, count
, rinfo
->mon2_EDID
);
2136 static struct bin_attribute edid1_attr
= {
2141 .size
= EDID_LENGTH
,
2142 .read
= radeon_show_edid1
,
2145 static struct bin_attribute edid2_attr
= {
2150 .size
= EDID_LENGTH
,
2151 .read
= radeon_show_edid2
,
2155 static int __devinit
radeonfb_pci_register (struct pci_dev
*pdev
,
2156 const struct pci_device_id
*ent
)
2158 struct fb_info
*info
;
2159 struct radeonfb_info
*rinfo
;
2162 RTRACE("radeonfb_pci_register BEGIN\n");
2164 /* Enable device in PCI config */
2165 ret
= pci_enable_device(pdev
);
2167 printk(KERN_ERR
"radeonfb (%s): Cannot enable PCI device\n",
2172 info
= framebuffer_alloc(sizeof(struct radeonfb_info
), &pdev
->dev
);
2174 printk (KERN_ERR
"radeonfb (%s): could not allocate memory\n",
2183 spin_lock_init(&rinfo
->reg_lock
);
2184 init_timer(&rinfo
->lvds_timer
);
2185 rinfo
->lvds_timer
.function
= radeon_lvds_timer_func
;
2186 rinfo
->lvds_timer
.data
= (unsigned long)rinfo
;
2188 strcpy(rinfo
->name
, "ATI Radeon XX ");
2189 rinfo
->name
[11] = ent
->device
>> 8;
2190 rinfo
->name
[12] = ent
->device
& 0xFF;
2191 rinfo
->family
= ent
->driver_data
& CHIP_FAMILY_MASK
;
2192 rinfo
->chipset
= pdev
->device
;
2193 rinfo
->has_CRTC2
= (ent
->driver_data
& CHIP_HAS_CRTC2
) != 0;
2194 rinfo
->is_mobility
= (ent
->driver_data
& CHIP_IS_MOBILITY
) != 0;
2195 rinfo
->is_IGP
= (ent
->driver_data
& CHIP_IS_IGP
) != 0;
2197 /* Set base addrs */
2198 rinfo
->fb_base_phys
= pci_resource_start (pdev
, 0);
2199 rinfo
->mmio_base_phys
= pci_resource_start (pdev
, 2);
2201 /* request the mem regions */
2202 ret
= pci_request_region(pdev
, 0, "radeonfb framebuffer");
2204 printk( KERN_ERR
"radeonfb (%s): cannot request region 0.\n",
2205 pci_name(rinfo
->pdev
));
2206 goto err_release_fb
;
2209 ret
= pci_request_region(pdev
, 2, "radeonfb mmio");
2211 printk( KERN_ERR
"radeonfb (%s): cannot request region 2.\n",
2212 pci_name(rinfo
->pdev
));
2213 goto err_release_pci0
;
2216 /* map the regions */
2217 rinfo
->mmio_base
= ioremap(rinfo
->mmio_base_phys
, RADEON_REGSIZE
);
2218 if (!rinfo
->mmio_base
) {
2219 printk(KERN_ERR
"radeonfb (%s): cannot map MMIO\n",
2220 pci_name(rinfo
->pdev
));
2222 goto err_release_pci2
;
2225 rinfo
->fb_local_base
= INREG(MC_FB_LOCATION
) << 16;
2231 if (rinfo
->family
== CHIP_FAMILY_R300
&&
2232 (INREG(CONFIG_CNTL
) & CFG_ATI_REV_ID_MASK
)
2234 rinfo
->errata
|= CHIP_ERRATA_R300_CG
;
2236 if (rinfo
->family
== CHIP_FAMILY_RV200
||
2237 rinfo
->family
== CHIP_FAMILY_RS200
)
2238 rinfo
->errata
|= CHIP_ERRATA_PLL_DUMMYREADS
;
2240 if (rinfo
->family
== CHIP_FAMILY_RV100
||
2241 rinfo
->family
== CHIP_FAMILY_RS100
||
2242 rinfo
->family
== CHIP_FAMILY_RS200
)
2243 rinfo
->errata
|= CHIP_ERRATA_PLL_DELAY
;
2245 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2246 /* On PPC, we obtain the OF device-node pointer to the firmware
2247 * data for this chip
2249 rinfo
->of_node
= pci_device_to_OF_node(pdev
);
2250 if (rinfo
->of_node
== NULL
)
2251 printk(KERN_WARNING
"radeonfb (%s): Cannot match card to OF node !\n",
2252 pci_name(rinfo
->pdev
));
2254 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2255 #ifdef CONFIG_PPC_OF
2256 /* On PPC, the firmware sets up a memory mapping that tends
2257 * to cause lockups when enabling the engine. We reconfigure
2258 * the card internal memory mappings properly
2260 fixup_memory_mappings(rinfo
);
2261 #endif /* CONFIG_PPC_OF */
2263 /* Get VRAM size and type */
2264 radeon_identify_vram(rinfo
);
2266 rinfo
->mapped_vram
= min_t(unsigned long, MAX_MAPPED_VRAM
, rinfo
->video_ram
);
2269 rinfo
->fb_base
= ioremap (rinfo
->fb_base_phys
,
2270 rinfo
->mapped_vram
);
2271 } while ( rinfo
->fb_base
== 0 &&
2272 ((rinfo
->mapped_vram
/=2) >= MIN_MAPPED_VRAM
) );
2274 if (rinfo
->fb_base
== NULL
) {
2275 printk (KERN_ERR
"radeonfb (%s): cannot map FB\n",
2276 pci_name(rinfo
->pdev
));
2281 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo
->pdev
),
2282 rinfo
->mapped_vram
/1024);
2285 * Map the BIOS ROM if any and retrieve PLL parameters from
2286 * the BIOS. We skip that on mobility chips as the real panel
2287 * values we need aren't in the ROM but in the BIOS image in
2288 * memory. This is definitely not the best meacnism though,
2289 * we really need the arch code to tell us which is the "primary"
2290 * video adapter to use the memory image (or better, the arch
2291 * should provide us a copy of the BIOS image to shield us from
2292 * archs who would store that elsewhere and/or could initialize
2293 * more than one adapter during boot).
2295 if (!rinfo
->is_mobility
)
2296 radeon_map_ROM(rinfo
, pdev
);
2299 * On x86, the primary display on laptop may have it's BIOS
2300 * ROM elsewhere, try to locate it at the legacy memory hole.
2301 * We probably need to make sure this is the primary display,
2302 * but that is difficult without some arch support.
2305 if (rinfo
->bios_seg
== NULL
)
2306 radeon_find_mem_vbios(rinfo
);
2309 /* If both above failed, try the BIOS ROM again for mobility
2312 if (rinfo
->bios_seg
== NULL
&& rinfo
->is_mobility
)
2313 radeon_map_ROM(rinfo
, pdev
);
2315 /* Get informations about the board's PLL */
2316 radeon_get_pllinfo(rinfo
);
2318 #ifdef CONFIG_FB_RADEON_I2C
2319 /* Register I2C bus */
2320 radeon_create_i2c_busses(rinfo
);
2323 /* set all the vital stuff */
2324 radeon_set_fbinfo (rinfo
);
2326 /* Probe screen types */
2327 radeon_probe_screens(rinfo
, monitor_layout
, ignore_edid
);
2329 /* Build mode list, check out panel native model */
2330 radeon_check_modes(rinfo
, mode_option
);
2332 /* Register some sysfs stuff (should be done better) */
2333 if (rinfo
->mon1_EDID
)
2334 sysfs_create_bin_file(&rinfo
->pdev
->dev
.kobj
, &edid1_attr
);
2335 if (rinfo
->mon2_EDID
)
2336 sysfs_create_bin_file(&rinfo
->pdev
->dev
.kobj
, &edid2_attr
);
2338 /* save current mode regs before we switch into the new one
2339 * so we can restore this upon __exit
2341 radeon_save_state (rinfo
, &rinfo
->init_state
);
2342 memcpy(&rinfo
->state
, &rinfo
->init_state
, sizeof(struct radeon_regs
));
2344 /* Setup Power Management capabilities */
2345 if (default_dynclk
< -1) {
2346 /* -2 is special: means ON on mobility chips and do not
2349 radeonfb_pm_init(rinfo
, rinfo
->is_mobility
? 1 : -1, ignore_devlist
, force_sleep
);
2351 radeonfb_pm_init(rinfo
, default_dynclk
, ignore_devlist
, force_sleep
);
2353 pci_set_drvdata(pdev
, info
);
2355 /* Register with fbdev layer */
2356 ret
= register_framebuffer(info
);
2358 printk (KERN_ERR
"radeonfb (%s): could not register framebuffer\n",
2359 pci_name(rinfo
->pdev
));
2364 rinfo
->mtrr_hdl
= nomtrr
? -1 : mtrr_add(rinfo
->fb_base_phys
,
2366 MTRR_TYPE_WRCOMB
, 1);
2370 radeonfb_bl_init(rinfo
);
2372 printk ("radeonfb (%s): %s\n", pci_name(rinfo
->pdev
), rinfo
->name
);
2374 if (rinfo
->bios_seg
)
2375 radeon_unmap_ROM(rinfo
, pdev
);
2376 RTRACE("radeonfb_pci_register END\n");
2380 iounmap(rinfo
->fb_base
);
2382 kfree(rinfo
->mon1_EDID
);
2383 kfree(rinfo
->mon2_EDID
);
2384 if (rinfo
->mon1_modedb
)
2385 fb_destroy_modedb(rinfo
->mon1_modedb
);
2386 fb_dealloc_cmap(&info
->cmap
);
2387 #ifdef CONFIG_FB_RADEON_I2C
2388 radeon_delete_i2c_busses(rinfo
);
2390 if (rinfo
->bios_seg
)
2391 radeon_unmap_ROM(rinfo
, pdev
);
2392 iounmap(rinfo
->mmio_base
);
2394 pci_release_region(pdev
, 2);
2396 pci_release_region(pdev
, 0);
2398 framebuffer_release(info
);
2406 static void __devexit
radeonfb_pci_unregister (struct pci_dev
*pdev
)
2408 struct fb_info
*info
= pci_get_drvdata(pdev
);
2409 struct radeonfb_info
*rinfo
= info
->par
;
2414 radeonfb_pm_exit(rinfo
);
2416 if (rinfo
->mon1_EDID
)
2417 sysfs_remove_bin_file(&rinfo
->pdev
->dev
.kobj
, &edid1_attr
);
2418 if (rinfo
->mon2_EDID
)
2419 sysfs_remove_bin_file(&rinfo
->pdev
->dev
.kobj
, &edid2_attr
);
2422 /* restore original state
2424 * Doesn't quite work yet, I suspect if we come from a legacy
2425 * VGA mode (or worse, text mode), we need to do some VGA black
2426 * magic here that I know nothing about. --BenH
2428 radeon_write_mode (rinfo
, &rinfo
->init_state
, 1);
2431 del_timer_sync(&rinfo
->lvds_timer
);
2434 if (rinfo
->mtrr_hdl
>= 0)
2435 mtrr_del(rinfo
->mtrr_hdl
, 0, 0);
2438 unregister_framebuffer(info
);
2440 radeonfb_bl_exit(rinfo
);
2442 iounmap(rinfo
->mmio_base
);
2443 iounmap(rinfo
->fb_base
);
2445 pci_release_region(pdev
, 2);
2446 pci_release_region(pdev
, 0);
2448 kfree(rinfo
->mon1_EDID
);
2449 kfree(rinfo
->mon2_EDID
);
2450 if (rinfo
->mon1_modedb
)
2451 fb_destroy_modedb(rinfo
->mon1_modedb
);
2452 #ifdef CONFIG_FB_RADEON_I2C
2453 radeon_delete_i2c_busses(rinfo
);
2455 fb_dealloc_cmap(&info
->cmap
);
2456 framebuffer_release(info
);
2460 static struct pci_driver radeonfb_driver
= {
2462 .id_table
= radeonfb_pci_table
,
2463 .probe
= radeonfb_pci_register
,
2464 .remove
= __devexit_p(radeonfb_pci_unregister
),
2466 .suspend
= radeonfb_pci_suspend
,
2467 .resume
= radeonfb_pci_resume
,
2468 #endif /* CONFIG_PM */
2472 static int __init
radeonfb_setup (char *options
)
2476 if (!options
|| !*options
)
2479 while ((this_opt
= strsep (&options
, ",")) != NULL
) {
2483 if (!strncmp(this_opt
, "noaccel", 7)) {
2485 } else if (!strncmp(this_opt
, "mirror", 6)) {
2487 } else if (!strncmp(this_opt
, "force_dfp", 9)) {
2489 } else if (!strncmp(this_opt
, "panel_yres:", 11)) {
2490 panel_yres
= simple_strtoul((this_opt
+11), NULL
, 0);
2491 } else if (!strncmp(this_opt
, "backlight:", 10)) {
2492 backlight
= simple_strtoul(this_opt
+10, NULL
, 0);
2494 } else if (!strncmp(this_opt
, "nomtrr", 6)) {
2497 } else if (!strncmp(this_opt
, "nomodeset", 9)) {
2499 } else if (!strncmp(this_opt
, "force_measure_pll", 17)) {
2500 force_measure_pll
= 1;
2501 } else if (!strncmp(this_opt
, "ignore_edid", 11)) {
2503 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2504 } else if (!strncmp(this_opt
, "force_sleep", 11)) {
2506 } else if (!strncmp(this_opt
, "ignore_devlist", 14)) {
2510 mode_option
= this_opt
;
2516 static int __init
radeonfb_init (void)
2519 char *option
= NULL
;
2521 if (fb_get_options("radeonfb", &option
))
2523 radeonfb_setup(option
);
2525 return pci_register_driver (&radeonfb_driver
);
2529 static void __exit
radeonfb_exit (void)
2531 pci_unregister_driver (&radeonfb_driver
);
2534 module_init(radeonfb_init
);
2535 module_exit(radeonfb_exit
);
2537 MODULE_AUTHOR("Ani Joshi");
2538 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2539 MODULE_LICENSE("GPL");
2540 module_param(noaccel
, bool, 0);
2541 module_param(default_dynclk
, int, 0);
2542 MODULE_PARM_DESC(default_dynclk
, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2543 MODULE_PARM_DESC(noaccel
, "bool: disable acceleration");
2544 module_param(nomodeset
, bool, 0);
2545 MODULE_PARM_DESC(nomodeset
, "bool: disable actual setting of video mode");
2546 module_param(mirror
, bool, 0);
2547 MODULE_PARM_DESC(mirror
, "bool: mirror the display to both monitors");
2548 module_param(force_dfp
, bool, 0);
2549 MODULE_PARM_DESC(force_dfp
, "bool: force display to dfp");
2550 module_param(ignore_edid
, bool, 0);
2551 MODULE_PARM_DESC(ignore_edid
, "bool: Ignore EDID data when doing DDC probe");
2552 module_param(monitor_layout
, charp
, 0);
2553 MODULE_PARM_DESC(monitor_layout
, "Specify monitor mapping (like XFree86)");
2554 module_param(force_measure_pll
, bool, 0);
2555 MODULE_PARM_DESC(force_measure_pll
, "Force measurement of PLL (debug)");
2557 module_param(nomtrr
, bool, 0);
2558 MODULE_PARM_DESC(nomtrr
, "bool: disable use of MTRR registers");
2560 module_param(panel_yres
, int, 0);
2561 MODULE_PARM_DESC(panel_yres
, "int: set panel yres");
2562 module_param(mode_option
, charp
, 0);
2563 MODULE_PARM_DESC(mode_option
, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2564 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2565 module_param(force_sleep
, bool, 0);
2566 MODULE_PARM_DESC(force_sleep
, "bool: force D2 sleep mode on all hardware");
2567 module_param(ignore_devlist
, bool, 0);
2568 MODULE_PARM_DESC(ignore_devlist
, "bool: ignore workarounds for bugs in specific laptops");