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regression: cifs endianness bug
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / ata / ata_piix.c
blobb538e1d22bf24c878c2debfc23cc0039f2e7bc45
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
95
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
98
99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */
104
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108
109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* controller IDs */
122 piix_pata_mwdma = 0, /* PIIX3 MWDMA only */
123 piix_pata_33, /* PIIX4 at 33Mhz */
124 ich_pata_33, /* ICH up to UDMA 33 only */
125 ich_pata_66, /* ICH up to 66 Mhz */
126 ich_pata_100, /* ICH up to UDMA 100 */
127 ich5_sata,
128 ich6_sata,
129 ich6_sata_ahci,
130 ich6m_sata_ahci,
131 ich8_sata_ahci,
132 ich8_2port_sata,
133 ich8m_apple_sata_ahci, /* locks up on second port enable */
134 tolapai_sata_ahci,
135
136 /* constants for mapping table */
137 P0 = 0, /* port 0 */
138 P1 = 1, /* port 1 */
139 P2 = 2, /* port 2 */
140 P3 = 3, /* port 3 */
141 IDE = -1, /* IDE */
142 NA = -2, /* not avaliable */
143 RV = -3, /* reserved */
144
145 PIIX_AHCI_DEVICE = 6,
146
147 /* host->flags bits */
148 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
149 };
150
151 struct piix_map_db {
152 const u32 mask;
153 const u16 port_enable;
154 const int map[][4];
155 };
156
157 struct piix_host_priv {
158 const int *map;
159 };
160
161 static int piix_init_one(struct pci_dev *pdev,
162 const struct pci_device_id *ent);
163 static void piix_pata_error_handler(struct ata_port *ap);
164 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
165 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
166 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
167 static int ich_pata_cable_detect(struct ata_port *ap);
168 #ifdef CONFIG_PM
169 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
170 static int piix_pci_device_resume(struct pci_dev *pdev);
171 #endif
172
173 static unsigned int in_module_init = 1;
174
175 static const struct pci_device_id piix_pci_tbl[] = {
176 /* Intel PIIX3 for the 430HX etc */
177 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
178 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
179 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
180 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 /* Intel PIIX4 */
182 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel PIIX4 */
184 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
185 /* Intel PIIX */
186 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
187 /* Intel ICH (i810, i815, i840) UDMA 66*/
188 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
189 /* Intel ICH0 : UDMA 33*/
190 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
191 /* Intel ICH2M */
192 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
194 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH3M */
196 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH3 (E7500/1) UDMA 100 */
198 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
200 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* Intel ICH5 */
203 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* C-ICH (i810E2) */
205 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
207 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* ICH6 (and 6) (i915) UDMA 100 */
209 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* ICH7/7-R (i945, i975) UDMA 100*/
211 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* ICH8 Mobile PATA Controller */
214 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215
216 /* NOTE: The following PCI ids must be kept in sync with the
217 * list in drivers/pci/quirks.c.
218 */
219
220 /* 82801EB (ICH5) */
221 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
222 /* 82801EB (ICH5) */
223 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
224 /* 6300ESB (ICH5 variant with broken PCS present bits) */
225 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
226 /* 6300ESB pretending RAID */
227 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
228 /* 82801FB/FW (ICH6/ICH6W) */
229 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
230 /* 82801FR/FRW (ICH6R/ICH6RW) */
231 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
232 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
233 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
234 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
235 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
236 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
237 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
238 /* Enterprise Southbridge 2 (631xESB/632xESB) */
239 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
240 /* SATA Controller 1 IDE (ICH8) */
241 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
242 /* SATA Controller 2 IDE (ICH8) */
243 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
244 /* Mobile SATA Controller IDE (ICH8M) */
245 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
246 /* Mobile SATA Controller IDE (ICH8M), Apple */
247 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
248 /* SATA Controller IDE (ICH9) */
249 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
250 /* SATA Controller IDE (ICH9) */
251 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* SATA Controller IDE (ICH9) */
253 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
254 /* SATA Controller IDE (ICH9M) */
255 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256 /* SATA Controller IDE (ICH9M) */
257 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
258 /* SATA Controller IDE (ICH9M) */
259 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
260 /* SATA Controller IDE (Tolapai) */
261 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
262
263 { } /* terminate list */
264 };
265
266 static struct pci_driver piix_pci_driver = {
267 .name = DRV_NAME,
268 .id_table = piix_pci_tbl,
269 .probe = piix_init_one,
270 .remove = ata_pci_remove_one,
271 #ifdef CONFIG_PM
272 .suspend = piix_pci_device_suspend,
273 .resume = piix_pci_device_resume,
274 #endif
275 };
276
277 static struct scsi_host_template piix_sht = {
278 .module = THIS_MODULE,
279 .name = DRV_NAME,
280 .ioctl = ata_scsi_ioctl,
281 .queuecommand = ata_scsi_queuecmd,
282 .can_queue = ATA_DEF_QUEUE,
283 .this_id = ATA_SHT_THIS_ID,
284 .sg_tablesize = LIBATA_MAX_PRD,
285 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
286 .emulated = ATA_SHT_EMULATED,
287 .use_clustering = ATA_SHT_USE_CLUSTERING,
288 .proc_name = DRV_NAME,
289 .dma_boundary = ATA_DMA_BOUNDARY,
290 .slave_configure = ata_scsi_slave_config,
291 .slave_destroy = ata_scsi_slave_destroy,
292 .bios_param = ata_std_bios_param,
293 };
294
295 static const struct ata_port_operations piix_pata_ops = {
296 .set_piomode = piix_set_piomode,
297 .set_dmamode = piix_set_dmamode,
298 .mode_filter = ata_pci_default_filter,
299
300 .tf_load = ata_tf_load,
301 .tf_read = ata_tf_read,
302 .check_status = ata_check_status,
303 .exec_command = ata_exec_command,
304 .dev_select = ata_std_dev_select,
305
306 .bmdma_setup = ata_bmdma_setup,
307 .bmdma_start = ata_bmdma_start,
308 .bmdma_stop = ata_bmdma_stop,
309 .bmdma_status = ata_bmdma_status,
310 .qc_prep = ata_qc_prep,
311 .qc_issue = ata_qc_issue_prot,
312 .data_xfer = ata_data_xfer,
313
314 .freeze = ata_bmdma_freeze,
315 .thaw = ata_bmdma_thaw,
316 .error_handler = piix_pata_error_handler,
317 .post_internal_cmd = ata_bmdma_post_internal_cmd,
318 .cable_detect = ata_cable_40wire,
319
320 .irq_handler = ata_interrupt,
321 .irq_clear = ata_bmdma_irq_clear,
322 .irq_on = ata_irq_on,
323
324 .port_start = ata_port_start,
325 };
326
327 static const struct ata_port_operations ich_pata_ops = {
328 .set_piomode = piix_set_piomode,
329 .set_dmamode = ich_set_dmamode,
330 .mode_filter = ata_pci_default_filter,
331
332 .tf_load = ata_tf_load,
333 .tf_read = ata_tf_read,
334 .check_status = ata_check_status,
335 .exec_command = ata_exec_command,
336 .dev_select = ata_std_dev_select,
337
338 .bmdma_setup = ata_bmdma_setup,
339 .bmdma_start = ata_bmdma_start,
340 .bmdma_stop = ata_bmdma_stop,
341 .bmdma_status = ata_bmdma_status,
342 .qc_prep = ata_qc_prep,
343 .qc_issue = ata_qc_issue_prot,
344 .data_xfer = ata_data_xfer,
345
346 .freeze = ata_bmdma_freeze,
347 .thaw = ata_bmdma_thaw,
348 .error_handler = piix_pata_error_handler,
349 .post_internal_cmd = ata_bmdma_post_internal_cmd,
350 .cable_detect = ich_pata_cable_detect,
351
352 .irq_handler = ata_interrupt,
353 .irq_clear = ata_bmdma_irq_clear,
354 .irq_on = ata_irq_on,
355
356 .port_start = ata_port_start,
357 };
358
359 static const struct ata_port_operations piix_sata_ops = {
360 .tf_load = ata_tf_load,
361 .tf_read = ata_tf_read,
362 .check_status = ata_check_status,
363 .exec_command = ata_exec_command,
364 .dev_select = ata_std_dev_select,
365
366 .bmdma_setup = ata_bmdma_setup,
367 .bmdma_start = ata_bmdma_start,
368 .bmdma_stop = ata_bmdma_stop,
369 .bmdma_status = ata_bmdma_status,
370 .qc_prep = ata_qc_prep,
371 .qc_issue = ata_qc_issue_prot,
372 .data_xfer = ata_data_xfer,
373
374 .freeze = ata_bmdma_freeze,
375 .thaw = ata_bmdma_thaw,
376 .error_handler = ata_bmdma_error_handler,
377 .post_internal_cmd = ata_bmdma_post_internal_cmd,
378
379 .irq_handler = ata_interrupt,
380 .irq_clear = ata_bmdma_irq_clear,
381 .irq_on = ata_irq_on,
382
383 .port_start = ata_port_start,
384 };
385
386 static const struct piix_map_db ich5_map_db = {
387 .mask = 0x7,
388 .port_enable = 0x3,
389 .map = {
390 /* PM PS SM SS MAP */
391 { P0, NA, P1, NA }, /* 000b */
392 { P1, NA, P0, NA }, /* 001b */
393 { RV, RV, RV, RV },
394 { RV, RV, RV, RV },
395 { P0, P1, IDE, IDE }, /* 100b */
396 { P1, P0, IDE, IDE }, /* 101b */
397 { IDE, IDE, P0, P1 }, /* 110b */
398 { IDE, IDE, P1, P0 }, /* 111b */
399 },
400 };
401
402 static const struct piix_map_db ich6_map_db = {
403 .mask = 0x3,
404 .port_enable = 0xf,
405 .map = {
406 /* PM PS SM SS MAP */
407 { P0, P2, P1, P3 }, /* 00b */
408 { IDE, IDE, P1, P3 }, /* 01b */
409 { P0, P2, IDE, IDE }, /* 10b */
410 { RV, RV, RV, RV },
411 },
412 };
413
414 static const struct piix_map_db ich6m_map_db = {
415 .mask = 0x3,
416 .port_enable = 0x5,
417
418 /* Map 01b isn't specified in the doc but some notebooks use
419 * it anyway. MAP 01b have been spotted on both ICH6M and
420 * ICH7M.
421 */
422 .map = {
423 /* PM PS SM SS MAP */
424 { P0, P2, NA, NA }, /* 00b */
425 { IDE, IDE, P1, P3 }, /* 01b */
426 { P0, P2, IDE, IDE }, /* 10b */
427 { RV, RV, RV, RV },
428 },
429 };
430
431 static const struct piix_map_db ich8_map_db = {
432 .mask = 0x3,
433 .port_enable = 0xf,
434 .map = {
435 /* PM PS SM SS MAP */
436 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
437 { RV, RV, RV, RV },
438 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
439 { RV, RV, RV, RV },
440 },
441 };
442
443 static const struct piix_map_db ich8_2port_map_db = {
444 .mask = 0x3,
445 .port_enable = 0x3,
446 .map = {
447 /* PM PS SM SS MAP */
448 { P0, NA, P1, NA }, /* 00b */
449 { RV, RV, RV, RV }, /* 01b */
450 { RV, RV, RV, RV }, /* 10b */
451 { RV, RV, RV, RV },
452 },
453 };
454
455 static const struct piix_map_db ich8m_apple_map_db = {
456 .mask = 0x3,
457 .port_enable = 0x1,
458 .map = {
459 /* PM PS SM SS MAP */
460 { P0, NA, NA, NA }, /* 00b */
461 { RV, RV, RV, RV },
462 { P0, P2, IDE, IDE }, /* 10b */
463 { RV, RV, RV, RV },
464 },
465 };
466
467 static const struct piix_map_db tolapai_map_db = {
468 .mask = 0x3,
469 .port_enable = 0x3,
470 .map = {
471 /* PM PS SM SS MAP */
472 { P0, NA, P1, NA }, /* 00b */
473 { RV, RV, RV, RV }, /* 01b */
474 { RV, RV, RV, RV }, /* 10b */
475 { RV, RV, RV, RV },
476 },
477 };
478
479 static const struct piix_map_db *piix_map_db_table[] = {
480 [ich5_sata] = &ich5_map_db,
481 [ich6_sata] = &ich6_map_db,
482 [ich6_sata_ahci] = &ich6_map_db,
483 [ich6m_sata_ahci] = &ich6m_map_db,
484 [ich8_sata_ahci] = &ich8_map_db,
485 [ich8_2port_sata] = &ich8_2port_map_db,
486 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
487 [tolapai_sata_ahci] = &tolapai_map_db,
488 };
489
490 static struct ata_port_info piix_port_info[] = {
491 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
492 {
493 .sht = &piix_sht,
494 .flags = PIIX_PATA_FLAGS,
495 .pio_mask = 0x1f, /* pio0-4 */
496 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
497 .port_ops = &piix_pata_ops,
498 },
499
500 [piix_pata_33] = /* PIIX4 at 33MHz */
501 {
502 .sht = &piix_sht,
503 .flags = PIIX_PATA_FLAGS,
504 .pio_mask = 0x1f, /* pio0-4 */
505 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
506 .udma_mask = ATA_UDMA_MASK_40C,
507 .port_ops = &piix_pata_ops,
508 },
509
510 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
511 {
512 .sht = &piix_sht,
513 .flags = PIIX_PATA_FLAGS,
514 .pio_mask = 0x1f, /* pio 0-4 */
515 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
516 .udma_mask = ATA_UDMA2, /* UDMA33 */
517 .port_ops = &ich_pata_ops,
518 },
519
520 [ich_pata_66] = /* ICH controllers up to 66MHz */
521 {
522 .sht = &piix_sht,
523 .flags = PIIX_PATA_FLAGS,
524 .pio_mask = 0x1f, /* pio 0-4 */
525 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
526 .udma_mask = ATA_UDMA4,
527 .port_ops = &ich_pata_ops,
528 },
529
530 [ich_pata_100] =
531 {
532 .sht = &piix_sht,
533 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
534 .pio_mask = 0x1f, /* pio0-4 */
535 .mwdma_mask = 0x06, /* mwdma1-2 */
536 .udma_mask = ATA_UDMA5, /* udma0-5 */
537 .port_ops = &ich_pata_ops,
538 },
539
540 [ich5_sata] =
541 {
542 .sht = &piix_sht,
543 .flags = PIIX_SATA_FLAGS,
544 .pio_mask = 0x1f, /* pio0-4 */
545 .mwdma_mask = 0x07, /* mwdma0-2 */
546 .udma_mask = ATA_UDMA6,
547 .port_ops = &piix_sata_ops,
548 },
549
550 [ich6_sata] =
551 {
552 .sht = &piix_sht,
553 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
554 .pio_mask = 0x1f, /* pio0-4 */
555 .mwdma_mask = 0x07, /* mwdma0-2 */
556 .udma_mask = ATA_UDMA6,
557 .port_ops = &piix_sata_ops,
558 },
559
560 [ich6_sata_ahci] =
561 {
562 .sht = &piix_sht,
563 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
564 PIIX_FLAG_AHCI,
565 .pio_mask = 0x1f, /* pio0-4 */
566 .mwdma_mask = 0x07, /* mwdma0-2 */
567 .udma_mask = ATA_UDMA6,
568 .port_ops = &piix_sata_ops,
569 },
570
571 [ich6m_sata_ahci] =
572 {
573 .sht = &piix_sht,
574 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
575 PIIX_FLAG_AHCI,
576 .pio_mask = 0x1f, /* pio0-4 */
577 .mwdma_mask = 0x07, /* mwdma0-2 */
578 .udma_mask = ATA_UDMA6,
579 .port_ops = &piix_sata_ops,
580 },
581
582 [ich8_sata_ahci] =
583 {
584 .sht = &piix_sht,
585 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
586 PIIX_FLAG_AHCI,
587 .pio_mask = 0x1f, /* pio0-4 */
588 .mwdma_mask = 0x07, /* mwdma0-2 */
589 .udma_mask = ATA_UDMA6,
590 .port_ops = &piix_sata_ops,
591 },
592
593 [ich8_2port_sata] =
594 {
595 .sht = &piix_sht,
596 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
597 PIIX_FLAG_AHCI,
598 .pio_mask = 0x1f, /* pio0-4 */
599 .mwdma_mask = 0x07, /* mwdma0-2 */
600 .udma_mask = ATA_UDMA6,
601 .port_ops = &piix_sata_ops,
602 },
603
604 [tolapai_sata_ahci] =
605 {
606 .sht = &piix_sht,
607 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
608 PIIX_FLAG_AHCI,
609 .pio_mask = 0x1f, /* pio0-4 */
610 .mwdma_mask = 0x07, /* mwdma0-2 */
611 .udma_mask = ATA_UDMA6,
612 .port_ops = &piix_sata_ops,
613 },
614
615 [ich8m_apple_sata_ahci] =
616 {
617 .sht = &piix_sht,
618 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
619 PIIX_FLAG_AHCI,
620 .pio_mask = 0x1f, /* pio0-4 */
621 .mwdma_mask = 0x07, /* mwdma0-2 */
622 .udma_mask = ATA_UDMA6,
623 .port_ops = &piix_sata_ops,
624 },
625
626 };
627
628 static struct pci_bits piix_enable_bits[] = {
629 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
630 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
631 };
632
633 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
634 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
635 MODULE_LICENSE("GPL");
636 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
637 MODULE_VERSION(DRV_VERSION);
638
639 struct ich_laptop {
640 u16 device;
641 u16 subvendor;
642 u16 subdevice;
643 };
644
645 /*
646 * List of laptops that use short cables rather than 80 wire
647 */
648
649 static const struct ich_laptop ich_laptop[] = {
650 /* devid, subvendor, subdev */
651 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
652 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
653 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
654 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
655 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
656 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
657 /* end marker */
658 { 0, }
659 };
660
661 /**
662 * ich_pata_cable_detect - Probe host controller cable detect info
663 * @ap: Port for which cable detect info is desired
664 *
665 * Read 80c cable indicator from ATA PCI device's PCI config
666 * register. This register is normally set by firmware (BIOS).
667 *
668 * LOCKING:
669 * None (inherited from caller).
670 */
671
672 static int ich_pata_cable_detect(struct ata_port *ap)
673 {
674 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
675 const struct ich_laptop *lap = &ich_laptop[0];
676 u8 tmp, mask;
677
678 /* Check for specials - Acer Aspire 5602WLMi */
679 while (lap->device) {
680 if (lap->device == pdev->device &&
681 lap->subvendor == pdev->subsystem_vendor &&
682 lap->subdevice == pdev->subsystem_device)
683 return ATA_CBL_PATA40_SHORT;
684
685 lap++;
686 }
687
688 /* check BIOS cable detect results */
689 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
690 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
691 if ((tmp & mask) == 0)
692 return ATA_CBL_PATA40;
693 return ATA_CBL_PATA80;
694 }
695
696 /**
697 * piix_pata_prereset - prereset for PATA host controller
698 * @link: Target link
699 * @deadline: deadline jiffies for the operation
700 *
701 * LOCKING:
702 * None (inherited from caller).
703 */
704 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
705 {
706 struct ata_port *ap = link->ap;
707 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
708
709 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
710 return -ENOENT;
711 return ata_std_prereset(link, deadline);
712 }
713
714 static void piix_pata_error_handler(struct ata_port *ap)
715 {
716 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
717 ata_std_postreset);
718 }
719
720 /**
721 * piix_set_piomode - Initialize host controller PATA PIO timings
722 * @ap: Port whose timings we are configuring
723 * @adev: um
724 *
725 * Set PIO mode for device, in host controller PCI config space.
726 *
727 * LOCKING:
728 * None (inherited from caller).
729 */
730
731 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
732 {
733 unsigned int pio = adev->pio_mode - XFER_PIO_0;
734 struct pci_dev *dev = to_pci_dev(ap->host->dev);
735 unsigned int is_slave = (adev->devno != 0);
736 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
737 unsigned int slave_port = 0x44;
738 u16 master_data;
739 u8 slave_data;
740 u8 udma_enable;
741 int control = 0;
742
743 /*
744 * See Intel Document 298600-004 for the timing programing rules
745 * for ICH controllers.
746 */
747
748 static const /* ISP RTC */
749 u8 timings[][2] = { { 0, 0 },
750 { 0, 0 },
751 { 1, 0 },
752 { 2, 1 },
753 { 2, 3 }, };
754
755 if (pio >= 2)
756 control |= 1; /* TIME1 enable */
757 if (ata_pio_need_iordy(adev))
758 control |= 2; /* IE enable */
759
760 /* Intel specifies that the PPE functionality is for disk only */
761 if (adev->class == ATA_DEV_ATA)
762 control |= 4; /* PPE enable */
763
764 /* PIO configuration clears DTE unconditionally. It will be
765 * programmed in set_dmamode which is guaranteed to be called
766 * after set_piomode if any DMA mode is available.
767 */
768 pci_read_config_word(dev, master_port, &master_data);
769 if (is_slave) {
770 /* clear TIME1|IE1|PPE1|DTE1 */
771 master_data &= 0xff0f;
772 /* Enable SITRE (seperate slave timing register) */
773 master_data |= 0x4000;
774 /* enable PPE1, IE1 and TIME1 as needed */
775 master_data |= (control << 4);
776 pci_read_config_byte(dev, slave_port, &slave_data);
777 slave_data &= (ap->port_no ? 0x0f : 0xf0);
778 /* Load the timing nibble for this slave */
779 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
780 << (ap->port_no ? 4 : 0);
781 } else {
782 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
783 master_data &= 0xccf0;
784 /* Enable PPE, IE and TIME as appropriate */
785 master_data |= control;
786 /* load ISP and RCT */
787 master_data |=
788 (timings[pio][0] << 12) |
789 (timings[pio][1] << 8);
790 }
791 pci_write_config_word(dev, master_port, master_data);
792 if (is_slave)
793 pci_write_config_byte(dev, slave_port, slave_data);
794
795 /* Ensure the UDMA bit is off - it will be turned back on if
796 UDMA is selected */
797
798 if (ap->udma_mask) {
799 pci_read_config_byte(dev, 0x48, &udma_enable);
800 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
801 pci_write_config_byte(dev, 0x48, udma_enable);
802 }
803 }
804
805 /**
806 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
807 * @ap: Port whose timings we are configuring
808 * @adev: Drive in question
809 * @udma: udma mode, 0 - 6
810 * @isich: set if the chip is an ICH device
811 *
812 * Set UDMA mode for device, in host controller PCI config space.
813 *
814 * LOCKING:
815 * None (inherited from caller).
816 */
817
818 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
819 {
820 struct pci_dev *dev = to_pci_dev(ap->host->dev);
821 u8 master_port = ap->port_no ? 0x42 : 0x40;
822 u16 master_data;
823 u8 speed = adev->dma_mode;
824 int devid = adev->devno + 2 * ap->port_no;
825 u8 udma_enable = 0;
826
827 static const /* ISP RTC */
828 u8 timings[][2] = { { 0, 0 },
829 { 0, 0 },
830 { 1, 0 },
831 { 2, 1 },
832 { 2, 3 }, };
833
834 pci_read_config_word(dev, master_port, &master_data);
835 if (ap->udma_mask)
836 pci_read_config_byte(dev, 0x48, &udma_enable);
837
838 if (speed >= XFER_UDMA_0) {
839 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
840 u16 udma_timing;
841 u16 ideconf;
842 int u_clock, u_speed;
843
844 /*
845 * UDMA is handled by a combination of clock switching and
846 * selection of dividers
847 *
848 * Handy rule: Odd modes are UDMATIMx 01, even are 02
849 * except UDMA0 which is 00
850 */
851 u_speed = min(2 - (udma & 1), udma);
852 if (udma == 5)
853 u_clock = 0x1000; /* 100Mhz */
854 else if (udma > 2)
855 u_clock = 1; /* 66Mhz */
856 else
857 u_clock = 0; /* 33Mhz */
858
859 udma_enable |= (1 << devid);
860
861 /* Load the CT/RP selection */
862 pci_read_config_word(dev, 0x4A, &udma_timing);
863 udma_timing &= ~(3 << (4 * devid));
864 udma_timing |= u_speed << (4 * devid);
865 pci_write_config_word(dev, 0x4A, udma_timing);
866
867 if (isich) {
868 /* Select a 33/66/100Mhz clock */
869 pci_read_config_word(dev, 0x54, &ideconf);
870 ideconf &= ~(0x1001 << devid);
871 ideconf |= u_clock << devid;
872 /* For ICH or later we should set bit 10 for better
873 performance (WR_PingPong_En) */
874 pci_write_config_word(dev, 0x54, ideconf);
875 }
876 } else {
877 /*
878 * MWDMA is driven by the PIO timings. We must also enable
879 * IORDY unconditionally along with TIME1. PPE has already
880 * been set when the PIO timing was set.
881 */
882 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
883 unsigned int control;
884 u8 slave_data;
885 const unsigned int needed_pio[3] = {
886 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
887 };
888 int pio = needed_pio[mwdma] - XFER_PIO_0;
889
890 control = 3; /* IORDY|TIME1 */
891
892 /* If the drive MWDMA is faster than it can do PIO then
893 we must force PIO into PIO0 */
894
895 if (adev->pio_mode < needed_pio[mwdma])
896 /* Enable DMA timing only */
897 control |= 8; /* PIO cycles in PIO0 */
898
899 if (adev->devno) { /* Slave */
900 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
901 master_data |= control << 4;
902 pci_read_config_byte(dev, 0x44, &slave_data);
903 slave_data &= (ap->port_no ? 0x0f : 0xf0);
904 /* Load the matching timing */
905 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
906 pci_write_config_byte(dev, 0x44, slave_data);
907 } else { /* Master */
908 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
909 and master timing bits */
910 master_data |= control;
911 master_data |=
912 (timings[pio][0] << 12) |
913 (timings[pio][1] << 8);
914 }
915
916 if (ap->udma_mask) {
917 udma_enable &= ~(1 << devid);
918 pci_write_config_word(dev, master_port, master_data);
919 }
920 }
921 /* Don't scribble on 0x48 if the controller does not support UDMA */
922 if (ap->udma_mask)
923 pci_write_config_byte(dev, 0x48, udma_enable);
924 }
925
926 /**
927 * piix_set_dmamode - Initialize host controller PATA DMA timings
928 * @ap: Port whose timings we are configuring
929 * @adev: um
930 *
931 * Set MW/UDMA mode for device, in host controller PCI config space.
932 *
933 * LOCKING:
934 * None (inherited from caller).
935 */
936
937 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
938 {
939 do_pata_set_dmamode(ap, adev, 0);
940 }
941
942 /**
943 * ich_set_dmamode - Initialize host controller PATA DMA timings
944 * @ap: Port whose timings we are configuring
945 * @adev: um
946 *
947 * Set MW/UDMA mode for device, in host controller PCI config space.
948 *
949 * LOCKING:
950 * None (inherited from caller).
951 */
952
953 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
954 {
955 do_pata_set_dmamode(ap, adev, 1);
956 }
957
958 #ifdef CONFIG_PM
959 static int piix_broken_suspend(void)
960 {
961 static const struct dmi_system_id sysids[] = {
962 {
963 .ident = "TECRA M3",
964 .matches = {
965 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
966 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
967 },
968 },
969 {
970 .ident = "TECRA M3",
971 .matches = {
972 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
974 },
975 },
976 {
977 .ident = "TECRA M5",
978 .matches = {
979 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
981 },
982 },
983 {
984 .ident = "TECRA M7",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
988 },
989 },
990 {
991 .ident = "TECRA A8",
992 .matches = {
993 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
994 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
995 },
996 },
997 {
998 .ident = "Satellite R25",
999 .matches = {
1000 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1001 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1002 },
1003 },
1004 {
1005 .ident = "Satellite U200",
1006 .matches = {
1007 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1008 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1009 },
1010 },
1011 {
1012 .ident = "Satellite U200",
1013 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1016 },
1017 },
1018 {
1019 .ident = "Satellite Pro U200",
1020 .matches = {
1021 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1022 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1023 },
1024 },
1025 {
1026 .ident = "Satellite U205",
1027 .matches = {
1028 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1029 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1030 },
1031 },
1032 {
1033 .ident = "SATELLITE U205",
1034 .matches = {
1035 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1036 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1037 },
1038 },
1039 {
1040 .ident = "Portege M500",
1041 .matches = {
1042 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1043 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1044 },
1045 },
1046
1047 { } /* terminate list */
1048 };
1049 static const char *oemstrs[] = {
1050 "Tecra M3,",
1051 };
1052 int i;
1053
1054 if (dmi_check_system(sysids))
1055 return 1;
1056
1057 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1058 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1059 return 1;
1060
1061 return 0;
1062 }
1063
1064 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1065 {
1066 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1067 unsigned long flags;
1068 int rc = 0;
1069
1070 rc = ata_host_suspend(host, mesg);
1071 if (rc)
1072 return rc;
1073
1074 /* Some braindamaged ACPI suspend implementations expect the
1075 * controller to be awake on entry; otherwise, it burns cpu
1076 * cycles and power trying to do something to the sleeping
1077 * beauty.
1078 */
1079 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
1080 pci_save_state(pdev);
1081
1082 /* mark its power state as "unknown", since we don't
1083 * know if e.g. the BIOS will change its device state
1084 * when we suspend.
1085 */
1086 if (pdev->current_state == PCI_D0)
1087 pdev->current_state = PCI_UNKNOWN;
1088
1089 /* tell resume that it's waking up from broken suspend */
1090 spin_lock_irqsave(&host->lock, flags);
1091 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1092 spin_unlock_irqrestore(&host->lock, flags);
1093 } else
1094 ata_pci_device_do_suspend(pdev, mesg);
1095
1096 return 0;
1097 }
1098
1099 static int piix_pci_device_resume(struct pci_dev *pdev)
1100 {
1101 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1102 unsigned long flags;
1103 int rc;
1104
1105 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1106 spin_lock_irqsave(&host->lock, flags);
1107 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1108 spin_unlock_irqrestore(&host->lock, flags);
1109
1110 pci_set_power_state(pdev, PCI_D0);
1111 pci_restore_state(pdev);
1112
1113 /* PCI device wasn't disabled during suspend. Use
1114 * pci_reenable_device() to avoid affecting the enable
1115 * count.
1116 */
1117 rc = pci_reenable_device(pdev);
1118 if (rc)
1119 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1120 "device after resume (%d)\n", rc);
1121 } else
1122 rc = ata_pci_device_do_resume(pdev);
1123
1124 if (rc == 0)
1125 ata_host_resume(host);
1126
1127 return rc;
1128 }
1129 #endif
1130
1131 #define AHCI_PCI_BAR 5
1132 #define AHCI_GLOBAL_CTL 0x04
1133 #define AHCI_ENABLE (1 << 31)
1134 static int piix_disable_ahci(struct pci_dev *pdev)
1135 {
1136 void __iomem *mmio;
1137 u32 tmp;
1138 int rc = 0;
1139
1140 /* BUG: pci_enable_device has not yet been called. This
1141 * works because this device is usually set up by BIOS.
1142 */
1143
1144 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1145 !pci_resource_len(pdev, AHCI_PCI_BAR))
1146 return 0;
1147
1148 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1149 if (!mmio)
1150 return -ENOMEM;
1151
1152 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1153 if (tmp & AHCI_ENABLE) {
1154 tmp &= ~AHCI_ENABLE;
1155 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1156
1157 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1158 if (tmp & AHCI_ENABLE)
1159 rc = -EIO;
1160 }
1161
1162 pci_iounmap(pdev, mmio);
1163 return rc;
1164 }
1165
1166 /**
1167 * piix_check_450nx_errata - Check for problem 450NX setup
1168 * @ata_dev: the PCI device to check
1169 *
1170 * Check for the present of 450NX errata #19 and errata #25. If
1171 * they are found return an error code so we can turn off DMA
1172 */
1173
1174 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1175 {
1176 struct pci_dev *pdev = NULL;
1177 u16 cfg;
1178 int no_piix_dma = 0;
1179
1180 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1181 /* Look for 450NX PXB. Check for problem configurations
1182 A PCI quirk checks bit 6 already */
1183 pci_read_config_word(pdev, 0x41, &cfg);
1184 /* Only on the original revision: IDE DMA can hang */
1185 if (pdev->revision == 0x00)
1186 no_piix_dma = 1;
1187 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1188 else if (cfg & (1<<14) && pdev->revision < 5)
1189 no_piix_dma = 2;
1190 }
1191 if (no_piix_dma)
1192 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1193 if (no_piix_dma == 2)
1194 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1195 return no_piix_dma;
1196 }
1197
1198 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1199 struct ata_port_info *pinfo,
1200 const struct piix_map_db *map_db)
1201 {
1202 u16 pcs, new_pcs;
1203
1204 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1205
1206 new_pcs = pcs | map_db->port_enable;
1207
1208 if (new_pcs != pcs) {
1209 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1210 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1211 msleep(150);
1212 }
1213 }
1214
1215 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1216 struct ata_port_info *pinfo,
1217 const struct piix_map_db *map_db)
1218 {
1219 struct piix_host_priv *hpriv = pinfo[0].private_data;
1220 const int *map;
1221 int i, invalid_map = 0;
1222 u8 map_value;
1223
1224 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1225
1226 map = map_db->map[map_value & map_db->mask];
1227
1228 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1229 for (i = 0; i < 4; i++) {
1230 switch (map[i]) {
1231 case RV:
1232 invalid_map = 1;
1233 printk(" XX");
1234 break;
1235
1236 case NA:
1237 printk(" --");
1238 break;
1239
1240 case IDE:
1241 WARN_ON((i & 1) || map[i + 1] != IDE);
1242 pinfo[i / 2] = piix_port_info[ich_pata_100];
1243 pinfo[i / 2].private_data = hpriv;
1244 i++;
1245 printk(" IDE IDE");
1246 break;
1247
1248 default:
1249 printk(" P%d", map[i]);
1250 if (i & 1)
1251 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1252 break;
1253 }
1254 }
1255 printk(" ]\n");
1256
1257 if (invalid_map)
1258 dev_printk(KERN_ERR, &pdev->dev,
1259 "invalid MAP value %u\n", map_value);
1260
1261 hpriv->map = map;
1262 }
1263
1264 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1265 {
1266 static const struct dmi_system_id sysids[] = {
1267 {
1268 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1269 * isn't used to boot the system which
1270 * disables the channel.
1271 */
1272 .ident = "M570U",
1273 .matches = {
1274 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1275 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1276 },
1277 },
1278
1279 { } /* terminate list */
1280 };
1281 u32 iocfg;
1282
1283 if (!dmi_check_system(sysids))
1284 return;
1285
1286 /* The datasheet says that bit 18 is NOOP but certain systems
1287 * seem to use it to disable a channel. Clear the bit on the
1288 * affected systems.
1289 */
1290 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1291 if (iocfg & (1 << 18)) {
1292 dev_printk(KERN_INFO, &pdev->dev,
1293 "applying IOCFG bit18 quirk\n");
1294 iocfg &= ~(1 << 18);
1295 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1296 }
1297 }
1298
1299 /**
1300 * piix_init_one - Register PIIX ATA PCI device with kernel services
1301 * @pdev: PCI device to register
1302 * @ent: Entry in piix_pci_tbl matching with @pdev
1303 *
1304 * Called from kernel PCI layer. We probe for combined mode (sigh),
1305 * and then hand over control to libata, for it to do the rest.
1306 *
1307 * LOCKING:
1308 * Inherited from PCI layer (may sleep).
1309 *
1310 * RETURNS:
1311 * Zero on success, or -ERRNO value.
1312 */
1313
1314 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1315 {
1316 static int printed_version;
1317 struct device *dev = &pdev->dev;
1318 struct ata_port_info port_info[2];
1319 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1320 struct piix_host_priv *hpriv;
1321 unsigned long port_flags;
1322
1323 if (!printed_version++)
1324 dev_printk(KERN_DEBUG, &pdev->dev,
1325 "version " DRV_VERSION "\n");
1326
1327 /* no hotplugging support (FIXME) */
1328 if (!in_module_init)
1329 return -ENODEV;
1330
1331 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1332 if (!hpriv)
1333 return -ENOMEM;
1334
1335 port_info[0] = piix_port_info[ent->driver_data];
1336 port_info[1] = piix_port_info[ent->driver_data];
1337 port_info[0].private_data = hpriv;
1338 port_info[1].private_data = hpriv;
1339
1340 port_flags = port_info[0].flags;
1341
1342 if (port_flags & PIIX_FLAG_AHCI) {
1343 u8 tmp;
1344 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1345 if (tmp == PIIX_AHCI_DEVICE) {
1346 int rc = piix_disable_ahci(pdev);
1347 if (rc)
1348 return rc;
1349 }
1350 }
1351
1352 /* Initialize SATA map */
1353 if (port_flags & ATA_FLAG_SATA) {
1354 piix_init_sata_map(pdev, port_info,
1355 piix_map_db_table[ent->driver_data]);
1356 piix_init_pcs(pdev, port_info,
1357 piix_map_db_table[ent->driver_data]);
1358 }
1359
1360 /* apply IOCFG bit18 quirk */
1361 piix_iocfg_bit18_quirk(pdev);
1362
1363 /* On ICH5, some BIOSen disable the interrupt using the
1364 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1365 * On ICH6, this bit has the same effect, but only when
1366 * MSI is disabled (and it is disabled, as we don't use
1367 * message-signalled interrupts currently).
1368 */
1369 if (port_flags & PIIX_FLAG_CHECKINTR)
1370 pci_intx(pdev, 1);
1371
1372 if (piix_check_450nx_errata(pdev)) {
1373 /* This writes into the master table but it does not
1374 really matter for this errata as we will apply it to
1375 all the PIIX devices on the board */
1376 port_info[0].mwdma_mask = 0;
1377 port_info[0].udma_mask = 0;
1378 port_info[1].mwdma_mask = 0;
1379 port_info[1].udma_mask = 0;
1380 }
1381 return ata_pci_init_one(pdev, ppi);
1382 }
1383
1384 static int __init piix_init(void)
1385 {
1386 int rc;
1387
1388 DPRINTK("pci_register_driver\n");
1389 rc = pci_register_driver(&piix_pci_driver);
1390 if (rc)
1391 return rc;
1392
1393 in_module_init = 0;
1394
1395 DPRINTK("done\n");
1396 return 0;
1397 }
1398
1399 static void __exit piix_exit(void)
1400 {
1401 pci_unregister_driver(&piix_pci_driver);
1402 }
1403
1404 module_init(piix_init);
1405 module_exit(piix_exit);
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