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regression: cifs endianness bug
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / serial / amba-pl011.c
blob40604a092921dac7352161ffeed1820caa11216f
1 /*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
26 *
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
33 */
34
35 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
36 #define SUPPORT_SYSRQ
37 #endif
38
39 #include <linux/module.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/console.h>
43 #include <linux/sysrq.h>
44 #include <linux/device.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial_core.h>
48 #include <linux/serial.h>
49 #include <linux/amba/bus.h>
50 #include <linux/amba/serial.h>
51 #include <linux/clk.h>
52
53 #include <asm/io.h>
54 #include <asm/sizes.h>
55
56 #define UART_NR 14
57
58 #define SERIAL_AMBA_MAJOR 204
59 #define SERIAL_AMBA_MINOR 64
60 #define SERIAL_AMBA_NR UART_NR
61
62 #define AMBA_ISR_PASS_LIMIT 256
63
64 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
65 #define UART_DUMMY_DR_RX (1 << 16)
66
67 /*
68 * We wrap our port structure around the generic uart_port.
69 */
70 struct uart_amba_port {
71 struct uart_port port;
72 struct clk *clk;
73 unsigned int im; /* interrupt mask */
74 unsigned int old_status;
75 };
76
77 static void pl011_stop_tx(struct uart_port *port)
78 {
79 struct uart_amba_port *uap = (struct uart_amba_port *)port;
80
81 uap->im &= ~UART011_TXIM;
82 writew(uap->im, uap->port.membase + UART011_IMSC);
83 }
84
85 static void pl011_start_tx(struct uart_port *port)
86 {
87 struct uart_amba_port *uap = (struct uart_amba_port *)port;
88
89 uap->im |= UART011_TXIM;
90 writew(uap->im, uap->port.membase + UART011_IMSC);
91 }
92
93 static void pl011_stop_rx(struct uart_port *port)
94 {
95 struct uart_amba_port *uap = (struct uart_amba_port *)port;
96
97 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
98 UART011_PEIM|UART011_BEIM|UART011_OEIM);
99 writew(uap->im, uap->port.membase + UART011_IMSC);
100 }
101
102 static void pl011_enable_ms(struct uart_port *port)
103 {
104 struct uart_amba_port *uap = (struct uart_amba_port *)port;
105
106 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
107 writew(uap->im, uap->port.membase + UART011_IMSC);
108 }
109
110 static void pl011_rx_chars(struct uart_amba_port *uap)
111 {
112 struct tty_struct *tty = uap->port.info->tty;
113 unsigned int status, ch, flag, max_count = 256;
114
115 status = readw(uap->port.membase + UART01x_FR);
116 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
117 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
118 flag = TTY_NORMAL;
119 uap->port.icount.rx++;
120
121 /*
122 * Note that the error handling code is
123 * out of the main execution path
124 */
125 if (unlikely(ch & UART_DR_ERROR)) {
126 if (ch & UART011_DR_BE) {
127 ch &= ~(UART011_DR_FE | UART011_DR_PE);
128 uap->port.icount.brk++;
129 if (uart_handle_break(&uap->port))
130 goto ignore_char;
131 } else if (ch & UART011_DR_PE)
132 uap->port.icount.parity++;
133 else if (ch & UART011_DR_FE)
134 uap->port.icount.frame++;
135 if (ch & UART011_DR_OE)
136 uap->port.icount.overrun++;
137
138 ch &= uap->port.read_status_mask;
139
140 if (ch & UART011_DR_BE)
141 flag = TTY_BREAK;
142 else if (ch & UART011_DR_PE)
143 flag = TTY_PARITY;
144 else if (ch & UART011_DR_FE)
145 flag = TTY_FRAME;
146 }
147
148 if (uart_handle_sysrq_char(&uap->port, ch & 255))
149 goto ignore_char;
150
151 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
152
153 ignore_char:
154 status = readw(uap->port.membase + UART01x_FR);
155 }
156 spin_unlock(&uap->port.lock);
157 tty_flip_buffer_push(tty);
158 spin_lock(&uap->port.lock);
159 }
160
161 static void pl011_tx_chars(struct uart_amba_port *uap)
162 {
163 struct circ_buf *xmit = &uap->port.info->xmit;
164 int count;
165
166 if (uap->port.x_char) {
167 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
168 uap->port.icount.tx++;
169 uap->port.x_char = 0;
170 return;
171 }
172 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
173 pl011_stop_tx(&uap->port);
174 return;
175 }
176
177 count = uap->port.fifosize >> 1;
178 do {
179 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
180 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
181 uap->port.icount.tx++;
182 if (uart_circ_empty(xmit))
183 break;
184 } while (--count > 0);
185
186 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
187 uart_write_wakeup(&uap->port);
188
189 if (uart_circ_empty(xmit))
190 pl011_stop_tx(&uap->port);
191 }
192
193 static void pl011_modem_status(struct uart_amba_port *uap)
194 {
195 unsigned int status, delta;
196
197 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
198
199 delta = status ^ uap->old_status;
200 uap->old_status = status;
201
202 if (!delta)
203 return;
204
205 if (delta & UART01x_FR_DCD)
206 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
207
208 if (delta & UART01x_FR_DSR)
209 uap->port.icount.dsr++;
210
211 if (delta & UART01x_FR_CTS)
212 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
213
214 wake_up_interruptible(&uap->port.info->delta_msr_wait);
215 }
216
217 static irqreturn_t pl011_int(int irq, void *dev_id)
218 {
219 struct uart_amba_port *uap = dev_id;
220 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
221 int handled = 0;
222
223 spin_lock(&uap->port.lock);
224
225 status = readw(uap->port.membase + UART011_MIS);
226 if (status) {
227 do {
228 writew(status & ~(UART011_TXIS|UART011_RTIS|
229 UART011_RXIS),
230 uap->port.membase + UART011_ICR);
231
232 if (status & (UART011_RTIS|UART011_RXIS))
233 pl011_rx_chars(uap);
234 if (status & (UART011_DSRMIS|UART011_DCDMIS|
235 UART011_CTSMIS|UART011_RIMIS))
236 pl011_modem_status(uap);
237 if (status & UART011_TXIS)
238 pl011_tx_chars(uap);
239
240 if (pass_counter-- == 0)
241 break;
242
243 status = readw(uap->port.membase + UART011_MIS);
244 } while (status != 0);
245 handled = 1;
246 }
247
248 spin_unlock(&uap->port.lock);
249
250 return IRQ_RETVAL(handled);
251 }
252
253 static unsigned int pl01x_tx_empty(struct uart_port *port)
254 {
255 struct uart_amba_port *uap = (struct uart_amba_port *)port;
256 unsigned int status = readw(uap->port.membase + UART01x_FR);
257 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
258 }
259
260 static unsigned int pl01x_get_mctrl(struct uart_port *port)
261 {
262 struct uart_amba_port *uap = (struct uart_amba_port *)port;
263 unsigned int result = 0;
264 unsigned int status = readw(uap->port.membase + UART01x_FR);
265
266 #define TIOCMBIT(uartbit, tiocmbit) \
267 if (status & uartbit) \
268 result |= tiocmbit
269
270 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
271 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
272 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
273 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
274 #undef TIOCMBIT
275 return result;
276 }
277
278 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
279 {
280 struct uart_amba_port *uap = (struct uart_amba_port *)port;
281 unsigned int cr;
282
283 cr = readw(uap->port.membase + UART011_CR);
284
285 #define TIOCMBIT(tiocmbit, uartbit) \
286 if (mctrl & tiocmbit) \
287 cr |= uartbit; \
288 else \
289 cr &= ~uartbit
290
291 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
292 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
293 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
294 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
295 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
296 #undef TIOCMBIT
297
298 writew(cr, uap->port.membase + UART011_CR);
299 }
300
301 static void pl011_break_ctl(struct uart_port *port, int break_state)
302 {
303 struct uart_amba_port *uap = (struct uart_amba_port *)port;
304 unsigned long flags;
305 unsigned int lcr_h;
306
307 spin_lock_irqsave(&uap->port.lock, flags);
308 lcr_h = readw(uap->port.membase + UART011_LCRH);
309 if (break_state == -1)
310 lcr_h |= UART01x_LCRH_BRK;
311 else
312 lcr_h &= ~UART01x_LCRH_BRK;
313 writew(lcr_h, uap->port.membase + UART011_LCRH);
314 spin_unlock_irqrestore(&uap->port.lock, flags);
315 }
316
317 static int pl011_startup(struct uart_port *port)
318 {
319 struct uart_amba_port *uap = (struct uart_amba_port *)port;
320 unsigned int cr;
321 int retval;
322
323 /*
324 * Try to enable the clock producer.
325 */
326 retval = clk_enable(uap->clk);
327 if (retval)
328 goto out;
329
330 uap->port.uartclk = clk_get_rate(uap->clk);
331
332 /*
333 * Allocate the IRQ
334 */
335 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
336 if (retval)
337 goto clk_dis;
338
339 writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
340 uap->port.membase + UART011_IFLS);
341
342 /*
343 * Provoke TX FIFO interrupt into asserting.
344 */
345 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
346 writew(cr, uap->port.membase + UART011_CR);
347 writew(0, uap->port.membase + UART011_FBRD);
348 writew(1, uap->port.membase + UART011_IBRD);
349 writew(0, uap->port.membase + UART011_LCRH);
350 writew(0, uap->port.membase + UART01x_DR);
351 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
352 barrier();
353
354 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
355 writew(cr, uap->port.membase + UART011_CR);
356
357 /*
358 * initialise the old status of the modem signals
359 */
360 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
361
362 /*
363 * Finally, enable interrupts
364 */
365 spin_lock_irq(&uap->port.lock);
366 uap->im = UART011_RXIM | UART011_RTIM;
367 writew(uap->im, uap->port.membase + UART011_IMSC);
368 spin_unlock_irq(&uap->port.lock);
369
370 return 0;
371
372 clk_dis:
373 clk_disable(uap->clk);
374 out:
375 return retval;
376 }
377
378 static void pl011_shutdown(struct uart_port *port)
379 {
380 struct uart_amba_port *uap = (struct uart_amba_port *)port;
381 unsigned long val;
382
383 /*
384 * disable all interrupts
385 */
386 spin_lock_irq(&uap->port.lock);
387 uap->im = 0;
388 writew(uap->im, uap->port.membase + UART011_IMSC);
389 writew(0xffff, uap->port.membase + UART011_ICR);
390 spin_unlock_irq(&uap->port.lock);
391
392 /*
393 * Free the interrupt
394 */
395 free_irq(uap->port.irq, uap);
396
397 /*
398 * disable the port
399 */
400 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
401
402 /*
403 * disable break condition and fifos
404 */
405 val = readw(uap->port.membase + UART011_LCRH);
406 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
407 writew(val, uap->port.membase + UART011_LCRH);
408
409 /*
410 * Shut down the clock producer
411 */
412 clk_disable(uap->clk);
413 }
414
415 static void
416 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
417 struct ktermios *old)
418 {
419 unsigned int lcr_h, old_cr;
420 unsigned long flags;
421 unsigned int baud, quot;
422
423 /*
424 * Ask the core to calculate the divisor for us.
425 */
426 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
427 quot = port->uartclk * 4 / baud;
428
429 switch (termios->c_cflag & CSIZE) {
430 case CS5:
431 lcr_h = UART01x_LCRH_WLEN_5;
432 break;
433 case CS6:
434 lcr_h = UART01x_LCRH_WLEN_6;
435 break;
436 case CS7:
437 lcr_h = UART01x_LCRH_WLEN_7;
438 break;
439 default: // CS8
440 lcr_h = UART01x_LCRH_WLEN_8;
441 break;
442 }
443 if (termios->c_cflag & CSTOPB)
444 lcr_h |= UART01x_LCRH_STP2;
445 if (termios->c_cflag & PARENB) {
446 lcr_h |= UART01x_LCRH_PEN;
447 if (!(termios->c_cflag & PARODD))
448 lcr_h |= UART01x_LCRH_EPS;
449 }
450 if (port->fifosize > 1)
451 lcr_h |= UART01x_LCRH_FEN;
452
453 spin_lock_irqsave(&port->lock, flags);
454
455 /*
456 * Update the per-port timeout.
457 */
458 uart_update_timeout(port, termios->c_cflag, baud);
459
460 port->read_status_mask = UART011_DR_OE | 255;
461 if (termios->c_iflag & INPCK)
462 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
463 if (termios->c_iflag & (BRKINT | PARMRK))
464 port->read_status_mask |= UART011_DR_BE;
465
466 /*
467 * Characters to ignore
468 */
469 port->ignore_status_mask = 0;
470 if (termios->c_iflag & IGNPAR)
471 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
472 if (termios->c_iflag & IGNBRK) {
473 port->ignore_status_mask |= UART011_DR_BE;
474 /*
475 * If we're ignoring parity and break indicators,
476 * ignore overruns too (for real raw support).
477 */
478 if (termios->c_iflag & IGNPAR)
479 port->ignore_status_mask |= UART011_DR_OE;
480 }
481
482 /*
483 * Ignore all characters if CREAD is not set.
484 */
485 if ((termios->c_cflag & CREAD) == 0)
486 port->ignore_status_mask |= UART_DUMMY_DR_RX;
487
488 if (UART_ENABLE_MS(port, termios->c_cflag))
489 pl011_enable_ms(port);
490
491 /* first, disable everything */
492 old_cr = readw(port->membase + UART011_CR);
493 writew(0, port->membase + UART011_CR);
494
495 /* Set baud rate */
496 writew(quot & 0x3f, port->membase + UART011_FBRD);
497 writew(quot >> 6, port->membase + UART011_IBRD);
498
499 /*
500 * ----------v----------v----------v----------v-----
501 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
502 * ----------^----------^----------^----------^-----
503 */
504 writew(lcr_h, port->membase + UART011_LCRH);
505 writew(old_cr, port->membase + UART011_CR);
506
507 spin_unlock_irqrestore(&port->lock, flags);
508 }
509
510 static const char *pl011_type(struct uart_port *port)
511 {
512 return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
513 }
514
515 /*
516 * Release the memory region(s) being used by 'port'
517 */
518 static void pl010_release_port(struct uart_port *port)
519 {
520 release_mem_region(port->mapbase, SZ_4K);
521 }
522
523 /*
524 * Request the memory region(s) being used by 'port'
525 */
526 static int pl010_request_port(struct uart_port *port)
527 {
528 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
529 != NULL ? 0 : -EBUSY;
530 }
531
532 /*
533 * Configure/autoconfigure the port.
534 */
535 static void pl010_config_port(struct uart_port *port, int flags)
536 {
537 if (flags & UART_CONFIG_TYPE) {
538 port->type = PORT_AMBA;
539 pl010_request_port(port);
540 }
541 }
542
543 /*
544 * verify the new serial_struct (for TIOCSSERIAL).
545 */
546 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
547 {
548 int ret = 0;
549 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
550 ret = -EINVAL;
551 if (ser->irq < 0 || ser->irq >= NR_IRQS)
552 ret = -EINVAL;
553 if (ser->baud_base < 9600)
554 ret = -EINVAL;
555 return ret;
556 }
557
558 static struct uart_ops amba_pl011_pops = {
559 .tx_empty = pl01x_tx_empty,
560 .set_mctrl = pl011_set_mctrl,
561 .get_mctrl = pl01x_get_mctrl,
562 .stop_tx = pl011_stop_tx,
563 .start_tx = pl011_start_tx,
564 .stop_rx = pl011_stop_rx,
565 .enable_ms = pl011_enable_ms,
566 .break_ctl = pl011_break_ctl,
567 .startup = pl011_startup,
568 .shutdown = pl011_shutdown,
569 .set_termios = pl011_set_termios,
570 .type = pl011_type,
571 .release_port = pl010_release_port,
572 .request_port = pl010_request_port,
573 .config_port = pl010_config_port,
574 .verify_port = pl010_verify_port,
575 };
576
577 static struct uart_amba_port *amba_ports[UART_NR];
578
579 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
580
581 static void pl011_console_putchar(struct uart_port *port, int ch)
582 {
583 struct uart_amba_port *uap = (struct uart_amba_port *)port;
584
585 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
586 barrier();
587 writew(ch, uap->port.membase + UART01x_DR);
588 }
589
590 static void
591 pl011_console_write(struct console *co, const char *s, unsigned int count)
592 {
593 struct uart_amba_port *uap = amba_ports[co->index];
594 unsigned int status, old_cr, new_cr;
595
596 clk_enable(uap->clk);
597
598 /*
599 * First save the CR then disable the interrupts
600 */
601 old_cr = readw(uap->port.membase + UART011_CR);
602 new_cr = old_cr & ~UART011_CR_CTSEN;
603 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
604 writew(new_cr, uap->port.membase + UART011_CR);
605
606 uart_console_write(&uap->port, s, count, pl011_console_putchar);
607
608 /*
609 * Finally, wait for transmitter to become empty
610 * and restore the TCR
611 */
612 do {
613 status = readw(uap->port.membase + UART01x_FR);
614 } while (status & UART01x_FR_BUSY);
615 writew(old_cr, uap->port.membase + UART011_CR);
616
617 clk_disable(uap->clk);
618 }
619
620 static void __init
621 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
622 int *parity, int *bits)
623 {
624 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
625 unsigned int lcr_h, ibrd, fbrd;
626
627 lcr_h = readw(uap->port.membase + UART011_LCRH);
628
629 *parity = 'n';
630 if (lcr_h & UART01x_LCRH_PEN) {
631 if (lcr_h & UART01x_LCRH_EPS)
632 *parity = 'e';
633 else
634 *parity = 'o';
635 }
636
637 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
638 *bits = 7;
639 else
640 *bits = 8;
641
642 ibrd = readw(uap->port.membase + UART011_IBRD);
643 fbrd = readw(uap->port.membase + UART011_FBRD);
644
645 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
646 }
647 }
648
649 static int __init pl011_console_setup(struct console *co, char *options)
650 {
651 struct uart_amba_port *uap;
652 int baud = 38400;
653 int bits = 8;
654 int parity = 'n';
655 int flow = 'n';
656
657 /*
658 * Check whether an invalid uart number has been specified, and
659 * if so, search for the first available port that does have
660 * console support.
661 */
662 if (co->index >= UART_NR)
663 co->index = 0;
664 uap = amba_ports[co->index];
665 if (!uap)
666 return -ENODEV;
667
668 uap->port.uartclk = clk_get_rate(uap->clk);
669
670 if (options)
671 uart_parse_options(options, &baud, &parity, &bits, &flow);
672 else
673 pl011_console_get_options(uap, &baud, &parity, &bits);
674
675 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
676 }
677
678 static struct uart_driver amba_reg;
679 static struct console amba_console = {
680 .name = "ttyAMA",
681 .write = pl011_console_write,
682 .device = uart_console_device,
683 .setup = pl011_console_setup,
684 .flags = CON_PRINTBUFFER,
685 .index = -1,
686 .data = &amba_reg,
687 };
688
689 #define AMBA_CONSOLE (&amba_console)
690 #else
691 #define AMBA_CONSOLE NULL
692 #endif
693
694 static struct uart_driver amba_reg = {
695 .owner = THIS_MODULE,
696 .driver_name = "ttyAMA",
697 .dev_name = "ttyAMA",
698 .major = SERIAL_AMBA_MAJOR,
699 .minor = SERIAL_AMBA_MINOR,
700 .nr = UART_NR,
701 .cons = AMBA_CONSOLE,
702 };
703
704 static int pl011_probe(struct amba_device *dev, void *id)
705 {
706 struct uart_amba_port *uap;
707 void __iomem *base;
708 int i, ret;
709
710 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
711 if (amba_ports[i] == NULL)
712 break;
713
714 if (i == ARRAY_SIZE(amba_ports)) {
715 ret = -EBUSY;
716 goto out;
717 }
718
719 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
720 if (uap == NULL) {
721 ret = -ENOMEM;
722 goto out;
723 }
724
725 base = ioremap(dev->res.start, PAGE_SIZE);
726 if (!base) {
727 ret = -ENOMEM;
728 goto free;
729 }
730
731 uap->clk = clk_get(&dev->dev, "UARTCLK");
732 if (IS_ERR(uap->clk)) {
733 ret = PTR_ERR(uap->clk);
734 goto unmap;
735 }
736
737 uap->port.dev = &dev->dev;
738 uap->port.mapbase = dev->res.start;
739 uap->port.membase = base;
740 uap->port.iotype = UPIO_MEM;
741 uap->port.irq = dev->irq[0];
742 uap->port.fifosize = 16;
743 uap->port.ops = &amba_pl011_pops;
744 uap->port.flags = UPF_BOOT_AUTOCONF;
745 uap->port.line = i;
746
747 amba_ports[i] = uap;
748
749 amba_set_drvdata(dev, uap);
750 ret = uart_add_one_port(&amba_reg, &uap->port);
751 if (ret) {
752 amba_set_drvdata(dev, NULL);
753 amba_ports[i] = NULL;
754 clk_put(uap->clk);
755 unmap:
756 iounmap(base);
757 free:
758 kfree(uap);
759 }
760 out:
761 return ret;
762 }
763
764 static int pl011_remove(struct amba_device *dev)
765 {
766 struct uart_amba_port *uap = amba_get_drvdata(dev);
767 int i;
768
769 amba_set_drvdata(dev, NULL);
770
771 uart_remove_one_port(&amba_reg, &uap->port);
772
773 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
774 if (amba_ports[i] == uap)
775 amba_ports[i] = NULL;
776
777 iounmap(uap->port.membase);
778 clk_put(uap->clk);
779 kfree(uap);
780 return 0;
781 }
782
783 static struct amba_id pl011_ids[] __initdata = {
784 {
785 .id = 0x00041011,
786 .mask = 0x000fffff,
787 },
788 { 0, 0 },
789 };
790
791 static struct amba_driver pl011_driver = {
792 .drv = {
793 .name = "uart-pl011",
794 },
795 .id_table = pl011_ids,
796 .probe = pl011_probe,
797 .remove = pl011_remove,
798 };
799
800 static int __init pl011_init(void)
801 {
802 int ret;
803 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
804
805 ret = uart_register_driver(&amba_reg);
806 if (ret == 0) {
807 ret = amba_driver_register(&pl011_driver);
808 if (ret)
809 uart_unregister_driver(&amba_reg);
810 }
811 return ret;
812 }
813
814 static void __exit pl011_exit(void)
815 {
816 amba_driver_unregister(&pl011_driver);
817 uart_unregister_driver(&amba_reg);
818 }
819
820 module_init(pl011_init);
821 module_exit(pl011_exit);
822
823 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
824 MODULE_DESCRIPTION("ARM AMBA serial port driver");
825 MODULE_LICENSE("GPL");
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