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regression: cifs endianness bug
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / serial / sh-sci.c
blob73440e26834beb8d09cd6b07edb0dd1e8b73208a
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44
45 #ifdef CONFIG_CPU_FREQ
46 #include <linux/notifier.h>
47 #include <linux/cpufreq.h>
48 #endif
49
50 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
51 #include <linux/ctype.h>
52 #include <asm/clock.h>
53 #include <asm/sh_bios.h>
54 #include <asm/kgdb.h>
55 #endif
56
57 #include <asm/sci.h>
58 #include "sh-sci.h"
59
60 struct sci_port {
61 struct uart_port port;
62
63 /* Port type */
64 unsigned int type;
65
66 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
67 unsigned int irqs[SCIx_NR_IRQS];
68
69 /* Port pin configuration */
70 void (*init_pins)(struct uart_port *port,
71 unsigned int cflag);
72
73 /* Port enable callback */
74 void (*enable)(struct uart_port *port);
75
76 /* Port disable callback */
77 void (*disable)(struct uart_port *port);
78
79 /* Break timer */
80 struct timer_list break_timer;
81 int break_flag;
82
83 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
84 /* Port clock */
85 struct clk *clk;
86 #endif
87 };
88
89 #ifdef CONFIG_SH_KGDB
90 static struct sci_port *kgdb_sci_port;
91 #endif
92
93 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
94 static struct sci_port *serial_console_port;
95 #endif
96
97 /* Function prototypes */
98 static void sci_stop_tx(struct uart_port *port);
99
100 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
101
102 static struct sci_port sci_ports[SCI_NPORTS];
103 static struct uart_driver sci_uart_driver;
104
105 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
106 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
107 static inline void handle_error(struct uart_port *port)
108 {
109 /* Clear error flags */
110 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
111 }
112
113 static int get_char(struct uart_port *port)
114 {
115 unsigned long flags;
116 unsigned short status;
117 int c;
118
119 spin_lock_irqsave(&port->lock, flags);
120 do {
121 status = sci_in(port, SCxSR);
122 if (status & SCxSR_ERRORS(port)) {
123 handle_error(port);
124 continue;
125 }
126 } while (!(status & SCxSR_RDxF(port)));
127 c = sci_in(port, SCxRDR);
128 sci_in(port, SCxSR); /* Dummy read */
129 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
130 spin_unlock_irqrestore(&port->lock, flags);
131
132 return c;
133 }
134 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
135
136 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
137 static void put_char(struct uart_port *port, char c)
138 {
139 unsigned long flags;
140 unsigned short status;
141
142 spin_lock_irqsave(&port->lock, flags);
143
144 do {
145 status = sci_in(port, SCxSR);
146 } while (!(status & SCxSR_TDxE(port)));
147
148 sci_out(port, SCxTDR, c);
149 sci_in(port, SCxSR); /* Dummy read */
150 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
151
152 spin_unlock_irqrestore(&port->lock, flags);
153 }
154 #endif
155
156 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
157 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
158 {
159 struct uart_port *port = &sci_port->port;
160 const unsigned char *p = buffer;
161 int i;
162
163 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
164 int checksum;
165 int usegdb=0;
166
167 #ifdef CONFIG_SH_STANDARD_BIOS
168 /* This call only does a trap the first time it is
169 * called, and so is safe to do here unconditionally
170 */
171 usegdb |= sh_bios_in_gdb_mode();
172 #endif
173 #ifdef CONFIG_SH_KGDB
174 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
175 #endif
176
177 if (usegdb) {
178 /* $<packet info>#<checksum>. */
179 do {
180 unsigned char c;
181 put_char(port, '$');
182 put_char(port, 'O'); /* 'O'utput to console */
183 checksum = 'O';
184
185 for (i=0; i<count; i++) { /* Don't use run length encoding */
186 int h, l;
187
188 c = *p++;
189 h = highhex(c);
190 l = lowhex(c);
191 put_char(port, h);
192 put_char(port, l);
193 checksum += h + l;
194 }
195 put_char(port, '#');
196 put_char(port, highhex(checksum));
197 put_char(port, lowhex(checksum));
198 } while (get_char(port) != '+');
199 } else
200 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
201 for (i=0; i<count; i++) {
202 if (*p == 10)
203 put_char(port, '\r');
204 put_char(port, *p++);
205 }
206 }
207 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
208
209 #ifdef CONFIG_SH_KGDB
210 static int kgdb_sci_getchar(void)
211 {
212 int c;
213
214 /* Keep trying to read a character, this could be neater */
215 while ((c = get_char(&kgdb_sci_port->port)) < 0)
216 cpu_relax();
217
218 return c;
219 }
220
221 static inline void kgdb_sci_putchar(int c)
222 {
223 put_char(&kgdb_sci_port->port, c);
224 }
225 #endif /* CONFIG_SH_KGDB */
226
227 #if defined(__H8300S__)
228 enum { sci_disable, sci_enable };
229
230 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
231 {
232 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
233 int ch = (port->mapbase - SMR0) >> 3;
234 unsigned char mask = 1 << (ch+1);
235
236 if (ctrl == sci_disable) {
237 *mstpcrl |= mask;
238 } else {
239 *mstpcrl &= ~mask;
240 }
241 }
242
243 static inline void h8300_sci_enable(struct uart_port *port)
244 {
245 h8300_sci_config(port, sci_enable);
246 }
247
248 static inline void h8300_sci_disable(struct uart_port *port)
249 {
250 h8300_sci_config(port, sci_disable);
251 }
252 #endif
253
254 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
255 defined(__H8300H__) || defined(__H8300S__)
256 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
257 {
258 int ch = (port->mapbase - SMR0) >> 3;
259
260 /* set DDR regs */
261 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
262 h8300_sci_pins[ch].rx,
263 H8300_GPIO_INPUT);
264 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
265 h8300_sci_pins[ch].tx,
266 H8300_GPIO_OUTPUT);
267
268 /* tx mark output*/
269 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
270 }
271 #else
272 #define sci_init_pins_sci NULL
273 #endif
274
275 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
276 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
277 {
278 unsigned int fcr_val = 0;
279
280 if (cflag & CRTSCTS)
281 fcr_val |= SCFCR_MCE;
282
283 sci_out(port, SCFCR, fcr_val);
284 }
285 #else
286 #define sci_init_pins_irda NULL
287 #endif
288
289 #ifdef SCI_ONLY
290 #define sci_init_pins_scif NULL
291 #endif
292
293 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
294 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
295 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
296 {
297 unsigned int fcr_val = 0;
298
299 set_sh771x_scif_pfc(port);
300 if (cflag & CRTSCTS) {
301 fcr_val |= SCFCR_MCE;
302 }
303 sci_out(port, SCFCR, fcr_val);
304 }
305 #elif defined(CONFIG_CPU_SUBTYPE_SH7720)
306 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
307 {
308 unsigned int fcr_val = 0;
309 unsigned short data;
310
311 if (cflag & CRTSCTS) {
312 /* enable RTS/CTS */
313 if (port->mapbase == 0xa4430000) { /* SCIF0 */
314 /* Clear PTCR bit 9-2; enable all scif pins but sck */
315 data = ctrl_inw(PORT_PTCR);
316 ctrl_outw((data & 0xfc03), PORT_PTCR);
317 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
318 /* Clear PVCR bit 9-2 */
319 data = ctrl_inw(PORT_PVCR);
320 ctrl_outw((data & 0xfc03), PORT_PVCR);
321 }
322 fcr_val |= SCFCR_MCE;
323 } else {
324 if (port->mapbase == 0xa4430000) { /* SCIF0 */
325 /* Clear PTCR bit 5-2; enable only tx and rx */
326 data = ctrl_inw(PORT_PTCR);
327 ctrl_outw((data & 0xffc3), PORT_PTCR);
328 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
329 /* Clear PVCR bit 5-2 */
330 data = ctrl_inw(PORT_PVCR);
331 ctrl_outw((data & 0xffc3), PORT_PVCR);
332 }
333 }
334 sci_out(port, SCFCR, fcr_val);
335 }
336
337 #elif defined(CONFIG_CPU_SH3)
338 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
339 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
340 {
341 unsigned int fcr_val = 0;
342 unsigned short data;
343
344 /* We need to set SCPCR to enable RTS/CTS */
345 data = ctrl_inw(SCPCR);
346 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
347 ctrl_outw(data & 0x0fcf, SCPCR);
348
349 if (cflag & CRTSCTS)
350 fcr_val |= SCFCR_MCE;
351 else {
352 /* We need to set SCPCR to enable RTS/CTS */
353 data = ctrl_inw(SCPCR);
354 /* Clear out SCP7MD1,0, SCP4MD1,0,
355 Set SCP6MD1,0 = {01} (output) */
356 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
357
358 data = ctrl_inb(SCPDR);
359 /* Set /RTS2 (bit6) = 0 */
360 ctrl_outb(data & 0xbf, SCPDR);
361 }
362
363 sci_out(port, SCFCR, fcr_val);
364 }
365 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
366 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
367 {
368 unsigned int fcr_val = 0;
369
370 if (cflag & CRTSCTS) {
371 fcr_val |= SCFCR_MCE;
372
373 ctrl_outw(0x0000, PORT_PSCR);
374 } else {
375 unsigned short data;
376
377 data = ctrl_inw(PORT_PSCR);
378 data &= 0x033f;
379 data |= 0x0400;
380 ctrl_outw(data, PORT_PSCR);
381
382 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
383 }
384
385 sci_out(port, SCFCR, fcr_val);
386 }
387 #else
388 /* For SH7750 */
389 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
390 {
391 unsigned int fcr_val = 0;
392
393 if (cflag & CRTSCTS) {
394 fcr_val |= SCFCR_MCE;
395 } else {
396 #ifdef CONFIG_CPU_SUBTYPE_SH7343
397 /* Nothing */
398 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
399 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
400 defined(CONFIG_CPU_SUBTYPE_SHX3)
401 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
402 #else
403 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
404 #endif
405 }
406 sci_out(port, SCFCR, fcr_val);
407 }
408 #endif
409
410 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
411 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
412 defined(CONFIG_CPU_SUBTYPE_SH7785)
413 static inline int scif_txroom(struct uart_port *port)
414 {
415 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
416 }
417
418 static inline int scif_rxroom(struct uart_port *port)
419 {
420 return sci_in(port, SCRFDR) & 0x7f;
421 }
422 #else
423 static inline int scif_txroom(struct uart_port *port)
424 {
425 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
426 }
427
428 static inline int scif_rxroom(struct uart_port *port)
429 {
430 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
431 }
432 #endif
433 #endif /* SCIF_ONLY || SCI_AND_SCIF */
434
435 static inline int sci_txroom(struct uart_port *port)
436 {
437 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
438 }
439
440 static inline int sci_rxroom(struct uart_port *port)
441 {
442 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
443 }
444
445 /* ********************************************************************** *
446 * the interrupt related routines *
447 * ********************************************************************** */
448
449 static void sci_transmit_chars(struct uart_port *port)
450 {
451 struct circ_buf *xmit = &port->info->xmit;
452 unsigned int stopped = uart_tx_stopped(port);
453 unsigned short status;
454 unsigned short ctrl;
455 int count;
456
457 status = sci_in(port, SCxSR);
458 if (!(status & SCxSR_TDxE(port))) {
459 ctrl = sci_in(port, SCSCR);
460 if (uart_circ_empty(xmit)) {
461 ctrl &= ~SCI_CTRL_FLAGS_TIE;
462 } else {
463 ctrl |= SCI_CTRL_FLAGS_TIE;
464 }
465 sci_out(port, SCSCR, ctrl);
466 return;
467 }
468
469 #ifndef SCI_ONLY
470 if (port->type == PORT_SCIF)
471 count = scif_txroom(port);
472 else
473 #endif
474 count = sci_txroom(port);
475
476 do {
477 unsigned char c;
478
479 if (port->x_char) {
480 c = port->x_char;
481 port->x_char = 0;
482 } else if (!uart_circ_empty(xmit) && !stopped) {
483 c = xmit->buf[xmit->tail];
484 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
485 } else {
486 break;
487 }
488
489 sci_out(port, SCxTDR, c);
490
491 port->icount.tx++;
492 } while (--count > 0);
493
494 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
495
496 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
497 uart_write_wakeup(port);
498 if (uart_circ_empty(xmit)) {
499 sci_stop_tx(port);
500 } else {
501 ctrl = sci_in(port, SCSCR);
502
503 #if !defined(SCI_ONLY)
504 if (port->type == PORT_SCIF) {
505 sci_in(port, SCxSR); /* Dummy read */
506 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
507 }
508 #endif
509
510 ctrl |= SCI_CTRL_FLAGS_TIE;
511 sci_out(port, SCSCR, ctrl);
512 }
513 }
514
515 /* On SH3, SCIF may read end-of-break as a space->mark char */
516 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
517
518 static inline void sci_receive_chars(struct uart_port *port)
519 {
520 struct sci_port *sci_port = (struct sci_port *)port;
521 struct tty_struct *tty = port->info->tty;
522 int i, count, copied = 0;
523 unsigned short status;
524 unsigned char flag;
525
526 status = sci_in(port, SCxSR);
527 if (!(status & SCxSR_RDxF(port)))
528 return;
529
530 while (1) {
531 #if !defined(SCI_ONLY)
532 if (port->type == PORT_SCIF)
533 count = scif_rxroom(port);
534 else
535 #endif
536 count = sci_rxroom(port);
537
538 /* Don't copy more bytes than there is room for in the buffer */
539 count = tty_buffer_request_room(tty, count);
540
541 /* If for any reason we can't copy more data, we're done! */
542 if (count == 0)
543 break;
544
545 if (port->type == PORT_SCI) {
546 char c = sci_in(port, SCxRDR);
547 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
548 count = 0;
549 else {
550 tty_insert_flip_char(tty, c, TTY_NORMAL);
551 }
552 } else {
553 for (i=0; i<count; i++) {
554 char c = sci_in(port, SCxRDR);
555 status = sci_in(port, SCxSR);
556 #if defined(CONFIG_CPU_SH3)
557 /* Skip "chars" during break */
558 if (sci_port->break_flag) {
559 if ((c == 0) &&
560 (status & SCxSR_FER(port))) {
561 count--; i--;
562 continue;
563 }
564
565 /* Nonzero => end-of-break */
566 pr_debug("scif: debounce<%02x>\n", c);
567 sci_port->break_flag = 0;
568
569 if (STEPFN(c)) {
570 count--; i--;
571 continue;
572 }
573 }
574 #endif /* CONFIG_CPU_SH3 */
575 if (uart_handle_sysrq_char(port, c)) {
576 count--; i--;
577 continue;
578 }
579
580 /* Store data and status */
581 if (status&SCxSR_FER(port)) {
582 flag = TTY_FRAME;
583 pr_debug("sci: frame error\n");
584 } else if (status&SCxSR_PER(port)) {
585 flag = TTY_PARITY;
586 pr_debug("sci: parity error\n");
587 } else
588 flag = TTY_NORMAL;
589 tty_insert_flip_char(tty, c, flag);
590 }
591 }
592
593 sci_in(port, SCxSR); /* dummy read */
594 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
595
596 copied += count;
597 port->icount.rx += count;
598 }
599
600 if (copied) {
601 /* Tell the rest of the system the news. New characters! */
602 tty_flip_buffer_push(tty);
603 } else {
604 sci_in(port, SCxSR); /* dummy read */
605 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
606 }
607 }
608
609 #define SCI_BREAK_JIFFIES (HZ/20)
610 /* The sci generates interrupts during the break,
611 * 1 per millisecond or so during the break period, for 9600 baud.
612 * So dont bother disabling interrupts.
613 * But dont want more than 1 break event.
614 * Use a kernel timer to periodically poll the rx line until
615 * the break is finished.
616 */
617 static void sci_schedule_break_timer(struct sci_port *port)
618 {
619 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
620 add_timer(&port->break_timer);
621 }
622 /* Ensure that two consecutive samples find the break over. */
623 static void sci_break_timer(unsigned long data)
624 {
625 struct sci_port *port = (struct sci_port *)data;
626
627 if (sci_rxd_in(&port->port) == 0) {
628 port->break_flag = 1;
629 sci_schedule_break_timer(port);
630 } else if (port->break_flag == 1) {
631 /* break is over. */
632 port->break_flag = 2;
633 sci_schedule_break_timer(port);
634 } else
635 port->break_flag = 0;
636 }
637
638 static inline int sci_handle_errors(struct uart_port *port)
639 {
640 int copied = 0;
641 unsigned short status = sci_in(port, SCxSR);
642 struct tty_struct *tty = port->info->tty;
643
644 if (status & SCxSR_ORER(port)) {
645 /* overrun error */
646 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
647 copied++;
648 pr_debug("sci: overrun error\n");
649 }
650
651 if (status & SCxSR_FER(port)) {
652 if (sci_rxd_in(port) == 0) {
653 /* Notify of BREAK */
654 struct sci_port *sci_port = (struct sci_port *)port;
655
656 if (!sci_port->break_flag) {
657 sci_port->break_flag = 1;
658 sci_schedule_break_timer(sci_port);
659
660 /* Do sysrq handling. */
661 if (uart_handle_break(port))
662 return 0;
663 pr_debug("sci: BREAK detected\n");
664 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
665 copied++;
666 }
667 } else {
668 /* frame error */
669 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
670 copied++;
671 pr_debug("sci: frame error\n");
672 }
673 }
674
675 if (status & SCxSR_PER(port)) {
676 /* parity error */
677 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
678 copied++;
679 pr_debug("sci: parity error\n");
680 }
681
682 if (copied)
683 tty_flip_buffer_push(tty);
684
685 return copied;
686 }
687
688 static inline int sci_handle_breaks(struct uart_port *port)
689 {
690 int copied = 0;
691 unsigned short status = sci_in(port, SCxSR);
692 struct tty_struct *tty = port->info->tty;
693 struct sci_port *s = &sci_ports[port->line];
694
695 if (uart_handle_break(port))
696 return 0;
697
698 if (!s->break_flag && status & SCxSR_BRK(port)) {
699 #if defined(CONFIG_CPU_SH3)
700 /* Debounce break */
701 s->break_flag = 1;
702 #endif
703 /* Notify of BREAK */
704 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
705 copied++;
706 pr_debug("sci: BREAK detected\n");
707 }
708
709 #if defined(SCIF_ORER)
710 /* XXX: Handle SCIF overrun error */
711 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
712 sci_out(port, SCLSR, 0);
713 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
714 copied++;
715 pr_debug("sci: overrun error\n");
716 }
717 }
718 #endif
719
720 if (copied)
721 tty_flip_buffer_push(tty);
722
723 return copied;
724 }
725
726 static irqreturn_t sci_rx_interrupt(int irq, void *port)
727 {
728 /* I think sci_receive_chars has to be called irrespective
729 * of whether the I_IXOFF is set, otherwise, how is the interrupt
730 * to be disabled?
731 */
732 sci_receive_chars(port);
733
734 return IRQ_HANDLED;
735 }
736
737 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
738 {
739 struct uart_port *port = ptr;
740
741 spin_lock_irq(&port->lock);
742 sci_transmit_chars(port);
743 spin_unlock_irq(&port->lock);
744
745 return IRQ_HANDLED;
746 }
747
748 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
749 {
750 struct uart_port *port = ptr;
751
752 /* Handle errors */
753 if (port->type == PORT_SCI) {
754 if (sci_handle_errors(port)) {
755 /* discard character in rx buffer */
756 sci_in(port, SCxSR);
757 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
758 }
759 } else {
760 #if defined(SCIF_ORER)
761 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
762 struct tty_struct *tty = port->info->tty;
763
764 sci_out(port, SCLSR, 0);
765 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
766 tty_flip_buffer_push(tty);
767 pr_debug("scif: overrun error\n");
768 }
769 #endif
770 sci_rx_interrupt(irq, ptr);
771 }
772
773 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
774
775 /* Kick the transmission */
776 sci_tx_interrupt(irq, ptr);
777
778 return IRQ_HANDLED;
779 }
780
781 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
782 {
783 struct uart_port *port = ptr;
784
785 /* Handle BREAKs */
786 sci_handle_breaks(port);
787 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
788
789 return IRQ_HANDLED;
790 }
791
792 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
793 {
794 unsigned short ssr_status, scr_status;
795 struct uart_port *port = ptr;
796
797 ssr_status = sci_in(port,SCxSR);
798 scr_status = sci_in(port,SCSCR);
799
800 /* Tx Interrupt */
801 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
802 sci_tx_interrupt(irq, ptr);
803 /* Rx Interrupt */
804 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
805 sci_rx_interrupt(irq, ptr);
806 /* Error Interrupt */
807 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
808 sci_er_interrupt(irq, ptr);
809 /* Break Interrupt */
810 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
811 sci_br_interrupt(irq, ptr);
812
813 return IRQ_HANDLED;
814 }
815
816 #ifdef CONFIG_CPU_FREQ
817 /*
818 * Here we define a transistion notifier so that we can update all of our
819 * ports' baud rate when the peripheral clock changes.
820 */
821 static int sci_notifier(struct notifier_block *self,
822 unsigned long phase, void *p)
823 {
824 struct cpufreq_freqs *freqs = p;
825 int i;
826
827 if ((phase == CPUFREQ_POSTCHANGE) ||
828 (phase == CPUFREQ_RESUMECHANGE)){
829 for (i = 0; i < SCI_NPORTS; i++) {
830 struct uart_port *port = &sci_ports[i].port;
831 struct clk *clk;
832
833 /*
834 * Update the uartclk per-port if frequency has
835 * changed, since it will no longer necessarily be
836 * consistent with the old frequency.
837 *
838 * Really we want to be able to do something like
839 * uart_change_speed() or something along those lines
840 * here to implicitly reset the per-port baud rate..
841 *
842 * Clean this up later..
843 */
844 clk = clk_get(NULL, "module_clk");
845 port->uartclk = clk_get_rate(clk) * 16;
846 clk_put(clk);
847 }
848
849 printk(KERN_INFO "%s: got a postchange notification "
850 "for cpu %d (old %d, new %d)\n",
851 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
852 }
853
854 return NOTIFY_OK;
855 }
856
857 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
858 #endif /* CONFIG_CPU_FREQ */
859
860 static int sci_request_irq(struct sci_port *port)
861 {
862 int i;
863 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
864 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
865 sci_br_interrupt,
866 };
867 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
868 "SCI Transmit Data Empty", "SCI Break" };
869
870 if (port->irqs[0] == port->irqs[1]) {
871 if (!port->irqs[0]) {
872 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
873 return -ENODEV;
874 }
875
876 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
877 IRQF_DISABLED, "sci", port)) {
878 printk(KERN_ERR "sci: Cannot allocate irq.\n");
879 return -ENODEV;
880 }
881 } else {
882 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
883 if (!port->irqs[i])
884 continue;
885 if (request_irq(port->irqs[i], handlers[i],
886 IRQF_DISABLED, desc[i], port)) {
887 printk(KERN_ERR "sci: Cannot allocate irq.\n");
888 return -ENODEV;
889 }
890 }
891 }
892
893 return 0;
894 }
895
896 static void sci_free_irq(struct sci_port *port)
897 {
898 int i;
899
900 if (port->irqs[0] == port->irqs[1]) {
901 if (!port->irqs[0])
902 printk("sci: sci_free_irq error\n");
903 else
904 free_irq(port->irqs[0], port);
905 } else {
906 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
907 if (!port->irqs[i])
908 continue;
909
910 free_irq(port->irqs[i], port);
911 }
912 }
913 }
914
915 static unsigned int sci_tx_empty(struct uart_port *port)
916 {
917 /* Can't detect */
918 return TIOCSER_TEMT;
919 }
920
921 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
922 {
923 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
924 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
925 /* If you have signals for DTR and DCD, please implement here. */
926 }
927
928 static unsigned int sci_get_mctrl(struct uart_port *port)
929 {
930 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
931 and CTS/RTS */
932
933 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
934 }
935
936 static void sci_start_tx(struct uart_port *port)
937 {
938 unsigned short ctrl;
939
940 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
941 ctrl = sci_in(port, SCSCR);
942 ctrl |= SCI_CTRL_FLAGS_TIE;
943 sci_out(port, SCSCR, ctrl);
944 }
945
946 static void sci_stop_tx(struct uart_port *port)
947 {
948 unsigned short ctrl;
949
950 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
951 ctrl = sci_in(port, SCSCR);
952 ctrl &= ~SCI_CTRL_FLAGS_TIE;
953 sci_out(port, SCSCR, ctrl);
954 }
955
956 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
957 {
958 unsigned short ctrl;
959
960 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
961 ctrl = sci_in(port, SCSCR);
962 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
963 sci_out(port, SCSCR, ctrl);
964 }
965
966 static void sci_stop_rx(struct uart_port *port)
967 {
968 unsigned short ctrl;
969
970 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
971 ctrl = sci_in(port, SCSCR);
972 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
973 sci_out(port, SCSCR, ctrl);
974 }
975
976 static void sci_enable_ms(struct uart_port *port)
977 {
978 /* Nothing here yet .. */
979 }
980
981 static void sci_break_ctl(struct uart_port *port, int break_state)
982 {
983 /* Nothing here yet .. */
984 }
985
986 static int sci_startup(struct uart_port *port)
987 {
988 struct sci_port *s = &sci_ports[port->line];
989
990 if (s->enable)
991 s->enable(port);
992
993 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
994 s->clk = clk_get(NULL, "module_clk");
995 #endif
996
997 sci_request_irq(s);
998 sci_start_tx(port);
999 sci_start_rx(port, 1);
1000
1001 return 0;
1002 }
1003
1004 static void sci_shutdown(struct uart_port *port)
1005 {
1006 struct sci_port *s = &sci_ports[port->line];
1007
1008 sci_stop_rx(port);
1009 sci_stop_tx(port);
1010 sci_free_irq(s);
1011
1012 if (s->disable)
1013 s->disable(port);
1014
1015 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1016 clk_put(s->clk);
1017 s->clk = NULL;
1018 #endif
1019 }
1020
1021 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1022 struct ktermios *old)
1023 {
1024 struct sci_port *s = &sci_ports[port->line];
1025 unsigned int status, baud, smr_val;
1026 int t;
1027
1028 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1029
1030 switch (baud) {
1031 case 0:
1032 t = -1;
1033 break;
1034 default:
1035 {
1036 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1037 t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
1038 #else
1039 t = SCBRR_VALUE(baud);
1040 #endif
1041 break;
1042 }
1043 }
1044
1045 do {
1046 status = sci_in(port, SCxSR);
1047 } while (!(status & SCxSR_TEND(port)));
1048
1049 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1050
1051 #if !defined(SCI_ONLY)
1052 if (port->type == PORT_SCIF)
1053 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1054 #endif
1055
1056 smr_val = sci_in(port, SCSMR) & 3;
1057 if ((termios->c_cflag & CSIZE) == CS7)
1058 smr_val |= 0x40;
1059 if (termios->c_cflag & PARENB)
1060 smr_val |= 0x20;
1061 if (termios->c_cflag & PARODD)
1062 smr_val |= 0x30;
1063 if (termios->c_cflag & CSTOPB)
1064 smr_val |= 0x08;
1065
1066 uart_update_timeout(port, termios->c_cflag, baud);
1067
1068 sci_out(port, SCSMR, smr_val);
1069
1070 if (t > 0) {
1071 if(t >= 256) {
1072 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1073 t >>= 2;
1074 } else {
1075 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1076 }
1077 sci_out(port, SCBRR, t);
1078 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1079 }
1080
1081 if (likely(s->init_pins))
1082 s->init_pins(port, termios->c_cflag);
1083
1084 sci_out(port, SCSCR, SCSCR_INIT(port));
1085
1086 if ((termios->c_cflag & CREAD) != 0)
1087 sci_start_rx(port,0);
1088 }
1089
1090 static const char *sci_type(struct uart_port *port)
1091 {
1092 switch (port->type) {
1093 case PORT_SCI: return "sci";
1094 case PORT_SCIF: return "scif";
1095 case PORT_IRDA: return "irda";
1096 }
1097
1098 return 0;
1099 }
1100
1101 static void sci_release_port(struct uart_port *port)
1102 {
1103 /* Nothing here yet .. */
1104 }
1105
1106 static int sci_request_port(struct uart_port *port)
1107 {
1108 /* Nothing here yet .. */
1109 return 0;
1110 }
1111
1112 static void sci_config_port(struct uart_port *port, int flags)
1113 {
1114 struct sci_port *s = &sci_ports[port->line];
1115
1116 port->type = s->type;
1117
1118 switch (port->type) {
1119 case PORT_SCI:
1120 s->init_pins = sci_init_pins_sci;
1121 break;
1122 case PORT_SCIF:
1123 s->init_pins = sci_init_pins_scif;
1124 break;
1125 case PORT_IRDA:
1126 s->init_pins = sci_init_pins_irda;
1127 break;
1128 }
1129
1130 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1131 if (port->mapbase == 0)
1132 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1133
1134 port->membase = (void __iomem *)port->mapbase;
1135 #endif
1136 }
1137
1138 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1139 {
1140 struct sci_port *s = &sci_ports[port->line];
1141
1142 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1143 return -EINVAL;
1144 if (ser->baud_base < 2400)
1145 /* No paper tape reader for Mitch.. */
1146 return -EINVAL;
1147
1148 return 0;
1149 }
1150
1151 static struct uart_ops sci_uart_ops = {
1152 .tx_empty = sci_tx_empty,
1153 .set_mctrl = sci_set_mctrl,
1154 .get_mctrl = sci_get_mctrl,
1155 .start_tx = sci_start_tx,
1156 .stop_tx = sci_stop_tx,
1157 .stop_rx = sci_stop_rx,
1158 .enable_ms = sci_enable_ms,
1159 .break_ctl = sci_break_ctl,
1160 .startup = sci_startup,
1161 .shutdown = sci_shutdown,
1162 .set_termios = sci_set_termios,
1163 .type = sci_type,
1164 .release_port = sci_release_port,
1165 .request_port = sci_request_port,
1166 .config_port = sci_config_port,
1167 .verify_port = sci_verify_port,
1168 };
1169
1170 static void __init sci_init_ports(void)
1171 {
1172 static int first = 1;
1173 int i;
1174
1175 if (!first)
1176 return;
1177
1178 first = 0;
1179
1180 for (i = 0; i < SCI_NPORTS; i++) {
1181 sci_ports[i].port.ops = &sci_uart_ops;
1182 sci_ports[i].port.iotype = UPIO_MEM;
1183 sci_ports[i].port.line = i;
1184 sci_ports[i].port.fifosize = 1;
1185
1186 #if defined(__H8300H__) || defined(__H8300S__)
1187 #ifdef __H8300S__
1188 sci_ports[i].enable = h8300_sci_enable;
1189 sci_ports[i].disable = h8300_sci_disable;
1190 #endif
1191 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1192 #elif defined(CONFIG_SUPERH64)
1193 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1194 #else
1195 /*
1196 * XXX: We should use a proper SCI/SCIF clock
1197 */
1198 {
1199 struct clk *clk = clk_get(NULL, "module_clk");
1200 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1201 clk_put(clk);
1202 }
1203 #endif
1204
1205 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1206 sci_ports[i].break_timer.function = sci_break_timer;
1207
1208 init_timer(&sci_ports[i].break_timer);
1209 }
1210 }
1211
1212 int __init early_sci_setup(struct uart_port *port)
1213 {
1214 if (unlikely(port->line > SCI_NPORTS))
1215 return -ENODEV;
1216
1217 sci_init_ports();
1218
1219 sci_ports[port->line].port.membase = port->membase;
1220 sci_ports[port->line].port.mapbase = port->mapbase;
1221 sci_ports[port->line].port.type = port->type;
1222
1223 return 0;
1224 }
1225
1226 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1227 /*
1228 * Print a string to the serial port trying not to disturb
1229 * any possible real use of the port...
1230 */
1231 static void serial_console_write(struct console *co, const char *s,
1232 unsigned count)
1233 {
1234 put_string(serial_console_port, s, count);
1235 }
1236
1237 static int __init serial_console_setup(struct console *co, char *options)
1238 {
1239 struct uart_port *port;
1240 int baud = 115200;
1241 int bits = 8;
1242 int parity = 'n';
1243 int flow = 'n';
1244 int ret;
1245
1246 /*
1247 * Check whether an invalid uart number has been specified, and
1248 * if so, search for the first available port that does have
1249 * console support.
1250 */
1251 if (co->index >= SCI_NPORTS)
1252 co->index = 0;
1253
1254 serial_console_port = &sci_ports[co->index];
1255 port = &serial_console_port->port;
1256
1257 /*
1258 * Also need to check port->type, we don't actually have any
1259 * UPIO_PORT ports, but uart_report_port() handily misreports
1260 * it anyways if we don't have a port available by the time this is
1261 * called.
1262 */
1263 if (!port->type)
1264 return -ENODEV;
1265 if (!port->membase || !port->mapbase)
1266 return -ENODEV;
1267
1268 port->type = serial_console_port->type;
1269
1270 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1271 if (!serial_console_port->clk)
1272 serial_console_port->clk = clk_get(NULL, "module_clk");
1273 #endif
1274
1275 if (port->flags & UPF_IOREMAP)
1276 sci_config_port(port, 0);
1277
1278 if (serial_console_port->enable)
1279 serial_console_port->enable(port);
1280
1281 if (options)
1282 uart_parse_options(options, &baud, &parity, &bits, &flow);
1283
1284 ret = uart_set_options(port, co, baud, parity, bits, flow);
1285 #if defined(__H8300H__) || defined(__H8300S__)
1286 /* disable rx interrupt */
1287 if (ret == 0)
1288 sci_stop_rx(port);
1289 #endif
1290 return ret;
1291 }
1292
1293 static struct console serial_console = {
1294 .name = "ttySC",
1295 .device = uart_console_device,
1296 .write = serial_console_write,
1297 .setup = serial_console_setup,
1298 .flags = CON_PRINTBUFFER,
1299 .index = -1,
1300 .data = &sci_uart_driver,
1301 };
1302
1303 static int __init sci_console_init(void)
1304 {
1305 sci_init_ports();
1306 register_console(&serial_console);
1307 return 0;
1308 }
1309 console_initcall(sci_console_init);
1310 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1311
1312 #ifdef CONFIG_SH_KGDB_CONSOLE
1313 /*
1314 * FIXME: Most of this can go away.. at the moment, we rely on
1315 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1316 * most of that can easily be done here instead.
1317 *
1318 * For the time being, just accept the values that were parsed earlier..
1319 */
1320 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1321 int *parity, int *bits)
1322 {
1323 *baud = kgdb_baud;
1324 *parity = tolower(kgdb_parity);
1325 *bits = kgdb_bits - '0';
1326 }
1327
1328 /*
1329 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1330 * care of the early-on initialization for kgdb, regardless of whether we
1331 * actually use kgdb as a console or not.
1332 *
1333 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1334 */
1335 int __init kgdb_console_setup(struct console *co, char *options)
1336 {
1337 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1338 int baud = 38400;
1339 int bits = 8;
1340 int parity = 'n';
1341 int flow = 'n';
1342
1343 if (co->index != kgdb_portnum)
1344 co->index = kgdb_portnum;
1345
1346 kgdb_sci_port = &sci_ports[co->index];
1347 port = &kgdb_sci_port->port;
1348
1349 /*
1350 * Also need to check port->type, we don't actually have any
1351 * UPIO_PORT ports, but uart_report_port() handily misreports
1352 * it anyways if we don't have a port available by the time this is
1353 * called.
1354 */
1355 if (!port->type)
1356 return -ENODEV;
1357 if (!port->membase || !port->mapbase)
1358 return -ENODEV;
1359
1360 if (options)
1361 uart_parse_options(options, &baud, &parity, &bits, &flow);
1362 else
1363 kgdb_console_get_options(port, &baud, &parity, &bits);
1364
1365 kgdb_getchar = kgdb_sci_getchar;
1366 kgdb_putchar = kgdb_sci_putchar;
1367
1368 return uart_set_options(port, co, baud, parity, bits, flow);
1369 }
1370
1371 static struct console kgdb_console = {
1372 .name = "ttySC",
1373 .device = uart_console_device,
1374 .write = kgdb_console_write,
1375 .setup = kgdb_console_setup,
1376 .flags = CON_PRINTBUFFER,
1377 .index = -1,
1378 .data = &sci_uart_driver,
1379 };
1380
1381 /* Register the KGDB console so we get messages (d'oh!) */
1382 static int __init kgdb_console_init(void)
1383 {
1384 sci_init_ports();
1385 register_console(&kgdb_console);
1386 return 0;
1387 }
1388 console_initcall(kgdb_console_init);
1389 #endif /* CONFIG_SH_KGDB_CONSOLE */
1390
1391 #if defined(CONFIG_SH_KGDB_CONSOLE)
1392 #define SCI_CONSOLE &kgdb_console
1393 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1394 #define SCI_CONSOLE &serial_console
1395 #else
1396 #define SCI_CONSOLE 0
1397 #endif
1398
1399 static char banner[] __initdata =
1400 KERN_INFO "SuperH SCI(F) driver initialized\n";
1401
1402 static struct uart_driver sci_uart_driver = {
1403 .owner = THIS_MODULE,
1404 .driver_name = "sci",
1405 .dev_name = "ttySC",
1406 .major = SCI_MAJOR,
1407 .minor = SCI_MINOR_START,
1408 .nr = SCI_NPORTS,
1409 .cons = SCI_CONSOLE,
1410 };
1411
1412 /*
1413 * Register a set of serial devices attached to a platform device. The
1414 * list is terminated with a zero flags entry, which means we expect
1415 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1416 * remapping (such as sh64) should also set UPF_IOREMAP.
1417 */
1418 static int __devinit sci_probe(struct platform_device *dev)
1419 {
1420 struct plat_sci_port *p = dev->dev.platform_data;
1421 int i;
1422
1423 for (i = 0; p && p->flags != 0; p++, i++) {
1424 struct sci_port *sciport = &sci_ports[i];
1425
1426 /* Sanity check */
1427 if (unlikely(i == SCI_NPORTS)) {
1428 dev_notice(&dev->dev, "Attempting to register port "
1429 "%d when only %d are available.\n",
1430 i+1, SCI_NPORTS);
1431 dev_notice(&dev->dev, "Consider bumping "
1432 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1433 break;
1434 }
1435
1436 sciport->port.mapbase = p->mapbase;
1437
1438 /*
1439 * For the simple (and majority of) cases where we don't need
1440 * to do any remapping, just cast the cookie directly.
1441 */
1442 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1443 p->membase = (void __iomem *)p->mapbase;
1444
1445 sciport->port.membase = p->membase;
1446
1447 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1448 sciport->port.flags = p->flags;
1449 sciport->port.dev = &dev->dev;
1450
1451 sciport->type = sciport->port.type = p->type;
1452
1453 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1454
1455 uart_add_one_port(&sci_uart_driver, &sciport->port);
1456 }
1457
1458 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1459 kgdb_sci_port = &sci_ports[kgdb_portnum];
1460 kgdb_getchar = kgdb_sci_getchar;
1461 kgdb_putchar = kgdb_sci_putchar;
1462 #endif
1463
1464 #ifdef CONFIG_CPU_FREQ
1465 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1466 dev_info(&dev->dev, "CPU frequency notifier registered\n");
1467 #endif
1468
1469 #ifdef CONFIG_SH_STANDARD_BIOS
1470 sh_bios_gdb_detach();
1471 #endif
1472
1473 return 0;
1474 }
1475
1476 static int __devexit sci_remove(struct platform_device *dev)
1477 {
1478 int i;
1479
1480 for (i = 0; i < SCI_NPORTS; i++)
1481 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1482
1483 return 0;
1484 }
1485
1486 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1487 {
1488 int i;
1489
1490 for (i = 0; i < SCI_NPORTS; i++) {
1491 struct sci_port *p = &sci_ports[i];
1492
1493 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1494 uart_suspend_port(&sci_uart_driver, &p->port);
1495 }
1496
1497 return 0;
1498 }
1499
1500 static int sci_resume(struct platform_device *dev)
1501 {
1502 int i;
1503
1504 for (i = 0; i < SCI_NPORTS; i++) {
1505 struct sci_port *p = &sci_ports[i];
1506
1507 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1508 uart_resume_port(&sci_uart_driver, &p->port);
1509 }
1510
1511 return 0;
1512 }
1513
1514 static struct platform_driver sci_driver = {
1515 .probe = sci_probe,
1516 .remove = __devexit_p(sci_remove),
1517 .suspend = sci_suspend,
1518 .resume = sci_resume,
1519 .driver = {
1520 .name = "sh-sci",
1521 .owner = THIS_MODULE,
1522 },
1523 };
1524
1525 static int __init sci_init(void)
1526 {
1527 int ret;
1528
1529 printk(banner);
1530
1531 sci_init_ports();
1532
1533 ret = uart_register_driver(&sci_uart_driver);
1534 if (likely(ret == 0)) {
1535 ret = platform_driver_register(&sci_driver);
1536 if (unlikely(ret))
1537 uart_unregister_driver(&sci_uart_driver);
1538 }
1539
1540 return ret;
1541 }
1542
1543 static void __exit sci_exit(void)
1544 {
1545 platform_driver_unregister(&sci_driver);
1546 uart_unregister_driver(&sci_uart_driver);
1547 }
1548
1549 module_init(sci_init);
1550 module_exit(sci_exit);
1551
1552 MODULE_LICENSE("GPL");
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