drivers/net/qla3xxx.h

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7 #ifndef _QLA3XXX_H_
   8 #define _QLA3XXX_H_
   9
  10 /*
  11  * IOCB Definitions...
  12  */
  13 #pragma pack(1)
  14
  15 #define OPCODE_OB_MAC_IOCB_FN0          0x01
  16 #define OPCODE_OB_MAC_IOCB_FN2          0x21
  17 #define OPCODE_OB_TCP_IOCB_FN0          0x03
  18 #define OPCODE_OB_TCP_IOCB_FN2          0x23
  19 #define OPCODE_UPDATE_NCB_IOCB_FN0      0x00
  20 #define OPCODE_UPDATE_NCB_IOCB_FN2      0x20
  21
  22 #define OPCODE_UPDATE_NCB_IOCB      0xF0
  23 #define OPCODE_IB_MAC_IOCB          0xF9
  24 #define OPCODE_IB_3032_MAC_IOCB     0x09
  25 #define OPCODE_IB_IP_IOCB           0xFA
  26 #define OPCODE_IB_3032_IP_IOCB      0x0A
  27 #define OPCODE_IB_TCP_IOCB          0xFB
  28 #define OPCODE_DUMP_PROTO_IOCB      0xFE
  29 #define OPCODE_BUFFER_ALERT_IOCB    0xFB
  30
  31 #define OPCODE_FUNC_ID_MASK                 0x30
  32 #define OUTBOUND_MAC_IOCB                   0x01        /* plus function bits */
  33 #define OUTBOUND_TCP_IOCB                   0x03        /* plus function bits */
  34 #define UPDATE_NCB_IOCB                     0x00        /* plus function bits */
  35
  36 #define FN0_MA_BITS_MASK    0x00
  37 #define FN1_MA_BITS_MASK    0x80
  38
  39 struct ob_mac_iocb_req {
  40         u8 opcode;
  41         u8 flags;
  42 #define OB_MAC_IOCB_REQ_MA  0xe0
  43 #define OB_MAC_IOCB_REQ_F   0x10
  44 #define OB_MAC_IOCB_REQ_X   0x08
  45 #define OB_MAC_IOCB_REQ_D   0x02
  46 #define OB_MAC_IOCB_REQ_I   0x01
  47         u8 flags1;
  48 #define OB_3032MAC_IOCB_REQ_IC  0x04
  49 #define OB_3032MAC_IOCB_REQ_TC  0x02
  50 #define OB_3032MAC_IOCB_REQ_UC  0x01
  51         u8 reserved0;
  52
  53         u32 transaction_id;     /* opaque for hardware */
  54         __le16 data_len;
  55         u8 ip_hdr_off;
  56         u8 ip_hdr_len;
  57         __le32 reserved1;
  58         __le32 reserved2;
  59         __le32 buf_addr0_low;
  60         __le32 buf_addr0_high;
  61         __le32 buf_0_len;
  62         __le32 buf_addr1_low;
  63         __le32 buf_addr1_high;
  64         __le32 buf_1_len;
  65         __le32 buf_addr2_low;
  66         __le32 buf_addr2_high;
  67         __le32 buf_2_len;
  68         __le32 reserved3;
  69         __le32 reserved4;
  70 };
  71 /*
  72  * The following constants define control bits for buffer
  73  * length fields for all IOCB's.
  74  */
  75 #define OB_MAC_IOCB_REQ_E   0x80000000  /* Last valid buffer in list. */
  76 #define OB_MAC_IOCB_REQ_C   0x40000000  /* points to an OAL. (continuation) */
  77 #define OB_MAC_IOCB_REQ_L   0x20000000  /* Auburn local address pointer. */
  78 #define OB_MAC_IOCB_REQ_R   0x10000000  /* 32-bit address pointer. */
  79
  80 struct ob_mac_iocb_rsp {
  81         u8 opcode;
  82         u8 flags;
  83 #define OB_MAC_IOCB_RSP_P   0x08
  84 #define OB_MAC_IOCB_RSP_L   0x04
  85 #define OB_MAC_IOCB_RSP_S   0x02
  86 #define OB_MAC_IOCB_RSP_I   0x01
  87
  88         __le16 reserved0;
  89         u32 transaction_id;     /* opaque for hardware */
  90         __le32 reserved1;
  91         __le32 reserved2;
  92 };
  93
  94 struct ib_mac_iocb_rsp {
  95         u8 opcode;
  96 #define IB_MAC_IOCB_RSP_V   0x80
  97         u8 flags;
  98 #define IB_MAC_IOCB_RSP_S   0x80
  99 #define IB_MAC_IOCB_RSP_H1  0x40
 100 #define IB_MAC_IOCB_RSP_H0  0x20
 101 #define IB_MAC_IOCB_RSP_B   0x10
 102 #define IB_MAC_IOCB_RSP_M   0x08
 103 #define IB_MAC_IOCB_RSP_MA  0x07
 104
 105         __le16 length;
 106         __le32 reserved;
 107         __le32 ial_low;
 108         __le32 ial_high;
 109
 110 };
 111
 112 struct ob_ip_iocb_req {
 113         u8 opcode;
 114         __le16 flags;
 115 #define OB_IP_IOCB_REQ_O        0x100
 116 #define OB_IP_IOCB_REQ_H        0x008
 117 #define OB_IP_IOCB_REQ_U        0x004
 118 #define OB_IP_IOCB_REQ_D        0x002
 119 #define OB_IP_IOCB_REQ_I        0x001
 120
 121         u8 reserved0;
 122
 123         __le32 transaction_id;
 124         __le16 data_len;
 125         __le16 reserved1;
 126         __le32 hncb_ptr_low;
 127         __le32 hncb_ptr_high;
 128         __le32 buf_addr0_low;
 129         __le32 buf_addr0_high;
 130         __le32 buf_0_len;
 131         __le32 buf_addr1_low;
 132         __le32 buf_addr1_high;
 133         __le32 buf_1_len;
 134         __le32 buf_addr2_low;
 135         __le32 buf_addr2_high;
 136         __le32 buf_2_len;
 137         __le32 reserved2;
 138         __le32 reserved3;
 139 };
 140
 141 /* defines for BufferLength fields above */
 142 #define OB_IP_IOCB_REQ_E    0x80000000
 143 #define OB_IP_IOCB_REQ_C    0x40000000
 144 #define OB_IP_IOCB_REQ_L    0x20000000
 145 #define OB_IP_IOCB_REQ_R    0x10000000
 146
 147 struct ob_ip_iocb_rsp {
 148         u8 opcode;
 149         u8 flags;
 150 #define OB_MAC_IOCB_RSP_H       0x10
 151 #define OB_MAC_IOCB_RSP_E       0x08
 152 #define OB_MAC_IOCB_RSP_L       0x04
 153 #define OB_MAC_IOCB_RSP_S       0x02
 154 #define OB_MAC_IOCB_RSP_I       0x01
 155
 156         __le16 reserved0;
 157         __le32 transaction_id;
 158         __le32 reserved1;
 159         __le32 reserved2;
 160 };
 161
 162 struct ob_tcp_iocb_req {
 163         u8 opcode;
 164
 165         u8 flags0;
 166 #define OB_TCP_IOCB_REQ_P       0x80
 167 #define OB_TCP_IOCB_REQ_CI      0x20
 168 #define OB_TCP_IOCB_REQ_H       0x10
 169 #define OB_TCP_IOCB_REQ_LN      0x08
 170 #define OB_TCP_IOCB_REQ_K       0x04
 171 #define OB_TCP_IOCB_REQ_D       0x02
 172 #define OB_TCP_IOCB_REQ_I       0x01
 173
 174         u8 flags1;
 175 #define OB_TCP_IOCB_REQ_OSM     0x40
 176 #define OB_TCP_IOCB_REQ_URG     0x20
 177 #define OB_TCP_IOCB_REQ_ACK     0x10
 178 #define OB_TCP_IOCB_REQ_PSH     0x08
 179 #define OB_TCP_IOCB_REQ_RST     0x04
 180 #define OB_TCP_IOCB_REQ_SYN     0x02
 181 #define OB_TCP_IOCB_REQ_FIN     0x01
 182
 183         u8 options_len;
 184 #define OB_TCP_IOCB_REQ_OMASK   0xF0
 185 #define OB_TCP_IOCB_REQ_SHIFT   4
 186
 187         __le32 transaction_id;
 188         __le32 data_len;
 189         __le32 hncb_ptr_low;
 190         __le32 hncb_ptr_high;
 191         __le32 buf_addr0_low;
 192         __le32 buf_addr0_high;
 193         __le32 buf_0_len;
 194         __le32 buf_addr1_low;
 195         __le32 buf_addr1_high;
 196         __le32 buf_1_len;
 197         __le32 buf_addr2_low;
 198         __le32 buf_addr2_high;
 199         __le32 buf_2_len;
 200         __le32 time_stamp;
 201         __le32 reserved1;
 202 };
 203
 204 struct ob_tcp_iocb_rsp {
 205         u8 opcode;
 206
 207         u8 flags0;
 208 #define OB_TCP_IOCB_RSP_C       0x20
 209 #define OB_TCP_IOCB_RSP_H       0x10
 210 #define OB_TCP_IOCB_RSP_LN      0x08
 211 #define OB_TCP_IOCB_RSP_K       0x04
 212 #define OB_TCP_IOCB_RSP_D       0x02
 213 #define OB_TCP_IOCB_RSP_I       0x01
 214
 215         u8 flags1;
 216 #define OB_TCP_IOCB_RSP_E       0x10
 217 #define OB_TCP_IOCB_RSP_W       0x08
 218 #define OB_TCP_IOCB_RSP_P       0x04
 219 #define OB_TCP_IOCB_RSP_T       0x02
 220 #define OB_TCP_IOCB_RSP_F       0x01
 221
 222         u8 state;
 223 #define OB_TCP_IOCB_RSP_SMASK   0xF0
 224 #define OB_TCP_IOCB_RSP_SHIFT   4
 225
 226         __le32 transaction_id;
 227         __le32 local_ncb_ptr;
 228         __le32 reserved0;
 229 };
 230
 231 struct ib_ip_iocb_rsp {
 232         u8 opcode;
 233 #define IB_IP_IOCB_RSP_3032_V   0x80
 234 #define IB_IP_IOCB_RSP_3032_O   0x40
 235 #define IB_IP_IOCB_RSP_3032_I   0x20
 236 #define IB_IP_IOCB_RSP_3032_R   0x10
 237         u8 flags;
 238 #define IB_IP_IOCB_RSP_S        0x80
 239 #define IB_IP_IOCB_RSP_H1       0x40
 240 #define IB_IP_IOCB_RSP_H0       0x20
 241 #define IB_IP_IOCB_RSP_B        0x10
 242 #define IB_IP_IOCB_RSP_M        0x08
 243 #define IB_IP_IOCB_RSP_MA       0x07
 244
 245         __le16 length;
 246         __le16 checksum;
 247 #define IB_IP_IOCB_RSP_3032_ICE         0x01
 248 #define IB_IP_IOCB_RSP_3032_CE          0x02
 249 #define IB_IP_IOCB_RSP_3032_NUC         0x04
 250 #define IB_IP_IOCB_RSP_3032_UDP         0x08
 251 #define IB_IP_IOCB_RSP_3032_TCP         0x10
 252 #define IB_IP_IOCB_RSP_3032_IPE         0x20
 253         __le16 reserved;
 254 #define IB_IP_IOCB_RSP_R        0x01
 255         __le32 ial_low;
 256         __le32 ial_high;
 257 };
 258
 259 struct ib_tcp_iocb_rsp {
 260         u8 opcode;
 261         u8 flags;
 262 #define IB_TCP_IOCB_RSP_P       0x80
 263 #define IB_TCP_IOCB_RSP_T       0x40
 264 #define IB_TCP_IOCB_RSP_D       0x20
 265 #define IB_TCP_IOCB_RSP_N       0x10
 266 #define IB_TCP_IOCB_RSP_IP      0x03
 267 #define IB_TCP_FLAG_MASK        0xf0
 268 #define IB_TCP_FLAG_IOCB_SYN    0x00
 269
 270 #define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)
 271
 272         __le16 length;
 273         __le32 hncb_ref_num;
 274         __le32 ial_low;
 275         __le32 ial_high;
 276 };
 277
 278 struct net_rsp_iocb {
 279         u8 opcode;
 280         u8 flags;
 281         __le16 reserved0;
 282         __le32 reserved[3];
 283 };
 284 #pragma pack()
 285
 286 /*
 287  * Register Definitions...
 288  */
 289 #define PORT0_PHY_ADDRESS   0x1e00
 290 #define PORT1_PHY_ADDRESS   0x1f00
 291
 292 #define ETHERNET_CRC_SIZE   4
 293
 294 #define MII_SCAN_REGISTER 0x00000001
 295
 296 #define PHY_ID_0_REG    2
 297 #define PHY_ID_1_REG    3
 298
 299 #define PHY_OUI_1_MASK       0xfc00
 300 #define PHY_MODEL_MASK       0x03f0
 301
 302 /*  Address for the Agere Phy */
 303 #define MII_AGERE_ADDR_1  0x00001000
 304 #define MII_AGERE_ADDR_2  0x00001100
 305
 306 /* 32-bit ispControlStatus */
 307 enum {
 308         ISP_CONTROL_NP_MASK = 0x0003,
 309         ISP_CONTROL_NP_PCSR = 0x0000,
 310         ISP_CONTROL_NP_HMCR = 0x0001,
 311         ISP_CONTROL_NP_LRAMCR = 0x0002,
 312         ISP_CONTROL_NP_PSR = 0x0003,
 313         ISP_CONTROL_RI = 0x0008,
 314         ISP_CONTROL_CI = 0x0010,
 315         ISP_CONTROL_PI = 0x0020,
 316         ISP_CONTROL_IN = 0x0040,
 317         ISP_CONTROL_BE = 0x0080,
 318         ISP_CONTROL_FN_MASK = 0x0700,
 319         ISP_CONTROL_FN0_NET = 0x0400,
 320         ISP_CONTROL_FN0_SCSI = 0x0500,
 321         ISP_CONTROL_FN1_NET = 0x0600,
 322         ISP_CONTROL_FN1_SCSI = 0x0700,
 323         ISP_CONTROL_LINK_DN_0 = 0x0800,
 324         ISP_CONTROL_LINK_DN_1 = 0x1000,
 325         ISP_CONTROL_FSR = 0x2000,
 326         ISP_CONTROL_FE = 0x4000,
 327         ISP_CONTROL_SR = 0x8000,
 328 };
 329
 330 /* 32-bit ispInterruptMaskReg */
 331 enum {
 332         ISP_IMR_ENABLE_INT = 0x0004,
 333         ISP_IMR_DISABLE_RESET_INT = 0x0008,
 334         ISP_IMR_DISABLE_CMPL_INT = 0x0010,
 335         ISP_IMR_DISABLE_PROC_INT = 0x0020,
 336 };
 337
 338 /* 32-bit serialPortInterfaceReg */
 339 enum {
 340         ISP_SERIAL_PORT_IF_CLK = 0x0001,
 341         ISP_SERIAL_PORT_IF_CS = 0x0002,
 342         ISP_SERIAL_PORT_IF_D0 = 0x0004,
 343         ISP_SERIAL_PORT_IF_DI = 0x0008,
 344         ISP_NVRAM_MASK = (0x000F << 16),
 345         ISP_SERIAL_PORT_IF_WE = 0x0010,
 346         ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
 347         ISP_SERIAL_PORT_IF_SCI = 0x0400,
 348         ISP_SERIAL_PORT_IF_SC0 = 0x0800,
 349         ISP_SERIAL_PORT_IF_SCE = 0x1000,
 350         ISP_SERIAL_PORT_IF_SDI = 0x2000,
 351         ISP_SERIAL_PORT_IF_SDO = 0x4000,
 352         ISP_SERIAL_PORT_IF_SDE = 0x8000,
 353         ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
 354 };
 355
 356 /* semaphoreReg */
 357 enum {
 358         QL_RESOURCE_MASK_BASE_CODE = 0x7,
 359         QL_RESOURCE_BITS_BASE_CODE = 0x4,
 360         QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
 361         QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
 362         QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
 363         QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
 364         QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
 365         QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
 366         QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
 367         QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
 368         QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
 369         QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
 370 };
 371
 372  /*
 373   * QL3XXX memory-mapped registers
 374   * QL3XXX has 4 "pages" of registers, each page occupying
 375   * 256 bytes.  Each page has a "common" area at the start and then
 376   * page-specific registers after that.
 377   */
 378 struct ql3xxx_common_registers {
 379         u32 MB0;                /* Offset 0x00 */
 380         u32 MB1;                /* Offset 0x04 */
 381         u32 MB2;                /* Offset 0x08 */
 382         u32 MB3;                /* Offset 0x0c */
 383         u32 MB4;                /* Offset 0x10 */
 384         u32 MB5;                /* Offset 0x14 */
 385         u32 MB6;                /* Offset 0x18 */
 386         u32 MB7;                /* Offset 0x1c */
 387         u32 flashBiosAddr;
 388         u32 flashBiosData;
 389         u32 ispControlStatus;
 390         u32 ispInterruptMaskReg;
 391         u32 serialPortInterfaceReg;
 392         u32 semaphoreReg;
 393         u32 reqQProducerIndex;
 394         u32 rspQConsumerIndex;
 395
 396         u32 rxLargeQProducerIndex;
 397         u32 rxSmallQProducerIndex;
 398         u32 arcMadiCommand;
 399         u32 arcMadiData;
 400 };
 401
 402 enum {
 403         EXT_HW_CONFIG_SP_MASK = 0x0006,
 404         EXT_HW_CONFIG_SP_NONE = 0x0000,
 405         EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
 406         EXT_HW_CONFIG_SP_ECC = 0x0004,
 407         EXT_HW_CONFIG_SP_ECCx = 0x0006,
 408         EXT_HW_CONFIG_SIZE_MASK = 0x0060,
 409         EXT_HW_CONFIG_SIZE_128M = 0x0000,
 410         EXT_HW_CONFIG_SIZE_256M = 0x0020,
 411         EXT_HW_CONFIG_SIZE_512M = 0x0040,
 412         EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
 413         EXT_HW_CONFIG_PD = 0x0080,
 414         EXT_HW_CONFIG_FW = 0x0200,
 415         EXT_HW_CONFIG_US = 0x0400,
 416         EXT_HW_CONFIG_DCS_MASK = 0x1800,
 417         EXT_HW_CONFIG_DCS_9MA = 0x0000,
 418         EXT_HW_CONFIG_DCS_15MA = 0x0800,
 419         EXT_HW_CONFIG_DCS_18MA = 0x1000,
 420         EXT_HW_CONFIG_DCS_24MA = 0x1800,
 421         EXT_HW_CONFIG_DDS_MASK = 0x6000,
 422         EXT_HW_CONFIG_DDS_9MA = 0x0000,
 423         EXT_HW_CONFIG_DDS_15MA = 0x2000,
 424         EXT_HW_CONFIG_DDS_18MA = 0x4000,
 425         EXT_HW_CONFIG_DDS_24MA = 0x6000,
 426 };
 427
 428 /* InternalChipConfig */
 429 enum {
 430         INTERNAL_CHIP_DM = 0x0001,
 431         INTERNAL_CHIP_SD = 0x0002,
 432         INTERNAL_CHIP_RAP_MASK = 0x000C,
 433         INTERNAL_CHIP_RAP_RR = 0x0000,
 434         INTERNAL_CHIP_RAP_NRM = 0x0004,
 435         INTERNAL_CHIP_RAP_ERM = 0x0008,
 436         INTERNAL_CHIP_RAP_ERMx = 0x000C,
 437         INTERNAL_CHIP_WE = 0x0010,
 438         INTERNAL_CHIP_EF = 0x0020,
 439         INTERNAL_CHIP_FR = 0x0040,
 440         INTERNAL_CHIP_FW = 0x0080,
 441         INTERNAL_CHIP_FI = 0x0100,
 442         INTERNAL_CHIP_FT = 0x0200,
 443 };
 444
 445 /* portControl */
 446 enum {
 447         PORT_CONTROL_DS = 0x0001,
 448         PORT_CONTROL_HH = 0x0002,
 449         PORT_CONTROL_EI = 0x0004,
 450         PORT_CONTROL_ET = 0x0008,
 451         PORT_CONTROL_EF = 0x0010,
 452         PORT_CONTROL_DRM = 0x0020,
 453         PORT_CONTROL_RLB = 0x0040,
 454         PORT_CONTROL_RCB = 0x0080,
 455         PORT_CONTROL_MAC = 0x0100,
 456         PORT_CONTROL_IPV = 0x0200,
 457         PORT_CONTROL_IFP = 0x0400,
 458         PORT_CONTROL_ITP = 0x0800,
 459         PORT_CONTROL_FI = 0x1000,
 460         PORT_CONTROL_DFP = 0x2000,
 461         PORT_CONTROL_OI = 0x4000,
 462         PORT_CONTROL_CC = 0x8000,
 463 };
 464
 465 /* portStatus */
 466 enum {
 467         PORT_STATUS_SM0 = 0x0001,
 468         PORT_STATUS_SM1 = 0x0002,
 469         PORT_STATUS_X = 0x0008,
 470         PORT_STATUS_DL = 0x0080,
 471         PORT_STATUS_IC = 0x0200,
 472         PORT_STATUS_MRC = 0x0400,
 473         PORT_STATUS_NL = 0x0800,
 474         PORT_STATUS_REV_ID_MASK = 0x7000,
 475         PORT_STATUS_REV_ID_1 = 0x1000,
 476         PORT_STATUS_REV_ID_2 = 0x2000,
 477         PORT_STATUS_REV_ID_3 = 0x3000,
 478         PORT_STATUS_64 = 0x8000,
 479         PORT_STATUS_UP0 = 0x10000,
 480         PORT_STATUS_AC0 = 0x20000,
 481         PORT_STATUS_AE0 = 0x40000,
 482         PORT_STATUS_UP1 = 0x100000,
 483         PORT_STATUS_AC1 = 0x200000,
 484         PORT_STATUS_AE1 = 0x400000,
 485         PORT_STATUS_F0_ENABLED = 0x1000000,
 486         PORT_STATUS_F1_ENABLED = 0x2000000,
 487         PORT_STATUS_F2_ENABLED = 0x4000000,
 488         PORT_STATUS_F3_ENABLED = 0x8000000,
 489 };
 490
 491 /* macMIIMgmtControlReg */
 492 enum {
 493         MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
 494         MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
 495         MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
 496         MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
 497         MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
 498         MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
 499         MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
 500         MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
 501         MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
 502         MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
 503 };
 504
 505 /* macMIIMgmtControlReg */
 506 enum {
 507         MAC_MII_CONTROL_RC = 0x0001,
 508         MAC_MII_CONTROL_SC = 0x0002,
 509         MAC_MII_CONTROL_AS = 0x0004,
 510         MAC_MII_CONTROL_NP = 0x0008,
 511         MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
 512         MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
 513         MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
 514         MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
 515         MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
 516         MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
 517         MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
 518         MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
 519         MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
 520         MAC_MII_CONTROL_RM = 0x8000,
 521 };
 522
 523 /* macMIIStatusReg */
 524 enum {
 525         MAC_MII_STATUS_BSY = 0x0001,
 526         MAC_MII_STATUS_SC = 0x0002,
 527         MAC_MII_STATUS_NV = 0x0004,
 528 };
 529
 530 enum {
 531         MAC_CONFIG_REG_PE = 0x0001,
 532         MAC_CONFIG_REG_TF = 0x0002,
 533         MAC_CONFIG_REG_RF = 0x0004,
 534         MAC_CONFIG_REG_FD = 0x0008,
 535         MAC_CONFIG_REG_GM = 0x0010,
 536         MAC_CONFIG_REG_LB = 0x0020,
 537         MAC_CONFIG_REG_SR = 0x8000,
 538 };
 539
 540 enum {
 541         MAC_HALF_DUPLEX_REG_ED = 0x10000,
 542         MAC_HALF_DUPLEX_REG_NB = 0x20000,
 543         MAC_HALF_DUPLEX_REG_BNB = 0x40000,
 544         MAC_HALF_DUPLEX_REG_ALT = 0x80000,
 545 };
 546
 547 enum {
 548         IP_ADDR_INDEX_REG_MASK = 0x000f,
 549         IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
 550         IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
 551         IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
 552         IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
 553         IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
 554         IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
 555         IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
 556         IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
 557         IP_ADDR_INDEX_REG_6 = 0x0008,
 558         IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
 559         IP_ADDR_INDEX_REG_E = 0x0040,
 560 };
 561 enum {
 562         QL3032_PORT_CONTROL_DS = 0x0001,
 563         QL3032_PORT_CONTROL_HH = 0x0002,
 564         QL3032_PORT_CONTROL_EIv6 = 0x0004,
 565         QL3032_PORT_CONTROL_EIv4 = 0x0008,
 566         QL3032_PORT_CONTROL_ET = 0x0010,
 567         QL3032_PORT_CONTROL_EF = 0x0020,
 568         QL3032_PORT_CONTROL_DRM = 0x0040,
 569         QL3032_PORT_CONTROL_RLB = 0x0080,
 570         QL3032_PORT_CONTROL_RCB = 0x0100,
 571         QL3032_PORT_CONTROL_KIE = 0x0200,
 572 };
 573
 574 enum {
 575         PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
 576         PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
 577         PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
 578         PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
 579         PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
 580         PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
 581         PROBE_MUX_ADDR_REG_UP = 0x4000,
 582         PROBE_MUX_ADDR_REG_RE = 0x8000,
 583 };
 584
 585 enum {
 586         STATISTICS_INDEX_REG_MASK = 0x01ff,
 587         STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
 588         STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
 589         STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
 590         STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
 591         STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
 592         STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
 593         STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
 594         STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
 595         STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
 596         STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
 597         STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
 598         STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
 599         STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
 600         STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
 601         STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
 602         STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
 603         STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
 604         STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
 605         STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
 606         STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
 607         STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
 608         STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
 609         STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
 610         STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
 611         STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
 612         STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
 613         STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
 614         STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
 615         STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
 616         STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
 617         STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
 618         STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
 619         STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
 620         STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
 621         STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
 622         STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
 623         STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
 624         STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
 625         STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
 626         STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
 627         STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
 628         STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
 629         STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
 630         STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
 631         STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
 632         STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
 633         STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
 634         STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
 635         STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
 636         STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
 637         STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
 638         STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
 639 };
 640
 641 enum {
 642         PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
 643         PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
 644         PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
 645         PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
 646         PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
 647         PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
 648         PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
 649         PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
 650         PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
 651         PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
 652         PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
 653         PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
 654         PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
 655         PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
 656         PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
 657         PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
 658         PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
 659         PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
 660         PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
 661         PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
 662         PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
 663         PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
 664         PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
 665         PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
 666         PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
 667 };
 668
 669 /*
 670  *  port control and status page - page 0
 671  */
 672
 673 struct ql3xxx_port_registers {
 674         struct ql3xxx_common_registers CommonRegs;
 675
 676         u32 ExternalHWConfig;
 677         u32 InternalChipConfig;
 678         u32 portControl;
 679         u32 portStatus;
 680         u32 macAddrIndirectPtrReg;
 681         u32 macAddrDataReg;
 682         u32 macMIIMgmtControlReg;
 683         u32 macMIIMgmtAddrReg;
 684         u32 macMIIMgmtDataReg;
 685         u32 macMIIStatusReg;
 686         u32 mac0ConfigReg;
 687         u32 mac0IpgIfgReg;
 688         u32 mac0HalfDuplexReg;
 689         u32 mac0MaxFrameLengthReg;
 690         u32 mac0PauseThresholdReg;
 691         u32 mac1ConfigReg;
 692         u32 mac1IpgIfgReg;
 693         u32 mac1HalfDuplexReg;
 694         u32 mac1MaxFrameLengthReg;
 695         u32 mac1PauseThresholdReg;
 696         u32 ipAddrIndexReg;
 697         u32 ipAddrDataReg;
 698         u32 ipReassemblyTimeout;
 699         u32 tcpMaxWindow;
 700         u32 currentTcpTimestamp[2];
 701         u32 internalRamRWAddrReg;
 702         u32 internalRamWDataReg;
 703         u32 reclaimedBufferAddrRegLow;
 704         u32 reclaimedBufferAddrRegHigh;
 705         u32 tcpConfiguration;
 706         u32 functionControl;
 707         u32 fpgaRevID;
 708         u32 localRamAddr;
 709         u32 localRamDataAutoIncr;
 710         u32 localRamDataNonIncr;
 711         u32 gpOutput;
 712         u32 gpInput;
 713         u32 probeMuxAddr;
 714         u32 probeMuxData;
 715         u32 statisticsIndexReg;
 716         u32 statisticsReadDataRegAutoIncr;
 717         u32 statisticsReadDataRegNoIncr;
 718         u32 PortFatalErrStatus;
 719 };
 720
 721 /*
 722  * port host memory config page - page 1
 723  */
 724 struct ql3xxx_host_memory_registers {
 725         struct ql3xxx_common_registers CommonRegs;
 726
 727         u32 reserved[12];
 728
 729         /* Network Request Queue */
 730         u32 reqConsumerIndex;
 731         u32 reqConsumerIndexAddrLow;
 732         u32 reqConsumerIndexAddrHigh;
 733         u32 reqBaseAddrLow;
 734         u32 reqBaseAddrHigh;
 735         u32 reqLength;
 736
 737         /* Network Completion Queue */
 738         u32 rspProducerIndex;
 739         u32 rspProducerIndexAddrLow;
 740         u32 rspProducerIndexAddrHigh;
 741         u32 rspBaseAddrLow;
 742         u32 rspBaseAddrHigh;
 743         u32 rspLength;
 744
 745         /* RX Large Buffer Queue */
 746         u32 rxLargeQConsumerIndex;
 747         u32 rxLargeQBaseAddrLow;
 748         u32 rxLargeQBaseAddrHigh;
 749         u32 rxLargeQLength;
 750         u32 rxLargeBufferLength;
 751
 752         /* RX Small Buffer Queue */
 753         u32 rxSmallQConsumerIndex;
 754         u32 rxSmallQBaseAddrLow;
 755         u32 rxSmallQBaseAddrHigh;
 756         u32 rxSmallQLength;
 757         u32 rxSmallBufferLength;
 758
 759 };
 760
 761 /*
 762  *  port local RAM page - page 2
 763  */
 764 struct ql3xxx_local_ram_registers {
 765         struct ql3xxx_common_registers CommonRegs;
 766         u32 bufletSize;
 767         u32 maxBufletCount;
 768         u32 currentBufletCount;
 769         u32 reserved;
 770         u32 freeBufletThresholdLow;
 771         u32 freeBufletThresholdHigh;
 772         u32 ipHashTableBase;
 773         u32 ipHashTableCount;
 774         u32 tcpHashTableBase;
 775         u32 tcpHashTableCount;
 776         u32 ncbBase;
 777         u32 maxNcbCount;
 778         u32 currentNcbCount;
 779         u32 drbBase;
 780         u32 maxDrbCount;
 781         u32 currentDrbCount;
 782 };
 783
 784 /*
 785  * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
 786  */
 787
 788 #define LS_64BITS(x)    (u32)(0xffffffff & ((u64)x))
 789 #define MS_64BITS(x)    (u32)(0xffffffff & (((u64)x)>>16>>16) )
 790
 791 /*
 792  * I/O register
 793  */
 794
 795 enum {
 796         CONTROL_REG = 0,
 797         STATUS_REG = 1,
 798         PHY_STAT_LINK_UP = 0x0004,
 799         PHY_CTRL_LOOPBACK = 0x4000,
 800
 801         PETBI_CONTROL_REG = 0x00,
 802         PETBI_CTRL_ALL_PARAMS = 0x7140,
 803         PETBI_CTRL_SOFT_RESET = 0x8000,
 804         PETBI_CTRL_AUTO_NEG = 0x1000,
 805         PETBI_CTRL_RESTART_NEG = 0x0200,
 806         PETBI_CTRL_FULL_DUPLEX = 0x0100,
 807         PETBI_CTRL_SPEED_1000 = 0x0040,
 808
 809         PETBI_STATUS_REG = 0x01,
 810         PETBI_STAT_NEG_DONE = 0x0020,
 811         PETBI_STAT_LINK_UP = 0x0004,
 812
 813         PETBI_NEG_ADVER = 0x04,
 814         PETBI_NEG_PAUSE = 0x0080,
 815         PETBI_NEG_PAUSE_MASK = 0x0180,
 816         PETBI_NEG_DUPLEX = 0x0020,
 817         PETBI_NEG_DUPLEX_MASK = 0x0060,
 818
 819         PETBI_NEG_PARTNER = 0x05,
 820         PETBI_NEG_ERROR_MASK = 0x3000,
 821
 822         PETBI_EXPANSION_REG = 0x06,
 823         PETBI_EXP_PAGE_RX = 0x0002,
 824
 825         PHY_GIG_CONTROL = 9,
 826         PHY_GIG_ENABLE_MAN = 0x1000,  /* Enable Master/Slave Manual Config*/
 827         PHY_GIG_SET_MASTER = 0x0800,  /* Set Master (slave if clear)*/
 828         PHY_GIG_ALL_PARAMS = 0x0300,
 829         PHY_GIG_ADV_1000F = 0x0200,
 830         PHY_GIG_ADV_1000H = 0x0100,
 831
 832         PHY_NEG_ADVER = 4,
 833         PHY_NEG_ALL_PARAMS = 0x0fe0,
 834         PHY_NEG_ASY_PAUSE =  0x0800,
 835         PHY_NEG_SYM_PAUSE =  0x0400,
 836         PHY_NEG_ADV_SPEED =  0x01e0,
 837         PHY_NEG_ADV_100F =   0x0100,
 838         PHY_NEG_ADV_100H =   0x0080,
 839         PHY_NEG_ADV_10F =    0x0040,
 840         PHY_NEG_ADV_10H =    0x0020,
 841
 842         PETBI_TBI_CTRL = 0x11,
 843         PETBI_TBI_RESET = 0x8000,
 844         PETBI_TBI_AUTO_SENSE = 0x0100,
 845         PETBI_TBI_SERDES_MODE = 0x0010,
 846         PETBI_TBI_SERDES_WRAP = 0x0002,
 847
 848         AUX_CONTROL_STATUS = 0x1c,
 849         PHY_AUX_NEG_DONE = 0x8000,
 850         PHY_NEG_PARTNER = 5,
 851         PHY_AUX_DUPLEX_STAT = 0x0020,
 852         PHY_AUX_SPEED_STAT = 0x0018,
 853         PHY_AUX_NO_HW_STRAP = 0x0004,
 854         PHY_AUX_RESET_STICK = 0x0002,
 855         PHY_NEG_PAUSE = 0x0400,
 856         PHY_CTRL_SOFT_RESET = 0x8000,
 857         PHY_CTRL_AUTO_NEG = 0x1000,
 858         PHY_CTRL_RESTART_NEG = 0x0200,
 859 };
 860 enum {
 861 /* AM29LV Flash definitions     */
 862         FM93C56A_START = 0x1,
 863 /* Commands */
 864         FM93C56A_READ = 0x2,
 865         FM93C56A_WEN = 0x0,
 866         FM93C56A_WRITE = 0x1,
 867         FM93C56A_WRITE_ALL = 0x0,
 868         FM93C56A_WDS = 0x0,
 869         FM93C56A_ERASE = 0x3,
 870         FM93C56A_ERASE_ALL = 0x0,
 871 /* Command Extentions */
 872         FM93C56A_WEN_EXT = 0x3,
 873         FM93C56A_WRITE_ALL_EXT = 0x1,
 874         FM93C56A_WDS_EXT = 0x0,
 875         FM93C56A_ERASE_ALL_EXT = 0x2,
 876 /* Special Bits */
 877         FM93C56A_READ_DUMMY_BITS = 1,
 878         FM93C56A_READY = 0,
 879         FM93C56A_BUSY = 1,
 880         FM93C56A_CMD_BITS = 2,
 881 /* AM29LV Flash definitions     */
 882         FM93C56A_SIZE_8 = 0x100,
 883         FM93C56A_SIZE_16 = 0x80,
 884         FM93C66A_SIZE_8 = 0x200,
 885         FM93C66A_SIZE_16 = 0x100,
 886         FM93C86A_SIZE_16 = 0x400,
 887 /* Address Bits */
 888         FM93C56A_NO_ADDR_BITS_16 = 8,
 889         FM93C56A_NO_ADDR_BITS_8 = 9,
 890         FM93C86A_NO_ADDR_BITS_16 = 10,
 891 /* Data Bits */
 892         FM93C56A_DATA_BITS_16 = 16,
 893         FM93C56A_DATA_BITS_8 = 8,
 894 };
 895 enum {
 896 /* Auburn Bits */
 897             AUBURN_EEPROM_DI = 0x8,
 898         AUBURN_EEPROM_DI_0 = 0x0,
 899         AUBURN_EEPROM_DI_1 = 0x8,
 900         AUBURN_EEPROM_DO = 0x4,
 901         AUBURN_EEPROM_DO_0 = 0x0,
 902         AUBURN_EEPROM_DO_1 = 0x4,
 903         AUBURN_EEPROM_CS = 0x2,
 904         AUBURN_EEPROM_CS_0 = 0x0,
 905         AUBURN_EEPROM_CS_1 = 0x2,
 906         AUBURN_EEPROM_CLK_RISE = 0x1,
 907         AUBURN_EEPROM_CLK_FALL = 0x0,
 908 };
 909 enum {EEPROM_SIZE = FM93C86A_SIZE_16,
 910         EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
 911         EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
 912 };
 913
 914 /*
 915  *  MAC Config data structure
 916  */
 917     struct eeprom_port_cfg {
 918         u16 etherMtu_mac;
 919         u16 pauseThreshold_mac;
 920         u16 resumeThreshold_mac;
 921         u16 portConfiguration;
 922 #define PORT_CONFIG_DEFAULT                 0xf700
 923 #define PORT_CONFIG_AUTO_NEG_ENABLED        0x8000
 924 #define PORT_CONFIG_SYM_PAUSE_ENABLED       0x4000
 925 #define PORT_CONFIG_FULL_DUPLEX_ENABLED     0x2000
 926 #define PORT_CONFIG_HALF_DUPLEX_ENABLED     0x1000
 927 #define PORT_CONFIG_1000MB_SPEED            0x0400
 928 #define PORT_CONFIG_100MB_SPEED             0x0200
 929 #define PORT_CONFIG_10MB_SPEED              0x0100
 930 #define PORT_CONFIG_LINK_SPEED_MASK         0x0F00
 931         u16 reserved[12];
 932
 933 };
 934
 935 /*
 936  * BIOS data structure
 937  */
 938 struct eeprom_bios_cfg {
 939         u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;
 940
 941         u8 bootID0:7, boodID0Valid:1;
 942         u8 bootLun0[8];
 943
 944         u8 bootID1:7, boodID1Valid:1;
 945         u8 bootLun1[8];
 946
 947         u16 MaxLunsTrgt;
 948         u8 reserved[10];
 949 };
 950
 951 /*
 952  *  Function Specific Data structure
 953  */
 954 struct eeprom_function_cfg {
 955         u8 reserved[30];
 956         u16 macAddress[3];
 957         u16 macAddressSecondary[3];
 958
 959         u16 subsysVendorId;
 960         u16 subsysDeviceId;
 961 };
 962
 963 /*
 964  *  EEPROM format
 965  */
 966 struct eeprom_data {
 967         u8 asicId[4];
 968         u16 version_and_numPorts; /* together to avoid endianness crap */
 969         u16 boardId;
 970
 971 #define EEPROM_BOARDID_STR_SIZE   16
 972 #define EEPROM_SERIAL_NUM_SIZE    16
 973
 974         u8 boardIdStr[16];
 975         u8 serialNumber[16];
 976         u16 extHwConfig;
 977         struct eeprom_port_cfg macCfg_port0;
 978         struct eeprom_port_cfg macCfg_port1;
 979         u16 bufletSize;
 980         u16 bufletCount;
 981         u16 tcpWindowThreshold50;
 982         u16 tcpWindowThreshold25;
 983         u16 tcpWindowThreshold0;
 984         u16 ipHashTableBaseHi;
 985         u16 ipHashTableBaseLo;
 986         u16 ipHashTableSize;
 987         u16 tcpHashTableBaseHi;
 988         u16 tcpHashTableBaseLo;
 989         u16 tcpHashTableSize;
 990         u16 ncbTableBaseHi;
 991         u16 ncbTableBaseLo;
 992         u16 ncbTableSize;
 993         u16 drbTableBaseHi;
 994         u16 drbTableBaseLo;
 995         u16 drbTableSize;
 996         u16 reserved_142[4];
 997         u16 ipReassemblyTimeout;
 998         u16 tcpMaxWindowSize;
 999         u16 ipSecurity;
1000 #define IPSEC_CONFIG_PRESENT 0x0001
1001         u8 reserved_156[294];
1002         u16 qDebug[8];
1003         struct eeprom_function_cfg funcCfg_fn0;
1004         u16 reserved_510;
1005         u8 oemSpace[432];
1006         struct eeprom_bios_cfg biosCfg_fn1;
1007         struct eeprom_function_cfg funcCfg_fn1;
1008         u16 reserved_1022;
1009         u8 reserved_1024[464];
1010         struct eeprom_function_cfg funcCfg_fn2;
1011         u16 reserved_1534;
1012         u8 reserved_1536[432];
1013         struct eeprom_bios_cfg biosCfg_fn3;
1014         struct eeprom_function_cfg funcCfg_fn3;
1015         u16 checksum;
1016 };
1017
1018 /*
1019  * General definitions...
1020  */
1021
1022 /*
1023  * Below are a number compiler switches for controlling driver behavior.
1024  * Some are not supported under certain conditions and are notated as such.
1025  */
1026
1027 #define QL3XXX_VENDOR_ID    0x1077
1028 #define QL3022_DEVICE_ID    0x3022
1029 #define QL3032_DEVICE_ID    0x3032
1030
1031 /* MTU & Frame Size stuff */
1032 #define NORMAL_MTU_SIZE                 ETH_DATA_LEN
1033 #define JUMBO_MTU_SIZE                  9000
1034 #define VLAN_ID_LEN                         2
1035
1036 /* Request Queue Related Definitions */
1037 #define NUM_REQ_Q_ENTRIES   256 /* so that 64 * 64  = 4096 (1 page) */
1038
1039 /* Response Queue Related Definitions */
1040 #define NUM_RSP_Q_ENTRIES   256 /* so that 256 * 16  = 4096 (1 page) */
1041
1042 /* Transmit and Receive Buffers */
1043 #define NUM_LBUFQ_ENTRIES       128
1044 #define JUMBO_NUM_LBUFQ_ENTRIES 32
1045 #define NUM_SBUFQ_ENTRIES       64
1046 #define QL_SMALL_BUFFER_SIZE    32
1047 #define QL_ADDR_ELE_PER_BUFQ_ENTRY \
1048 (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
1049     /* Each send has at least control block.  This is how many we keep. */
1050 #define NUM_SMALL_BUFFERS       NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
1051
1052 #define QL_HEADER_SPACE 32      /* make header space at top of skb. */
1053 /*
1054  * Large & Small Buffers for Receives
1055  */
1056 struct lrg_buf_q_entry {
1057
1058         __le32 addr0_lower;
1059 #define IAL_LAST_ENTRY 0x00000001
1060 #define IAL_CONT_ENTRY 0x00000002
1061 #define IAL_FLAG_MASK  0x00000003
1062         __le32 addr0_upper;
1063         __le32 addr1_lower;
1064         __le32 addr1_upper;
1065         __le32 addr2_lower;
1066         __le32 addr2_upper;
1067         __le32 addr3_lower;
1068         __le32 addr3_upper;
1069         __le32 addr4_lower;
1070         __le32 addr4_upper;
1071         __le32 addr5_lower;
1072         __le32 addr5_upper;
1073         __le32 addr6_lower;
1074         __le32 addr6_upper;
1075         __le32 addr7_lower;
1076         __le32 addr7_upper;
1077
1078 };
1079
1080 struct bufq_addr_element {
1081         __le32 addr_low;
1082         __le32 addr_high;
1083 };
1084
1085 #define QL_NO_RESET                     0
1086 #define QL_DO_RESET                     1
1087
1088 enum link_state_t {
1089         LS_UNKNOWN = 0,
1090         LS_DOWN,
1091         LS_DEGRADE,
1092         LS_RECOVER,
1093         LS_UP,
1094 };
1095
1096 struct ql_rcv_buf_cb {
1097         struct ql_rcv_buf_cb *next;
1098         struct sk_buff *skb;
1099          DECLARE_PCI_UNMAP_ADDR(mapaddr);
1100          DECLARE_PCI_UNMAP_LEN(maplen);
1101         __le32 buf_phy_addr_low;
1102         __le32 buf_phy_addr_high;
1103         int index;
1104 };
1105
1106 /*
1107  * Original IOCB has 3 sg entries:
1108  * first points to skb-data area
1109  * second points to first frag
1110  * third points to next oal.
1111  * OAL has 5 entries:
1112  * 1 thru 4 point to frags
1113  * fifth points to next oal.
1114  */
1115 #define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
1116
1117 struct oal_entry {
1118         __le32 dma_lo;
1119         __le32 dma_hi;
1120         __le32 len;
1121 #define OAL_LAST_ENTRY   0x80000000     /* Last valid buffer in list. */
1122 #define OAL_CONT_ENTRY   0x40000000     /* points to an OAL. (continuation) */
1123 };
1124
1125 struct oal {
1126         struct oal_entry oal_entry[5];
1127 };
1128
1129 struct map_list {
1130          DECLARE_PCI_UNMAP_ADDR(mapaddr);
1131          DECLARE_PCI_UNMAP_LEN(maplen);
1132 };
1133
1134 struct ql_tx_buf_cb {
1135         struct sk_buff *skb;
1136         struct ob_mac_iocb_req *queue_entry ;
1137         int seg_count;
1138         struct oal *oal;
1139         struct map_list map[MAX_SKB_FRAGS+1];
1140 };
1141
1142 /* definitions for type field */
1143 #define QL_BUF_TYPE_MACIOCB 0x01
1144 #define QL_BUF_TYPE_IPIOCB  0x02
1145 #define QL_BUF_TYPE_TCPIOCB 0x03
1146
1147 /* qdev->flags definitions. */
1148 enum { QL_RESET_DONE = 1,       /* Reset finished. */
1149         QL_RESET_ACTIVE = 2,    /* Waiting for reset to finish. */
1150         QL_RESET_START = 3,     /* Please reset the chip. */
1151         QL_RESET_PER_SCSI = 4,  /* SCSI driver requests reset. */
1152         QL_TX_TIMEOUT = 5,      /* Timeout in progress. */
1153         QL_LINK_MASTER = 6,     /* This driver controls the link. */
1154         QL_ADAPTER_UP = 7,      /* Adapter has been brought up. */
1155         QL_THREAD_UP = 8,       /* This flag is available. */
1156         QL_LINK_UP = 9, /* Link Status. */
1157         QL_ALLOC_REQ_RSP_Q_DONE = 10,
1158         QL_ALLOC_BUFQS_DONE = 11,
1159         QL_ALLOC_SMALL_BUF_DONE = 12,
1160         QL_LINK_OPTICAL = 13,
1161         QL_MSI_ENABLED = 14,
1162 };
1163
1164 /*
1165  * ql3_adapter - The main Adapter structure definition.
1166  * This structure has all fields relevant to the hardware.
1167  */
1168
1169 struct ql3_adapter {
1170         u32 reserved_00;
1171         unsigned long flags;
1172
1173         /* PCI Configuration information for this device */
1174         struct pci_dev *pdev;
1175         struct net_device *ndev;        /* Parent NET device */
1176
1177         struct napi_struct napi;
1178
1179         /* Hardware information */
1180         u8 chip_rev_id;
1181         u8 pci_slot;
1182         u8 pci_width;
1183         u8 pci_x;
1184         u32 msi;
1185         int index;
1186         struct timer_list adapter_timer;        /* timer used for various functions */
1187
1188         spinlock_t adapter_lock;
1189         spinlock_t hw_lock;
1190
1191         /* PCI Bus Relative Register Addresses */
1192         u8 __iomem *mmap_virt_base;     /* stores return value from ioremap() */
1193         struct ql3xxx_port_registers __iomem *mem_map_registers;
1194         u32 current_page;       /* tracks current register page */
1195
1196         u32 msg_enable;
1197         u8 reserved_01[2];
1198         u8 reserved_02[2];
1199
1200         /* Page for Shadow Registers */
1201         void *shadow_reg_virt_addr;
1202         dma_addr_t shadow_reg_phy_addr;
1203
1204         /* Net Request Queue */
1205         u32 req_q_size;
1206         u32 reserved_03;
1207         struct ob_mac_iocb_req *req_q_virt_addr;
1208         dma_addr_t req_q_phy_addr;
1209         u16 req_producer_index;
1210         u16 reserved_04;
1211         u16 *preq_consumer_index;
1212         u32 req_consumer_index_phy_addr_high;
1213         u32 req_consumer_index_phy_addr_low;
1214         atomic_t tx_count;
1215         struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];
1216
1217         /* Net Response Queue */
1218         u32 rsp_q_size;
1219         u32 eeprom_cmd_data;
1220         struct net_rsp_iocb *rsp_q_virt_addr;
1221         dma_addr_t rsp_q_phy_addr;
1222         struct net_rsp_iocb *rsp_current;
1223         u16 rsp_consumer_index;
1224         u16 reserved_06;
1225         volatile __le32 *prsp_producer_index;
1226         u32 rsp_producer_index_phy_addr_high;
1227         u32 rsp_producer_index_phy_addr_low;
1228
1229         /* Large Buffer Queue */
1230         u32 lrg_buf_q_alloc_size;
1231         u32 lrg_buf_q_size;
1232         void *lrg_buf_q_alloc_virt_addr;
1233         void *lrg_buf_q_virt_addr;
1234         dma_addr_t lrg_buf_q_alloc_phy_addr;
1235         dma_addr_t lrg_buf_q_phy_addr;
1236         u32 lrg_buf_q_producer_index;
1237         u32 lrg_buf_release_cnt;
1238         struct bufq_addr_element *lrg_buf_next_free;
1239         u32 num_large_buffers;
1240         u32 num_lbufq_entries;
1241
1242         /* Large (Receive) Buffers */
1243         struct ql_rcv_buf_cb *lrg_buf;
1244         struct ql_rcv_buf_cb *lrg_buf_free_head;
1245         struct ql_rcv_buf_cb *lrg_buf_free_tail;
1246         u32 lrg_buf_free_count;
1247         u32 lrg_buffer_len;
1248         u32 lrg_buf_index;
1249         u32 lrg_buf_skb_check;
1250
1251         /* Small Buffer Queue */
1252         u32 small_buf_q_alloc_size;
1253         u32 small_buf_q_size;
1254         u32 small_buf_q_producer_index;
1255         void *small_buf_q_alloc_virt_addr;
1256         void *small_buf_q_virt_addr;
1257         dma_addr_t small_buf_q_alloc_phy_addr;
1258         dma_addr_t small_buf_q_phy_addr;
1259         u32 small_buf_index;
1260
1261         /* Small (Receive) Buffers */
1262         void *small_buf_virt_addr;
1263         dma_addr_t small_buf_phy_addr;
1264         u32 small_buf_phy_addr_low;
1265         u32 small_buf_phy_addr_high;
1266         u32 small_buf_release_cnt;
1267         u32 small_buf_total_size;
1268
1269         /* ISR related, saves status for DPC. */
1270         u32 control_status;
1271
1272         struct eeprom_data nvram_data;
1273         struct timer_list ioctl_timer;
1274         u32 port_link_state;
1275         u32 last_rsp_offset;
1276
1277         /* 4022 specific */
1278         u32 mac_index;          /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
1279         u32 PHYAddr;            /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
1280         u32 mac_ob_opcode;      /* Opcode to use on mac transmission */
1281         u32 tcp_ob_opcode;      /* Opcode to use on tcp transmission */
1282         u32 update_ob_opcode;   /* Opcode to use for updating NCB */
1283         u32 mb_bit_mask;        /* MA Bits mask to use on transmission */
1284         u32 numPorts;
1285         struct workqueue_struct *workqueue;
1286         struct delayed_work reset_work;
1287         struct delayed_work tx_timeout_work;
1288         struct delayed_work link_state_work;
1289         u32 max_frame_size;
1290         u32 device_id;
1291         u16 phyType;
1292 };
1293
1294 #endif                          /* _QLA3XXX_H_ */