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Linux 2.6.26-rc5
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / net / atlx / atl1.c
blob6ddc911e7d159730e26c3dd79c916d5395c93d9d
1 /*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong_huang@attansic.com>
28 * Attansic Technology Corp. 3F 147, Xianzheng 9th Road, Zhubei,
29 * Xinzhu 302, TAIWAN, REPUBLIC OF CHINA
30 *
31 * Chris Snook <csnook@redhat.com>
32 * Jay Cliburn <jcliburn@gmail.com>
33 *
34 * This version is adapted from the Attansic reference driver for
35 * inclusion in the Linux kernel. It is currently under heavy development.
36 * A very incomplete list of things that need to be dealt with:
37 *
38 * TODO:
39 * Add more ethtool functions.
40 * Fix abstruse irq enable/disable condition described here:
41 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
42 *
43 * NEEDS TESTING:
44 * VLAN
45 * multicast
46 * promiscuous mode
47 * interrupt coalescing
48 * SMP torture testing
49 */
50
51 #include <asm/atomic.h>
52 #include <asm/byteorder.h>
53
54 #include <linux/compiler.h>
55 #include <linux/crc32.h>
56 #include <linux/delay.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/etherdevice.h>
59 #include <linux/hardirq.h>
60 #include <linux/if_ether.h>
61 #include <linux/if_vlan.h>
62 #include <linux/in.h>
63 #include <linux/interrupt.h>
64 #include <linux/ip.h>
65 #include <linux/irqflags.h>
66 #include <linux/irqreturn.h>
67 #include <linux/jiffies.h>
68 #include <linux/mii.h>
69 #include <linux/module.h>
70 #include <linux/moduleparam.h>
71 #include <linux/net.h>
72 #include <linux/netdevice.h>
73 #include <linux/pci.h>
74 #include <linux/pci_ids.h>
75 #include <linux/pm.h>
76 #include <linux/skbuff.h>
77 #include <linux/slab.h>
78 #include <linux/spinlock.h>
79 #include <linux/string.h>
80 #include <linux/tcp.h>
81 #include <linux/timer.h>
82 #include <linux/types.h>
83 #include <linux/workqueue.h>
84
85 #include <net/checksum.h>
86
87 #include "atl1.h"
88
89 /* Temporary hack for merging atl1 and atl2 */
90 #include "atlx.c"
91
92 /*
93 * This is the only thing that needs to be changed to adjust the
94 * maximum number of ports that the driver can manage.
95 */
96 #define ATL1_MAX_NIC 4
97
98 #define OPTION_UNSET -1
99 #define OPTION_DISABLED 0
100 #define OPTION_ENABLED 1
101
102 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
103
104 /*
105 * Interrupt Moderate Timer in units of 2 us
106 *
107 * Valid Range: 10-65535
108 *
109 * Default Value: 100 (200us)
110 */
111 static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
112 static int num_int_mod_timer;
113 module_param_array_named(int_mod_timer, int_mod_timer, int,
114 &num_int_mod_timer, 0);
115 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
116
117 #define DEFAULT_INT_MOD_CNT 100 /* 200us */
118 #define MAX_INT_MOD_CNT 65000
119 #define MIN_INT_MOD_CNT 50
120
121 struct atl1_option {
122 enum { enable_option, range_option, list_option } type;
123 char *name;
124 char *err;
125 int def;
126 union {
127 struct { /* range_option info */
128 int min;
129 int max;
130 } r;
131 struct { /* list_option info */
132 int nr;
133 struct atl1_opt_list {
134 int i;
135 char *str;
136 } *p;
137 } l;
138 } arg;
139 };
140
141 static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
142 struct pci_dev *pdev)
143 {
144 if (*value == OPTION_UNSET) {
145 *value = opt->def;
146 return 0;
147 }
148
149 switch (opt->type) {
150 case enable_option:
151 switch (*value) {
152 case OPTION_ENABLED:
153 dev_info(&pdev->dev, "%s enabled\n", opt->name);
154 return 0;
155 case OPTION_DISABLED:
156 dev_info(&pdev->dev, "%s disabled\n", opt->name);
157 return 0;
158 }
159 break;
160 case range_option:
161 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
162 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
163 *value);
164 return 0;
165 }
166 break;
167 case list_option:{
168 int i;
169 struct atl1_opt_list *ent;
170
171 for (i = 0; i < opt->arg.l.nr; i++) {
172 ent = &opt->arg.l.p[i];
173 if (*value == ent->i) {
174 if (ent->str[0] != '\0')
175 dev_info(&pdev->dev, "%s\n",
176 ent->str);
177 return 0;
178 }
179 }
180 }
181 break;
182
183 default:
184 break;
185 }
186
187 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
188 opt->name, *value, opt->err);
189 *value = opt->def;
190 return -1;
191 }
192
193 /*
194 * atl1_check_options - Range Checking for Command Line Parameters
195 * @adapter: board private structure
196 *
197 * This routine checks all command line parameters for valid user
198 * input. If an invalid value is given, or if no user specified
199 * value exists, a default value is used. The final value is stored
200 * in a variable in the adapter structure.
201 */
202 void __devinit atl1_check_options(struct atl1_adapter *adapter)
203 {
204 struct pci_dev *pdev = adapter->pdev;
205 int bd = adapter->bd_number;
206 if (bd >= ATL1_MAX_NIC) {
207 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
208 dev_notice(&pdev->dev, "using defaults for all values\n");
209 }
210 { /* Interrupt Moderate Timer */
211 struct atl1_option opt = {
212 .type = range_option,
213 .name = "Interrupt Moderator Timer",
214 .err = "using default of "
215 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
216 .def = DEFAULT_INT_MOD_CNT,
217 .arg = {.r = {.min = MIN_INT_MOD_CNT,
218 .max = MAX_INT_MOD_CNT} }
219 };
220 int val;
221 if (num_int_mod_timer > bd) {
222 val = int_mod_timer[bd];
223 atl1_validate_option(&val, &opt, pdev);
224 adapter->imt = (u16) val;
225 } else
226 adapter->imt = (u16) (opt.def);
227 }
228 }
229
230 /*
231 * atl1_pci_tbl - PCI Device ID Table
232 */
233 static const struct pci_device_id atl1_pci_tbl[] = {
234 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
235 /* required last entry */
236 {0,}
237 };
238 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
239
240 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
241 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
242
243 static int debug = -1;
244 module_param(debug, int, 0);
245 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
246
247 /*
248 * Reset the transmit and receive units; mask and clear all interrupts.
249 * hw - Struct containing variables accessed by shared code
250 * return : 0 or idle status (if error)
251 */
252 static s32 atl1_reset_hw(struct atl1_hw *hw)
253 {
254 struct pci_dev *pdev = hw->back->pdev;
255 struct atl1_adapter *adapter = hw->back;
256 u32 icr;
257 int i;
258
259 /*
260 * Clear Interrupt mask to stop board from generating
261 * interrupts & Clear any pending interrupt events
262 */
263 /*
264 * iowrite32(0, hw->hw_addr + REG_IMR);
265 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
266 */
267
268 /*
269 * Issue Soft Reset to the MAC. This will reset the chip's
270 * transmit, receive, DMA. It will not effect
271 * the current PCI configuration. The global reset bit is self-
272 * clearing, and should clear within a microsecond.
273 */
274 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
275 ioread32(hw->hw_addr + REG_MASTER_CTRL);
276
277 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
278 ioread16(hw->hw_addr + REG_PHY_ENABLE);
279
280 /* delay about 1ms */
281 msleep(1);
282
283 /* Wait at least 10ms for All module to be Idle */
284 for (i = 0; i < 10; i++) {
285 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
286 if (!icr)
287 break;
288 /* delay 1 ms */
289 msleep(1);
290 /* FIXME: still the right way to do this? */
291 cpu_relax();
292 }
293
294 if (icr) {
295 if (netif_msg_hw(adapter))
296 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
297 return icr;
298 }
299
300 return 0;
301 }
302
303 /* function about EEPROM
304 *
305 * check_eeprom_exist
306 * return 0 if eeprom exist
307 */
308 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
309 {
310 u32 value;
311 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
312 if (value & SPI_FLASH_CTRL_EN_VPD) {
313 value &= ~SPI_FLASH_CTRL_EN_VPD;
314 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
315 }
316
317 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
318 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
319 }
320
321 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
322 {
323 int i;
324 u32 control;
325
326 if (offset & 3)
327 /* address do not align */
328 return false;
329
330 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
331 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
332 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
333 ioread32(hw->hw_addr + REG_VPD_CAP);
334
335 for (i = 0; i < 10; i++) {
336 msleep(2);
337 control = ioread32(hw->hw_addr + REG_VPD_CAP);
338 if (control & VPD_CAP_VPD_FLAG)
339 break;
340 }
341 if (control & VPD_CAP_VPD_FLAG) {
342 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
343 return true;
344 }
345 /* timeout */
346 return false;
347 }
348
349 /*
350 * Reads the value from a PHY register
351 * hw - Struct containing variables accessed by shared code
352 * reg_addr - address of the PHY register to read
353 */
354 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
355 {
356 u32 val;
357 int i;
358
359 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
360 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
361 MDIO_CLK_SEL_SHIFT;
362 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
363 ioread32(hw->hw_addr + REG_MDIO_CTRL);
364
365 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
366 udelay(2);
367 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
368 if (!(val & (MDIO_START | MDIO_BUSY)))
369 break;
370 }
371 if (!(val & (MDIO_START | MDIO_BUSY))) {
372 *phy_data = (u16) val;
373 return 0;
374 }
375 return ATLX_ERR_PHY;
376 }
377
378 #define CUSTOM_SPI_CS_SETUP 2
379 #define CUSTOM_SPI_CLK_HI 2
380 #define CUSTOM_SPI_CLK_LO 2
381 #define CUSTOM_SPI_CS_HOLD 2
382 #define CUSTOM_SPI_CS_HI 3
383
384 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
385 {
386 int i;
387 u32 value;
388
389 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
390 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
391
392 value = SPI_FLASH_CTRL_WAIT_READY |
393 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
394 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
395 SPI_FLASH_CTRL_CLK_HI_MASK) <<
396 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
397 SPI_FLASH_CTRL_CLK_LO_MASK) <<
398 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
399 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
400 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
401 SPI_FLASH_CTRL_CS_HI_MASK) <<
402 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
403 SPI_FLASH_CTRL_INS_SHIFT;
404
405 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
406
407 value |= SPI_FLASH_CTRL_START;
408 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
409 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
410
411 for (i = 0; i < 10; i++) {
412 msleep(1);
413 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
414 if (!(value & SPI_FLASH_CTRL_START))
415 break;
416 }
417
418 if (value & SPI_FLASH_CTRL_START)
419 return false;
420
421 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
422
423 return true;
424 }
425
426 /*
427 * get_permanent_address
428 * return 0 if get valid mac address,
429 */
430 static int atl1_get_permanent_address(struct atl1_hw *hw)
431 {
432 u32 addr[2];
433 u32 i, control;
434 u16 reg;
435 u8 eth_addr[ETH_ALEN];
436 bool key_valid;
437
438 if (is_valid_ether_addr(hw->perm_mac_addr))
439 return 0;
440
441 /* init */
442 addr[0] = addr[1] = 0;
443
444 if (!atl1_check_eeprom_exist(hw)) {
445 reg = 0;
446 key_valid = false;
447 /* Read out all EEPROM content */
448 i = 0;
449 while (1) {
450 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
451 if (key_valid) {
452 if (reg == REG_MAC_STA_ADDR)
453 addr[0] = control;
454 else if (reg == (REG_MAC_STA_ADDR + 4))
455 addr[1] = control;
456 key_valid = false;
457 } else if ((control & 0xff) == 0x5A) {
458 key_valid = true;
459 reg = (u16) (control >> 16);
460 } else
461 break;
462 } else
463 /* read error */
464 break;
465 i += 4;
466 }
467
468 *(u32 *) &eth_addr[2] = swab32(addr[0]);
469 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
470 if (is_valid_ether_addr(eth_addr)) {
471 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
472 return 0;
473 }
474 return 1;
475 }
476
477 /* see if SPI FLAGS exist ? */
478 addr[0] = addr[1] = 0;
479 reg = 0;
480 key_valid = false;
481 i = 0;
482 while (1) {
483 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
484 if (key_valid) {
485 if (reg == REG_MAC_STA_ADDR)
486 addr[0] = control;
487 else if (reg == (REG_MAC_STA_ADDR + 4))
488 addr[1] = control;
489 key_valid = false;
490 } else if ((control & 0xff) == 0x5A) {
491 key_valid = true;
492 reg = (u16) (control >> 16);
493 } else
494 /* data end */
495 break;
496 } else
497 /* read error */
498 break;
499 i += 4;
500 }
501
502 *(u32 *) &eth_addr[2] = swab32(addr[0]);
503 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
504 if (is_valid_ether_addr(eth_addr)) {
505 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
506 return 0;
507 }
508
509 /*
510 * On some motherboards, the MAC address is written by the
511 * BIOS directly to the MAC register during POST, and is
512 * not stored in eeprom. If all else thus far has failed
513 * to fetch the permanent MAC address, try reading it directly.
514 */
515 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
516 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
517 *(u32 *) &eth_addr[2] = swab32(addr[0]);
518 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
519 if (is_valid_ether_addr(eth_addr)) {
520 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
521 return 0;
522 }
523
524 return 1;
525 }
526
527 /*
528 * Reads the adapter's MAC address from the EEPROM
529 * hw - Struct containing variables accessed by shared code
530 */
531 s32 atl1_read_mac_addr(struct atl1_hw *hw)
532 {
533 u16 i;
534
535 if (atl1_get_permanent_address(hw))
536 random_ether_addr(hw->perm_mac_addr);
537
538 for (i = 0; i < ETH_ALEN; i++)
539 hw->mac_addr[i] = hw->perm_mac_addr[i];
540 return 0;
541 }
542
543 /*
544 * Hashes an address to determine its location in the multicast table
545 * hw - Struct containing variables accessed by shared code
546 * mc_addr - the multicast address to hash
547 *
548 * atl1_hash_mc_addr
549 * purpose
550 * set hash value for a multicast address
551 * hash calcu processing :
552 * 1. calcu 32bit CRC for multicast address
553 * 2. reverse crc with MSB to LSB
554 */
555 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
556 {
557 u32 crc32, value = 0;
558 int i;
559
560 crc32 = ether_crc_le(6, mc_addr);
561 for (i = 0; i < 32; i++)
562 value |= (((crc32 >> i) & 1) << (31 - i));
563
564 return value;
565 }
566
567 /*
568 * Sets the bit in the multicast table corresponding to the hash value.
569 * hw - Struct containing variables accessed by shared code
570 * hash_value - Multicast address hash value
571 */
572 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
573 {
574 u32 hash_bit, hash_reg;
575 u32 mta;
576
577 /*
578 * The HASH Table is a register array of 2 32-bit registers.
579 * It is treated like an array of 64 bits. We want to set
580 * bit BitArray[hash_value]. So we figure out what register
581 * the bit is in, read it, OR in the new bit, then write
582 * back the new value. The register is determined by the
583 * upper 7 bits of the hash value and the bit within that
584 * register are determined by the lower 5 bits of the value.
585 */
586 hash_reg = (hash_value >> 31) & 0x1;
587 hash_bit = (hash_value >> 26) & 0x1F;
588 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
589 mta |= (1 << hash_bit);
590 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
591 }
592
593 /*
594 * Writes a value to a PHY register
595 * hw - Struct containing variables accessed by shared code
596 * reg_addr - address of the PHY register to write
597 * data - data to write to the PHY
598 */
599 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
600 {
601 int i;
602 u32 val;
603
604 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
605 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
606 MDIO_SUP_PREAMBLE |
607 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
608 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
609 ioread32(hw->hw_addr + REG_MDIO_CTRL);
610
611 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
612 udelay(2);
613 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
614 if (!(val & (MDIO_START | MDIO_BUSY)))
615 break;
616 }
617
618 if (!(val & (MDIO_START | MDIO_BUSY)))
619 return 0;
620
621 return ATLX_ERR_PHY;
622 }
623
624 /*
625 * Make L001's PHY out of Power Saving State (bug)
626 * hw - Struct containing variables accessed by shared code
627 * when power on, L001's PHY always on Power saving State
628 * (Gigabit Link forbidden)
629 */
630 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
631 {
632 s32 ret;
633 ret = atl1_write_phy_reg(hw, 29, 0x0029);
634 if (ret)
635 return ret;
636 return atl1_write_phy_reg(hw, 30, 0);
637 }
638
639 /*
640 * Force the PHY into power saving mode using vendor magic.
641 */
642 #ifdef CONFIG_PM
643 static void atl1_phy_enter_power_saving(struct atl1_hw *hw)
644 {
645 atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
646 atl1_write_phy_reg(hw, MII_DBG_DATA, 0x124E);
647 atl1_write_phy_reg(hw, MII_DBG_ADDR, 2);
648 atl1_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
649 atl1_write_phy_reg(hw, MII_DBG_ADDR, 3);
650 atl1_write_phy_reg(hw, MII_DBG_DATA, 0);
651
652 }
653 #endif
654
655 /*
656 * Resets the PHY and make all config validate
657 * hw - Struct containing variables accessed by shared code
658 *
659 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
660 */
661 static s32 atl1_phy_reset(struct atl1_hw *hw)
662 {
663 struct pci_dev *pdev = hw->back->pdev;
664 struct atl1_adapter *adapter = hw->back;
665 s32 ret_val;
666 u16 phy_data;
667
668 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
669 hw->media_type == MEDIA_TYPE_1000M_FULL)
670 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
671 else {
672 switch (hw->media_type) {
673 case MEDIA_TYPE_100M_FULL:
674 phy_data =
675 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
676 MII_CR_RESET;
677 break;
678 case MEDIA_TYPE_100M_HALF:
679 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
680 break;
681 case MEDIA_TYPE_10M_FULL:
682 phy_data =
683 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
684 break;
685 default:
686 /* MEDIA_TYPE_10M_HALF: */
687 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
688 break;
689 }
690 }
691
692 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
693 if (ret_val) {
694 u32 val;
695 int i;
696 /* pcie serdes link may be down! */
697 if (netif_msg_hw(adapter))
698 dev_dbg(&pdev->dev, "pcie phy link down\n");
699
700 for (i = 0; i < 25; i++) {
701 msleep(1);
702 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
703 if (!(val & (MDIO_START | MDIO_BUSY)))
704 break;
705 }
706
707 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
708 if (netif_msg_hw(adapter))
709 dev_warn(&pdev->dev,
710 "pcie link down at least 25ms\n");
711 return ret_val;
712 }
713 }
714 return 0;
715 }
716
717 /*
718 * Configures PHY autoneg and flow control advertisement settings
719 * hw - Struct containing variables accessed by shared code
720 */
721 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
722 {
723 s32 ret_val;
724 s16 mii_autoneg_adv_reg;
725 s16 mii_1000t_ctrl_reg;
726
727 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
728 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
729
730 /* Read the MII 1000Base-T Control Register (Address 9). */
731 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
732
733 /*
734 * First we clear all the 10/100 mb speed bits in the Auto-Neg
735 * Advertisement Register (Address 4) and the 1000 mb speed bits in
736 * the 1000Base-T Control Register (Address 9).
737 */
738 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
739 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
740
741 /*
742 * Need to parse media_type and set up
743 * the appropriate PHY registers.
744 */
745 switch (hw->media_type) {
746 case MEDIA_TYPE_AUTO_SENSOR:
747 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
748 MII_AR_10T_FD_CAPS |
749 MII_AR_100TX_HD_CAPS |
750 MII_AR_100TX_FD_CAPS);
751 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
752 break;
753
754 case MEDIA_TYPE_1000M_FULL:
755 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
756 break;
757
758 case MEDIA_TYPE_100M_FULL:
759 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
760 break;
761
762 case MEDIA_TYPE_100M_HALF:
763 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
764 break;
765
766 case MEDIA_TYPE_10M_FULL:
767 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
768 break;
769
770 default:
771 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
772 break;
773 }
774
775 /* flow control fixed to enable all */
776 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
777
778 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
779 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
780
781 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
782 if (ret_val)
783 return ret_val;
784
785 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
786 if (ret_val)
787 return ret_val;
788
789 return 0;
790 }
791
792 /*
793 * Configures link settings.
794 * hw - Struct containing variables accessed by shared code
795 * Assumes the hardware has previously been reset and the
796 * transmitter and receiver are not enabled.
797 */
798 static s32 atl1_setup_link(struct atl1_hw *hw)
799 {
800 struct pci_dev *pdev = hw->back->pdev;
801 struct atl1_adapter *adapter = hw->back;
802 s32 ret_val;
803
804 /*
805 * Options:
806 * PHY will advertise value(s) parsed from
807 * autoneg_advertised and fc
808 * no matter what autoneg is , We will not wait link result.
809 */
810 ret_val = atl1_phy_setup_autoneg_adv(hw);
811 if (ret_val) {
812 if (netif_msg_link(adapter))
813 dev_dbg(&pdev->dev,
814 "error setting up autonegotiation\n");
815 return ret_val;
816 }
817 /* SW.Reset , En-Auto-Neg if needed */
818 ret_val = atl1_phy_reset(hw);
819 if (ret_val) {
820 if (netif_msg_link(adapter))
821 dev_dbg(&pdev->dev, "error resetting phy\n");
822 return ret_val;
823 }
824 hw->phy_configured = true;
825 return ret_val;
826 }
827
828 static void atl1_init_flash_opcode(struct atl1_hw *hw)
829 {
830 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
831 /* Atmel */
832 hw->flash_vendor = 0;
833
834 /* Init OP table */
835 iowrite8(flash_table[hw->flash_vendor].cmd_program,
836 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
837 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
838 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
839 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
840 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
841 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
842 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
843 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
844 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
845 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
846 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
847 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
848 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
849 iowrite8(flash_table[hw->flash_vendor].cmd_read,
850 hw->hw_addr + REG_SPI_FLASH_OP_READ);
851 }
852
853 /*
854 * Performs basic configuration of the adapter.
855 * hw - Struct containing variables accessed by shared code
856 * Assumes that the controller has previously been reset and is in a
857 * post-reset uninitialized state. Initializes multicast table,
858 * and Calls routines to setup link
859 * Leaves the transmit and receive units disabled and uninitialized.
860 */
861 static s32 atl1_init_hw(struct atl1_hw *hw)
862 {
863 u32 ret_val = 0;
864
865 /* Zero out the Multicast HASH table */
866 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
867 /* clear the old settings from the multicast hash table */
868 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
869
870 atl1_init_flash_opcode(hw);
871
872 if (!hw->phy_configured) {
873 /* enable GPHY LinkChange Interrrupt */
874 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
875 if (ret_val)
876 return ret_val;
877 /* make PHY out of power-saving state */
878 ret_val = atl1_phy_leave_power_saving(hw);
879 if (ret_val)
880 return ret_val;
881 /* Call a subroutine to configure the link */
882 ret_val = atl1_setup_link(hw);
883 }
884 return ret_val;
885 }
886
887 /*
888 * Detects the current speed and duplex settings of the hardware.
889 * hw - Struct containing variables accessed by shared code
890 * speed - Speed of the connection
891 * duplex - Duplex setting of the connection
892 */
893 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
894 {
895 struct pci_dev *pdev = hw->back->pdev;
896 struct atl1_adapter *adapter = hw->back;
897 s32 ret_val;
898 u16 phy_data;
899
900 /* ; --- Read PHY Specific Status Register (17) */
901 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
902 if (ret_val)
903 return ret_val;
904
905 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
906 return ATLX_ERR_PHY_RES;
907
908 switch (phy_data & MII_ATLX_PSSR_SPEED) {
909 case MII_ATLX_PSSR_1000MBS:
910 *speed = SPEED_1000;
911 break;
912 case MII_ATLX_PSSR_100MBS:
913 *speed = SPEED_100;
914 break;
915 case MII_ATLX_PSSR_10MBS:
916 *speed = SPEED_10;
917 break;
918 default:
919 if (netif_msg_hw(adapter))
920 dev_dbg(&pdev->dev, "error getting speed\n");
921 return ATLX_ERR_PHY_SPEED;
922 break;
923 }
924 if (phy_data & MII_ATLX_PSSR_DPLX)
925 *duplex = FULL_DUPLEX;
926 else
927 *duplex = HALF_DUPLEX;
928
929 return 0;
930 }
931
932 void atl1_set_mac_addr(struct atl1_hw *hw)
933 {
934 u32 value;
935 /*
936 * 00-0B-6A-F6-00-DC
937 * 0: 6AF600DC 1: 000B
938 * low dword
939 */
940 value = (((u32) hw->mac_addr[2]) << 24) |
941 (((u32) hw->mac_addr[3]) << 16) |
942 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
943 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
944 /* high dword */
945 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
946 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
947 }
948
949 /*
950 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
951 * @adapter: board private structure to initialize
952 *
953 * atl1_sw_init initializes the Adapter private data structure.
954 * Fields are initialized based on PCI device information and
955 * OS network device settings (MTU size).
956 */
957 static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
958 {
959 struct atl1_hw *hw = &adapter->hw;
960 struct net_device *netdev = adapter->netdev;
961
962 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
963 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
964
965 adapter->wol = 0;
966 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
967 adapter->ict = 50000; /* 100ms */
968 adapter->link_speed = SPEED_0; /* hardware init */
969 adapter->link_duplex = FULL_DUPLEX;
970
971 hw->phy_configured = false;
972 hw->preamble_len = 7;
973 hw->ipgt = 0x60;
974 hw->min_ifg = 0x50;
975 hw->ipgr1 = 0x40;
976 hw->ipgr2 = 0x60;
977 hw->max_retry = 0xf;
978 hw->lcol = 0x37;
979 hw->jam_ipg = 7;
980 hw->rfd_burst = 8;
981 hw->rrd_burst = 8;
982 hw->rfd_fetch_gap = 1;
983 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
984 hw->rx_jumbo_lkah = 1;
985 hw->rrd_ret_timer = 16;
986 hw->tpd_burst = 4;
987 hw->tpd_fetch_th = 16;
988 hw->txf_burst = 0x100;
989 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
990 hw->tpd_fetch_gap = 1;
991 hw->rcb_value = atl1_rcb_64;
992 hw->dma_ord = atl1_dma_ord_enh;
993 hw->dmar_block = atl1_dma_req_256;
994 hw->dmaw_block = atl1_dma_req_256;
995 hw->cmb_rrd = 4;
996 hw->cmb_tpd = 4;
997 hw->cmb_rx_timer = 1; /* about 2us */
998 hw->cmb_tx_timer = 1; /* about 2us */
999 hw->smb_timer = 100000; /* about 200ms */
1000
1001 spin_lock_init(&adapter->lock);
1002 spin_lock_init(&adapter->mb_lock);
1003
1004 return 0;
1005 }
1006
1007 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
1008 {
1009 struct atl1_adapter *adapter = netdev_priv(netdev);
1010 u16 result;
1011
1012 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1013
1014 return result;
1015 }
1016
1017 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1018 int val)
1019 {
1020 struct atl1_adapter *adapter = netdev_priv(netdev);
1021
1022 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1023 }
1024
1025 /*
1026 * atl1_mii_ioctl -
1027 * @netdev:
1028 * @ifreq:
1029 * @cmd:
1030 */
1031 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1032 {
1033 struct atl1_adapter *adapter = netdev_priv(netdev);
1034 unsigned long flags;
1035 int retval;
1036
1037 if (!netif_running(netdev))
1038 return -EINVAL;
1039
1040 spin_lock_irqsave(&adapter->lock, flags);
1041 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1042 spin_unlock_irqrestore(&adapter->lock, flags);
1043
1044 return retval;
1045 }
1046
1047 /*
1048 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1049 * @adapter: board private structure
1050 *
1051 * Return 0 on success, negative on failure
1052 */
1053 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1054 {
1055 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1056 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1057 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1058 struct atl1_ring_header *ring_header = &adapter->ring_header;
1059 struct pci_dev *pdev = adapter->pdev;
1060 int size;
1061 u8 offset = 0;
1062
1063 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1064 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1065 if (unlikely(!tpd_ring->buffer_info)) {
1066 if (netif_msg_drv(adapter))
1067 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1068 size);
1069 goto err_nomem;
1070 }
1071 rfd_ring->buffer_info =
1072 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
1073
1074 /*
1075 * real ring DMA buffer
1076 * each ring/block may need up to 8 bytes for alignment, hence the
1077 * additional 40 bytes tacked onto the end.
1078 */
1079 ring_header->size = size =
1080 sizeof(struct tx_packet_desc) * tpd_ring->count
1081 + sizeof(struct rx_free_desc) * rfd_ring->count
1082 + sizeof(struct rx_return_desc) * rrd_ring->count
1083 + sizeof(struct coals_msg_block)
1084 + sizeof(struct stats_msg_block)
1085 + 40;
1086
1087 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1088 &ring_header->dma);
1089 if (unlikely(!ring_header->desc)) {
1090 if (netif_msg_drv(adapter))
1091 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1092 goto err_nomem;
1093 }
1094
1095 memset(ring_header->desc, 0, ring_header->size);
1096
1097 /* init TPD ring */
1098 tpd_ring->dma = ring_header->dma;
1099 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1100 tpd_ring->dma += offset;
1101 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1102 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1103
1104 /* init RFD ring */
1105 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1106 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1107 rfd_ring->dma += offset;
1108 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1109 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1110
1111
1112 /* init RRD ring */
1113 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1114 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1115 rrd_ring->dma += offset;
1116 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1117 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1118
1119
1120 /* init CMB */
1121 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1122 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1123 adapter->cmb.dma += offset;
1124 adapter->cmb.cmb = (struct coals_msg_block *)
1125 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1126
1127 /* init SMB */
1128 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1129 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1130 adapter->smb.dma += offset;
1131 adapter->smb.smb = (struct stats_msg_block *)
1132 ((u8 *) adapter->cmb.cmb +
1133 (sizeof(struct coals_msg_block) + offset));
1134
1135 return 0;
1136
1137 err_nomem:
1138 kfree(tpd_ring->buffer_info);
1139 return -ENOMEM;
1140 }
1141
1142 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1143 {
1144 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1145 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1146 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1147
1148 atomic_set(&tpd_ring->next_to_use, 0);
1149 atomic_set(&tpd_ring->next_to_clean, 0);
1150
1151 rfd_ring->next_to_clean = 0;
1152 atomic_set(&rfd_ring->next_to_use, 0);
1153
1154 rrd_ring->next_to_use = 0;
1155 atomic_set(&rrd_ring->next_to_clean, 0);
1156 }
1157
1158 /*
1159 * atl1_clean_rx_ring - Free RFD Buffers
1160 * @adapter: board private structure
1161 */
1162 static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1163 {
1164 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1165 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1166 struct atl1_buffer *buffer_info;
1167 struct pci_dev *pdev = adapter->pdev;
1168 unsigned long size;
1169 unsigned int i;
1170
1171 /* Free all the Rx ring sk_buffs */
1172 for (i = 0; i < rfd_ring->count; i++) {
1173 buffer_info = &rfd_ring->buffer_info[i];
1174 if (buffer_info->dma) {
1175 pci_unmap_page(pdev, buffer_info->dma,
1176 buffer_info->length, PCI_DMA_FROMDEVICE);
1177 buffer_info->dma = 0;
1178 }
1179 if (buffer_info->skb) {
1180 dev_kfree_skb(buffer_info->skb);
1181 buffer_info->skb = NULL;
1182 }
1183 }
1184
1185 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1186 memset(rfd_ring->buffer_info, 0, size);
1187
1188 /* Zero out the descriptor ring */
1189 memset(rfd_ring->desc, 0, rfd_ring->size);
1190
1191 rfd_ring->next_to_clean = 0;
1192 atomic_set(&rfd_ring->next_to_use, 0);
1193
1194 rrd_ring->next_to_use = 0;
1195 atomic_set(&rrd_ring->next_to_clean, 0);
1196 }
1197
1198 /*
1199 * atl1_clean_tx_ring - Free Tx Buffers
1200 * @adapter: board private structure
1201 */
1202 static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1203 {
1204 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1205 struct atl1_buffer *buffer_info;
1206 struct pci_dev *pdev = adapter->pdev;
1207 unsigned long size;
1208 unsigned int i;
1209
1210 /* Free all the Tx ring sk_buffs */
1211 for (i = 0; i < tpd_ring->count; i++) {
1212 buffer_info = &tpd_ring->buffer_info[i];
1213 if (buffer_info->dma) {
1214 pci_unmap_page(pdev, buffer_info->dma,
1215 buffer_info->length, PCI_DMA_TODEVICE);
1216 buffer_info->dma = 0;
1217 }
1218 }
1219
1220 for (i = 0; i < tpd_ring->count; i++) {
1221 buffer_info = &tpd_ring->buffer_info[i];
1222 if (buffer_info->skb) {
1223 dev_kfree_skb_any(buffer_info->skb);
1224 buffer_info->skb = NULL;
1225 }
1226 }
1227
1228 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1229 memset(tpd_ring->buffer_info, 0, size);
1230
1231 /* Zero out the descriptor ring */
1232 memset(tpd_ring->desc, 0, tpd_ring->size);
1233
1234 atomic_set(&tpd_ring->next_to_use, 0);
1235 atomic_set(&tpd_ring->next_to_clean, 0);
1236 }
1237
1238 /*
1239 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1240 * @adapter: board private structure
1241 *
1242 * Free all transmit software resources
1243 */
1244 static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1245 {
1246 struct pci_dev *pdev = adapter->pdev;
1247 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1248 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1249 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1250 struct atl1_ring_header *ring_header = &adapter->ring_header;
1251
1252 atl1_clean_tx_ring(adapter);
1253 atl1_clean_rx_ring(adapter);
1254
1255 kfree(tpd_ring->buffer_info);
1256 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1257 ring_header->dma);
1258
1259 tpd_ring->buffer_info = NULL;
1260 tpd_ring->desc = NULL;
1261 tpd_ring->dma = 0;
1262
1263 rfd_ring->buffer_info = NULL;
1264 rfd_ring->desc = NULL;
1265 rfd_ring->dma = 0;
1266
1267 rrd_ring->desc = NULL;
1268 rrd_ring->dma = 0;
1269 }
1270
1271 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1272 {
1273 u32 value;
1274 struct atl1_hw *hw = &adapter->hw;
1275 struct net_device *netdev = adapter->netdev;
1276 /* Config MAC CTRL Register */
1277 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1278 /* duplex */
1279 if (FULL_DUPLEX == adapter->link_duplex)
1280 value |= MAC_CTRL_DUPLX;
1281 /* speed */
1282 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1283 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1284 MAC_CTRL_SPEED_SHIFT);
1285 /* flow control */
1286 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1287 /* PAD & CRC */
1288 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1289 /* preamble length */
1290 value |= (((u32) adapter->hw.preamble_len
1291 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1292 /* vlan */
1293 if (adapter->vlgrp)
1294 value |= MAC_CTRL_RMV_VLAN;
1295 /* rx checksum
1296 if (adapter->rx_csum)
1297 value |= MAC_CTRL_RX_CHKSUM_EN;
1298 */
1299 /* filter mode */
1300 value |= MAC_CTRL_BC_EN;
1301 if (netdev->flags & IFF_PROMISC)
1302 value |= MAC_CTRL_PROMIS_EN;
1303 else if (netdev->flags & IFF_ALLMULTI)
1304 value |= MAC_CTRL_MC_ALL_EN;
1305 /* value |= MAC_CTRL_LOOPBACK; */
1306 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1307 }
1308
1309 static u32 atl1_check_link(struct atl1_adapter *adapter)
1310 {
1311 struct atl1_hw *hw = &adapter->hw;
1312 struct net_device *netdev = adapter->netdev;
1313 u32 ret_val;
1314 u16 speed, duplex, phy_data;
1315 int reconfig = 0;
1316
1317 /* MII_BMSR must read twice */
1318 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1319 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1320 if (!(phy_data & BMSR_LSTATUS)) {
1321 /* link down */
1322 if (netif_carrier_ok(netdev)) {
1323 /* old link state: Up */
1324 if (netif_msg_link(adapter))
1325 dev_info(&adapter->pdev->dev, "link is down\n");
1326 adapter->link_speed = SPEED_0;
1327 netif_carrier_off(netdev);
1328 netif_stop_queue(netdev);
1329 }
1330 return 0;
1331 }
1332
1333 /* Link Up */
1334 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1335 if (ret_val)
1336 return ret_val;
1337
1338 switch (hw->media_type) {
1339 case MEDIA_TYPE_1000M_FULL:
1340 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1341 reconfig = 1;
1342 break;
1343 case MEDIA_TYPE_100M_FULL:
1344 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1345 reconfig = 1;
1346 break;
1347 case MEDIA_TYPE_100M_HALF:
1348 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1349 reconfig = 1;
1350 break;
1351 case MEDIA_TYPE_10M_FULL:
1352 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1353 reconfig = 1;
1354 break;
1355 case MEDIA_TYPE_10M_HALF:
1356 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1357 reconfig = 1;
1358 break;
1359 }
1360
1361 /* link result is our setting */
1362 if (!reconfig) {
1363 if (adapter->link_speed != speed
1364 || adapter->link_duplex != duplex) {
1365 adapter->link_speed = speed;
1366 adapter->link_duplex = duplex;
1367 atl1_setup_mac_ctrl(adapter);
1368 if (netif_msg_link(adapter))
1369 dev_info(&adapter->pdev->dev,
1370 "%s link is up %d Mbps %s\n",
1371 netdev->name, adapter->link_speed,
1372 adapter->link_duplex == FULL_DUPLEX ?
1373 "full duplex" : "half duplex");
1374 }
1375 if (!netif_carrier_ok(netdev)) {
1376 /* Link down -> Up */
1377 netif_carrier_on(netdev);
1378 netif_wake_queue(netdev);
1379 }
1380 return 0;
1381 }
1382
1383 /* change original link status */
1384 if (netif_carrier_ok(netdev)) {
1385 adapter->link_speed = SPEED_0;
1386 netif_carrier_off(netdev);
1387 netif_stop_queue(netdev);
1388 }
1389
1390 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1391 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1392 switch (hw->media_type) {
1393 case MEDIA_TYPE_100M_FULL:
1394 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1395 MII_CR_RESET;
1396 break;
1397 case MEDIA_TYPE_100M_HALF:
1398 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1399 break;
1400 case MEDIA_TYPE_10M_FULL:
1401 phy_data =
1402 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1403 break;
1404 default:
1405 /* MEDIA_TYPE_10M_HALF: */
1406 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1407 break;
1408 }
1409 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1410 return 0;
1411 }
1412
1413 /* auto-neg, insert timer to re-config phy */
1414 if (!adapter->phy_timer_pending) {
1415 adapter->phy_timer_pending = true;
1416 mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
1417 }
1418
1419 return 0;
1420 }
1421
1422 static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1423 {
1424 u32 hi, lo, value;
1425
1426 /* RFD Flow Control */
1427 value = adapter->rfd_ring.count;
1428 hi = value / 16;
1429 if (hi < 2)
1430 hi = 2;
1431 lo = value * 7 / 8;
1432
1433 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1434 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1435 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1436
1437 /* RRD Flow Control */
1438 value = adapter->rrd_ring.count;
1439 lo = value / 16;
1440 hi = value * 7 / 8;
1441 if (lo < 2)
1442 lo = 2;
1443 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1444 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1445 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1446 }
1447
1448 static void set_flow_ctrl_new(struct atl1_hw *hw)
1449 {
1450 u32 hi, lo, value;
1451
1452 /* RXF Flow Control */
1453 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1454 lo = value / 16;
1455 if (lo < 192)
1456 lo = 192;
1457 hi = value * 7 / 8;
1458 if (hi < lo)
1459 hi = lo + 16;
1460 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1461 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1462 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1463
1464 /* RRD Flow Control */
1465 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1466 lo = value / 8;
1467 hi = value * 7 / 8;
1468 if (lo < 2)
1469 lo = 2;
1470 if (hi < lo)
1471 hi = lo + 3;
1472 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1473 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1474 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1475 }
1476
1477 /*
1478 * atl1_configure - Configure Transmit&Receive Unit after Reset
1479 * @adapter: board private structure
1480 *
1481 * Configure the Tx /Rx unit of the MAC after a reset.
1482 */
1483 static u32 atl1_configure(struct atl1_adapter *adapter)
1484 {
1485 struct atl1_hw *hw = &adapter->hw;
1486 u32 value;
1487
1488 /* clear interrupt status */
1489 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1490
1491 /* set MAC Address */
1492 value = (((u32) hw->mac_addr[2]) << 24) |
1493 (((u32) hw->mac_addr[3]) << 16) |
1494 (((u32) hw->mac_addr[4]) << 8) |
1495 (((u32) hw->mac_addr[5]));
1496 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1497 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1498 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1499
1500 /* tx / rx ring */
1501
1502 /* HI base address */
1503 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1504 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1505 /* LO base address */
1506 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1507 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1508 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1509 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1510 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1511 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1512 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1513 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1514 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1515 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1516
1517 /* element count */
1518 value = adapter->rrd_ring.count;
1519 value <<= 16;
1520 value += adapter->rfd_ring.count;
1521 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1522 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1523 REG_DESC_TPD_RING_SIZE);
1524
1525 /* Load Ptr */
1526 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1527
1528 /* config Mailbox */
1529 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1530 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1531 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1532 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1533 ((atomic_read(&adapter->rfd_ring.next_to_use)
1534 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1535 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1536
1537 /* config IPG/IFG */
1538 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1539 << MAC_IPG_IFG_IPGT_SHIFT) |
1540 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1541 << MAC_IPG_IFG_MIFG_SHIFT) |
1542 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1543 << MAC_IPG_IFG_IPGR1_SHIFT) |
1544 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1545 << MAC_IPG_IFG_IPGR2_SHIFT);
1546 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1547
1548 /* config Half-Duplex Control */
1549 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1550 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1551 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1552 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1553 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1554 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1555 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1556 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1557
1558 /* set Interrupt Moderator Timer */
1559 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1560 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1561
1562 /* set Interrupt Clear Timer */
1563 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1564
1565 /* set max frame size hw will accept */
1566 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1567
1568 /* jumbo size & rrd retirement timer */
1569 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1570 << RXQ_JMBOSZ_TH_SHIFT) |
1571 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1572 << RXQ_JMBO_LKAH_SHIFT) |
1573 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1574 << RXQ_RRD_TIMER_SHIFT);
1575 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1576
1577 /* Flow Control */
1578 switch (hw->dev_rev) {
1579 case 0x8001:
1580 case 0x9001:
1581 case 0x9002:
1582 case 0x9003:
1583 set_flow_ctrl_old(adapter);
1584 break;
1585 default:
1586 set_flow_ctrl_new(hw);
1587 break;
1588 }
1589
1590 /* config TXQ */
1591 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1592 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1593 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1594 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1595 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1596 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1597 TXQ_CTRL_EN;
1598 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1599
1600 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1601 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1602 << TX_JUMBO_TASK_TH_SHIFT) |
1603 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1604 << TX_TPD_MIN_IPG_SHIFT);
1605 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1606
1607 /* config RXQ */
1608 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1609 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1610 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1611 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1612 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1613 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1614 RXQ_CTRL_EN;
1615 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1616
1617 /* config DMA Engine */
1618 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1619 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1620 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1621 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1622 DMA_CTRL_DMAW_EN;
1623 value |= (u32) hw->dma_ord;
1624 if (atl1_rcb_128 == hw->rcb_value)
1625 value |= DMA_CTRL_RCB_VALUE;
1626 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1627
1628 /* config CMB / SMB */
1629 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1630 hw->cmb_tpd : adapter->tpd_ring.count;
1631 value <<= 16;
1632 value |= hw->cmb_rrd;
1633 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1634 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1635 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1636 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1637
1638 /* --- enable CMB / SMB */
1639 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1640 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1641
1642 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1643 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1644 value = 1; /* config failed */
1645 else
1646 value = 0;
1647
1648 /* clear all interrupt status */
1649 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1650 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1651 return value;
1652 }
1653
1654 /*
1655 * atl1_pcie_patch - Patch for PCIE module
1656 */
1657 static void atl1_pcie_patch(struct atl1_adapter *adapter)
1658 {
1659 u32 value;
1660
1661 /* much vendor magic here */
1662 value = 0x6500;
1663 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1664 /* pcie flow control mode change */
1665 value = ioread32(adapter->hw.hw_addr + 0x1008);
1666 value |= 0x8000;
1667 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1668 }
1669
1670 /*
1671 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1672 * on PCI Command register is disable.
1673 * The function enable this bit.
1674 * Brackett, 2006/03/15
1675 */
1676 static void atl1_via_workaround(struct atl1_adapter *adapter)
1677 {
1678 unsigned long value;
1679
1680 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1681 if (value & PCI_COMMAND_INTX_DISABLE)
1682 value &= ~PCI_COMMAND_INTX_DISABLE;
1683 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1684 }
1685
1686 static void atl1_inc_smb(struct atl1_adapter *adapter)
1687 {
1688 struct stats_msg_block *smb = adapter->smb.smb;
1689
1690 /* Fill out the OS statistics structure */
1691 adapter->soft_stats.rx_packets += smb->rx_ok;
1692 adapter->soft_stats.tx_packets += smb->tx_ok;
1693 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1694 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1695 adapter->soft_stats.multicast += smb->rx_mcast;
1696 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1697 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1698
1699 /* Rx Errors */
1700 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1701 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1702 smb->rx_rrd_ov + smb->rx_align_err);
1703 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1704 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1705 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1706 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1707 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1708 smb->rx_rxf_ov);
1709
1710 adapter->soft_stats.rx_pause += smb->rx_pause;
1711 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1712 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1713
1714 /* Tx Errors */
1715 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1716 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1717 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1718 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1719 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1720
1721 adapter->soft_stats.excecol += smb->tx_abort_col;
1722 adapter->soft_stats.deffer += smb->tx_defer;
1723 adapter->soft_stats.scc += smb->tx_1_col;
1724 adapter->soft_stats.mcc += smb->tx_2_col;
1725 adapter->soft_stats.latecol += smb->tx_late_col;
1726 adapter->soft_stats.tx_underun += smb->tx_underrun;
1727 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1728 adapter->soft_stats.tx_pause += smb->tx_pause;
1729
1730 adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets;
1731 adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets;
1732 adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
1733 adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
1734 adapter->net_stats.multicast = adapter->soft_stats.multicast;
1735 adapter->net_stats.collisions = adapter->soft_stats.collisions;
1736 adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
1737 adapter->net_stats.rx_over_errors =
1738 adapter->soft_stats.rx_missed_errors;
1739 adapter->net_stats.rx_length_errors =
1740 adapter->soft_stats.rx_length_errors;
1741 adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1742 adapter->net_stats.rx_frame_errors =
1743 adapter->soft_stats.rx_frame_errors;
1744 adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1745 adapter->net_stats.rx_missed_errors =
1746 adapter->soft_stats.rx_missed_errors;
1747 adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
1748 adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1749 adapter->net_stats.tx_aborted_errors =
1750 adapter->soft_stats.tx_aborted_errors;
1751 adapter->net_stats.tx_window_errors =
1752 adapter->soft_stats.tx_window_errors;
1753 adapter->net_stats.tx_carrier_errors =
1754 adapter->soft_stats.tx_carrier_errors;
1755 }
1756
1757 static void atl1_update_mailbox(struct atl1_adapter *adapter)
1758 {
1759 unsigned long flags;
1760 u32 tpd_next_to_use;
1761 u32 rfd_next_to_use;
1762 u32 rrd_next_to_clean;
1763 u32 value;
1764
1765 spin_lock_irqsave(&adapter->mb_lock, flags);
1766
1767 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1768 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1769 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1770
1771 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1772 MB_RFD_PROD_INDX_SHIFT) |
1773 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1774 MB_RRD_CONS_INDX_SHIFT) |
1775 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1776 MB_TPD_PROD_INDX_SHIFT);
1777 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1778
1779 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1780 }
1781
1782 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1783 struct rx_return_desc *rrd, u16 offset)
1784 {
1785 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1786
1787 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1788 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1789 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1790 rfd_ring->next_to_clean = 0;
1791 }
1792 }
1793 }
1794
1795 static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1796 struct rx_return_desc *rrd)
1797 {
1798 u16 num_buf;
1799
1800 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1801 adapter->rx_buffer_len;
1802 if (rrd->num_buf == num_buf)
1803 /* clean alloc flag for bad rrd */
1804 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1805 }
1806
1807 static void atl1_rx_checksum(struct atl1_adapter *adapter,
1808 struct rx_return_desc *rrd, struct sk_buff *skb)
1809 {
1810 struct pci_dev *pdev = adapter->pdev;
1811
1812 skb->ip_summed = CHECKSUM_NONE;
1813
1814 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1815 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1816 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1817 adapter->hw_csum_err++;
1818 if (netif_msg_rx_err(adapter))
1819 dev_printk(KERN_DEBUG, &pdev->dev,
1820 "rx checksum error\n");
1821 return;
1822 }
1823 }
1824
1825 /* not IPv4 */
1826 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1827 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1828 return;
1829
1830 /* IPv4 packet */
1831 if (likely(!(rrd->err_flg &
1832 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1833 skb->ip_summed = CHECKSUM_UNNECESSARY;
1834 adapter->hw_csum_good++;
1835 return;
1836 }
1837
1838 /* IPv4, but hardware thinks its checksum is wrong */
1839 if (netif_msg_rx_err(adapter))
1840 dev_printk(KERN_DEBUG, &pdev->dev,
1841 "hw csum wrong, pkt_flag:%x, err_flag:%x\n",
1842 rrd->pkt_flg, rrd->err_flg);
1843 skb->ip_summed = CHECKSUM_COMPLETE;
1844 skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum);
1845 adapter->hw_csum_err++;
1846 return;
1847 }
1848
1849 /*
1850 * atl1_alloc_rx_buffers - Replace used receive buffers
1851 * @adapter: address of board private structure
1852 */
1853 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1854 {
1855 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1856 struct pci_dev *pdev = adapter->pdev;
1857 struct page *page;
1858 unsigned long offset;
1859 struct atl1_buffer *buffer_info, *next_info;
1860 struct sk_buff *skb;
1861 u16 num_alloc = 0;
1862 u16 rfd_next_to_use, next_next;
1863 struct rx_free_desc *rfd_desc;
1864
1865 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1866 if (++next_next == rfd_ring->count)
1867 next_next = 0;
1868 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1869 next_info = &rfd_ring->buffer_info[next_next];
1870
1871 while (!buffer_info->alloced && !next_info->alloced) {
1872 if (buffer_info->skb) {
1873 buffer_info->alloced = 1;
1874 goto next;
1875 }
1876
1877 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1878
1879 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
1880 if (unlikely(!skb)) {
1881 /* Better luck next round */
1882 adapter->net_stats.rx_dropped++;
1883 break;
1884 }
1885
1886 /*
1887 * Make buffer alignment 2 beyond a 16 byte boundary
1888 * this will result in a 16 byte aligned IP header after
1889 * the 14 byte MAC header is removed
1890 */
1891 skb_reserve(skb, NET_IP_ALIGN);
1892
1893 buffer_info->alloced = 1;
1894 buffer_info->skb = skb;
1895 buffer_info->length = (u16) adapter->rx_buffer_len;
1896 page = virt_to_page(skb->data);
1897 offset = (unsigned long)skb->data & ~PAGE_MASK;
1898 buffer_info->dma = pci_map_page(pdev, page, offset,
1899 adapter->rx_buffer_len,
1900 PCI_DMA_FROMDEVICE);
1901 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1902 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1903 rfd_desc->coalese = 0;
1904
1905 next:
1906 rfd_next_to_use = next_next;
1907 if (unlikely(++next_next == rfd_ring->count))
1908 next_next = 0;
1909
1910 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1911 next_info = &rfd_ring->buffer_info[next_next];
1912 num_alloc++;
1913 }
1914
1915 if (num_alloc) {
1916 /*
1917 * Force memory writes to complete before letting h/w
1918 * know there are new descriptors to fetch. (Only
1919 * applicable for weak-ordered memory model archs,
1920 * such as IA-64).
1921 */
1922 wmb();
1923 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1924 }
1925 return num_alloc;
1926 }
1927
1928 static void atl1_intr_rx(struct atl1_adapter *adapter)
1929 {
1930 int i, count;
1931 u16 length;
1932 u16 rrd_next_to_clean;
1933 u32 value;
1934 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1935 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1936 struct atl1_buffer *buffer_info;
1937 struct rx_return_desc *rrd;
1938 struct sk_buff *skb;
1939
1940 count = 0;
1941
1942 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1943
1944 while (1) {
1945 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1946 i = 1;
1947 if (likely(rrd->xsz.valid)) { /* packet valid */
1948 chk_rrd:
1949 /* check rrd status */
1950 if (likely(rrd->num_buf == 1))
1951 goto rrd_ok;
1952 else if (netif_msg_rx_err(adapter)) {
1953 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1954 "unexpected RRD buffer count\n");
1955 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1956 "rx_buf_len = %d\n",
1957 adapter->rx_buffer_len);
1958 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1959 "RRD num_buf = %d\n",
1960 rrd->num_buf);
1961 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1962 "RRD pkt_len = %d\n",
1963 rrd->xsz.xsum_sz.pkt_size);
1964 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1965 "RRD pkt_flg = 0x%08X\n",
1966 rrd->pkt_flg);
1967 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1968 "RRD err_flg = 0x%08X\n",
1969 rrd->err_flg);
1970 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1971 "RRD vlan_tag = 0x%08X\n",
1972 rrd->vlan_tag);
1973 }
1974
1975 /* rrd seems to be bad */
1976 if (unlikely(i-- > 0)) {
1977 /* rrd may not be DMAed completely */
1978 udelay(1);
1979 goto chk_rrd;
1980 }
1981 /* bad rrd */
1982 if (netif_msg_rx_err(adapter))
1983 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1984 "bad RRD\n");
1985 /* see if update RFD index */
1986 if (rrd->num_buf > 1)
1987 atl1_update_rfd_index(adapter, rrd);
1988
1989 /* update rrd */
1990 rrd->xsz.valid = 0;
1991 if (++rrd_next_to_clean == rrd_ring->count)
1992 rrd_next_to_clean = 0;
1993 count++;
1994 continue;
1995 } else { /* current rrd still not be updated */
1996
1997 break;
1998 }
1999 rrd_ok:
2000 /* clean alloc flag for bad rrd */
2001 atl1_clean_alloc_flag(adapter, rrd, 0);
2002
2003 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
2004 if (++rfd_ring->next_to_clean == rfd_ring->count)
2005 rfd_ring->next_to_clean = 0;
2006
2007 /* update rrd next to clean */
2008 if (++rrd_next_to_clean == rrd_ring->count)
2009 rrd_next_to_clean = 0;
2010 count++;
2011
2012 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2013 if (!(rrd->err_flg &
2014 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2015 | ERR_FLAG_LEN))) {
2016 /* packet error, don't need upstream */
2017 buffer_info->alloced = 0;
2018 rrd->xsz.valid = 0;
2019 continue;
2020 }
2021 }
2022
2023 /* Good Receive */
2024 pci_unmap_page(adapter->pdev, buffer_info->dma,
2025 buffer_info->length, PCI_DMA_FROMDEVICE);
2026 buffer_info->dma = 0;
2027 skb = buffer_info->skb;
2028 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
2029
2030 skb_put(skb, length - ETH_FCS_LEN);
2031
2032 /* Receive Checksum Offload */
2033 atl1_rx_checksum(adapter, rrd, skb);
2034 skb->protocol = eth_type_trans(skb, adapter->netdev);
2035
2036 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
2037 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2038 ((rrd->vlan_tag & 7) << 13) |
2039 ((rrd->vlan_tag & 8) << 9);
2040 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
2041 } else
2042 netif_rx(skb);
2043
2044 /* let protocol layer free skb */
2045 buffer_info->skb = NULL;
2046 buffer_info->alloced = 0;
2047 rrd->xsz.valid = 0;
2048
2049 adapter->netdev->last_rx = jiffies;
2050 }
2051
2052 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
2053
2054 atl1_alloc_rx_buffers(adapter);
2055
2056 /* update mailbox ? */
2057 if (count) {
2058 u32 tpd_next_to_use;
2059 u32 rfd_next_to_use;
2060
2061 spin_lock(&adapter->mb_lock);
2062
2063 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2064 rfd_next_to_use =
2065 atomic_read(&adapter->rfd_ring.next_to_use);
2066 rrd_next_to_clean =
2067 atomic_read(&adapter->rrd_ring.next_to_clean);
2068 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2069 MB_RFD_PROD_INDX_SHIFT) |
2070 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2071 MB_RRD_CONS_INDX_SHIFT) |
2072 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2073 MB_TPD_PROD_INDX_SHIFT);
2074 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2075 spin_unlock(&adapter->mb_lock);
2076 }
2077 }
2078
2079 static void atl1_intr_tx(struct atl1_adapter *adapter)
2080 {
2081 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2082 struct atl1_buffer *buffer_info;
2083 u16 sw_tpd_next_to_clean;
2084 u16 cmb_tpd_next_to_clean;
2085
2086 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2087 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
2088
2089 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2090 struct tx_packet_desc *tpd;
2091
2092 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
2093 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2094 if (buffer_info->dma) {
2095 pci_unmap_page(adapter->pdev, buffer_info->dma,
2096 buffer_info->length, PCI_DMA_TODEVICE);
2097 buffer_info->dma = 0;
2098 }
2099
2100 if (buffer_info->skb) {
2101 dev_kfree_skb_irq(buffer_info->skb);
2102 buffer_info->skb = NULL;
2103 }
2104
2105 if (++sw_tpd_next_to_clean == tpd_ring->count)
2106 sw_tpd_next_to_clean = 0;
2107 }
2108 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2109
2110 if (netif_queue_stopped(adapter->netdev)
2111 && netif_carrier_ok(adapter->netdev))
2112 netif_wake_queue(adapter->netdev);
2113 }
2114
2115 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
2116 {
2117 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2118 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
2119 return ((next_to_clean > next_to_use) ?
2120 next_to_clean - next_to_use - 1 :
2121 tpd_ring->count + next_to_clean - next_to_use - 1);
2122 }
2123
2124 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
2125 struct tx_packet_desc *ptpd)
2126 {
2127 /* spinlock held */
2128 u8 hdr_len, ip_off;
2129 u32 real_len;
2130 int err;
2131
2132 if (skb_shinfo(skb)->gso_size) {
2133 if (skb_header_cloned(skb)) {
2134 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2135 if (unlikely(err))
2136 return -1;
2137 }
2138
2139 if (skb->protocol == htons(ETH_P_IP)) {
2140 struct iphdr *iph = ip_hdr(skb);
2141
2142 real_len = (((unsigned char *)iph - skb->data) +
2143 ntohs(iph->tot_len));
2144 if (real_len < skb->len)
2145 pskb_trim(skb, real_len);
2146 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2147 if (skb->len == hdr_len) {
2148 iph->check = 0;
2149 tcp_hdr(skb)->check =
2150 ~csum_tcpudp_magic(iph->saddr,
2151 iph->daddr, tcp_hdrlen(skb),
2152 IPPROTO_TCP, 0);
2153 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2154 TPD_IPHL_SHIFT;
2155 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2156 TPD_TCPHDRLEN_MASK) <<
2157 TPD_TCPHDRLEN_SHIFT;
2158 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2159 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2160 return 1;
2161 }
2162
2163 iph->check = 0;
2164 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2165 iph->daddr, 0, IPPROTO_TCP, 0);
2166 ip_off = (unsigned char *)iph -
2167 (unsigned char *) skb_network_header(skb);
2168 if (ip_off == 8) /* 802.3-SNAP frame */
2169 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2170 else if (ip_off != 0)
2171 return -2;
2172
2173 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2174 TPD_IPHL_SHIFT;
2175 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2176 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2177 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2178 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2179 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2180 return 3;
2181 }
2182 }
2183 return false;
2184 }
2185
2186 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
2187 struct tx_packet_desc *ptpd)
2188 {
2189 u8 css, cso;
2190
2191 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2192 css = (u8) (skb->csum_start - skb_headroom(skb));
2193 cso = css + (u8) skb->csum_offset;
2194 if (unlikely(css & 0x1)) {
2195 /* L1 hardware requires an even number here */
2196 if (netif_msg_tx_err(adapter))
2197 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2198 "payload offset not an even number\n");
2199 return -1;
2200 }
2201 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2202 TPD_PLOADOFFSET_SHIFT;
2203 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2204 TPD_CCSUMOFFSET_SHIFT;
2205 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
2206 return true;
2207 }
2208 return 0;
2209 }
2210
2211 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
2212 struct tx_packet_desc *ptpd)
2213 {
2214 /* spinlock held */
2215 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2216 struct atl1_buffer *buffer_info;
2217 u16 buf_len = skb->len;
2218 struct page *page;
2219 unsigned long offset;
2220 unsigned int nr_frags;
2221 unsigned int f;
2222 int retval;
2223 u16 next_to_use;
2224 u16 data_len;
2225 u8 hdr_len;
2226
2227 buf_len -= skb->data_len;
2228 nr_frags = skb_shinfo(skb)->nr_frags;
2229 next_to_use = atomic_read(&tpd_ring->next_to_use);
2230 buffer_info = &tpd_ring->buffer_info[next_to_use];
2231 if (unlikely(buffer_info->skb))
2232 BUG();
2233 /* put skb in last TPD */
2234 buffer_info->skb = NULL;
2235
2236 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2237 if (retval) {
2238 /* TSO */
2239 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2240 buffer_info->length = hdr_len;
2241 page = virt_to_page(skb->data);
2242 offset = (unsigned long)skb->data & ~PAGE_MASK;
2243 buffer_info->dma = pci_map_page(adapter->pdev, page,
2244 offset, hdr_len,
2245 PCI_DMA_TODEVICE);
2246
2247 if (++next_to_use == tpd_ring->count)
2248 next_to_use = 0;
2249
2250 if (buf_len > hdr_len) {
2251 int i, nseg;
2252
2253 data_len = buf_len - hdr_len;
2254 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
2255 ATL1_MAX_TX_BUF_LEN;
2256 for (i = 0; i < nseg; i++) {
2257 buffer_info =
2258 &tpd_ring->buffer_info[next_to_use];
2259 buffer_info->skb = NULL;
2260 buffer_info->length =
2261 (ATL1_MAX_TX_BUF_LEN >=
2262 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2263 data_len -= buffer_info->length;
2264 page = virt_to_page(skb->data +
2265 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
2266 offset = (unsigned long)(skb->data +
2267 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2268 ~PAGE_MASK;
2269 buffer_info->dma = pci_map_page(adapter->pdev,
2270 page, offset, buffer_info->length,
2271 PCI_DMA_TODEVICE);
2272 if (++next_to_use == tpd_ring->count)
2273 next_to_use = 0;
2274 }
2275 }
2276 } else {
2277 /* not TSO */
2278 buffer_info->length = buf_len;
2279 page = virt_to_page(skb->data);
2280 offset = (unsigned long)skb->data & ~PAGE_MASK;
2281 buffer_info->dma = pci_map_page(adapter->pdev, page,
2282 offset, buf_len, PCI_DMA_TODEVICE);
2283 if (++next_to_use == tpd_ring->count)
2284 next_to_use = 0;
2285 }
2286
2287 for (f = 0; f < nr_frags; f++) {
2288 struct skb_frag_struct *frag;
2289 u16 i, nseg;
2290
2291 frag = &skb_shinfo(skb)->frags[f];
2292 buf_len = frag->size;
2293
2294 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2295 ATL1_MAX_TX_BUF_LEN;
2296 for (i = 0; i < nseg; i++) {
2297 buffer_info = &tpd_ring->buffer_info[next_to_use];
2298 if (unlikely(buffer_info->skb))
2299 BUG();
2300 buffer_info->skb = NULL;
2301 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2302 ATL1_MAX_TX_BUF_LEN : buf_len;
2303 buf_len -= buffer_info->length;
2304 buffer_info->dma = pci_map_page(adapter->pdev,
2305 frag->page,
2306 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
2307 buffer_info->length, PCI_DMA_TODEVICE);
2308
2309 if (++next_to_use == tpd_ring->count)
2310 next_to_use = 0;
2311 }
2312 }
2313
2314 /* last tpd's buffer-info */
2315 buffer_info->skb = skb;
2316 }
2317
2318 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2319 struct tx_packet_desc *ptpd)
2320 {
2321 /* spinlock held */
2322 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2323 struct atl1_buffer *buffer_info;
2324 struct tx_packet_desc *tpd;
2325 u16 j;
2326 u32 val;
2327 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
2328
2329 for (j = 0; j < count; j++) {
2330 buffer_info = &tpd_ring->buffer_info[next_to_use];
2331 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2332 if (tpd != ptpd)
2333 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
2334 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2335 tpd->word2 = (cpu_to_le16(buffer_info->length) &
2336 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
2337
2338 /*
2339 * if this is the first packet in a TSO chain, set
2340 * TPD_HDRFLAG, otherwise, clear it.
2341 */
2342 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2343 TPD_SEGMENT_EN_MASK;
2344 if (val) {
2345 if (!j)
2346 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2347 else
2348 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2349 }
2350
2351 if (j == (count - 1))
2352 tpd->word3 |= 1 << TPD_EOP_SHIFT;
2353
2354 if (++next_to_use == tpd_ring->count)
2355 next_to_use = 0;
2356 }
2357 /*
2358 * Force memory writes to complete before letting h/w
2359 * know there are new descriptors to fetch. (Only
2360 * applicable for weak-ordered memory model archs,
2361 * such as IA-64).
2362 */
2363 wmb();
2364
2365 atomic_set(&tpd_ring->next_to_use, next_to_use);
2366 }
2367
2368 static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2369 {
2370 struct atl1_adapter *adapter = netdev_priv(netdev);
2371 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2372 int len = skb->len;
2373 int tso;
2374 int count = 1;
2375 int ret_val;
2376 struct tx_packet_desc *ptpd;
2377 u16 frag_size;
2378 u16 vlan_tag;
2379 unsigned long flags;
2380 unsigned int nr_frags = 0;
2381 unsigned int mss = 0;
2382 unsigned int f;
2383 unsigned int proto_hdr_len;
2384
2385 len -= skb->data_len;
2386
2387 if (unlikely(skb->len <= 0)) {
2388 dev_kfree_skb_any(skb);
2389 return NETDEV_TX_OK;
2390 }
2391
2392 nr_frags = skb_shinfo(skb)->nr_frags;
2393 for (f = 0; f < nr_frags; f++) {
2394 frag_size = skb_shinfo(skb)->frags[f].size;
2395 if (frag_size)
2396 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
2397 ATL1_MAX_TX_BUF_LEN;
2398 }
2399
2400 mss = skb_shinfo(skb)->gso_size;
2401 if (mss) {
2402 if (skb->protocol == ntohs(ETH_P_IP)) {
2403 proto_hdr_len = (skb_transport_offset(skb) +
2404 tcp_hdrlen(skb));
2405 if (unlikely(proto_hdr_len > len)) {
2406 dev_kfree_skb_any(skb);
2407 return NETDEV_TX_OK;
2408 }
2409 /* need additional TPD ? */
2410 if (proto_hdr_len != len)
2411 count += (len - proto_hdr_len +
2412 ATL1_MAX_TX_BUF_LEN - 1) /
2413 ATL1_MAX_TX_BUF_LEN;
2414 }
2415 }
2416
2417 if (!spin_trylock_irqsave(&adapter->lock, flags)) {
2418 /* Can't get lock - tell upper layer to requeue */
2419 if (netif_msg_tx_queued(adapter))
2420 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2421 "tx locked\n");
2422 return NETDEV_TX_LOCKED;
2423 }
2424
2425 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
2426 /* not enough descriptors */
2427 netif_stop_queue(netdev);
2428 spin_unlock_irqrestore(&adapter->lock, flags);
2429 if (netif_msg_tx_queued(adapter))
2430 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2431 "tx busy\n");
2432 return NETDEV_TX_BUSY;
2433 }
2434
2435 ptpd = ATL1_TPD_DESC(tpd_ring,
2436 (u16) atomic_read(&tpd_ring->next_to_use));
2437 memset(ptpd, 0, sizeof(struct tx_packet_desc));
2438
2439 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2440 vlan_tag = vlan_tx_tag_get(skb);
2441 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2442 ((vlan_tag >> 9) & 0x8);
2443 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2444 ptpd->word3 |= (vlan_tag & TPD_VL_TAGGED_MASK) <<
2445 TPD_VL_TAGGED_SHIFT;
2446 }
2447
2448 tso = atl1_tso(adapter, skb, ptpd);
2449 if (tso < 0) {
2450 spin_unlock_irqrestore(&adapter->lock, flags);
2451 dev_kfree_skb_any(skb);
2452 return NETDEV_TX_OK;
2453 }
2454
2455 if (!tso) {
2456 ret_val = atl1_tx_csum(adapter, skb, ptpd);
2457 if (ret_val < 0) {
2458 spin_unlock_irqrestore(&adapter->lock, flags);
2459 dev_kfree_skb_any(skb);
2460 return NETDEV_TX_OK;
2461 }
2462 }
2463
2464 atl1_tx_map(adapter, skb, ptpd);
2465 atl1_tx_queue(adapter, count, ptpd);
2466 atl1_update_mailbox(adapter);
2467 spin_unlock_irqrestore(&adapter->lock, flags);
2468 netdev->trans_start = jiffies;
2469 return NETDEV_TX_OK;
2470 }
2471
2472 /*
2473 * atl1_intr - Interrupt Handler
2474 * @irq: interrupt number
2475 * @data: pointer to a network interface device structure
2476 * @pt_regs: CPU registers structure
2477 */
2478 static irqreturn_t atl1_intr(int irq, void *data)
2479 {
2480 struct atl1_adapter *adapter = netdev_priv(data);
2481 u32 status;
2482 int max_ints = 10;
2483
2484 status = adapter->cmb.cmb->int_stats;
2485 if (!status)
2486 return IRQ_NONE;
2487
2488 do {
2489 /* clear CMB interrupt status at once */
2490 adapter->cmb.cmb->int_stats = 0;
2491
2492 if (status & ISR_GPHY) /* clear phy status */
2493 atlx_clear_phy_int(adapter);
2494
2495 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2496 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2497
2498 /* check if SMB intr */
2499 if (status & ISR_SMB)
2500 atl1_inc_smb(adapter);
2501
2502 /* check if PCIE PHY Link down */
2503 if (status & ISR_PHY_LINKDOWN) {
2504 if (netif_msg_intr(adapter))
2505 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2506 "pcie phy link down %x\n", status);
2507 if (netif_running(adapter->netdev)) { /* reset MAC */
2508 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2509 schedule_work(&adapter->pcie_dma_to_rst_task);
2510 return IRQ_HANDLED;
2511 }
2512 }
2513
2514 /* check if DMA read/write error ? */
2515 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
2516 if (netif_msg_intr(adapter))
2517 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2518 "pcie DMA r/w error (status = 0x%x)\n",
2519 status);
2520 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2521 schedule_work(&adapter->pcie_dma_to_rst_task);
2522 return IRQ_HANDLED;
2523 }
2524
2525 /* link event */
2526 if (status & ISR_GPHY) {
2527 adapter->soft_stats.tx_carrier_errors++;
2528 atl1_check_for_link(adapter);
2529 }
2530
2531 /* transmit event */
2532 if (status & ISR_CMB_TX)
2533 atl1_intr_tx(adapter);
2534
2535 /* rx exception */
2536 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2537 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2538 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2539 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2540 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2541 ISR_HOST_RRD_OV))
2542 if (netif_msg_intr(adapter))
2543 dev_printk(KERN_DEBUG,
2544 &adapter->pdev->dev,
2545 "rx exception, ISR = 0x%x\n",
2546 status);
2547 atl1_intr_rx(adapter);
2548 }
2549
2550 if (--max_ints < 0)
2551 break;
2552
2553 } while ((status = adapter->cmb.cmb->int_stats));
2554
2555 /* re-enable Interrupt */
2556 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2557 return IRQ_HANDLED;
2558 }
2559
2560 /*
2561 * atl1_watchdog - Timer Call-back
2562 * @data: pointer to netdev cast into an unsigned long
2563 */
2564 static void atl1_watchdog(unsigned long data)
2565 {
2566 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2567
2568 /* Reset the timer */
2569 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2570 }
2571
2572 /*
2573 * atl1_phy_config - Timer Call-back
2574 * @data: pointer to netdev cast into an unsigned long
2575 */
2576 static void atl1_phy_config(unsigned long data)
2577 {
2578 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2579 struct atl1_hw *hw = &adapter->hw;
2580 unsigned long flags;
2581
2582 spin_lock_irqsave(&adapter->lock, flags);
2583 adapter->phy_timer_pending = false;
2584 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2585 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2586 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2587 spin_unlock_irqrestore(&adapter->lock, flags);
2588 }
2589
2590 /*
2591 * Orphaned vendor comment left intact here:
2592 * <vendor comment>
2593 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2594 * will assert. We do soft reset <0x1400=1> according
2595 * with the SPEC. BUT, it seemes that PCIE or DMA
2596 * state-machine will not be reset. DMAR_TO_INT will
2597 * assert again and again.
2598 * </vendor comment>
2599 */
2600
2601 static int atl1_reset(struct atl1_adapter *adapter)
2602 {
2603 int ret;
2604 ret = atl1_reset_hw(&adapter->hw);
2605 if (ret)
2606 return ret;
2607 return atl1_init_hw(&adapter->hw);
2608 }
2609
2610 static s32 atl1_up(struct atl1_adapter *adapter)
2611 {
2612 struct net_device *netdev = adapter->netdev;
2613 int err;
2614 int irq_flags = IRQF_SAMPLE_RANDOM;
2615
2616 /* hardware has been reset, we need to reload some things */
2617 atlx_set_multi(netdev);
2618 atl1_init_ring_ptrs(adapter);
2619 atlx_restore_vlan(adapter);
2620 err = atl1_alloc_rx_buffers(adapter);
2621 if (unlikely(!err))
2622 /* no RX BUFFER allocated */
2623 return -ENOMEM;
2624
2625 if (unlikely(atl1_configure(adapter))) {
2626 err = -EIO;
2627 goto err_up;
2628 }
2629
2630 err = pci_enable_msi(adapter->pdev);
2631 if (err) {
2632 if (netif_msg_ifup(adapter))
2633 dev_info(&adapter->pdev->dev,
2634 "Unable to enable MSI: %d\n", err);
2635 irq_flags |= IRQF_SHARED;
2636 }
2637
2638 err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags,
2639 netdev->name, netdev);
2640 if (unlikely(err))
2641 goto err_up;
2642
2643 mod_timer(&adapter->watchdog_timer, jiffies);
2644 atlx_irq_enable(adapter);
2645 atl1_check_link(adapter);
2646 return 0;
2647
2648 err_up:
2649 pci_disable_msi(adapter->pdev);
2650 /* free rx_buffers */
2651 atl1_clean_rx_ring(adapter);
2652 return err;
2653 }
2654
2655 static void atl1_down(struct atl1_adapter *adapter)
2656 {
2657 struct net_device *netdev = adapter->netdev;
2658
2659 del_timer_sync(&adapter->watchdog_timer);
2660 del_timer_sync(&adapter->phy_config_timer);
2661 adapter->phy_timer_pending = false;
2662
2663 atlx_irq_disable(adapter);
2664 free_irq(adapter->pdev->irq, netdev);
2665 pci_disable_msi(adapter->pdev);
2666 atl1_reset_hw(&adapter->hw);
2667 adapter->cmb.cmb->int_stats = 0;
2668
2669 adapter->link_speed = SPEED_0;
2670 adapter->link_duplex = -1;
2671 netif_carrier_off(netdev);
2672 netif_stop_queue(netdev);
2673
2674 atl1_clean_tx_ring(adapter);
2675 atl1_clean_rx_ring(adapter);
2676 }
2677
2678 static void atl1_tx_timeout_task(struct work_struct *work)
2679 {
2680 struct atl1_adapter *adapter =
2681 container_of(work, struct atl1_adapter, tx_timeout_task);
2682 struct net_device *netdev = adapter->netdev;
2683
2684 netif_device_detach(netdev);
2685 atl1_down(adapter);
2686 atl1_up(adapter);
2687 netif_device_attach(netdev);
2688 }
2689
2690 /*
2691 * atl1_change_mtu - Change the Maximum Transfer Unit
2692 * @netdev: network interface device structure
2693 * @new_mtu: new value for maximum frame size
2694 *
2695 * Returns 0 on success, negative on failure
2696 */
2697 static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
2698 {
2699 struct atl1_adapter *adapter = netdev_priv(netdev);
2700 int old_mtu = netdev->mtu;
2701 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2702
2703 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2704 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2705 if (netif_msg_link(adapter))
2706 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2707 return -EINVAL;
2708 }
2709
2710 adapter->hw.max_frame_size = max_frame;
2711 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2712 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2713 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2714
2715 netdev->mtu = new_mtu;
2716 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2717 atl1_down(adapter);
2718 atl1_up(adapter);
2719 }
2720
2721 return 0;
2722 }
2723
2724 /*
2725 * atl1_open - Called when a network interface is made active
2726 * @netdev: network interface device structure
2727 *
2728 * Returns 0 on success, negative value on failure
2729 *
2730 * The open entry point is called when a network interface is made
2731 * active by the system (IFF_UP). At this point all resources needed
2732 * for transmit and receive operations are allocated, the interrupt
2733 * handler is registered with the OS, the watchdog timer is started,
2734 * and the stack is notified that the interface is ready.
2735 */
2736 static int atl1_open(struct net_device *netdev)
2737 {
2738 struct atl1_adapter *adapter = netdev_priv(netdev);
2739 int err;
2740
2741 /* allocate transmit descriptors */
2742 err = atl1_setup_ring_resources(adapter);
2743 if (err)
2744 return err;
2745
2746 err = atl1_up(adapter);
2747 if (err)
2748 goto err_up;
2749
2750 return 0;
2751
2752 err_up:
2753 atl1_reset(adapter);
2754 return err;
2755 }
2756
2757 /*
2758 * atl1_close - Disables a network interface
2759 * @netdev: network interface device structure
2760 *
2761 * Returns 0, this is not allowed to fail
2762 *
2763 * The close entry point is called when an interface is de-activated
2764 * by the OS. The hardware is still under the drivers control, but
2765 * needs to be disabled. A global MAC reset is issued to stop the
2766 * hardware, and all transmit and receive resources are freed.
2767 */
2768 static int atl1_close(struct net_device *netdev)
2769 {
2770 struct atl1_adapter *adapter = netdev_priv(netdev);
2771 atl1_down(adapter);
2772 atl1_free_ring_resources(adapter);
2773 return 0;
2774 }
2775
2776 #ifdef CONFIG_PM
2777 static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
2778 {
2779 struct net_device *netdev = pci_get_drvdata(pdev);
2780 struct atl1_adapter *adapter = netdev_priv(netdev);
2781 struct atl1_hw *hw = &adapter->hw;
2782 u32 ctrl = 0;
2783 u32 wufc = adapter->wol;
2784 u32 val;
2785 int retval;
2786 u16 speed;
2787 u16 duplex;
2788
2789 netif_device_detach(netdev);
2790 if (netif_running(netdev))
2791 atl1_down(adapter);
2792
2793 retval = pci_save_state(pdev);
2794 if (retval)
2795 return retval;
2796
2797 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2798 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2799 val = ctrl & BMSR_LSTATUS;
2800 if (val)
2801 wufc &= ~ATLX_WUFC_LNKC;
2802
2803 if (val && wufc) {
2804 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2805 if (val) {
2806 if (netif_msg_ifdown(adapter))
2807 dev_printk(KERN_DEBUG, &pdev->dev,
2808 "error getting speed/duplex\n");
2809 goto disable_wol;
2810 }
2811
2812 ctrl = 0;
2813
2814 /* enable magic packet WOL */
2815 if (wufc & ATLX_WUFC_MAG)
2816 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
2817 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2818 ioread32(hw->hw_addr + REG_WOL_CTRL);
2819
2820 /* configure the mac */
2821 ctrl = MAC_CTRL_RX_EN;
2822 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2823 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2824 if (duplex == FULL_DUPLEX)
2825 ctrl |= MAC_CTRL_DUPLX;
2826 ctrl |= (((u32)adapter->hw.preamble_len &
2827 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2828 if (adapter->vlgrp)
2829 ctrl |= MAC_CTRL_RMV_VLAN;
2830 if (wufc & ATLX_WUFC_MAG)
2831 ctrl |= MAC_CTRL_BC_EN;
2832 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2833 ioread32(hw->hw_addr + REG_MAC_CTRL);
2834
2835 /* poke the PHY */
2836 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2837 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2838 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2839 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2840
2841 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2842 goto exit;
2843 }
2844
2845 if (!val && wufc) {
2846 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2847 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2848 ioread32(hw->hw_addr + REG_WOL_CTRL);
2849 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2850 ioread32(hw->hw_addr + REG_MAC_CTRL);
2851 hw->phy_configured = false;
2852 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2853 goto exit;
2854 }
2855
2856 disable_wol:
2857 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2858 ioread32(hw->hw_addr + REG_WOL_CTRL);
2859 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2860 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2861 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2862 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2863 atl1_phy_enter_power_saving(hw);
2864 hw->phy_configured = false;
2865 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2866 exit:
2867 if (netif_running(netdev))
2868 pci_disable_msi(adapter->pdev);
2869 pci_disable_device(pdev);
2870 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2871
2872 return 0;
2873 }
2874
2875 static int atl1_resume(struct pci_dev *pdev)
2876 {
2877 struct net_device *netdev = pci_get_drvdata(pdev);
2878 struct atl1_adapter *adapter = netdev_priv(netdev);
2879 u32 err;
2880
2881 pci_set_power_state(pdev, PCI_D0);
2882 pci_restore_state(pdev);
2883
2884 err = pci_enable_device(pdev);
2885 if (err) {
2886 if (netif_msg_ifup(adapter))
2887 dev_printk(KERN_DEBUG, &pdev->dev,
2888 "error enabling pci device\n");
2889 return err;
2890 }
2891
2892 pci_set_master(pdev);
2893 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2894 pci_enable_wake(pdev, PCI_D3hot, 0);
2895 pci_enable_wake(pdev, PCI_D3cold, 0);
2896
2897 atl1_reset_hw(&adapter->hw);
2898 adapter->cmb.cmb->int_stats = 0;
2899
2900 if (netif_running(netdev))
2901 atl1_up(adapter);
2902 netif_device_attach(netdev);
2903
2904 return 0;
2905 }
2906 #else
2907 #define atl1_suspend NULL
2908 #define atl1_resume NULL
2909 #endif
2910
2911 static void atl1_shutdown(struct pci_dev *pdev)
2912 {
2913 #ifdef CONFIG_PM
2914 atl1_suspend(pdev, PMSG_SUSPEND);
2915 #endif
2916 }
2917
2918 #ifdef CONFIG_NET_POLL_CONTROLLER
2919 static void atl1_poll_controller(struct net_device *netdev)
2920 {
2921 disable_irq(netdev->irq);
2922 atl1_intr(netdev->irq, netdev);
2923 enable_irq(netdev->irq);
2924 }
2925 #endif
2926
2927 /*
2928 * atl1_probe - Device Initialization Routine
2929 * @pdev: PCI device information struct
2930 * @ent: entry in atl1_pci_tbl
2931 *
2932 * Returns 0 on success, negative on failure
2933 *
2934 * atl1_probe initializes an adapter identified by a pci_dev structure.
2935 * The OS initialization, configuring of the adapter private structure,
2936 * and a hardware reset occur.
2937 */
2938 static int __devinit atl1_probe(struct pci_dev *pdev,
2939 const struct pci_device_id *ent)
2940 {
2941 struct net_device *netdev;
2942 struct atl1_adapter *adapter;
2943 static int cards_found = 0;
2944 int err;
2945
2946 err = pci_enable_device(pdev);
2947 if (err)
2948 return err;
2949
2950 /*
2951 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2952 * shared register for the high 32 bits, so only a single, aligned,
2953 * 4 GB physical address range can be used at a time.
2954 *
2955 * Supporting 64-bit DMA on this hardware is more trouble than it's
2956 * worth. It is far easier to limit to 32-bit DMA than update
2957 * various kernel subsystems to support the mechanics required by a
2958 * fixed-high-32-bit system.
2959 */
2960 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2961 if (err) {
2962 dev_err(&pdev->dev, "no usable DMA configuration\n");
2963 goto err_dma;
2964 }
2965 /*
2966 * Mark all PCI regions associated with PCI device
2967 * pdev as being reserved by owner atl1_driver_name
2968 */
2969 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2970 if (err)
2971 goto err_request_regions;
2972
2973 /*
2974 * Enables bus-mastering on the device and calls
2975 * pcibios_set_master to do the needed arch specific settings
2976 */
2977 pci_set_master(pdev);
2978
2979 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2980 if (!netdev) {
2981 err = -ENOMEM;
2982 goto err_alloc_etherdev;
2983 }
2984 SET_NETDEV_DEV(netdev, &pdev->dev);
2985
2986 pci_set_drvdata(pdev, netdev);
2987 adapter = netdev_priv(netdev);
2988 adapter->netdev = netdev;
2989 adapter->pdev = pdev;
2990 adapter->hw.back = adapter;
2991 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
2992
2993 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2994 if (!adapter->hw.hw_addr) {
2995 err = -EIO;
2996 goto err_pci_iomap;
2997 }
2998 /* get device revision number */
2999 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
3000 (REG_MASTER_CTRL + 2));
3001 if (netif_msg_probe(adapter))
3002 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
3003
3004 /* set default ring resource counts */
3005 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
3006 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
3007
3008 adapter->mii.dev = netdev;
3009 adapter->mii.mdio_read = mdio_read;
3010 adapter->mii.mdio_write = mdio_write;
3011 adapter->mii.phy_id_mask = 0x1f;
3012 adapter->mii.reg_num_mask = 0x1f;
3013
3014 netdev->open = &atl1_open;
3015 netdev->stop = &atl1_close;
3016 netdev->hard_start_xmit = &atl1_xmit_frame;
3017 netdev->get_stats = &atlx_get_stats;
3018 netdev->set_multicast_list = &atlx_set_multi;
3019 netdev->set_mac_address = &atl1_set_mac;
3020 netdev->change_mtu = &atl1_change_mtu;
3021 netdev->do_ioctl = &atlx_ioctl;
3022 netdev->tx_timeout = &atlx_tx_timeout;
3023 netdev->watchdog_timeo = 5 * HZ;
3024 #ifdef CONFIG_NET_POLL_CONTROLLER
3025 netdev->poll_controller = atl1_poll_controller;
3026 #endif
3027 netdev->vlan_rx_register = atlx_vlan_rx_register;
3028
3029 netdev->ethtool_ops = &atl1_ethtool_ops;
3030 adapter->bd_number = cards_found;
3031
3032 /* setup the private structure */
3033 err = atl1_sw_init(adapter);
3034 if (err)
3035 goto err_common;
3036
3037 netdev->features = NETIF_F_HW_CSUM;
3038 netdev->features |= NETIF_F_SG;
3039 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
3040 netdev->features |= NETIF_F_TSO;
3041 netdev->features |= NETIF_F_LLTX;
3042
3043 /*
3044 * patch for some L1 of old version,
3045 * the final version of L1 may not need these
3046 * patches
3047 */
3048 /* atl1_pcie_patch(adapter); */
3049
3050 /* really reset GPHY core */
3051 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3052
3053 /*
3054 * reset the controller to
3055 * put the device in a known good starting state
3056 */
3057 if (atl1_reset_hw(&adapter->hw)) {
3058 err = -EIO;
3059 goto err_common;
3060 }
3061
3062 /* copy the MAC address out of the EEPROM */
3063 atl1_read_mac_addr(&adapter->hw);
3064 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3065
3066 if (!is_valid_ether_addr(netdev->dev_addr)) {
3067 err = -EIO;
3068 goto err_common;
3069 }
3070
3071 atl1_check_options(adapter);
3072
3073 /* pre-init the MAC, and setup link */
3074 err = atl1_init_hw(&adapter->hw);
3075 if (err) {
3076 err = -EIO;
3077 goto err_common;
3078 }
3079
3080 atl1_pcie_patch(adapter);
3081 /* assume we have no link for now */
3082 netif_carrier_off(netdev);
3083 netif_stop_queue(netdev);
3084
3085 init_timer(&adapter->watchdog_timer);
3086 adapter->watchdog_timer.function = &atl1_watchdog;
3087 adapter->watchdog_timer.data = (unsigned long)adapter;
3088
3089 init_timer(&adapter->phy_config_timer);
3090 adapter->phy_config_timer.function = &atl1_phy_config;
3091 adapter->phy_config_timer.data = (unsigned long)adapter;
3092 adapter->phy_timer_pending = false;
3093
3094 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
3095
3096 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
3097
3098 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
3099
3100 err = register_netdev(netdev);
3101 if (err)
3102 goto err_common;
3103
3104 cards_found++;
3105 atl1_via_workaround(adapter);
3106 return 0;
3107
3108 err_common:
3109 pci_iounmap(pdev, adapter->hw.hw_addr);
3110 err_pci_iomap:
3111 free_netdev(netdev);
3112 err_alloc_etherdev:
3113 pci_release_regions(pdev);
3114 err_dma:
3115 err_request_regions:
3116 pci_disable_device(pdev);
3117 return err;
3118 }
3119
3120 /*
3121 * atl1_remove - Device Removal Routine
3122 * @pdev: PCI device information struct
3123 *
3124 * atl1_remove is called by the PCI subsystem to alert the driver
3125 * that it should release a PCI device. The could be caused by a
3126 * Hot-Plug event, or because the driver is going to be removed from
3127 * memory.
3128 */
3129 static void __devexit atl1_remove(struct pci_dev *pdev)
3130 {
3131 struct net_device *netdev = pci_get_drvdata(pdev);
3132 struct atl1_adapter *adapter;
3133 /* Device not available. Return. */
3134 if (!netdev)
3135 return;
3136
3137 adapter = netdev_priv(netdev);
3138
3139 /*
3140 * Some atl1 boards lack persistent storage for their MAC, and get it
3141 * from the BIOS during POST. If we've been messing with the MAC
3142 * address, we need to save the permanent one.
3143 */
3144 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
3145 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3146 ETH_ALEN);
3147 atl1_set_mac_addr(&adapter->hw);
3148 }
3149
3150 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3151 unregister_netdev(netdev);
3152 pci_iounmap(pdev, adapter->hw.hw_addr);
3153 pci_release_regions(pdev);
3154 free_netdev(netdev);
3155 pci_disable_device(pdev);
3156 }
3157
3158 static struct pci_driver atl1_driver = {
3159 .name = ATLX_DRIVER_NAME,
3160 .id_table = atl1_pci_tbl,
3161 .probe = atl1_probe,
3162 .remove = __devexit_p(atl1_remove),
3163 .suspend = atl1_suspend,
3164 .resume = atl1_resume,
3165 .shutdown = atl1_shutdown
3166 };
3167
3168 /*
3169 * atl1_exit_module - Driver Exit Cleanup Routine
3170 *
3171 * atl1_exit_module is called just before the driver is removed
3172 * from memory.
3173 */
3174 static void __exit atl1_exit_module(void)
3175 {
3176 pci_unregister_driver(&atl1_driver);
3177 }
3178
3179 /*
3180 * atl1_init_module - Driver Registration Routine
3181 *
3182 * atl1_init_module is the first routine called when the driver is
3183 * loaded. All it does is register with the PCI subsystem.
3184 */
3185 static int __init atl1_init_module(void)
3186 {
3187 return pci_register_driver(&atl1_driver);
3188 }
3189
3190 module_init(atl1_init_module);
3191 module_exit(atl1_exit_module);
3192
3193 struct atl1_stats {
3194 char stat_string[ETH_GSTRING_LEN];
3195 int sizeof_stat;
3196 int stat_offset;
3197 };
3198
3199 #define ATL1_STAT(m) \
3200 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3201
3202 static struct atl1_stats atl1_gstrings_stats[] = {
3203 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3204 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3205 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3206 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3207 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3208 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3209 {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
3210 {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
3211 {"multicast", ATL1_STAT(soft_stats.multicast)},
3212 {"collisions", ATL1_STAT(soft_stats.collisions)},
3213 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3214 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3215 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3216 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3217 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3218 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3219 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3220 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3221 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3222 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3223 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3224 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3225 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3226 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3227 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3228 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3229 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3230 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3231 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3232 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3233 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3234 };
3235
3236 static void atl1_get_ethtool_stats(struct net_device *netdev,
3237 struct ethtool_stats *stats, u64 *data)
3238 {
3239 struct atl1_adapter *adapter = netdev_priv(netdev);
3240 int i;
3241 char *p;
3242
3243 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3244 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3245 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3246 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
3247 }
3248
3249 }
3250
3251 static int atl1_get_sset_count(struct net_device *netdev, int sset)
3252 {
3253 switch (sset) {
3254 case ETH_SS_STATS:
3255 return ARRAY_SIZE(atl1_gstrings_stats);
3256 default:
3257 return -EOPNOTSUPP;
3258 }
3259 }
3260
3261 static int atl1_get_settings(struct net_device *netdev,
3262 struct ethtool_cmd *ecmd)
3263 {
3264 struct atl1_adapter *adapter = netdev_priv(netdev);
3265 struct atl1_hw *hw = &adapter->hw;
3266
3267 ecmd->supported = (SUPPORTED_10baseT_Half |
3268 SUPPORTED_10baseT_Full |
3269 SUPPORTED_100baseT_Half |
3270 SUPPORTED_100baseT_Full |
3271 SUPPORTED_1000baseT_Full |
3272 SUPPORTED_Autoneg | SUPPORTED_TP);
3273 ecmd->advertising = ADVERTISED_TP;
3274 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3275 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3276 ecmd->advertising |= ADVERTISED_Autoneg;
3277 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3278 ecmd->advertising |= ADVERTISED_Autoneg;
3279 ecmd->advertising |=
3280 (ADVERTISED_10baseT_Half |
3281 ADVERTISED_10baseT_Full |
3282 ADVERTISED_100baseT_Half |
3283 ADVERTISED_100baseT_Full |
3284 ADVERTISED_1000baseT_Full);
3285 } else
3286 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3287 }
3288 ecmd->port = PORT_TP;
3289 ecmd->phy_address = 0;
3290 ecmd->transceiver = XCVR_INTERNAL;
3291
3292 if (netif_carrier_ok(adapter->netdev)) {
3293 u16 link_speed, link_duplex;
3294 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3295 ecmd->speed = link_speed;
3296 if (link_duplex == FULL_DUPLEX)
3297 ecmd->duplex = DUPLEX_FULL;
3298 else
3299 ecmd->duplex = DUPLEX_HALF;
3300 } else {
3301 ecmd->speed = -1;
3302 ecmd->duplex = -1;
3303 }
3304 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3305 hw->media_type == MEDIA_TYPE_1000M_FULL)
3306 ecmd->autoneg = AUTONEG_ENABLE;
3307 else
3308 ecmd->autoneg = AUTONEG_DISABLE;
3309
3310 return 0;
3311 }
3312
3313 static int atl1_set_settings(struct net_device *netdev,
3314 struct ethtool_cmd *ecmd)
3315 {
3316 struct atl1_adapter *adapter = netdev_priv(netdev);
3317 struct atl1_hw *hw = &adapter->hw;
3318 u16 phy_data;
3319 int ret_val = 0;
3320 u16 old_media_type = hw->media_type;
3321
3322 if (netif_running(adapter->netdev)) {
3323 if (netif_msg_link(adapter))
3324 dev_dbg(&adapter->pdev->dev,
3325 "ethtool shutting down adapter\n");
3326 atl1_down(adapter);
3327 }
3328
3329 if (ecmd->autoneg == AUTONEG_ENABLE)
3330 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3331 else {
3332 if (ecmd->speed == SPEED_1000) {
3333 if (ecmd->duplex != DUPLEX_FULL) {
3334 if (netif_msg_link(adapter))
3335 dev_warn(&adapter->pdev->dev,
3336 "1000M half is invalid\n");
3337 ret_val = -EINVAL;
3338 goto exit_sset;
3339 }
3340 hw->media_type = MEDIA_TYPE_1000M_FULL;
3341 } else if (ecmd->speed == SPEED_100) {
3342 if (ecmd->duplex == DUPLEX_FULL)
3343 hw->media_type = MEDIA_TYPE_100M_FULL;
3344 else
3345 hw->media_type = MEDIA_TYPE_100M_HALF;
3346 } else {
3347 if (ecmd->duplex == DUPLEX_FULL)
3348 hw->media_type = MEDIA_TYPE_10M_FULL;
3349 else
3350 hw->media_type = MEDIA_TYPE_10M_HALF;
3351 }
3352 }
3353 switch (hw->media_type) {
3354 case MEDIA_TYPE_AUTO_SENSOR:
3355 ecmd->advertising =
3356 ADVERTISED_10baseT_Half |
3357 ADVERTISED_10baseT_Full |
3358 ADVERTISED_100baseT_Half |
3359 ADVERTISED_100baseT_Full |
3360 ADVERTISED_1000baseT_Full |
3361 ADVERTISED_Autoneg | ADVERTISED_TP;
3362 break;
3363 case MEDIA_TYPE_1000M_FULL:
3364 ecmd->advertising =
3365 ADVERTISED_1000baseT_Full |
3366 ADVERTISED_Autoneg | ADVERTISED_TP;
3367 break;
3368 default:
3369 ecmd->advertising = 0;
3370 break;
3371 }
3372 if (atl1_phy_setup_autoneg_adv(hw)) {
3373 ret_val = -EINVAL;
3374 if (netif_msg_link(adapter))
3375 dev_warn(&adapter->pdev->dev,
3376 "invalid ethtool speed/duplex setting\n");
3377 goto exit_sset;
3378 }
3379 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3380 hw->media_type == MEDIA_TYPE_1000M_FULL)
3381 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3382 else {
3383 switch (hw->media_type) {
3384 case MEDIA_TYPE_100M_FULL:
3385 phy_data =
3386 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3387 MII_CR_RESET;
3388 break;
3389 case MEDIA_TYPE_100M_HALF:
3390 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3391 break;
3392 case MEDIA_TYPE_10M_FULL:
3393 phy_data =
3394 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3395 break;
3396 default:
3397 /* MEDIA_TYPE_10M_HALF: */
3398 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3399 break;
3400 }
3401 }
3402 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3403 exit_sset:
3404 if (ret_val)
3405 hw->media_type = old_media_type;
3406
3407 if (netif_running(adapter->netdev)) {
3408 if (netif_msg_link(adapter))
3409 dev_dbg(&adapter->pdev->dev,
3410 "ethtool starting adapter\n");
3411 atl1_up(adapter);
3412 } else if (!ret_val) {
3413 if (netif_msg_link(adapter))
3414 dev_dbg(&adapter->pdev->dev,
3415 "ethtool resetting adapter\n");
3416 atl1_reset(adapter);
3417 }
3418 return ret_val;
3419 }
3420
3421 static void atl1_get_drvinfo(struct net_device *netdev,
3422 struct ethtool_drvinfo *drvinfo)
3423 {
3424 struct atl1_adapter *adapter = netdev_priv(netdev);
3425
3426 strncpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3427 strncpy(drvinfo->version, ATLX_DRIVER_VERSION,
3428 sizeof(drvinfo->version));
3429 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
3430 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
3431 sizeof(drvinfo->bus_info));
3432 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3433 }
3434
3435 static void atl1_get_wol(struct net_device *netdev,
3436 struct ethtool_wolinfo *wol)
3437 {
3438 struct atl1_adapter *adapter = netdev_priv(netdev);
3439
3440 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
3441 wol->wolopts = 0;
3442 if (adapter->wol & ATLX_WUFC_EX)
3443 wol->wolopts |= WAKE_UCAST;
3444 if (adapter->wol & ATLX_WUFC_MC)
3445 wol->wolopts |= WAKE_MCAST;
3446 if (adapter->wol & ATLX_WUFC_BC)
3447 wol->wolopts |= WAKE_BCAST;
3448 if (adapter->wol & ATLX_WUFC_MAG)
3449 wol->wolopts |= WAKE_MAGIC;
3450 return;
3451 }
3452
3453 static int atl1_set_wol(struct net_device *netdev,
3454 struct ethtool_wolinfo *wol)
3455 {
3456 struct atl1_adapter *adapter = netdev_priv(netdev);
3457
3458 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
3459 return -EOPNOTSUPP;
3460 adapter->wol = 0;
3461 if (wol->wolopts & WAKE_UCAST)
3462 adapter->wol |= ATLX_WUFC_EX;
3463 if (wol->wolopts & WAKE_MCAST)
3464 adapter->wol |= ATLX_WUFC_MC;
3465 if (wol->wolopts & WAKE_BCAST)
3466 adapter->wol |= ATLX_WUFC_BC;
3467 if (wol->wolopts & WAKE_MAGIC)
3468 adapter->wol |= ATLX_WUFC_MAG;
3469 return 0;
3470 }
3471
3472 static u32 atl1_get_msglevel(struct net_device *netdev)
3473 {
3474 struct atl1_adapter *adapter = netdev_priv(netdev);
3475 return adapter->msg_enable;
3476 }
3477
3478 static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3479 {
3480 struct atl1_adapter *adapter = netdev_priv(netdev);
3481 adapter->msg_enable = value;
3482 }
3483
3484 static int atl1_get_regs_len(struct net_device *netdev)
3485 {
3486 return ATL1_REG_COUNT * sizeof(u32);
3487 }
3488
3489 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3490 void *p)
3491 {
3492 struct atl1_adapter *adapter = netdev_priv(netdev);
3493 struct atl1_hw *hw = &adapter->hw;
3494 unsigned int i;
3495 u32 *regbuf = p;
3496
3497 for (i = 0; i < ATL1_REG_COUNT; i++) {
3498 /*
3499 * This switch statement avoids reserved regions
3500 * of register space.
3501 */
3502 switch (i) {
3503 case 6 ... 9:
3504 case 14:
3505 case 29 ... 31:
3506 case 34 ... 63:
3507 case 75 ... 127:
3508 case 136 ... 1023:
3509 case 1027 ... 1087:
3510 case 1091 ... 1151:
3511 case 1194 ... 1195:
3512 case 1200 ... 1201:
3513 case 1206 ... 1213:
3514 case 1216 ... 1279:
3515 case 1290 ... 1311:
3516 case 1323 ... 1343:
3517 case 1358 ... 1359:
3518 case 1368 ... 1375:
3519 case 1378 ... 1383:
3520 case 1388 ... 1391:
3521 case 1393 ... 1395:
3522 case 1402 ... 1403:
3523 case 1410 ... 1471:
3524 case 1522 ... 1535:
3525 /* reserved region; don't read it */
3526 regbuf[i] = 0;
3527 break;
3528 default:
3529 /* unreserved region */
3530 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3531 }
3532 }
3533 }
3534
3535 static void atl1_get_ringparam(struct net_device *netdev,
3536 struct ethtool_ringparam *ring)
3537 {
3538 struct atl1_adapter *adapter = netdev_priv(netdev);
3539 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3540 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
3541
3542 ring->rx_max_pending = ATL1_MAX_RFD;
3543 ring->tx_max_pending = ATL1_MAX_TPD;
3544 ring->rx_mini_max_pending = 0;
3545 ring->rx_jumbo_max_pending = 0;
3546 ring->rx_pending = rxdr->count;
3547 ring->tx_pending = txdr->count;
3548 ring->rx_mini_pending = 0;
3549 ring->rx_jumbo_pending = 0;
3550 }
3551
3552 static int atl1_set_ringparam(struct net_device *netdev,
3553 struct ethtool_ringparam *ring)
3554 {
3555 struct atl1_adapter *adapter = netdev_priv(netdev);
3556 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3557 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3558 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
3559
3560 struct atl1_tpd_ring tpd_old, tpd_new;
3561 struct atl1_rfd_ring rfd_old, rfd_new;
3562 struct atl1_rrd_ring rrd_old, rrd_new;
3563 struct atl1_ring_header rhdr_old, rhdr_new;
3564 int err;
3565
3566 tpd_old = adapter->tpd_ring;
3567 rfd_old = adapter->rfd_ring;
3568 rrd_old = adapter->rrd_ring;
3569 rhdr_old = adapter->ring_header;
3570
3571 if (netif_running(adapter->netdev))
3572 atl1_down(adapter);
3573
3574 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3575 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3576 rfdr->count;
3577 rfdr->count = (rfdr->count + 3) & ~3;
3578 rrdr->count = rfdr->count;
3579
3580 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3581 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3582 tpdr->count;
3583 tpdr->count = (tpdr->count + 3) & ~3;
3584
3585 if (netif_running(adapter->netdev)) {
3586 /* try to get new resources before deleting old */
3587 err = atl1_setup_ring_resources(adapter);
3588 if (err)
3589 goto err_setup_ring;
3590
3591 /*
3592 * save the new, restore the old in order to free it,
3593 * then restore the new back again
3594 */
3595
3596 rfd_new = adapter->rfd_ring;
3597 rrd_new = adapter->rrd_ring;
3598 tpd_new = adapter->tpd_ring;
3599 rhdr_new = adapter->ring_header;
3600 adapter->rfd_ring = rfd_old;
3601 adapter->rrd_ring = rrd_old;
3602 adapter->tpd_ring = tpd_old;
3603 adapter->ring_header = rhdr_old;
3604 atl1_free_ring_resources(adapter);
3605 adapter->rfd_ring = rfd_new;
3606 adapter->rrd_ring = rrd_new;
3607 adapter->tpd_ring = tpd_new;
3608 adapter->ring_header = rhdr_new;
3609
3610 err = atl1_up(adapter);
3611 if (err)
3612 return err;
3613 }
3614 return 0;
3615
3616 err_setup_ring:
3617 adapter->rfd_ring = rfd_old;
3618 adapter->rrd_ring = rrd_old;
3619 adapter->tpd_ring = tpd_old;
3620 adapter->ring_header = rhdr_old;
3621 atl1_up(adapter);
3622 return err;
3623 }
3624
3625 static void atl1_get_pauseparam(struct net_device *netdev,
3626 struct ethtool_pauseparam *epause)
3627 {
3628 struct atl1_adapter *adapter = netdev_priv(netdev);
3629 struct atl1_hw *hw = &adapter->hw;
3630
3631 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3632 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3633 epause->autoneg = AUTONEG_ENABLE;
3634 } else {
3635 epause->autoneg = AUTONEG_DISABLE;
3636 }
3637 epause->rx_pause = 1;
3638 epause->tx_pause = 1;
3639 }
3640
3641 static int atl1_set_pauseparam(struct net_device *netdev,
3642 struct ethtool_pauseparam *epause)
3643 {
3644 struct atl1_adapter *adapter = netdev_priv(netdev);
3645 struct atl1_hw *hw = &adapter->hw;
3646
3647 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3648 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3649 epause->autoneg = AUTONEG_ENABLE;
3650 } else {
3651 epause->autoneg = AUTONEG_DISABLE;
3652 }
3653
3654 epause->rx_pause = 1;
3655 epause->tx_pause = 1;
3656
3657 return 0;
3658 }
3659
3660 /* FIXME: is this right? -- CHS */
3661 static u32 atl1_get_rx_csum(struct net_device *netdev)
3662 {
3663 return 1;
3664 }
3665
3666 static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3667 u8 *data)
3668 {
3669 u8 *p = data;
3670 int i;
3671
3672 switch (stringset) {
3673 case ETH_SS_STATS:
3674 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3675 memcpy(p, atl1_gstrings_stats[i].stat_string,
3676 ETH_GSTRING_LEN);
3677 p += ETH_GSTRING_LEN;
3678 }
3679 break;
3680 }
3681 }
3682
3683 static int atl1_nway_reset(struct net_device *netdev)
3684 {
3685 struct atl1_adapter *adapter = netdev_priv(netdev);
3686 struct atl1_hw *hw = &adapter->hw;
3687
3688 if (netif_running(netdev)) {
3689 u16 phy_data;
3690 atl1_down(adapter);
3691
3692 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3693 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3694 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3695 } else {
3696 switch (hw->media_type) {
3697 case MEDIA_TYPE_100M_FULL:
3698 phy_data = MII_CR_FULL_DUPLEX |
3699 MII_CR_SPEED_100 | MII_CR_RESET;
3700 break;
3701 case MEDIA_TYPE_100M_HALF:
3702 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3703 break;
3704 case MEDIA_TYPE_10M_FULL:
3705 phy_data = MII_CR_FULL_DUPLEX |
3706 MII_CR_SPEED_10 | MII_CR_RESET;
3707 break;
3708 default:
3709 /* MEDIA_TYPE_10M_HALF */
3710 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3711 }
3712 }
3713 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3714 atl1_up(adapter);
3715 }
3716 return 0;
3717 }
3718
3719 const struct ethtool_ops atl1_ethtool_ops = {
3720 .get_settings = atl1_get_settings,
3721 .set_settings = atl1_set_settings,
3722 .get_drvinfo = atl1_get_drvinfo,
3723 .get_wol = atl1_get_wol,
3724 .set_wol = atl1_set_wol,
3725 .get_msglevel = atl1_get_msglevel,
3726 .set_msglevel = atl1_set_msglevel,
3727 .get_regs_len = atl1_get_regs_len,
3728 .get_regs = atl1_get_regs,
3729 .get_ringparam = atl1_get_ringparam,
3730 .set_ringparam = atl1_set_ringparam,
3731 .get_pauseparam = atl1_get_pauseparam,
3732 .set_pauseparam = atl1_set_pauseparam,
3733 .get_rx_csum = atl1_get_rx_csum,
3734 .set_tx_csum = ethtool_op_set_tx_hw_csum,
3735 .get_link = ethtool_op_get_link,
3736 .set_sg = ethtool_op_set_sg,
3737 .get_strings = atl1_get_strings,
3738 .nway_reset = atl1_nway_reset,
3739 .get_ethtool_stats = atl1_get_ethtool_stats,
3740 .get_sset_count = atl1_get_sset_count,
3741 .set_tso = ethtool_op_set_tso,
3742 };
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