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Linux 2.6.26-rc5
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / net / sfc / falcon.c
blobd3f749c72d41d76f5291407b946fefd93217241e
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include "net_driver.h"
17 #include "bitfield.h"
18 #include "efx.h"
19 #include "mac.h"
20 #include "gmii.h"
21 #include "spi.h"
22 #include "falcon.h"
23 #include "falcon_hwdefs.h"
24 #include "falcon_io.h"
25 #include "mdio_10g.h"
26 #include "phy.h"
27 #include "boards.h"
28 #include "workarounds.h"
29
30 /* Falcon hardware control.
31 * Falcon is the internal codename for the SFC4000 controller that is
32 * present in SFE400X evaluation boards
33 */
34
35 /**
36 * struct falcon_nic_data - Falcon NIC state
37 * @next_buffer_table: First available buffer table id
38 * @pci_dev2: The secondary PCI device if present
39 */
40 struct falcon_nic_data {
41 unsigned next_buffer_table;
42 struct pci_dev *pci_dev2;
43 };
44
45 /**************************************************************************
46 *
47 * Configurable values
48 *
49 **************************************************************************
50 */
51
52 static int disable_dma_stats;
53
54 /* This is set to 16 for a good reason. In summary, if larger than
55 * 16, the descriptor cache holds more than a default socket
56 * buffer's worth of packets (for UDP we can only have at most one
57 * socket buffer's worth outstanding). This combined with the fact
58 * that we only get 1 TX event per descriptor cache means the NIC
59 * goes idle.
60 */
61 #define TX_DC_ENTRIES 16
62 #define TX_DC_ENTRIES_ORDER 0
63 #define TX_DC_BASE 0x130000
64
65 #define RX_DC_ENTRIES 64
66 #define RX_DC_ENTRIES_ORDER 2
67 #define RX_DC_BASE 0x100000
68
69 /* RX FIFO XOFF watermark
70 *
71 * When the amount of the RX FIFO increases used increases past this
72 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
73 * This also has an effect on RX/TX arbitration
74 */
75 static int rx_xoff_thresh_bytes = -1;
76 module_param(rx_xoff_thresh_bytes, int, 0644);
77 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
78
79 /* RX FIFO XON watermark
80 *
81 * When the amount of the RX FIFO used decreases below this
82 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
83 * This also has an effect on RX/TX arbitration
84 */
85 static int rx_xon_thresh_bytes = -1;
86 module_param(rx_xon_thresh_bytes, int, 0644);
87 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
88
89 /* TX descriptor ring size - min 512 max 4k */
90 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
91 #define FALCON_TXD_RING_SIZE 1024
92 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
93
94 /* RX descriptor ring size - min 512 max 4k */
95 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
96 #define FALCON_RXD_RING_SIZE 1024
97 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
98
99 /* Event queue size - max 32k */
100 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
101 #define FALCON_EVQ_SIZE 4096
102 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
103
104 /* Max number of internal errors. After this resets will not be performed */
105 #define FALCON_MAX_INT_ERRORS 4
106
107 /* Maximum period that we wait for flush events. If the flush event
108 * doesn't arrive in this period of time then we check if the queue
109 * was disabled anyway. */
110 #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
111
112 /**************************************************************************
113 *
114 * Falcon constants
115 *
116 **************************************************************************
117 */
118
119 /* DMA address mask */
120 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
121
122 /* TX DMA length mask (13-bit) */
123 #define FALCON_TX_DMA_MASK (4096 - 1)
124
125 /* Size and alignment of special buffers (4KB) */
126 #define FALCON_BUF_SIZE 4096
127
128 /* Dummy SRAM size code */
129 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
130
131 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
132 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
133 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
134 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
135 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
136 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
137
138 #define FALCON_IS_DUAL_FUNC(efx) \
139 (falcon_rev(efx) < FALCON_REV_B0)
140
141 /**************************************************************************
142 *
143 * Falcon hardware access
144 *
145 **************************************************************************/
146
147 /* Read the current event from the event queue */
148 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
149 unsigned int index)
150 {
151 return (((efx_qword_t *) (channel->eventq.addr)) + index);
152 }
153
154 /* See if an event is present
155 *
156 * We check both the high and low dword of the event for all ones. We
157 * wrote all ones when we cleared the event, and no valid event can
158 * have all ones in either its high or low dwords. This approach is
159 * robust against reordering.
160 *
161 * Note that using a single 64-bit comparison is incorrect; even
162 * though the CPU read will be atomic, the DMA write may not be.
163 */
164 static inline int falcon_event_present(efx_qword_t *event)
165 {
166 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
167 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
168 }
169
170 /**************************************************************************
171 *
172 * I2C bus - this is a bit-bashing interface using GPIO pins
173 * Note that it uses the output enables to tristate the outputs
174 * SDA is the data pin and SCL is the clock
175 *
176 **************************************************************************
177 */
178 static void falcon_setsdascl(struct efx_i2c_interface *i2c)
179 {
180 efx_oword_t reg;
181
182 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
183 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, (i2c->scl ? 0 : 1));
184 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, (i2c->sda ? 0 : 1));
185 falcon_write(i2c->efx, &reg, GPIO_CTL_REG_KER);
186 }
187
188 static int falcon_getsda(struct efx_i2c_interface *i2c)
189 {
190 efx_oword_t reg;
191
192 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
193 return EFX_OWORD_FIELD(reg, GPIO3_IN);
194 }
195
196 static int falcon_getscl(struct efx_i2c_interface *i2c)
197 {
198 efx_oword_t reg;
199
200 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
201 return EFX_DWORD_FIELD(reg, GPIO0_IN);
202 }
203
204 static struct efx_i2c_bit_operations falcon_i2c_bit_operations = {
205 .setsda = falcon_setsdascl,
206 .setscl = falcon_setsdascl,
207 .getsda = falcon_getsda,
208 .getscl = falcon_getscl,
209 .udelay = 100,
210 .mdelay = 10,
211 };
212
213 /**************************************************************************
214 *
215 * Falcon special buffer handling
216 * Special buffers are used for event queues and the TX and RX
217 * descriptor rings.
218 *
219 *************************************************************************/
220
221 /*
222 * Initialise a Falcon special buffer
223 *
224 * This will define a buffer (previously allocated via
225 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
226 * it to be used for event queues, descriptor rings etc.
227 */
228 static int
229 falcon_init_special_buffer(struct efx_nic *efx,
230 struct efx_special_buffer *buffer)
231 {
232 efx_qword_t buf_desc;
233 int index;
234 dma_addr_t dma_addr;
235 int i;
236
237 EFX_BUG_ON_PARANOID(!buffer->addr);
238
239 /* Write buffer descriptors to NIC */
240 for (i = 0; i < buffer->entries; i++) {
241 index = buffer->index + i;
242 dma_addr = buffer->dma_addr + (i * 4096);
243 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
244 index, (unsigned long long)dma_addr);
245 EFX_POPULATE_QWORD_4(buf_desc,
246 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
247 BUF_ADR_REGION, 0,
248 BUF_ADR_FBUF, (dma_addr >> 12),
249 BUF_OWNER_ID_FBUF, 0);
250 falcon_write_sram(efx, &buf_desc, index);
251 }
252
253 return 0;
254 }
255
256 /* Unmaps a buffer from Falcon and clears the buffer table entries */
257 static void
258 falcon_fini_special_buffer(struct efx_nic *efx,
259 struct efx_special_buffer *buffer)
260 {
261 efx_oword_t buf_tbl_upd;
262 unsigned int start = buffer->index;
263 unsigned int end = (buffer->index + buffer->entries - 1);
264
265 if (!buffer->entries)
266 return;
267
268 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
269 buffer->index, buffer->index + buffer->entries - 1);
270
271 EFX_POPULATE_OWORD_4(buf_tbl_upd,
272 BUF_UPD_CMD, 0,
273 BUF_CLR_CMD, 1,
274 BUF_CLR_END_ID, end,
275 BUF_CLR_START_ID, start);
276 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
277 }
278
279 /*
280 * Allocate a new Falcon special buffer
281 *
282 * This allocates memory for a new buffer, clears it and allocates a
283 * new buffer ID range. It does not write into Falcon's buffer table.
284 *
285 * This call will allocate 4KB buffers, since Falcon can't use 8KB
286 * buffers for event queues and descriptor rings.
287 */
288 static int falcon_alloc_special_buffer(struct efx_nic *efx,
289 struct efx_special_buffer *buffer,
290 unsigned int len)
291 {
292 struct falcon_nic_data *nic_data = efx->nic_data;
293
294 len = ALIGN(len, FALCON_BUF_SIZE);
295
296 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
297 &buffer->dma_addr);
298 if (!buffer->addr)
299 return -ENOMEM;
300 buffer->len = len;
301 buffer->entries = len / FALCON_BUF_SIZE;
302 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
303
304 /* All zeros is a potentially valid event so memset to 0xff */
305 memset(buffer->addr, 0xff, len);
306
307 /* Select new buffer ID */
308 buffer->index = nic_data->next_buffer_table;
309 nic_data->next_buffer_table += buffer->entries;
310
311 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
312 "(virt %p phys %lx)\n", buffer->index,
313 buffer->index + buffer->entries - 1,
314 (unsigned long long)buffer->dma_addr, len,
315 buffer->addr, virt_to_phys(buffer->addr));
316
317 return 0;
318 }
319
320 static void falcon_free_special_buffer(struct efx_nic *efx,
321 struct efx_special_buffer *buffer)
322 {
323 if (!buffer->addr)
324 return;
325
326 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
327 "(virt %p phys %lx)\n", buffer->index,
328 buffer->index + buffer->entries - 1,
329 (unsigned long long)buffer->dma_addr, buffer->len,
330 buffer->addr, virt_to_phys(buffer->addr));
331
332 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
333 buffer->dma_addr);
334 buffer->addr = NULL;
335 buffer->entries = 0;
336 }
337
338 /**************************************************************************
339 *
340 * Falcon generic buffer handling
341 * These buffers are used for interrupt status and MAC stats
342 *
343 **************************************************************************/
344
345 static int falcon_alloc_buffer(struct efx_nic *efx,
346 struct efx_buffer *buffer, unsigned int len)
347 {
348 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
349 &buffer->dma_addr);
350 if (!buffer->addr)
351 return -ENOMEM;
352 buffer->len = len;
353 memset(buffer->addr, 0, len);
354 return 0;
355 }
356
357 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
358 {
359 if (buffer->addr) {
360 pci_free_consistent(efx->pci_dev, buffer->len,
361 buffer->addr, buffer->dma_addr);
362 buffer->addr = NULL;
363 }
364 }
365
366 /**************************************************************************
367 *
368 * Falcon TX path
369 *
370 **************************************************************************/
371
372 /* Returns a pointer to the specified transmit descriptor in the TX
373 * descriptor queue belonging to the specified channel.
374 */
375 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
376 unsigned int index)
377 {
378 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
379 }
380
381 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
382 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
383 {
384 unsigned write_ptr;
385 efx_dword_t reg;
386
387 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
388 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
389 falcon_writel_page(tx_queue->efx, &reg,
390 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
391 }
392
393
394 /* For each entry inserted into the software descriptor ring, create a
395 * descriptor in the hardware TX descriptor ring (in host memory), and
396 * write a doorbell.
397 */
398 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
399 {
400
401 struct efx_tx_buffer *buffer;
402 efx_qword_t *txd;
403 unsigned write_ptr;
404
405 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
406
407 do {
408 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
409 buffer = &tx_queue->buffer[write_ptr];
410 txd = falcon_tx_desc(tx_queue, write_ptr);
411 ++tx_queue->write_count;
412
413 /* Create TX descriptor ring entry */
414 EFX_POPULATE_QWORD_5(*txd,
415 TX_KER_PORT, 0,
416 TX_KER_CONT, buffer->continuation,
417 TX_KER_BYTE_CNT, buffer->len,
418 TX_KER_BUF_REGION, 0,
419 TX_KER_BUF_ADR, buffer->dma_addr);
420 } while (tx_queue->write_count != tx_queue->insert_count);
421
422 wmb(); /* Ensure descriptors are written before they are fetched */
423 falcon_notify_tx_desc(tx_queue);
424 }
425
426 /* Allocate hardware resources for a TX queue */
427 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
428 {
429 struct efx_nic *efx = tx_queue->efx;
430 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
431 FALCON_TXD_RING_SIZE *
432 sizeof(efx_qword_t));
433 }
434
435 int falcon_init_tx(struct efx_tx_queue *tx_queue)
436 {
437 efx_oword_t tx_desc_ptr;
438 struct efx_nic *efx = tx_queue->efx;
439 int rc;
440
441 /* Pin TX descriptor ring */
442 rc = falcon_init_special_buffer(efx, &tx_queue->txd);
443 if (rc)
444 return rc;
445
446 /* Push TX descriptor ring to card */
447 EFX_POPULATE_OWORD_10(tx_desc_ptr,
448 TX_DESCQ_EN, 1,
449 TX_ISCSI_DDIG_EN, 0,
450 TX_ISCSI_HDIG_EN, 0,
451 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
452 TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum,
453 TX_DESCQ_OWNER_ID, 0,
454 TX_DESCQ_LABEL, tx_queue->queue,
455 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
456 TX_DESCQ_TYPE, 0,
457 TX_NON_IP_DROP_DIS_B0, 1);
458
459 if (falcon_rev(efx) >= FALCON_REV_B0) {
460 int csum = !(efx->net_dev->features & NETIF_F_IP_CSUM);
461 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, csum);
462 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, csum);
463 }
464
465 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
466 tx_queue->queue);
467
468 if (falcon_rev(efx) < FALCON_REV_B0) {
469 efx_oword_t reg;
470
471 BUG_ON(tx_queue->queue >= 128); /* HW limit */
472
473 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
474 if (efx->net_dev->features & NETIF_F_IP_CSUM)
475 clear_bit_le(tx_queue->queue, (void *)&reg);
476 else
477 set_bit_le(tx_queue->queue, (void *)&reg);
478 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
479 }
480
481 return 0;
482 }
483
484 static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
485 {
486 struct efx_nic *efx = tx_queue->efx;
487 struct efx_channel *channel = &efx->channel[0];
488 efx_oword_t tx_flush_descq;
489 unsigned int read_ptr, i;
490
491 /* Post a flush command */
492 EFX_POPULATE_OWORD_2(tx_flush_descq,
493 TX_FLUSH_DESCQ_CMD, 1,
494 TX_FLUSH_DESCQ, tx_queue->queue);
495 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
496 msleep(FALCON_FLUSH_TIMEOUT);
497
498 if (EFX_WORKAROUND_7803(efx))
499 return 0;
500
501 /* Look for a flush completed event */
502 read_ptr = channel->eventq_read_ptr;
503 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
504 efx_qword_t *event = falcon_event(channel, read_ptr);
505 int ev_code, ev_sub_code, ev_queue;
506 if (!falcon_event_present(event))
507 break;
508
509 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
510 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
511 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
512 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
513 (ev_queue == tx_queue->queue)) {
514 EFX_LOG(efx, "tx queue %d flush command succesful\n",
515 tx_queue->queue);
516 return 0;
517 }
518
519 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
520 }
521
522 if (EFX_WORKAROUND_11557(efx)) {
523 efx_oword_t reg;
524 int enabled;
525
526 falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
527 tx_queue->queue);
528 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
529 if (!enabled) {
530 EFX_LOG(efx, "tx queue %d disabled without a "
531 "flush event seen\n", tx_queue->queue);
532 return 0;
533 }
534 }
535
536 EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
537 return -ETIMEDOUT;
538 }
539
540 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
541 {
542 struct efx_nic *efx = tx_queue->efx;
543 efx_oword_t tx_desc_ptr;
544
545 /* Stop the hardware using the queue */
546 if (falcon_flush_tx_queue(tx_queue))
547 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
548
549 /* Remove TX descriptor ring from card */
550 EFX_ZERO_OWORD(tx_desc_ptr);
551 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
552 tx_queue->queue);
553
554 /* Unpin TX descriptor ring */
555 falcon_fini_special_buffer(efx, &tx_queue->txd);
556 }
557
558 /* Free buffers backing TX queue */
559 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
560 {
561 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
562 }
563
564 /**************************************************************************
565 *
566 * Falcon RX path
567 *
568 **************************************************************************/
569
570 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
571 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
572 unsigned int index)
573 {
574 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
575 }
576
577 /* This creates an entry in the RX descriptor queue */
578 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
579 unsigned index)
580 {
581 struct efx_rx_buffer *rx_buf;
582 efx_qword_t *rxd;
583
584 rxd = falcon_rx_desc(rx_queue, index);
585 rx_buf = efx_rx_buffer(rx_queue, index);
586 EFX_POPULATE_QWORD_3(*rxd,
587 RX_KER_BUF_SIZE,
588 rx_buf->len -
589 rx_queue->efx->type->rx_buffer_padding,
590 RX_KER_BUF_REGION, 0,
591 RX_KER_BUF_ADR, rx_buf->dma_addr);
592 }
593
594 /* This writes to the RX_DESC_WPTR register for the specified receive
595 * descriptor ring.
596 */
597 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
598 {
599 efx_dword_t reg;
600 unsigned write_ptr;
601
602 while (rx_queue->notified_count != rx_queue->added_count) {
603 falcon_build_rx_desc(rx_queue,
604 rx_queue->notified_count &
605 FALCON_RXD_RING_MASK);
606 ++rx_queue->notified_count;
607 }
608
609 wmb();
610 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
611 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
612 falcon_writel_page(rx_queue->efx, &reg,
613 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
614 }
615
616 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
617 {
618 struct efx_nic *efx = rx_queue->efx;
619 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
620 FALCON_RXD_RING_SIZE *
621 sizeof(efx_qword_t));
622 }
623
624 int falcon_init_rx(struct efx_rx_queue *rx_queue)
625 {
626 efx_oword_t rx_desc_ptr;
627 struct efx_nic *efx = rx_queue->efx;
628 int rc;
629 int is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
630 int iscsi_digest_en = is_b0;
631
632 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
633 rx_queue->queue, rx_queue->rxd.index,
634 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
635
636 /* Pin RX descriptor ring */
637 rc = falcon_init_special_buffer(efx, &rx_queue->rxd);
638 if (rc)
639 return rc;
640
641 /* Push RX descriptor ring to card */
642 EFX_POPULATE_OWORD_10(rx_desc_ptr,
643 RX_ISCSI_DDIG_EN, iscsi_digest_en,
644 RX_ISCSI_HDIG_EN, iscsi_digest_en,
645 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
646 RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum,
647 RX_DESCQ_OWNER_ID, 0,
648 RX_DESCQ_LABEL, rx_queue->queue,
649 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
650 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
651 /* For >=B0 this is scatter so disable */
652 RX_DESCQ_JUMBO, !is_b0,
653 RX_DESCQ_EN, 1);
654 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
655 rx_queue->queue);
656 return 0;
657 }
658
659 static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
660 {
661 struct efx_nic *efx = rx_queue->efx;
662 struct efx_channel *channel = &efx->channel[0];
663 unsigned int read_ptr, i;
664 efx_oword_t rx_flush_descq;
665
666 /* Post a flush command */
667 EFX_POPULATE_OWORD_2(rx_flush_descq,
668 RX_FLUSH_DESCQ_CMD, 1,
669 RX_FLUSH_DESCQ, rx_queue->queue);
670 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
671 msleep(FALCON_FLUSH_TIMEOUT);
672
673 if (EFX_WORKAROUND_7803(efx))
674 return 0;
675
676 /* Look for a flush completed event */
677 read_ptr = channel->eventq_read_ptr;
678 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
679 efx_qword_t *event = falcon_event(channel, read_ptr);
680 int ev_code, ev_sub_code, ev_queue, ev_failed;
681 if (!falcon_event_present(event))
682 break;
683
684 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
685 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
686 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
687 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
688
689 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
690 (ev_queue == rx_queue->queue)) {
691 if (ev_failed) {
692 EFX_INFO(efx, "rx queue %d flush command "
693 "failed\n", rx_queue->queue);
694 return -EAGAIN;
695 } else {
696 EFX_LOG(efx, "rx queue %d flush command "
697 "succesful\n", rx_queue->queue);
698 return 0;
699 }
700 }
701
702 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
703 }
704
705 if (EFX_WORKAROUND_11557(efx)) {
706 efx_oword_t reg;
707 int enabled;
708
709 falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
710 rx_queue->queue);
711 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
712 if (!enabled) {
713 EFX_LOG(efx, "rx queue %d disabled without a "
714 "flush event seen\n", rx_queue->queue);
715 return 0;
716 }
717 }
718
719 EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
720 return -ETIMEDOUT;
721 }
722
723 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
724 {
725 efx_oword_t rx_desc_ptr;
726 struct efx_nic *efx = rx_queue->efx;
727 int i, rc;
728
729 /* Try and flush the rx queue. This may need to be repeated */
730 for (i = 0; i < 5; i++) {
731 rc = falcon_flush_rx_queue(rx_queue);
732 if (rc == -EAGAIN)
733 continue;
734 break;
735 }
736 if (rc)
737 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
738
739 /* Remove RX descriptor ring from card */
740 EFX_ZERO_OWORD(rx_desc_ptr);
741 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
742 rx_queue->queue);
743
744 /* Unpin RX descriptor ring */
745 falcon_fini_special_buffer(efx, &rx_queue->rxd);
746 }
747
748 /* Free buffers backing RX queue */
749 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
750 {
751 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
752 }
753
754 /**************************************************************************
755 *
756 * Falcon event queue processing
757 * Event queues are processed by per-channel tasklets.
758 *
759 **************************************************************************/
760
761 /* Update a channel's event queue's read pointer (RPTR) register
762 *
763 * This writes the EVQ_RPTR_REG register for the specified channel's
764 * event queue.
765 *
766 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
767 * whereas channel->eventq_read_ptr contains the index of the "next to
768 * read" event.
769 */
770 void falcon_eventq_read_ack(struct efx_channel *channel)
771 {
772 efx_dword_t reg;
773 struct efx_nic *efx = channel->efx;
774
775 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
776 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
777 channel->evqnum);
778 }
779
780 /* Use HW to insert a SW defined event */
781 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
782 {
783 efx_oword_t drv_ev_reg;
784
785 EFX_POPULATE_OWORD_2(drv_ev_reg,
786 DRV_EV_QID, channel->evqnum,
787 DRV_EV_DATA,
788 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
789 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
790 }
791
792 /* Handle a transmit completion event
793 *
794 * Falcon batches TX completion events; the message we receive is of
795 * the form "complete all TX events up to this index".
796 */
797 static inline void falcon_handle_tx_event(struct efx_channel *channel,
798 efx_qword_t *event)
799 {
800 unsigned int tx_ev_desc_ptr;
801 unsigned int tx_ev_q_label;
802 struct efx_tx_queue *tx_queue;
803 struct efx_nic *efx = channel->efx;
804
805 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
806 /* Transmit completion */
807 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
808 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
809 tx_queue = &efx->tx_queue[tx_ev_q_label];
810 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
811 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
812 /* Rewrite the FIFO write pointer */
813 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
814 tx_queue = &efx->tx_queue[tx_ev_q_label];
815
816 if (efx_dev_registered(efx))
817 netif_tx_lock(efx->net_dev);
818 falcon_notify_tx_desc(tx_queue);
819 if (efx_dev_registered(efx))
820 netif_tx_unlock(efx->net_dev);
821 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
822 EFX_WORKAROUND_10727(efx)) {
823 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
824 } else {
825 EFX_ERR(efx, "channel %d unexpected TX event "
826 EFX_QWORD_FMT"\n", channel->channel,
827 EFX_QWORD_VAL(*event));
828 }
829 }
830
831 /* Check received packet's destination MAC address. */
832 static int check_dest_mac(struct efx_rx_queue *rx_queue,
833 const efx_qword_t *event)
834 {
835 struct efx_rx_buffer *rx_buf;
836 struct efx_nic *efx = rx_queue->efx;
837 int rx_ev_desc_ptr;
838 struct ethhdr *eh;
839
840 if (efx->promiscuous)
841 return 1;
842
843 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
844 rx_buf = efx_rx_buffer(rx_queue, rx_ev_desc_ptr);
845 eh = (struct ethhdr *)rx_buf->data;
846 if (memcmp(eh->h_dest, efx->net_dev->dev_addr, ETH_ALEN))
847 return 0;
848 return 1;
849 }
850
851 /* Detect errors included in the rx_evt_pkt_ok bit. */
852 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
853 const efx_qword_t *event,
854 unsigned *rx_ev_pkt_ok,
855 int *discard, int byte_count)
856 {
857 struct efx_nic *efx = rx_queue->efx;
858 unsigned rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
859 unsigned rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
860 unsigned rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
861 unsigned rx_ev_pkt_type, rx_ev_other_err, rx_ev_pause_frm;
862 unsigned rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
863 int snap, non_ip;
864
865 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
866 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
867 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
868 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
869 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
870 RX_EV_BUF_OWNER_ID_ERR);
871 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
872 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
873 RX_EV_IP_HDR_CHKSUM_ERR);
874 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
875 RX_EV_TCP_UDP_CHKSUM_ERR);
876 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
877 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
878 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
879 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
880 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
881
882 /* Every error apart from tobe_disc and pause_frm */
883 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
884 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
885 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
886
887 snap = (rx_ev_pkt_type == RX_EV_PKT_TYPE_LLC_DECODE) ||
888 (rx_ev_pkt_type == RX_EV_PKT_TYPE_VLAN_LLC_DECODE);
889 non_ip = (rx_ev_hdr_type == RX_EV_HDR_TYPE_NON_IP_DECODE);
890
891 /* SFC bug 5475/8970: The Falcon XMAC incorrectly calculates the
892 * length field of an LLC frame, which sets TOBE_DISC. We could set
893 * PASS_LEN_ERR, but we want the MAC to filter out short frames (to
894 * protect the RX block).
895 *
896 * bug5475 - LLC/SNAP: Falcon identifies SNAP packets.
897 * bug8970 - LLC/noSNAP: Falcon does not provide an LLC flag.
898 * LLC can't encapsulate IP, so by definition
899 * these packets are NON_IP.
900 *
901 * Unicast mismatch will also cause TOBE_DISC, so the driver needs
902 * to check this.
903 */
904 if (EFX_WORKAROUND_5475(efx) && rx_ev_tobe_disc && (snap || non_ip)) {
905 /* If all the other flags are zero then we can state the
906 * entire packet is ok, which will flag to the kernel not
907 * to recalculate checksums.
908 */
909 if (!(non_ip | rx_ev_other_err | rx_ev_pause_frm))
910 *rx_ev_pkt_ok = 1;
911
912 rx_ev_tobe_disc = 0;
913
914 /* TOBE_DISC is set for unicast mismatch. But given that
915 * we can't trust TOBE_DISC here, we must validate the dest
916 * MAC address ourselves.
917 */
918 if (!rx_ev_mcast_pkt && !check_dest_mac(rx_queue, event))
919 rx_ev_tobe_disc = 1;
920 }
921
922 /* Count errors that are not in MAC stats. */
923 if (rx_ev_frm_trunc)
924 ++rx_queue->channel->n_rx_frm_trunc;
925 else if (rx_ev_tobe_disc)
926 ++rx_queue->channel->n_rx_tobe_disc;
927 else if (rx_ev_ip_hdr_chksum_err)
928 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
929 else if (rx_ev_tcp_udp_chksum_err)
930 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
931 if (rx_ev_ip_frag_err)
932 ++rx_queue->channel->n_rx_ip_frag_err;
933
934 /* The frame must be discarded if any of these are true. */
935 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
936 rx_ev_tobe_disc | rx_ev_pause_frm);
937
938 /* TOBE_DISC is expected on unicast mismatches; don't print out an
939 * error message. FRM_TRUNC indicates RXDP dropped the packet due
940 * to a FIFO overflow.
941 */
942 #ifdef EFX_ENABLE_DEBUG
943 if (rx_ev_other_err) {
944 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
945 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s%s\n",
946 rx_queue->queue, EFX_QWORD_VAL(*event),
947 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
948 rx_ev_ip_hdr_chksum_err ?
949 " [IP_HDR_CHKSUM_ERR]" : "",
950 rx_ev_tcp_udp_chksum_err ?
951 " [TCP_UDP_CHKSUM_ERR]" : "",
952 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
953 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
954 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
955 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
956 rx_ev_pause_frm ? " [PAUSE]" : "",
957 snap ? " [SNAP/LLC]" : "");
958 }
959 #endif
960
961 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
962 efx->phy_type == PHY_TYPE_10XPRESS))
963 tenxpress_crc_err(efx);
964 }
965
966 /* Handle receive events that are not in-order. */
967 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
968 unsigned index)
969 {
970 struct efx_nic *efx = rx_queue->efx;
971 unsigned expected, dropped;
972
973 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
974 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
975 FALCON_RXD_RING_MASK);
976 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
977 dropped, index, expected);
978
979 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
980 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
981 }
982
983 /* Handle a packet received event
984 *
985 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
986 * wrong destination address
987 * Also "is multicast" and "matches multicast filter" flags can be used to
988 * discard non-matching multicast packets.
989 */
990 static inline int falcon_handle_rx_event(struct efx_channel *channel,
991 const efx_qword_t *event)
992 {
993 unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt;
994 unsigned int rx_ev_pkt_ok, rx_ev_hdr_type, rx_ev_mcast_pkt;
995 unsigned expected_ptr;
996 int discard = 0, checksummed;
997 struct efx_rx_queue *rx_queue;
998 struct efx_nic *efx = channel->efx;
999
1000 /* Basic packet information */
1001 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
1002 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
1003 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
1004 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
1005 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
1006
1007 rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL);
1008 rx_queue = &efx->rx_queue[rx_ev_q_label];
1009
1010 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
1011 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
1012 if (unlikely(rx_ev_desc_ptr != expected_ptr)) {
1013 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
1014 return rx_ev_q_label;
1015 }
1016
1017 if (likely(rx_ev_pkt_ok)) {
1018 /* If packet is marked as OK and packet type is TCP/IPv4 or
1019 * UDP/IPv4, then we can rely on the hardware checksum.
1020 */
1021 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
1022 } else {
1023 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
1024 &discard, rx_ev_byte_cnt);
1025 checksummed = 0;
1026 }
1027
1028 /* Detect multicast packets that didn't match the filter */
1029 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
1030 if (rx_ev_mcast_pkt) {
1031 unsigned int rx_ev_mcast_hash_match =
1032 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
1033
1034 if (unlikely(!rx_ev_mcast_hash_match))
1035 discard = 1;
1036 }
1037
1038 /* Handle received packet */
1039 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
1040 checksummed, discard);
1041
1042 return rx_ev_q_label;
1043 }
1044
1045 /* Global events are basically PHY events */
1046 static void falcon_handle_global_event(struct efx_channel *channel,
1047 efx_qword_t *event)
1048 {
1049 struct efx_nic *efx = channel->efx;
1050 int is_phy_event = 0, handled = 0;
1051
1052 /* Check for interrupt on either port. Some boards have a
1053 * single PHY wired to the interrupt line for port 1. */
1054 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1055 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1056 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
1057 is_phy_event = 1;
1058
1059 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
1060 EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
1061 is_phy_event = 1;
1062
1063 if (is_phy_event) {
1064 efx->phy_op->clear_interrupt(efx);
1065 queue_work(efx->workqueue, &efx->reconfigure_work);
1066 handled = 1;
1067 }
1068
1069 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1070 EFX_ERR(efx, "channel %d seen global RX_RESET "
1071 "event. Resetting.\n", channel->channel);
1072
1073 atomic_inc(&efx->rx_reset);
1074 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1075 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1076 handled = 1;
1077 }
1078
1079 if (!handled)
1080 EFX_ERR(efx, "channel %d unknown global event "
1081 EFX_QWORD_FMT "\n", channel->channel,
1082 EFX_QWORD_VAL(*event));
1083 }
1084
1085 static void falcon_handle_driver_event(struct efx_channel *channel,
1086 efx_qword_t *event)
1087 {
1088 struct efx_nic *efx = channel->efx;
1089 unsigned int ev_sub_code;
1090 unsigned int ev_sub_data;
1091
1092 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1093 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1094
1095 switch (ev_sub_code) {
1096 case TX_DESCQ_FLS_DONE_EV_DECODE:
1097 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1098 channel->channel, ev_sub_data);
1099 break;
1100 case RX_DESCQ_FLS_DONE_EV_DECODE:
1101 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1102 channel->channel, ev_sub_data);
1103 break;
1104 case EVQ_INIT_DONE_EV_DECODE:
1105 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1106 channel->channel, ev_sub_data);
1107 break;
1108 case SRM_UPD_DONE_EV_DECODE:
1109 EFX_TRACE(efx, "channel %d SRAM update done\n",
1110 channel->channel);
1111 break;
1112 case WAKE_UP_EV_DECODE:
1113 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1114 channel->channel, ev_sub_data);
1115 break;
1116 case TIMER_EV_DECODE:
1117 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1118 channel->channel, ev_sub_data);
1119 break;
1120 case RX_RECOVERY_EV_DECODE:
1121 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1122 "Resetting.\n", channel->channel);
1123 atomic_inc(&efx->rx_reset);
1124 efx_schedule_reset(efx,
1125 EFX_WORKAROUND_6555(efx) ?
1126 RESET_TYPE_RX_RECOVERY :
1127 RESET_TYPE_DISABLE);
1128 break;
1129 case RX_DSC_ERROR_EV_DECODE:
1130 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1131 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1132 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1133 break;
1134 case TX_DSC_ERROR_EV_DECODE:
1135 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1136 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1137 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1138 break;
1139 default:
1140 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1141 "data %04x\n", channel->channel, ev_sub_code,
1142 ev_sub_data);
1143 break;
1144 }
1145 }
1146
1147 int falcon_process_eventq(struct efx_channel *channel, int *rx_quota)
1148 {
1149 unsigned int read_ptr;
1150 efx_qword_t event, *p_event;
1151 int ev_code;
1152 int rxq;
1153 int rxdmaqs = 0;
1154
1155 read_ptr = channel->eventq_read_ptr;
1156
1157 do {
1158 p_event = falcon_event(channel, read_ptr);
1159 event = *p_event;
1160
1161 if (!falcon_event_present(&event))
1162 /* End of events */
1163 break;
1164
1165 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1166 channel->channel, EFX_QWORD_VAL(event));
1167
1168 /* Clear this event by marking it all ones */
1169 EFX_SET_QWORD(*p_event);
1170
1171 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1172
1173 switch (ev_code) {
1174 case RX_IP_EV_DECODE:
1175 rxq = falcon_handle_rx_event(channel, &event);
1176 rxdmaqs |= (1 << rxq);
1177 (*rx_quota)--;
1178 break;
1179 case TX_IP_EV_DECODE:
1180 falcon_handle_tx_event(channel, &event);
1181 break;
1182 case DRV_GEN_EV_DECODE:
1183 channel->eventq_magic
1184 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1185 EFX_LOG(channel->efx, "channel %d received generated "
1186 "event "EFX_QWORD_FMT"\n", channel->channel,
1187 EFX_QWORD_VAL(event));
1188 break;
1189 case GLOBAL_EV_DECODE:
1190 falcon_handle_global_event(channel, &event);
1191 break;
1192 case DRIVER_EV_DECODE:
1193 falcon_handle_driver_event(channel, &event);
1194 break;
1195 default:
1196 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1197 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1198 ev_code, EFX_QWORD_VAL(event));
1199 }
1200
1201 /* Increment read pointer */
1202 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1203
1204 } while (*rx_quota);
1205
1206 channel->eventq_read_ptr = read_ptr;
1207 return rxdmaqs;
1208 }
1209
1210 void falcon_set_int_moderation(struct efx_channel *channel)
1211 {
1212 efx_dword_t timer_cmd;
1213 struct efx_nic *efx = channel->efx;
1214
1215 /* Set timer register */
1216 if (channel->irq_moderation) {
1217 /* Round to resolution supported by hardware. The value we
1218 * program is based at 0. So actual interrupt moderation
1219 * achieved is ((x + 1) * res).
1220 */
1221 unsigned int res = 5;
1222 channel->irq_moderation -= (channel->irq_moderation % res);
1223 if (channel->irq_moderation < res)
1224 channel->irq_moderation = res;
1225 EFX_POPULATE_DWORD_2(timer_cmd,
1226 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1227 TIMER_VAL,
1228 (channel->irq_moderation / res) - 1);
1229 } else {
1230 EFX_POPULATE_DWORD_2(timer_cmd,
1231 TIMER_MODE, TIMER_MODE_DIS,
1232 TIMER_VAL, 0);
1233 }
1234 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1235 channel->evqnum);
1236
1237 }
1238
1239 /* Allocate buffer table entries for event queue */
1240 int falcon_probe_eventq(struct efx_channel *channel)
1241 {
1242 struct efx_nic *efx = channel->efx;
1243 unsigned int evq_size;
1244
1245 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1246 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1247 }
1248
1249 int falcon_init_eventq(struct efx_channel *channel)
1250 {
1251 efx_oword_t evq_ptr;
1252 struct efx_nic *efx = channel->efx;
1253 int rc;
1254
1255 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1256 channel->channel, channel->eventq.index,
1257 channel->eventq.index + channel->eventq.entries - 1);
1258
1259 /* Pin event queue buffer */
1260 rc = falcon_init_special_buffer(efx, &channel->eventq);
1261 if (rc)
1262 return rc;
1263
1264 /* Fill event queue with all ones (i.e. empty events) */
1265 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1266
1267 /* Push event queue to card */
1268 EFX_POPULATE_OWORD_3(evq_ptr,
1269 EVQ_EN, 1,
1270 EVQ_SIZE, FALCON_EVQ_ORDER,
1271 EVQ_BUF_BASE_ID, channel->eventq.index);
1272 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1273 channel->evqnum);
1274
1275 falcon_set_int_moderation(channel);
1276
1277 return 0;
1278 }
1279
1280 void falcon_fini_eventq(struct efx_channel *channel)
1281 {
1282 efx_oword_t eventq_ptr;
1283 struct efx_nic *efx = channel->efx;
1284
1285 /* Remove event queue from card */
1286 EFX_ZERO_OWORD(eventq_ptr);
1287 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1288 channel->evqnum);
1289
1290 /* Unpin event queue */
1291 falcon_fini_special_buffer(efx, &channel->eventq);
1292 }
1293
1294 /* Free buffers backing event queue */
1295 void falcon_remove_eventq(struct efx_channel *channel)
1296 {
1297 falcon_free_special_buffer(channel->efx, &channel->eventq);
1298 }
1299
1300
1301 /* Generates a test event on the event queue. A subsequent call to
1302 * process_eventq() should pick up the event and place the value of
1303 * "magic" into channel->eventq_magic;
1304 */
1305 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1306 {
1307 efx_qword_t test_event;
1308
1309 EFX_POPULATE_QWORD_2(test_event,
1310 EV_CODE, DRV_GEN_EV_DECODE,
1311 EVQ_MAGIC, magic);
1312 falcon_generate_event(channel, &test_event);
1313 }
1314
1315
1316 /**************************************************************************
1317 *
1318 * Falcon hardware interrupts
1319 * The hardware interrupt handler does very little work; all the event
1320 * queue processing is carried out by per-channel tasklets.
1321 *
1322 **************************************************************************/
1323
1324 /* Enable/disable/generate Falcon interrupts */
1325 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1326 int force)
1327 {
1328 efx_oword_t int_en_reg_ker;
1329
1330 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1331 KER_INT_KER, force,
1332 DRV_INT_EN_KER, enabled);
1333 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1334 }
1335
1336 void falcon_enable_interrupts(struct efx_nic *efx)
1337 {
1338 efx_oword_t int_adr_reg_ker;
1339 struct efx_channel *channel;
1340
1341 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1342 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1343
1344 /* Program address */
1345 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1346 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1347 INT_ADR_KER, efx->irq_status.dma_addr);
1348 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1349
1350 /* Enable interrupts */
1351 falcon_interrupts(efx, 1, 0);
1352
1353 /* Force processing of all the channels to get the EVQ RPTRs up to
1354 date */
1355 efx_for_each_channel_with_interrupt(channel, efx)
1356 efx_schedule_channel(channel);
1357 }
1358
1359 void falcon_disable_interrupts(struct efx_nic *efx)
1360 {
1361 /* Disable interrupts */
1362 falcon_interrupts(efx, 0, 0);
1363 }
1364
1365 /* Generate a Falcon test interrupt
1366 * Interrupt must already have been enabled, otherwise nasty things
1367 * may happen.
1368 */
1369 void falcon_generate_interrupt(struct efx_nic *efx)
1370 {
1371 falcon_interrupts(efx, 1, 1);
1372 }
1373
1374 /* Acknowledge a legacy interrupt from Falcon
1375 *
1376 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1377 *
1378 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1379 * BIU. Interrupt acknowledge is read sensitive so must write instead
1380 * (then read to ensure the BIU collector is flushed)
1381 *
1382 * NB most hardware supports MSI interrupts
1383 */
1384 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1385 {
1386 efx_dword_t reg;
1387
1388 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1389 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1390 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1391 }
1392
1393 /* Process a fatal interrupt
1394 * Disable bus mastering ASAP and schedule a reset
1395 */
1396 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1397 {
1398 struct falcon_nic_data *nic_data = efx->nic_data;
1399 efx_oword_t *int_ker = efx->irq_status.addr;
1400 efx_oword_t fatal_intr;
1401 int error, mem_perr;
1402 static int n_int_errors;
1403
1404 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1405 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1406
1407 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1408 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1409 EFX_OWORD_VAL(fatal_intr),
1410 error ? "disabling bus mastering" : "no recognised error");
1411 if (error == 0)
1412 goto out;
1413
1414 /* If this is a memory parity error dump which blocks are offending */
1415 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1416 if (mem_perr) {
1417 efx_oword_t reg;
1418 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1419 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1420 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1421 }
1422
1423 /* Disable DMA bus mastering on both devices */
1424 pci_disable_device(efx->pci_dev);
1425 if (FALCON_IS_DUAL_FUNC(efx))
1426 pci_disable_device(nic_data->pci_dev2);
1427
1428 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1429 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1430 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1431 } else {
1432 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1433 "NIC will be disabled\n");
1434 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1435 }
1436 out:
1437 return IRQ_HANDLED;
1438 }
1439
1440 /* Handle a legacy interrupt from Falcon
1441 * Acknowledges the interrupt and schedule event queue processing.
1442 */
1443 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1444 {
1445 struct efx_nic *efx = dev_id;
1446 efx_oword_t *int_ker = efx->irq_status.addr;
1447 struct efx_channel *channel;
1448 efx_dword_t reg;
1449 u32 queues;
1450 int syserr;
1451
1452 /* Read the ISR which also ACKs the interrupts */
1453 falcon_readl(efx, &reg, INT_ISR0_B0);
1454 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1455
1456 /* Check to see if we have a serious error condition */
1457 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1458 if (unlikely(syserr))
1459 return falcon_fatal_interrupt(efx);
1460
1461 if (queues == 0)
1462 return IRQ_NONE;
1463
1464 efx->last_irq_cpu = raw_smp_processor_id();
1465 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1466 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1467
1468 /* Schedule processing of any interrupting queues */
1469 channel = &efx->channel[0];
1470 while (queues) {
1471 if (queues & 0x01)
1472 efx_schedule_channel(channel);
1473 channel++;
1474 queues >>= 1;
1475 }
1476
1477 return IRQ_HANDLED;
1478 }
1479
1480
1481 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1482 {
1483 struct efx_nic *efx = dev_id;
1484 efx_oword_t *int_ker = efx->irq_status.addr;
1485 struct efx_channel *channel;
1486 int syserr;
1487 int queues;
1488
1489 /* Check to see if this is our interrupt. If it isn't, we
1490 * exit without having touched the hardware.
1491 */
1492 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1493 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1494 raw_smp_processor_id());
1495 return IRQ_NONE;
1496 }
1497 efx->last_irq_cpu = raw_smp_processor_id();
1498 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1499 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1500
1501 /* Check to see if we have a serious error condition */
1502 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1503 if (unlikely(syserr))
1504 return falcon_fatal_interrupt(efx);
1505
1506 /* Determine interrupting queues, clear interrupt status
1507 * register and acknowledge the device interrupt.
1508 */
1509 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1510 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1511 EFX_ZERO_OWORD(*int_ker);
1512 wmb(); /* Ensure the vector is cleared before interrupt ack */
1513 falcon_irq_ack_a1(efx);
1514
1515 /* Schedule processing of any interrupting queues */
1516 channel = &efx->channel[0];
1517 while (queues) {
1518 if (queues & 0x01)
1519 efx_schedule_channel(channel);
1520 channel++;
1521 queues >>= 1;
1522 }
1523
1524 return IRQ_HANDLED;
1525 }
1526
1527 /* Handle an MSI interrupt from Falcon
1528 *
1529 * Handle an MSI hardware interrupt. This routine schedules event
1530 * queue processing. No interrupt acknowledgement cycle is necessary.
1531 * Also, we never need to check that the interrupt is for us, since
1532 * MSI interrupts cannot be shared.
1533 */
1534 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1535 {
1536 struct efx_channel *channel = dev_id;
1537 struct efx_nic *efx = channel->efx;
1538 efx_oword_t *int_ker = efx->irq_status.addr;
1539 int syserr;
1540
1541 efx->last_irq_cpu = raw_smp_processor_id();
1542 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1543 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1544
1545 /* Check to see if we have a serious error condition */
1546 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1547 if (unlikely(syserr))
1548 return falcon_fatal_interrupt(efx);
1549
1550 /* Schedule processing of the channel */
1551 efx_schedule_channel(channel);
1552
1553 return IRQ_HANDLED;
1554 }
1555
1556
1557 /* Setup RSS indirection table.
1558 * This maps from the hash value of the packet to RXQ
1559 */
1560 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1561 {
1562 int i = 0;
1563 unsigned long offset;
1564 efx_dword_t dword;
1565
1566 if (falcon_rev(efx) < FALCON_REV_B0)
1567 return;
1568
1569 for (offset = RX_RSS_INDIR_TBL_B0;
1570 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1571 offset += 0x10) {
1572 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1573 i % efx->rss_queues);
1574 falcon_writel(efx, &dword, offset);
1575 i++;
1576 }
1577 }
1578
1579 /* Hook interrupt handler(s)
1580 * Try MSI and then legacy interrupts.
1581 */
1582 int falcon_init_interrupt(struct efx_nic *efx)
1583 {
1584 struct efx_channel *channel;
1585 int rc;
1586
1587 if (!EFX_INT_MODE_USE_MSI(efx)) {
1588 irq_handler_t handler;
1589 if (falcon_rev(efx) >= FALCON_REV_B0)
1590 handler = falcon_legacy_interrupt_b0;
1591 else
1592 handler = falcon_legacy_interrupt_a1;
1593
1594 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1595 efx->name, efx);
1596 if (rc) {
1597 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1598 efx->pci_dev->irq);
1599 goto fail1;
1600 }
1601 return 0;
1602 }
1603
1604 /* Hook MSI or MSI-X interrupt */
1605 efx_for_each_channel_with_interrupt(channel, efx) {
1606 rc = request_irq(channel->irq, falcon_msi_interrupt,
1607 IRQF_PROBE_SHARED, /* Not shared */
1608 efx->name, channel);
1609 if (rc) {
1610 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1611 goto fail2;
1612 }
1613 }
1614
1615 return 0;
1616
1617 fail2:
1618 efx_for_each_channel_with_interrupt(channel, efx)
1619 free_irq(channel->irq, channel);
1620 fail1:
1621 return rc;
1622 }
1623
1624 void falcon_fini_interrupt(struct efx_nic *efx)
1625 {
1626 struct efx_channel *channel;
1627 efx_oword_t reg;
1628
1629 /* Disable MSI/MSI-X interrupts */
1630 efx_for_each_channel_with_interrupt(channel, efx) {
1631 if (channel->irq)
1632 free_irq(channel->irq, channel);
1633 }
1634
1635 /* ACK legacy interrupt */
1636 if (falcon_rev(efx) >= FALCON_REV_B0)
1637 falcon_read(efx, &reg, INT_ISR0_B0);
1638 else
1639 falcon_irq_ack_a1(efx);
1640
1641 /* Disable legacy interrupt */
1642 if (efx->legacy_irq)
1643 free_irq(efx->legacy_irq, efx);
1644 }
1645
1646 /**************************************************************************
1647 *
1648 * EEPROM/flash
1649 *
1650 **************************************************************************
1651 */
1652
1653 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1654
1655 /* Wait for SPI command completion */
1656 static int falcon_spi_wait(struct efx_nic *efx)
1657 {
1658 efx_oword_t reg;
1659 int cmd_en, timer_active;
1660 int count;
1661
1662 count = 0;
1663 do {
1664 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1665 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1666 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1667 if (!cmd_en && !timer_active)
1668 return 0;
1669 udelay(10);
1670 } while (++count < 10000); /* wait upto 100msec */
1671 EFX_ERR(efx, "timed out waiting for SPI\n");
1672 return -ETIMEDOUT;
1673 }
1674
1675 static int
1676 falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command,
1677 unsigned int address, unsigned int addr_len,
1678 void *data, unsigned int len)
1679 {
1680 efx_oword_t reg;
1681 int rc;
1682
1683 BUG_ON(len > FALCON_SPI_MAX_LEN);
1684
1685 /* Check SPI not currently being accessed */
1686 rc = falcon_spi_wait(efx);
1687 if (rc)
1688 return rc;
1689
1690 /* Program address register */
1691 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1692 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1693
1694 /* Issue read command */
1695 EFX_POPULATE_OWORD_7(reg,
1696 EE_SPI_HCMD_CMD_EN, 1,
1697 EE_SPI_HCMD_SF_SEL, device_id,
1698 EE_SPI_HCMD_DABCNT, len,
1699 EE_SPI_HCMD_READ, EE_SPI_READ,
1700 EE_SPI_HCMD_DUBCNT, 0,
1701 EE_SPI_HCMD_ADBCNT, addr_len,
1702 EE_SPI_HCMD_ENC, command);
1703 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1704
1705 /* Wait for read to complete */
1706 rc = falcon_spi_wait(efx);
1707 if (rc)
1708 return rc;
1709
1710 /* Read data */
1711 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1712 memcpy(data, &reg, len);
1713 return 0;
1714 }
1715
1716 /**************************************************************************
1717 *
1718 * MAC wrapper
1719 *
1720 **************************************************************************
1721 */
1722 void falcon_drain_tx_fifo(struct efx_nic *efx)
1723 {
1724 efx_oword_t temp;
1725 int count;
1726
1727 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1728 (efx->loopback_mode != LOOPBACK_NONE))
1729 return;
1730
1731 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1732 /* There is no point in draining more than once */
1733 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1734 return;
1735
1736 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1737 * the drain sequence with the statistics fetch */
1738 spin_lock(&efx->stats_lock);
1739
1740 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1741 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1742
1743 /* Reset the MAC and EM block. */
1744 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1745 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1746 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1747 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1748 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1749
1750 count = 0;
1751 while (1) {
1752 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1753 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1754 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1755 !EFX_OWORD_FIELD(temp, RST_EM)) {
1756 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1757 count);
1758 break;
1759 }
1760 if (count > 20) {
1761 EFX_ERR(efx, "MAC reset failed\n");
1762 break;
1763 }
1764 count++;
1765 udelay(10);
1766 }
1767
1768 spin_unlock(&efx->stats_lock);
1769
1770 /* If we've reset the EM block and the link is up, then
1771 * we'll have to kick the XAUI link so the PHY can recover */
1772 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1773 falcon_reset_xaui(efx);
1774 }
1775
1776 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1777 {
1778 efx_oword_t temp;
1779
1780 if (falcon_rev(efx) < FALCON_REV_B0)
1781 return;
1782
1783 /* Isolate the MAC -> RX */
1784 falcon_read(efx, &temp, RX_CFG_REG_KER);
1785 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1786 falcon_write(efx, &temp, RX_CFG_REG_KER);
1787
1788 if (!efx->link_up)
1789 falcon_drain_tx_fifo(efx);
1790 }
1791
1792 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1793 {
1794 efx_oword_t reg;
1795 int link_speed;
1796 unsigned int tx_fc;
1797
1798 if (efx->link_options & GM_LPA_10000)
1799 link_speed = 0x3;
1800 else if (efx->link_options & GM_LPA_1000)
1801 link_speed = 0x2;
1802 else if (efx->link_options & GM_LPA_100)
1803 link_speed = 0x1;
1804 else
1805 link_speed = 0x0;
1806 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1807 * as advertised. Disable to ensure packets are not
1808 * indefinitely held and TX queue can be flushed at any point
1809 * while the link is down. */
1810 EFX_POPULATE_OWORD_5(reg,
1811 MAC_XOFF_VAL, 0xffff /* max pause time */,
1812 MAC_BCAD_ACPT, 1,
1813 MAC_UC_PROM, efx->promiscuous,
1814 MAC_LINK_STATUS, 1, /* always set */
1815 MAC_SPEED, link_speed);
1816 /* On B0, MAC backpressure can be disabled and packets get
1817 * discarded. */
1818 if (falcon_rev(efx) >= FALCON_REV_B0) {
1819 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1820 !efx->link_up);
1821 }
1822
1823 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1824
1825 /* Restore the multicast hash registers. */
1826 falcon_set_multicast_hash(efx);
1827
1828 /* Transmission of pause frames when RX crosses the threshold is
1829 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1830 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1831 tx_fc = (efx->flow_control & EFX_FC_TX) ? 1 : 0;
1832 falcon_read(efx, &reg, RX_CFG_REG_KER);
1833 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1834
1835 /* Unisolate the MAC -> RX */
1836 if (falcon_rev(efx) >= FALCON_REV_B0)
1837 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1838 falcon_write(efx, &reg, RX_CFG_REG_KER);
1839 }
1840
1841 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1842 {
1843 efx_oword_t reg;
1844 u32 *dma_done;
1845 int i;
1846
1847 if (disable_dma_stats)
1848 return 0;
1849
1850 /* Statistics fetch will fail if the MAC is in TX drain */
1851 if (falcon_rev(efx) >= FALCON_REV_B0) {
1852 efx_oword_t temp;
1853 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1854 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1855 return 0;
1856 }
1857
1858 dma_done = (efx->stats_buffer.addr + done_offset);
1859 *dma_done = FALCON_STATS_NOT_DONE;
1860 wmb(); /* ensure done flag is clear */
1861
1862 /* Initiate DMA transfer of stats */
1863 EFX_POPULATE_OWORD_2(reg,
1864 MAC_STAT_DMA_CMD, 1,
1865 MAC_STAT_DMA_ADR,
1866 efx->stats_buffer.dma_addr);
1867 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1868
1869 /* Wait for transfer to complete */
1870 for (i = 0; i < 400; i++) {
1871 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1872 return 0;
1873 udelay(10);
1874 }
1875
1876 EFX_ERR(efx, "timed out waiting for statistics\n");
1877 return -ETIMEDOUT;
1878 }
1879
1880 /**************************************************************************
1881 *
1882 * PHY access via GMII
1883 *
1884 **************************************************************************
1885 */
1886
1887 /* Use the top bit of the MII PHY id to indicate the PHY type
1888 * (1G/10G), with the remaining bits as the actual PHY id.
1889 *
1890 * This allows us to avoid leaking information from the mii_if_info
1891 * structure into other data structures.
1892 */
1893 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1894 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1895 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1896 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1897 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1898
1899
1900 /* Packing the clause 45 port and device fields into a single value */
1901 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1902 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1903 #define MD_DEV_ADR_COMP_LBN 0
1904 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1905
1906
1907 /* Wait for GMII access to complete */
1908 static int falcon_gmii_wait(struct efx_nic *efx)
1909 {
1910 efx_dword_t md_stat;
1911 int count;
1912
1913 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
1914 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
1915 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
1916 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
1917 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
1918 EFX_ERR(efx, "error from GMII access "
1919 EFX_DWORD_FMT"\n",
1920 EFX_DWORD_VAL(md_stat));
1921 return -EIO;
1922 }
1923 return 0;
1924 }
1925 udelay(10);
1926 }
1927 EFX_ERR(efx, "timed out waiting for GMII\n");
1928 return -ETIMEDOUT;
1929 }
1930
1931 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1932 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
1933 int addr, int value)
1934 {
1935 struct efx_nic *efx = net_dev->priv;
1936 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
1937 efx_oword_t reg;
1938
1939 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1940 * chosen so that the only current user, Falcon, can take the
1941 * packed value and use them directly.
1942 * Fail to build if this assumption is broken.
1943 */
1944 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
1945 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
1946 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
1947 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
1948
1949 if (phy_id2 == PHY_ADDR_INVALID)
1950 return;
1951
1952 /* See falcon_mdio_read for an explanation. */
1953 if (!(phy_id & FALCON_PHY_ID_10G)) {
1954 int mmd = ffs(efx->phy_op->mmds) - 1;
1955 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
1956 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
1957 & FALCON_PHY_ID_ID_MASK;
1958 }
1959
1960 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
1961 addr, value);
1962
1963 spin_lock_bh(&efx->phy_lock);
1964
1965 /* Check MII not currently being accessed */
1966 if (falcon_gmii_wait(efx) != 0)
1967 goto out;
1968
1969 /* Write the address/ID register */
1970 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
1971 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
1972
1973 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
1974 falcon_write(efx, &reg, MD_ID_REG_KER);
1975
1976 /* Write data */
1977 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
1978 falcon_write(efx, &reg, MD_TXD_REG_KER);
1979
1980 EFX_POPULATE_OWORD_2(reg,
1981 MD_WRC, 1,
1982 MD_GC, 0);
1983 falcon_write(efx, &reg, MD_CS_REG_KER);
1984
1985 /* Wait for data to be written */
1986 if (falcon_gmii_wait(efx) != 0) {
1987 /* Abort the write operation */
1988 EFX_POPULATE_OWORD_2(reg,
1989 MD_WRC, 0,
1990 MD_GC, 1);
1991 falcon_write(efx, &reg, MD_CS_REG_KER);
1992 udelay(10);
1993 }
1994
1995 out:
1996 spin_unlock_bh(&efx->phy_lock);
1997 }
1998
1999 /* Reads a GMII register from a PHY connected to Falcon. If no value
2000 * could be read, -1 will be returned. */
2001 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2002 {
2003 struct efx_nic *efx = net_dev->priv;
2004 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2005 efx_oword_t reg;
2006 int value = -1;
2007
2008 if (phy_addr == PHY_ADDR_INVALID)
2009 return -1;
2010
2011 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2012 * but the generic Linux code does not make any distinction or have
2013 * any state for this.
2014 * We spot the case where someone tried to talk 22 to a 45 PHY and
2015 * redirect the request to the lowest numbered MMD as a clause45
2016 * request. This is enough to allow simple queries like id and link
2017 * state to succeed. TODO: We may need to do more in future.
2018 */
2019 if (!(phy_id & FALCON_PHY_ID_10G)) {
2020 int mmd = ffs(efx->phy_op->mmds) - 1;
2021 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2022 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2023 & FALCON_PHY_ID_ID_MASK;
2024 }
2025
2026 spin_lock_bh(&efx->phy_lock);
2027
2028 /* Check MII not currently being accessed */
2029 if (falcon_gmii_wait(efx) != 0)
2030 goto out;
2031
2032 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2033 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2034
2035 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2036 falcon_write(efx, &reg, MD_ID_REG_KER);
2037
2038 /* Request data to be read */
2039 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2040 falcon_write(efx, &reg, MD_CS_REG_KER);
2041
2042 /* Wait for data to become available */
2043 value = falcon_gmii_wait(efx);
2044 if (value == 0) {
2045 falcon_read(efx, &reg, MD_RXD_REG_KER);
2046 value = EFX_OWORD_FIELD(reg, MD_RXD);
2047 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2048 phy_id, addr, value);
2049 } else {
2050 /* Abort the read operation */
2051 EFX_POPULATE_OWORD_2(reg,
2052 MD_RIC, 0,
2053 MD_GC, 1);
2054 falcon_write(efx, &reg, MD_CS_REG_KER);
2055
2056 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2057 "error %d\n", phy_id, addr, value);
2058 }
2059
2060 out:
2061 spin_unlock_bh(&efx->phy_lock);
2062
2063 return value;
2064 }
2065
2066 static void falcon_init_mdio(struct mii_if_info *gmii)
2067 {
2068 gmii->mdio_read = falcon_mdio_read;
2069 gmii->mdio_write = falcon_mdio_write;
2070 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2071 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2072 }
2073
2074 static int falcon_probe_phy(struct efx_nic *efx)
2075 {
2076 switch (efx->phy_type) {
2077 case PHY_TYPE_10XPRESS:
2078 efx->phy_op = &falcon_tenxpress_phy_ops;
2079 break;
2080 case PHY_TYPE_XFP:
2081 efx->phy_op = &falcon_xfp_phy_ops;
2082 break;
2083 default:
2084 EFX_ERR(efx, "Unknown PHY type %d\n",
2085 efx->phy_type);
2086 return -1;
2087 }
2088
2089 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
2090 return 0;
2091 }
2092
2093 /* This call is responsible for hooking in the MAC and PHY operations */
2094 int falcon_probe_port(struct efx_nic *efx)
2095 {
2096 int rc;
2097
2098 /* Hook in PHY operations table */
2099 rc = falcon_probe_phy(efx);
2100 if (rc)
2101 return rc;
2102
2103 /* Set up GMII structure for PHY */
2104 efx->mii.supports_gmii = 1;
2105 falcon_init_mdio(&efx->mii);
2106
2107 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2108 if (falcon_rev(efx) >= FALCON_REV_B0)
2109 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2110 else
2111 efx->flow_control = EFX_FC_RX;
2112
2113 /* Allocate buffer for stats */
2114 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2115 FALCON_MAC_STATS_SIZE);
2116 if (rc)
2117 return rc;
2118 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2119 (unsigned long long)efx->stats_buffer.dma_addr,
2120 efx->stats_buffer.addr,
2121 virt_to_phys(efx->stats_buffer.addr));
2122
2123 return 0;
2124 }
2125
2126 void falcon_remove_port(struct efx_nic *efx)
2127 {
2128 falcon_free_buffer(efx, &efx->stats_buffer);
2129 }
2130
2131 /**************************************************************************
2132 *
2133 * Multicast filtering
2134 *
2135 **************************************************************************
2136 */
2137
2138 void falcon_set_multicast_hash(struct efx_nic *efx)
2139 {
2140 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2141
2142 /* Broadcast packets go through the multicast hash filter.
2143 * ether_crc_le() of the broadcast address is 0xbe2612ff
2144 * so we always add bit 0xff to the mask.
2145 */
2146 set_bit_le(0xff, mc_hash->byte);
2147
2148 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2149 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2150 }
2151
2152 /**************************************************************************
2153 *
2154 * Device reset
2155 *
2156 **************************************************************************
2157 */
2158
2159 /* Resets NIC to known state. This routine must be called in process
2160 * context and is allowed to sleep. */
2161 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2162 {
2163 struct falcon_nic_data *nic_data = efx->nic_data;
2164 efx_oword_t glb_ctl_reg_ker;
2165 int rc;
2166
2167 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2168
2169 /* Initiate device reset */
2170 if (method == RESET_TYPE_WORLD) {
2171 rc = pci_save_state(efx->pci_dev);
2172 if (rc) {
2173 EFX_ERR(efx, "failed to backup PCI state of primary "
2174 "function prior to hardware reset\n");
2175 goto fail1;
2176 }
2177 if (FALCON_IS_DUAL_FUNC(efx)) {
2178 rc = pci_save_state(nic_data->pci_dev2);
2179 if (rc) {
2180 EFX_ERR(efx, "failed to backup PCI state of "
2181 "secondary function prior to "
2182 "hardware reset\n");
2183 goto fail2;
2184 }
2185 }
2186
2187 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2188 EXT_PHY_RST_DUR, 0x7,
2189 SWRST, 1);
2190 } else {
2191 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2192 EXCLUDE_FROM_RESET : 0);
2193
2194 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2195 EXT_PHY_RST_CTL, reset_phy,
2196 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2197 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2198 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2199 EE_RST_CTL, EXCLUDE_FROM_RESET,
2200 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2201 SWRST, 1);
2202 }
2203 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2204
2205 EFX_LOG(efx, "waiting for hardware reset\n");
2206 schedule_timeout_uninterruptible(HZ / 20);
2207
2208 /* Restore PCI configuration if needed */
2209 if (method == RESET_TYPE_WORLD) {
2210 if (FALCON_IS_DUAL_FUNC(efx)) {
2211 rc = pci_restore_state(nic_data->pci_dev2);
2212 if (rc) {
2213 EFX_ERR(efx, "failed to restore PCI config for "
2214 "the secondary function\n");
2215 goto fail3;
2216 }
2217 }
2218 rc = pci_restore_state(efx->pci_dev);
2219 if (rc) {
2220 EFX_ERR(efx, "failed to restore PCI config for the "
2221 "primary function\n");
2222 goto fail4;
2223 }
2224 EFX_LOG(efx, "successfully restored PCI config\n");
2225 }
2226
2227 /* Assert that reset complete */
2228 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2229 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2230 rc = -ETIMEDOUT;
2231 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2232 goto fail5;
2233 }
2234 EFX_LOG(efx, "hardware reset complete\n");
2235
2236 return 0;
2237
2238 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2239 fail2:
2240 fail3:
2241 pci_restore_state(efx->pci_dev);
2242 fail1:
2243 fail4:
2244 fail5:
2245 return rc;
2246 }
2247
2248 /* Zeroes out the SRAM contents. This routine must be called in
2249 * process context and is allowed to sleep.
2250 */
2251 static int falcon_reset_sram(struct efx_nic *efx)
2252 {
2253 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2254 int count;
2255
2256 /* Set the SRAM wake/sleep GPIO appropriately. */
2257 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2258 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2259 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2260 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2261
2262 /* Initiate SRAM reset */
2263 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2264 SRAM_OOB_BT_INIT_EN, 1,
2265 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2266 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2267
2268 /* Wait for SRAM reset to complete */
2269 count = 0;
2270 do {
2271 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2272
2273 /* SRAM reset is slow; expect around 16ms */
2274 schedule_timeout_uninterruptible(HZ / 50);
2275
2276 /* Check for reset complete */
2277 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2278 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2279 EFX_LOG(efx, "SRAM reset complete\n");
2280
2281 return 0;
2282 }
2283 } while (++count < 20); /* wait upto 0.4 sec */
2284
2285 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2286 return -ETIMEDOUT;
2287 }
2288
2289 /* Extract non-volatile configuration */
2290 static int falcon_probe_nvconfig(struct efx_nic *efx)
2291 {
2292 struct falcon_nvconfig *nvconfig;
2293 efx_oword_t nic_stat;
2294 int device_id;
2295 unsigned addr_len;
2296 size_t offset, len;
2297 int magic_num, struct_ver, board_rev;
2298 int rc;
2299
2300 /* Find the boot device. */
2301 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2302 if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) {
2303 device_id = EE_SPI_FLASH;
2304 addr_len = 3;
2305 } else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) {
2306 device_id = EE_SPI_EEPROM;
2307 addr_len = 2;
2308 } else {
2309 return -ENODEV;
2310 }
2311
2312 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2313
2314 /* Read the whole configuration structure into memory. */
2315 for (offset = 0; offset < sizeof(*nvconfig); offset += len) {
2316 len = min(sizeof(*nvconfig) - offset,
2317 (size_t) FALCON_SPI_MAX_LEN);
2318 rc = falcon_spi_read(efx, device_id, SPI_READ,
2319 NVCONFIG_BASE + offset, addr_len,
2320 (char *)nvconfig + offset, len);
2321 if (rc)
2322 goto out;
2323 }
2324
2325 /* Read the MAC addresses */
2326 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2327
2328 /* Read the board configuration. */
2329 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2330 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2331
2332 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
2333 EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
2334 "therefore using defaults\n", magic_num, struct_ver);
2335 efx->phy_type = PHY_TYPE_NONE;
2336 efx->mii.phy_id = PHY_ADDR_INVALID;
2337 board_rev = 0;
2338 } else {
2339 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2340
2341 efx->phy_type = v2->port0_phy_type;
2342 efx->mii.phy_id = v2->port0_phy_addr;
2343 board_rev = le16_to_cpu(v2->board_revision);
2344 }
2345
2346 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2347
2348 efx_set_board_info(efx, board_rev);
2349
2350 out:
2351 kfree(nvconfig);
2352 return rc;
2353 }
2354
2355 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2356 * count, port speed). Set workaround and feature flags accordingly.
2357 */
2358 static int falcon_probe_nic_variant(struct efx_nic *efx)
2359 {
2360 efx_oword_t altera_build;
2361
2362 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2363 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2364 EFX_ERR(efx, "Falcon FPGA not supported\n");
2365 return -ENODEV;
2366 }
2367
2368 switch (falcon_rev(efx)) {
2369 case FALCON_REV_A0:
2370 case 0xff:
2371 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2372 return -ENODEV;
2373
2374 case FALCON_REV_A1:{
2375 efx_oword_t nic_stat;
2376
2377 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2378
2379 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2380 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2381 return -ENODEV;
2382 }
2383 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2384 EFX_ERR(efx, "1G mode not supported\n");
2385 return -ENODEV;
2386 }
2387 break;
2388 }
2389
2390 case FALCON_REV_B0:
2391 break;
2392
2393 default:
2394 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2395 return -ENODEV;
2396 }
2397
2398 return 0;
2399 }
2400
2401 int falcon_probe_nic(struct efx_nic *efx)
2402 {
2403 struct falcon_nic_data *nic_data;
2404 int rc;
2405
2406 /* Initialise I2C interface state */
2407 efx->i2c.efx = efx;
2408 efx->i2c.op = &falcon_i2c_bit_operations;
2409 efx->i2c.sda = 1;
2410 efx->i2c.scl = 1;
2411
2412 /* Allocate storage for hardware specific data */
2413 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2414 efx->nic_data = nic_data;
2415
2416 /* Determine number of ports etc. */
2417 rc = falcon_probe_nic_variant(efx);
2418 if (rc)
2419 goto fail1;
2420
2421 /* Probe secondary function if expected */
2422 if (FALCON_IS_DUAL_FUNC(efx)) {
2423 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2424
2425 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2426 dev))) {
2427 if (dev->bus == efx->pci_dev->bus &&
2428 dev->devfn == efx->pci_dev->devfn + 1) {
2429 nic_data->pci_dev2 = dev;
2430 break;
2431 }
2432 }
2433 if (!nic_data->pci_dev2) {
2434 EFX_ERR(efx, "failed to find secondary function\n");
2435 rc = -ENODEV;
2436 goto fail2;
2437 }
2438 }
2439
2440 /* Now we can reset the NIC */
2441 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2442 if (rc) {
2443 EFX_ERR(efx, "failed to reset NIC\n");
2444 goto fail3;
2445 }
2446
2447 /* Allocate memory for INT_KER */
2448 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2449 if (rc)
2450 goto fail4;
2451 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2452
2453 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2454 (unsigned long long)efx->irq_status.dma_addr,
2455 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2456
2457 /* Read in the non-volatile configuration */
2458 rc = falcon_probe_nvconfig(efx);
2459 if (rc)
2460 goto fail5;
2461
2462 return 0;
2463
2464 fail5:
2465 falcon_free_buffer(efx, &efx->irq_status);
2466 fail4:
2467 fail3:
2468 if (nic_data->pci_dev2) {
2469 pci_dev_put(nic_data->pci_dev2);
2470 nic_data->pci_dev2 = NULL;
2471 }
2472 fail2:
2473 fail1:
2474 kfree(efx->nic_data);
2475 return rc;
2476 }
2477
2478 /* This call performs hardware-specific global initialisation, such as
2479 * defining the descriptor cache sizes and number of RSS channels.
2480 * It does not set up any buffers, descriptor rings or event queues.
2481 */
2482 int falcon_init_nic(struct efx_nic *efx)
2483 {
2484 efx_oword_t temp;
2485 unsigned thresh;
2486 int rc;
2487
2488 /* Set up the address region register. This is only needed
2489 * for the B0 FPGA, but since we are just pushing in the
2490 * reset defaults this may as well be unconditional. */
2491 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2492 ADR_REGION1, (1 << 16),
2493 ADR_REGION2, (2 << 16),
2494 ADR_REGION3, (3 << 16));
2495 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2496
2497 /* Use on-chip SRAM */
2498 falcon_read(efx, &temp, NIC_STAT_REG);
2499 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2500 falcon_write(efx, &temp, NIC_STAT_REG);
2501
2502 /* Set buffer table mode */
2503 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2504 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2505
2506 rc = falcon_reset_sram(efx);
2507 if (rc)
2508 return rc;
2509
2510 /* Set positions of descriptor caches in SRAM. */
2511 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2512 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2513 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2514 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2515
2516 /* Set TX descriptor cache size. */
2517 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2518 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2519 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2520
2521 /* Set RX descriptor cache size. Set low watermark to size-8, as
2522 * this allows most efficient prefetching.
2523 */
2524 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2525 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2526 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2527 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2528 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2529
2530 /* Clear the parity enables on the TX data fifos as
2531 * they produce false parity errors because of timing issues
2532 */
2533 if (EFX_WORKAROUND_5129(efx)) {
2534 falcon_read(efx, &temp, SPARE_REG_KER);
2535 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2536 falcon_write(efx, &temp, SPARE_REG_KER);
2537 }
2538
2539 /* Enable all the genuinely fatal interrupts. (They are still
2540 * masked by the overall interrupt mask, controlled by
2541 * falcon_interrupts()).
2542 *
2543 * Note: All other fatal interrupts are enabled
2544 */
2545 EFX_POPULATE_OWORD_3(temp,
2546 ILL_ADR_INT_KER_EN, 1,
2547 RBUF_OWN_INT_KER_EN, 1,
2548 TBUF_OWN_INT_KER_EN, 1);
2549 EFX_INVERT_OWORD(temp);
2550 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2551
2552 /* Set number of RSS queues for receive path. */
2553 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2554 if (falcon_rev(efx) >= FALCON_REV_B0)
2555 EFX_SET_OWORD_FIELD(temp, NUM_KER, 0);
2556 else
2557 EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1);
2558 if (EFX_WORKAROUND_7244(efx)) {
2559 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2560 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2561 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2562 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2563 }
2564 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2565
2566 falcon_setup_rss_indir_table(efx);
2567
2568 /* Setup RX. Wait for descriptor is broken and must
2569 * be disabled. RXDP recovery shouldn't be needed, but is.
2570 */
2571 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2572 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2573 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2574 if (EFX_WORKAROUND_5583(efx))
2575 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2576 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2577
2578 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2579 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2580 */
2581 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2582 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2583 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2584 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2585 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2586 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2587 /* Enable SW_EV to inherit in char driver - assume harmless here */
2588 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2589 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2590 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2591 /* Squash TX of packets of 16 bytes or less */
2592 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
2593 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2594 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2595
2596 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2597 * descriptors (which is bad).
2598 */
2599 falcon_read(efx, &temp, TX_CFG_REG_KER);
2600 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2601 falcon_write(efx, &temp, TX_CFG_REG_KER);
2602
2603 /* RX config */
2604 falcon_read(efx, &temp, RX_CFG_REG_KER);
2605 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2606 if (EFX_WORKAROUND_7575(efx))
2607 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2608 (3 * 4096) / 32);
2609 if (falcon_rev(efx) >= FALCON_REV_B0)
2610 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2611
2612 /* RX FIFO flow control thresholds */
2613 thresh = ((rx_xon_thresh_bytes >= 0) ?
2614 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2615 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2616 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2617 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2618 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2619 /* RX control FIFO thresholds [32 entries] */
2620 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 25);
2621 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 20);
2622 falcon_write(efx, &temp, RX_CFG_REG_KER);
2623
2624 /* Set destination of both TX and RX Flush events */
2625 if (falcon_rev(efx) >= FALCON_REV_B0) {
2626 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2627 falcon_write(efx, &temp, DP_CTRL_REG);
2628 }
2629
2630 return 0;
2631 }
2632
2633 void falcon_remove_nic(struct efx_nic *efx)
2634 {
2635 struct falcon_nic_data *nic_data = efx->nic_data;
2636
2637 falcon_free_buffer(efx, &efx->irq_status);
2638
2639 falcon_reset_hw(efx, RESET_TYPE_ALL);
2640
2641 /* Release the second function after the reset */
2642 if (nic_data->pci_dev2) {
2643 pci_dev_put(nic_data->pci_dev2);
2644 nic_data->pci_dev2 = NULL;
2645 }
2646
2647 /* Tear down the private nic state */
2648 kfree(efx->nic_data);
2649 efx->nic_data = NULL;
2650 }
2651
2652 void falcon_update_nic_stats(struct efx_nic *efx)
2653 {
2654 efx_oword_t cnt;
2655
2656 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
2657 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
2658 }
2659
2660 /**************************************************************************
2661 *
2662 * Revision-dependent attributes used by efx.c
2663 *
2664 **************************************************************************
2665 */
2666
2667 struct efx_nic_type falcon_a_nic_type = {
2668 .mem_bar = 2,
2669 .mem_map_size = 0x20000,
2670 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
2671 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
2672 .buf_tbl_base = BUF_TBL_KER_A1,
2673 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
2674 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
2675 .txd_ring_mask = FALCON_TXD_RING_MASK,
2676 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2677 .evq_size = FALCON_EVQ_SIZE,
2678 .max_dma_mask = FALCON_DMA_MASK,
2679 .tx_dma_mask = FALCON_TX_DMA_MASK,
2680 .bug5391_mask = 0xf,
2681 .rx_xoff_thresh = 2048,
2682 .rx_xon_thresh = 512,
2683 .rx_buffer_padding = 0x24,
2684 .max_interrupt_mode = EFX_INT_MODE_MSI,
2685 .phys_addr_channels = 4,
2686 };
2687
2688 struct efx_nic_type falcon_b_nic_type = {
2689 .mem_bar = 2,
2690 /* Map everything up to and including the RSS indirection
2691 * table. Don't map MSI-X table, MSI-X PBA since Linux
2692 * requires that they not be mapped. */
2693 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
2694 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
2695 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
2696 .buf_tbl_base = BUF_TBL_KER_B0,
2697 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
2698 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
2699 .txd_ring_mask = FALCON_TXD_RING_MASK,
2700 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2701 .evq_size = FALCON_EVQ_SIZE,
2702 .max_dma_mask = FALCON_DMA_MASK,
2703 .tx_dma_mask = FALCON_TX_DMA_MASK,
2704 .bug5391_mask = 0,
2705 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
2706 .rx_xon_thresh = 27648, /* ~3*max MTU */
2707 .rx_buffer_padding = 0,
2708 .max_interrupt_mode = EFX_INT_MODE_MSIX,
2709 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
2710 * interrupt handler only supports 32
2711 * channels */
2712 };
2713
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