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Linux 2.6.26-rc5
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / video / tridentfb.c
blobbeefab2992c042834fff60ad45a6ee92680ffcb0
1 /*
2 * Frame buffer driver for Trident Blade and Image series
3 *
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 *
6 *
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
14 * TODO:
15 * timing value tweaking so it looks good on every monitor in every mode
16 * TGUI acceleration
17 */
18
19 #include <linux/module.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23
24 #include <linux/delay.h>
25 #include <video/trident.h>
26
27 #define VERSION "0.7.8-NEWAPI"
28
29 struct tridentfb_par {
30 void __iomem *io_virt; /* iospace virtual memory address */
31 };
32
33 static unsigned char eng_oper; /* engine operation... */
34 static struct fb_ops tridentfb_ops;
35
36 static struct tridentfb_par default_par;
37
38 /* FIXME:kmalloc these 3 instead */
39 static struct fb_info fb_info;
40 static u32 pseudo_pal[16];
41
42 static struct fb_var_screeninfo default_var;
43
44 static struct fb_fix_screeninfo tridentfb_fix = {
45 .id = "Trident",
46 .type = FB_TYPE_PACKED_PIXELS,
47 .ypanstep = 1,
48 .visual = FB_VISUAL_PSEUDOCOLOR,
49 .accel = FB_ACCEL_NONE,
50 };
51
52 static int chip_id;
53
54 static int defaultaccel;
55 static int displaytype;
56
57 /* defaults which are normally overriden by user values */
58
59 /* video mode */
60 static char *mode_option __devinitdata = "640x480";
61 static int bpp = 8;
62
63 static int noaccel;
64
65 static int center;
66 static int stretch;
67
68 static int fp;
69 static int crt;
70
71 static int memsize;
72 static int memdiff;
73 static int nativex;
74
75 module_param(mode_option, charp, 0);
76 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
77 module_param_named(mode, mode_option, charp, 0);
78 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
79 module_param(bpp, int, 0);
80 module_param(center, int, 0);
81 module_param(stretch, int, 0);
82 module_param(noaccel, int, 0);
83 module_param(memsize, int, 0);
84 module_param(memdiff, int, 0);
85 module_param(nativex, int, 0);
86 module_param(fp, int, 0);
87 module_param(crt, int, 0);
88
89 static int chip3D;
90 static int chipcyber;
91
92 static int is3Dchip(int id)
93 {
94 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
95 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
96 (id == CYBER9397) || (id == CYBER9397DVD) ||
97 (id == CYBER9520) || (id == CYBER9525DVD) ||
98 (id == IMAGE975) || (id == IMAGE985) ||
99 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
100 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
101 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
102 (id == CYBERBLADEXPAi1));
103 }
104
105 static int iscyber(int id)
106 {
107 switch (id) {
108 case CYBER9388:
109 case CYBER9382:
110 case CYBER9385:
111 case CYBER9397:
112 case CYBER9397DVD:
113 case CYBER9520:
114 case CYBER9525DVD:
115 case CYBERBLADEE4:
116 case CYBERBLADEi7D:
117 case CYBERBLADEi1:
118 case CYBERBLADEi1D:
119 case CYBERBLADEAi1:
120 case CYBERBLADEAi1D:
121 case CYBERBLADEXPAi1:
122 return 1;
123
124 case CYBER9320:
125 case TGUI9660:
126 case IMAGE975:
127 case IMAGE985:
128 case BLADE3D:
129 case CYBERBLADEi7: /* VIA MPV4 integrated version */
130
131 default:
132 /* case CYBERBLDAEXPm8: Strange */
133 /* case CYBERBLDAEXPm16: Strange */
134 return 0;
135 }
136 }
137
138 #define CRT 0x3D0 /* CRTC registers offset for color display */
139
140 #ifndef TRIDENT_MMIO
141 #define TRIDENT_MMIO 1
142 #endif
143
144 #if TRIDENT_MMIO
145 #define t_outb(val, reg) writeb(val,((struct tridentfb_par *)(fb_info.par))->io_virt + reg)
146 #define t_inb(reg) readb(((struct tridentfb_par*)(fb_info.par))->io_virt + reg)
147 #else
148 #define t_outb(val, reg) outb(val, reg)
149 #define t_inb(reg) inb(reg)
150 #endif
151
152
153 static struct accel_switch {
154 void (*init_accel) (int, int);
155 void (*wait_engine) (void);
156 void (*fill_rect) (u32, u32, u32, u32, u32, u32);
157 void (*copy_rect) (u32, u32, u32, u32, u32, u32);
158 } *acc;
159
160 #define writemmr(r, v) writel(v, ((struct tridentfb_par *)fb_info.par)->io_virt + r)
161 #define readmmr(r) readl(((struct tridentfb_par *)fb_info.par)->io_virt + r)
162
163 /*
164 * Blade specific acceleration.
165 */
166
167 #define point(x, y) ((y) << 16 | (x))
168 #define STA 0x2120
169 #define CMD 0x2144
170 #define ROP 0x2148
171 #define CLR 0x2160
172 #define SR1 0x2100
173 #define SR2 0x2104
174 #define DR1 0x2108
175 #define DR2 0x210C
176
177 #define ROP_S 0xCC
178
179 static void blade_init_accel(int pitch, int bpp)
180 {
181 int v1 = (pitch >> 3) << 20;
182 int tmp = 0, v2;
183 switch (bpp) {
184 case 8:
185 tmp = 0;
186 break;
187 case 15:
188 tmp = 5;
189 break;
190 case 16:
191 tmp = 1;
192 break;
193 case 24:
194 case 32:
195 tmp = 2;
196 break;
197 }
198 v2 = v1 | (tmp << 29);
199 writemmr(0x21C0, v2);
200 writemmr(0x21C4, v2);
201 writemmr(0x21B8, v2);
202 writemmr(0x21BC, v2);
203 writemmr(0x21D0, v1);
204 writemmr(0x21D4, v1);
205 writemmr(0x21C8, v1);
206 writemmr(0x21CC, v1);
207 writemmr(0x216C, 0);
208 }
209
210 static void blade_wait_engine(void)
211 {
212 while (readmmr(STA) & 0xFA800000) ;
213 }
214
215 static void blade_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
216 {
217 writemmr(CLR, c);
218 writemmr(ROP, rop ? 0x66 : ROP_S);
219 writemmr(CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
220
221 writemmr(DR1, point(x, y));
222 writemmr(DR2, point(x + w - 1, y + h - 1));
223 }
224
225 static void blade_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
226 {
227 u32 s1, s2, d1, d2;
228 int direction = 2;
229 s1 = point(x1, y1);
230 s2 = point(x1 + w - 1, y1 + h - 1);
231 d1 = point(x2, y2);
232 d2 = point(x2 + w - 1, y2 + h - 1);
233
234 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
235 direction = 0;
236
237 writemmr(ROP, ROP_S);
238 writemmr(CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
239
240 writemmr(SR1, direction ? s2 : s1);
241 writemmr(SR2, direction ? s1 : s2);
242 writemmr(DR1, direction ? d2 : d1);
243 writemmr(DR2, direction ? d1 : d2);
244 }
245
246 static struct accel_switch accel_blade = {
247 blade_init_accel,
248 blade_wait_engine,
249 blade_fill_rect,
250 blade_copy_rect,
251 };
252
253 /*
254 * BladeXP specific acceleration functions
255 */
256
257 #define ROP_P 0xF0
258 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
259
260 static void xp_init_accel(int pitch, int bpp)
261 {
262 int tmp = 0, v1;
263 unsigned char x = 0;
264
265 switch (bpp) {
266 case 8:
267 x = 0;
268 break;
269 case 16:
270 x = 1;
271 break;
272 case 24:
273 x = 3;
274 break;
275 case 32:
276 x = 2;
277 break;
278 }
279
280 switch (pitch << (bpp >> 3)) {
281 case 8192:
282 case 512:
283 x |= 0x00;
284 break;
285 case 1024:
286 x |= 0x04;
287 break;
288 case 2048:
289 x |= 0x08;
290 break;
291 case 4096:
292 x |= 0x0C;
293 break;
294 }
295
296 t_outb(x, 0x2125);
297
298 eng_oper = x | 0x40;
299
300 switch (bpp) {
301 case 8:
302 tmp = 18;
303 break;
304 case 15:
305 case 16:
306 tmp = 19;
307 break;
308 case 24:
309 case 32:
310 tmp = 20;
311 break;
312 }
313
314 v1 = pitch << tmp;
315
316 writemmr(0x2154, v1);
317 writemmr(0x2150, v1);
318 t_outb(3, 0x2126);
319 }
320
321 static void xp_wait_engine(void)
322 {
323 int busy;
324 int count, timeout;
325
326 count = 0;
327 timeout = 0;
328 for (;;) {
329 busy = t_inb(STA) & 0x80;
330 if (busy != 0x80)
331 return;
332 count++;
333 if (count == 10000000) {
334 /* Timeout */
335 count = 9990000;
336 timeout++;
337 if (timeout == 8) {
338 /* Reset engine */
339 t_outb(0x00, 0x2120);
340 return;
341 }
342 }
343 }
344 }
345
346 static void xp_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
347 {
348 writemmr(0x2127, ROP_P);
349 writemmr(0x2158, c);
350 writemmr(0x2128, 0x4000);
351 writemmr(0x2140, masked_point(h, w));
352 writemmr(0x2138, masked_point(y, x));
353 t_outb(0x01, 0x2124);
354 t_outb(eng_oper, 0x2125);
355 }
356
357 static void xp_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
358 {
359 int direction;
360 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
361
362 direction = 0x0004;
363
364 if ((x1 < x2) && (y1 == y2)) {
365 direction |= 0x0200;
366 x1_tmp = x1 + w - 1;
367 x2_tmp = x2 + w - 1;
368 } else {
369 x1_tmp = x1;
370 x2_tmp = x2;
371 }
372
373 if (y1 < y2) {
374 direction |= 0x0100;
375 y1_tmp = y1 + h - 1;
376 y2_tmp = y2 + h - 1;
377 } else {
378 y1_tmp = y1;
379 y2_tmp = y2;
380 }
381
382 writemmr(0x2128, direction);
383 t_outb(ROP_S, 0x2127);
384 writemmr(0x213C, masked_point(y1_tmp, x1_tmp));
385 writemmr(0x2138, masked_point(y2_tmp, x2_tmp));
386 writemmr(0x2140, masked_point(h, w));
387 t_outb(0x01, 0x2124);
388 }
389
390 static struct accel_switch accel_xp = {
391 xp_init_accel,
392 xp_wait_engine,
393 xp_fill_rect,
394 xp_copy_rect,
395 };
396
397 /*
398 * Image specific acceleration functions
399 */
400 static void image_init_accel(int pitch, int bpp)
401 {
402 int tmp = 0;
403 switch (bpp) {
404 case 8:
405 tmp = 0;
406 break;
407 case 15:
408 tmp = 5;
409 break;
410 case 16:
411 tmp = 1;
412 break;
413 case 24:
414 case 32:
415 tmp = 2;
416 break;
417 }
418 writemmr(0x2120, 0xF0000000);
419 writemmr(0x2120, 0x40000000 | tmp);
420 writemmr(0x2120, 0x80000000);
421 writemmr(0x2144, 0x00000000);
422 writemmr(0x2148, 0x00000000);
423 writemmr(0x2150, 0x00000000);
424 writemmr(0x2154, 0x00000000);
425 writemmr(0x2120, 0x60000000 | (pitch << 16) | pitch);
426 writemmr(0x216C, 0x00000000);
427 writemmr(0x2170, 0x00000000);
428 writemmr(0x217C, 0x00000000);
429 writemmr(0x2120, 0x10000000);
430 writemmr(0x2130, (2047 << 16) | 2047);
431 }
432
433 static void image_wait_engine(void)
434 {
435 while (readmmr(0x2164) & 0xF0000000) ;
436 }
437
438 static void image_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
439 {
440 writemmr(0x2120, 0x80000000);
441 writemmr(0x2120, 0x90000000 | ROP_S);
442
443 writemmr(0x2144, c);
444
445 writemmr(DR1, point(x, y));
446 writemmr(DR2, point(x + w - 1, y + h - 1));
447
448 writemmr(0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
449 }
450
451 static void image_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
452 {
453 u32 s1, s2, d1, d2;
454 int direction = 2;
455 s1 = point(x1, y1);
456 s2 = point(x1 + w - 1, y1 + h - 1);
457 d1 = point(x2, y2);
458 d2 = point(x2 + w - 1, y2 + h - 1);
459
460 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
461 direction = 0;
462
463 writemmr(0x2120, 0x80000000);
464 writemmr(0x2120, 0x90000000 | ROP_S);
465
466 writemmr(SR1, direction ? s2 : s1);
467 writemmr(SR2, direction ? s1 : s2);
468 writemmr(DR1, direction ? d2 : d1);
469 writemmr(DR2, direction ? d1 : d2);
470 writemmr(0x2124, 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
471 }
472
473 static struct accel_switch accel_image = {
474 image_init_accel,
475 image_wait_engine,
476 image_fill_rect,
477 image_copy_rect,
478 };
479
480 /*
481 * Accel functions called by the upper layers
482 */
483 #ifdef CONFIG_FB_TRIDENT_ACCEL
484 static void tridentfb_fillrect(struct fb_info *info,
485 const struct fb_fillrect *fr)
486 {
487 int bpp = info->var.bits_per_pixel;
488 int col = 0;
489
490 switch (bpp) {
491 default:
492 case 8:
493 col |= fr->color;
494 col |= col << 8;
495 col |= col << 16;
496 break;
497 case 16:
498 col = ((u32 *)(info->pseudo_palette))[fr->color];
499 break;
500 case 32:
501 col = ((u32 *)(info->pseudo_palette))[fr->color];
502 break;
503 }
504
505 acc->fill_rect(fr->dx, fr->dy, fr->width, fr->height, col, fr->rop);
506 acc->wait_engine();
507 }
508 static void tridentfb_copyarea(struct fb_info *info,
509 const struct fb_copyarea *ca)
510 {
511 acc->copy_rect(ca->sx, ca->sy, ca->dx, ca->dy, ca->width, ca->height);
512 acc->wait_engine();
513 }
514 #else /* !CONFIG_FB_TRIDENT_ACCEL */
515 #define tridentfb_fillrect cfb_fillrect
516 #define tridentfb_copyarea cfb_copyarea
517 #endif /* CONFIG_FB_TRIDENT_ACCEL */
518
519
520 /*
521 * Hardware access functions
522 */
523
524 static inline unsigned char read3X4(int reg)
525 {
526 struct tridentfb_par *par = (struct tridentfb_par *)fb_info.par;
527 writeb(reg, par->io_virt + CRT + 4);
528 return readb(par->io_virt + CRT + 5);
529 }
530
531 static inline void write3X4(int reg, unsigned char val)
532 {
533 struct tridentfb_par *par = (struct tridentfb_par *)fb_info.par;
534 writeb(reg, par->io_virt + CRT + 4);
535 writeb(val, par->io_virt + CRT + 5);
536 }
537
538 static inline unsigned char read3C4(int reg)
539 {
540 t_outb(reg, 0x3C4);
541 return t_inb(0x3C5);
542 }
543
544 static inline void write3C4(int reg, unsigned char val)
545 {
546 t_outb(reg, 0x3C4);
547 t_outb(val, 0x3C5);
548 }
549
550 static inline unsigned char read3CE(int reg)
551 {
552 t_outb(reg, 0x3CE);
553 return t_inb(0x3CF);
554 }
555
556 static inline void writeAttr(int reg, unsigned char val)
557 {
558 readb(((struct tridentfb_par *)fb_info.par)->io_virt + CRT + 0x0A); /* flip-flop to index */
559 t_outb(reg, 0x3C0);
560 t_outb(val, 0x3C0);
561 }
562
563 static inline void write3CE(int reg, unsigned char val)
564 {
565 t_outb(reg, 0x3CE);
566 t_outb(val, 0x3CF);
567 }
568
569 static void enable_mmio(void)
570 {
571 /* Goto New Mode */
572 outb(0x0B, 0x3C4);
573 inb(0x3C5);
574
575 /* Unprotect registers */
576 outb(NewMode1, 0x3C4);
577 outb(0x80, 0x3C5);
578
579 /* Enable MMIO */
580 outb(PCIReg, 0x3D4);
581 outb(inb(0x3D5) | 0x01, 0x3D5);
582 }
583
584 static void disable_mmio(void)
585 {
586 /* Goto New Mode */
587 t_outb(0x0B, 0x3C4);
588 t_inb(0x3C5);
589
590 /* Unprotect registers */
591 t_outb(NewMode1, 0x3C4);
592 t_outb(0x80, 0x3C5);
593
594 /* Disable MMIO */
595 t_outb(PCIReg, 0x3D4);
596 t_outb(t_inb(0x3D5) & ~0x01, 0x3D5);
597 }
598
599 #define crtc_unlock() write3X4(CRTVSyncEnd, read3X4(CRTVSyncEnd) & 0x7F)
600
601 /* Return flat panel's maximum x resolution */
602 static int __devinit get_nativex(void)
603 {
604 int x, y, tmp;
605
606 if (nativex)
607 return nativex;
608
609 tmp = (read3CE(VertStretch) >> 4) & 3;
610
611 switch (tmp) {
612 case 0:
613 x = 1280; y = 1024;
614 break;
615 case 2:
616 x = 1024; y = 768;
617 break;
618 case 3:
619 x = 800; y = 600;
620 break;
621 case 4:
622 x = 1400; y = 1050;
623 break;
624 case 1:
625 default:
626 x = 640; y = 480;
627 break;
628 }
629
630 output("%dx%d flat panel found\n", x, y);
631 return x;
632 }
633
634 /* Set pitch */
635 static void set_lwidth(int width)
636 {
637 write3X4(Offset, width & 0xFF);
638 write3X4(AddColReg,
639 (read3X4(AddColReg) & 0xCF) | ((width & 0x300) >> 4));
640 }
641
642 /* For resolutions smaller than FP resolution stretch */
643 static void screen_stretch(void)
644 {
645 if (chip_id != CYBERBLADEXPAi1)
646 write3CE(BiosReg, 0);
647 else
648 write3CE(BiosReg, 8);
649 write3CE(VertStretch, (read3CE(VertStretch) & 0x7C) | 1);
650 write3CE(HorStretch, (read3CE(HorStretch) & 0x7C) | 1);
651 }
652
653 /* For resolutions smaller than FP resolution center */
654 static void screen_center(void)
655 {
656 write3CE(VertStretch, (read3CE(VertStretch) & 0x7C) | 0x80);
657 write3CE(HorStretch, (read3CE(HorStretch) & 0x7C) | 0x80);
658 }
659
660 /* Address of first shown pixel in display memory */
661 static void set_screen_start(int base)
662 {
663 write3X4(StartAddrLow, base & 0xFF);
664 write3X4(StartAddrHigh, (base & 0xFF00) >> 8);
665 write3X4(CRTCModuleTest,
666 (read3X4(CRTCModuleTest) & 0xDF) | ((base & 0x10000) >> 11));
667 write3X4(CRTHiOrd,
668 (read3X4(CRTHiOrd) & 0xF8) | ((base & 0xE0000) >> 17));
669 }
670
671 /* Set dotclock frequency */
672 static void set_vclk(unsigned long freq)
673 {
674 int m, n, k;
675 unsigned long f, fi, d, di;
676 unsigned char lo = 0, hi = 0;
677
678 d = 20000;
679 for (k = 2; k >= 0; k--)
680 for (m = 0; m < 63; m++)
681 for (n = 0; n < 128; n++) {
682 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
683 if ((di = abs(fi - freq)) < d) {
684 d = di;
685 f = fi;
686 lo = n;
687 hi = (k << 6) | m;
688 }
689 if (fi > freq)
690 break;
691 }
692 if (chip3D) {
693 write3C4(ClockHigh, hi);
694 write3C4(ClockLow, lo);
695 } else {
696 outb(lo, 0x43C8);
697 outb(hi, 0x43C9);
698 }
699 debug("VCLK = %X %X\n", hi, lo);
700 }
701
702 /* Set number of lines for flat panels*/
703 static void set_number_of_lines(int lines)
704 {
705 int tmp = read3CE(CyberEnhance) & 0x8F;
706 if (lines > 1024)
707 tmp |= 0x50;
708 else if (lines > 768)
709 tmp |= 0x30;
710 else if (lines > 600)
711 tmp |= 0x20;
712 else if (lines > 480)
713 tmp |= 0x10;
714 write3CE(CyberEnhance, tmp);
715 }
716
717 /*
718 * If we see that FP is active we assume we have one.
719 * Otherwise we have a CRT display.User can override.
720 */
721 static unsigned int __devinit get_displaytype(void)
722 {
723 if (fp)
724 return DISPLAY_FP;
725 if (crt || !chipcyber)
726 return DISPLAY_CRT;
727 return (read3CE(FPConfig) & 0x10) ? DISPLAY_FP : DISPLAY_CRT;
728 }
729
730 /* Try detecting the video memory size */
731 static unsigned int __devinit get_memsize(void)
732 {
733 unsigned char tmp, tmp2;
734 unsigned int k;
735
736 /* If memory size provided by user */
737 if (memsize)
738 k = memsize * Kb;
739 else
740 switch (chip_id) {
741 case CYBER9525DVD:
742 k = 2560 * Kb;
743 break;
744 default:
745 tmp = read3X4(SPR) & 0x0F;
746 switch (tmp) {
747
748 case 0x01:
749 k = 512 * Kb;
750 break;
751 case 0x02:
752 k = 6 * Mb; /* XP */
753 break;
754 case 0x03:
755 k = 1 * Mb;
756 break;
757 case 0x04:
758 k = 8 * Mb;
759 break;
760 case 0x06:
761 k = 10 * Mb; /* XP */
762 break;
763 case 0x07:
764 k = 2 * Mb;
765 break;
766 case 0x08:
767 k = 12 * Mb; /* XP */
768 break;
769 case 0x0A:
770 k = 14 * Mb; /* XP */
771 break;
772 case 0x0C:
773 k = 16 * Mb; /* XP */
774 break;
775 case 0x0E: /* XP */
776
777 tmp2 = read3C4(0xC1);
778 switch (tmp2) {
779 case 0x00:
780 k = 20 * Mb;
781 break;
782 case 0x01:
783 k = 24 * Mb;
784 break;
785 case 0x10:
786 k = 28 * Mb;
787 break;
788 case 0x11:
789 k = 32 * Mb;
790 break;
791 default:
792 k = 1 * Mb;
793 break;
794 }
795 break;
796
797 case 0x0F:
798 k = 4 * Mb;
799 break;
800 default:
801 k = 1 * Mb;
802 break;
803 }
804 }
805
806 k -= memdiff * Kb;
807 output("framebuffer size = %d Kb\n", k / Kb);
808 return k;
809 }
810
811 /* See if we can handle the video mode described in var */
812 static int tridentfb_check_var(struct fb_var_screeninfo *var,
813 struct fb_info *info)
814 {
815 int bpp = var->bits_per_pixel;
816 debug("enter\n");
817
818 /* check color depth */
819 if (bpp == 24)
820 bpp = var->bits_per_pixel = 32;
821 /* check whether resolution fits on panel and in memory */
822 if (flatpanel && nativex && var->xres > nativex)
823 return -EINVAL;
824 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
825 return -EINVAL;
826
827 switch (bpp) {
828 case 8:
829 var->red.offset = 0;
830 var->green.offset = 0;
831 var->blue.offset = 0;
832 var->red.length = 6;
833 var->green.length = 6;
834 var->blue.length = 6;
835 break;
836 case 16:
837 var->red.offset = 11;
838 var->green.offset = 5;
839 var->blue.offset = 0;
840 var->red.length = 5;
841 var->green.length = 6;
842 var->blue.length = 5;
843 break;
844 case 32:
845 var->red.offset = 16;
846 var->green.offset = 8;
847 var->blue.offset = 0;
848 var->red.length = 8;
849 var->green.length = 8;
850 var->blue.length = 8;
851 break;
852 default:
853 return -EINVAL;
854 }
855 debug("exit\n");
856
857 return 0;
858
859 }
860
861 /* Pan the display */
862 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
863 struct fb_info *info)
864 {
865 unsigned int offset;
866
867 debug("enter\n");
868 offset = (var->xoffset + (var->yoffset * var->xres))
869 * var->bits_per_pixel / 32;
870 info->var.xoffset = var->xoffset;
871 info->var.yoffset = var->yoffset;
872 set_screen_start(offset);
873 debug("exit\n");
874 return 0;
875 }
876
877 #define shadowmode_on() write3CE(CyberControl, read3CE(CyberControl) | 0x81)
878 #define shadowmode_off() write3CE(CyberControl, read3CE(CyberControl) & 0x7E)
879
880 /* Set the hardware to the requested video mode */
881 static int tridentfb_set_par(struct fb_info *info)
882 {
883 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
884 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
885 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
886 struct fb_var_screeninfo *var = &info->var;
887 int bpp = var->bits_per_pixel;
888 unsigned char tmp;
889 unsigned long vclk;
890
891 debug("enter\n");
892 hdispend = var->xres / 8 - 1;
893 hsyncstart = (var->xres + var->right_margin) / 8;
894 hsyncend = var->hsync_len / 8;
895 htotal =
896 (var->xres + var->left_margin + var->right_margin +
897 var->hsync_len) / 8 - 10;
898 hblankstart = hdispend + 1;
899 hblankend = htotal + 5;
900
901 vdispend = var->yres - 1;
902 vsyncstart = var->yres + var->lower_margin;
903 vsyncend = var->vsync_len;
904 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
905 vblankstart = var->yres;
906 vblankend = vtotal + 2;
907
908 crtc_unlock();
909 write3CE(CyberControl, 8);
910
911 if (flatpanel && var->xres < nativex) {
912 /*
913 * on flat panels with native size larger
914 * than requested resolution decide whether
915 * we stretch or center
916 */
917 t_outb(0xEB, 0x3C2);
918
919 shadowmode_on();
920
921 if (center)
922 screen_center();
923 else if (stretch)
924 screen_stretch();
925
926 } else {
927 t_outb(0x2B, 0x3C2);
928 write3CE(CyberControl, 8);
929 }
930
931 /* vertical timing values */
932 write3X4(CRTVTotal, vtotal & 0xFF);
933 write3X4(CRTVDispEnd, vdispend & 0xFF);
934 write3X4(CRTVSyncStart, vsyncstart & 0xFF);
935 write3X4(CRTVSyncEnd, (vsyncend & 0x0F));
936 write3X4(CRTVBlankStart, vblankstart & 0xFF);
937 write3X4(CRTVBlankEnd, 0 /* p->vblankend & 0xFF */ );
938
939 /* horizontal timing values */
940 write3X4(CRTHTotal, htotal & 0xFF);
941 write3X4(CRTHDispEnd, hdispend & 0xFF);
942 write3X4(CRTHSyncStart, hsyncstart & 0xFF);
943 write3X4(CRTHSyncEnd, (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
944 write3X4(CRTHBlankStart, hblankstart & 0xFF);
945 write3X4(CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */ );
946
947 /* higher bits of vertical timing values */
948 tmp = 0x10;
949 if (vtotal & 0x100) tmp |= 0x01;
950 if (vdispend & 0x100) tmp |= 0x02;
951 if (vsyncstart & 0x100) tmp |= 0x04;
952 if (vblankstart & 0x100) tmp |= 0x08;
953
954 if (vtotal & 0x200) tmp |= 0x20;
955 if (vdispend & 0x200) tmp |= 0x40;
956 if (vsyncstart & 0x200) tmp |= 0x80;
957 write3X4(CRTOverflow, tmp);
958
959 tmp = read3X4(CRTHiOrd) | 0x08; /* line compare bit 10 */
960 if (vtotal & 0x400) tmp |= 0x80;
961 if (vblankstart & 0x400) tmp |= 0x40;
962 if (vsyncstart & 0x400) tmp |= 0x20;
963 if (vdispend & 0x400) tmp |= 0x10;
964 write3X4(CRTHiOrd, tmp);
965
966 tmp = 0;
967 if (htotal & 0x800) tmp |= 0x800 >> 11;
968 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
969 write3X4(HorizOverflow, tmp);
970
971 tmp = 0x40;
972 if (vblankstart & 0x200) tmp |= 0x20;
973 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
974 write3X4(CRTMaxScanLine, tmp);
975
976 write3X4(CRTLineCompare, 0xFF);
977 write3X4(CRTPRowScan, 0);
978 write3X4(CRTModeControl, 0xC3);
979
980 write3X4(LinearAddReg, 0x20); /* enable linear addressing */
981
982 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
983 write3X4(CRTCModuleTest, tmp); /* enable access extended memory */
984
985 write3X4(GraphEngReg, 0x80); /* enable GE for text acceleration */
986
987 #ifdef CONFIG_FB_TRIDENT_ACCEL
988 acc->init_accel(info->var.xres, bpp);
989 #endif
990
991 switch (bpp) {
992 case 8:
993 tmp = 0x00;
994 break;
995 case 16:
996 tmp = 0x05;
997 break;
998 case 24:
999 tmp = 0x29;
1000 break;
1001 case 32:
1002 tmp = 0x09;
1003 break;
1004 }
1005
1006 write3X4(PixelBusReg, tmp);
1007
1008 tmp = 0x10;
1009 if (chipcyber)
1010 tmp |= 0x20;
1011 write3X4(DRAMControl, tmp); /* both IO, linear enable */
1012
1013 write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40);
1014 write3X4(Performance, 0x92);
1015 write3X4(PCIReg, 0x07); /* MMIO & PCI read and write burst enable */
1016
1017 /* convert from picoseconds to kHz */
1018 vclk = PICOS2KHZ(info->var.pixclock);
1019 if (bpp == 32)
1020 vclk *= 2;
1021 set_vclk(vclk);
1022
1023 write3C4(0, 3);
1024 write3C4(1, 1); /* set char clock 8 dots wide */
1025 write3C4(2, 0x0F); /* enable 4 maps because needed in chain4 mode */
1026 write3C4(3, 0);
1027 write3C4(4, 0x0E); /* memory mode enable bitmaps ?? */
1028
1029 write3CE(MiscExtFunc, (bpp == 32) ? 0x1A : 0x12); /* divide clock by 2 if 32bpp */
1030 /* chain4 mode display and CPU path */
1031 write3CE(0x5, 0x40); /* no CGA compat, allow 256 col */
1032 write3CE(0x6, 0x05); /* graphics mode */
1033 write3CE(0x7, 0x0F); /* planes? */
1034
1035 if (chip_id == CYBERBLADEXPAi1) {
1036 /* This fixes snow-effect in 32 bpp */
1037 write3X4(CRTHSyncStart, 0x84);
1038 }
1039
1040 writeAttr(0x10, 0x41); /* graphics mode and support 256 color modes */
1041 writeAttr(0x12, 0x0F); /* planes */
1042 writeAttr(0x13, 0); /* horizontal pel panning */
1043
1044 /* colors */
1045 for (tmp = 0; tmp < 0x10; tmp++)
1046 writeAttr(tmp, tmp);
1047 readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
1048 t_outb(0x20, 0x3C0); /* enable attr */
1049
1050 switch (bpp) {
1051 case 8:
1052 tmp = 0;
1053 break;
1054 case 15:
1055 tmp = 0x10;
1056 break;
1057 case 16:
1058 tmp = 0x30;
1059 break;
1060 case 24:
1061 case 32:
1062 tmp = 0xD0;
1063 break;
1064 }
1065
1066 t_inb(0x3C8);
1067 t_inb(0x3C6);
1068 t_inb(0x3C6);
1069 t_inb(0x3C6);
1070 t_inb(0x3C6);
1071 t_outb(tmp, 0x3C6);
1072 t_inb(0x3C8);
1073
1074 if (flatpanel)
1075 set_number_of_lines(info->var.yres);
1076 set_lwidth(info->var.xres * bpp / (4 * 16));
1077 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1078 info->fix.line_length = info->var.xres * (bpp >> 3);
1079 info->cmap.len = (bpp == 8) ? 256 : 16;
1080 debug("exit\n");
1081 return 0;
1082 }
1083
1084 /* Set one color register */
1085 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1086 unsigned blue, unsigned transp,
1087 struct fb_info *info)
1088 {
1089 int bpp = info->var.bits_per_pixel;
1090
1091 if (regno >= info->cmap.len)
1092 return 1;
1093
1094 if (bpp == 8) {
1095 t_outb(0xFF, 0x3C6);
1096 t_outb(regno, 0x3C8);
1097
1098 t_outb(red >> 10, 0x3C9);
1099 t_outb(green >> 10, 0x3C9);
1100 t_outb(blue >> 10, 0x3C9);
1101
1102 } else if (regno < 16) {
1103 if (bpp == 16) { /* RGB 565 */
1104 u32 col;
1105
1106 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1107 ((blue & 0xF800) >> 11);
1108 col |= col << 16;
1109 ((u32 *)(info->pseudo_palette))[regno] = col;
1110 } else if (bpp == 32) /* ARGB 8888 */
1111 ((u32*)info->pseudo_palette)[regno] =
1112 ((transp & 0xFF00) << 16) |
1113 ((red & 0xFF00) << 8) |
1114 ((green & 0xFF00)) |
1115 ((blue & 0xFF00) >> 8);
1116 }
1117
1118 /* debug("exit\n"); */
1119 return 0;
1120 }
1121
1122 /* Try blanking the screen.For flat panels it does nothing */
1123 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1124 {
1125 unsigned char PMCont, DPMSCont;
1126
1127 debug("enter\n");
1128 if (flatpanel)
1129 return 0;
1130 t_outb(0x04, 0x83C8); /* Read DPMS Control */
1131 PMCont = t_inb(0x83C6) & 0xFC;
1132 DPMSCont = read3CE(PowerStatus) & 0xFC;
1133 switch (blank_mode) {
1134 case FB_BLANK_UNBLANK:
1135 /* Screen: On, HSync: On, VSync: On */
1136 case FB_BLANK_NORMAL:
1137 /* Screen: Off, HSync: On, VSync: On */
1138 PMCont |= 0x03;
1139 DPMSCont |= 0x00;
1140 break;
1141 case FB_BLANK_HSYNC_SUSPEND:
1142 /* Screen: Off, HSync: Off, VSync: On */
1143 PMCont |= 0x02;
1144 DPMSCont |= 0x01;
1145 break;
1146 case FB_BLANK_VSYNC_SUSPEND:
1147 /* Screen: Off, HSync: On, VSync: Off */
1148 PMCont |= 0x02;
1149 DPMSCont |= 0x02;
1150 break;
1151 case FB_BLANK_POWERDOWN:
1152 /* Screen: Off, HSync: Off, VSync: Off */
1153 PMCont |= 0x00;
1154 DPMSCont |= 0x03;
1155 break;
1156 }
1157
1158 write3CE(PowerStatus, DPMSCont);
1159 t_outb(4, 0x83C8);
1160 t_outb(PMCont, 0x83C6);
1161
1162 debug("exit\n");
1163
1164 /* let fbcon do a softblank for us */
1165 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1166 }
1167
1168 static struct fb_ops tridentfb_ops = {
1169 .owner = THIS_MODULE,
1170 .fb_setcolreg = tridentfb_setcolreg,
1171 .fb_pan_display = tridentfb_pan_display,
1172 .fb_blank = tridentfb_blank,
1173 .fb_check_var = tridentfb_check_var,
1174 .fb_set_par = tridentfb_set_par,
1175 .fb_fillrect = tridentfb_fillrect,
1176 .fb_copyarea = tridentfb_copyarea,
1177 .fb_imageblit = cfb_imageblit,
1178 };
1179
1180 static int __devinit trident_pci_probe(struct pci_dev * dev,
1181 const struct pci_device_id * id)
1182 {
1183 int err;
1184 unsigned char revision;
1185
1186 err = pci_enable_device(dev);
1187 if (err)
1188 return err;
1189
1190 chip_id = id->device;
1191
1192 if (chip_id == CYBERBLADEi1)
1193 output("*** Please do use cyblafb, Cyberblade/i1 support "
1194 "will soon be removed from tridentfb!\n");
1195
1196
1197 /* If PCI id is 0x9660 then further detect chip type */
1198
1199 if (chip_id == TGUI9660) {
1200 outb(RevisionID, 0x3C4);
1201 revision = inb(0x3C5);
1202
1203 switch (revision) {
1204 case 0x22:
1205 case 0x23:
1206 chip_id = CYBER9397;
1207 break;
1208 case 0x2A:
1209 chip_id = CYBER9397DVD;
1210 break;
1211 case 0x30:
1212 case 0x33:
1213 case 0x34:
1214 case 0x35:
1215 case 0x38:
1216 case 0x3A:
1217 case 0xB3:
1218 chip_id = CYBER9385;
1219 break;
1220 case 0x40 ... 0x43:
1221 chip_id = CYBER9382;
1222 break;
1223 case 0x4A:
1224 chip_id = CYBER9388;
1225 break;
1226 default:
1227 break;
1228 }
1229 }
1230
1231 chip3D = is3Dchip(chip_id);
1232 chipcyber = iscyber(chip_id);
1233
1234 if (is_xp(chip_id)) {
1235 acc = &accel_xp;
1236 } else if (is_blade(chip_id)) {
1237 acc = &accel_blade;
1238 } else {
1239 acc = &accel_image;
1240 }
1241
1242 /* acceleration is on by default for 3D chips */
1243 defaultaccel = chip3D && !noaccel;
1244
1245 fb_info.par = &default_par;
1246
1247 /* setup MMIO region */
1248 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1249 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1250
1251 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1252 debug("request_region failed!\n");
1253 return -1;
1254 }
1255
1256 default_par.io_virt = ioremap_nocache(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1257
1258 if (!default_par.io_virt) {
1259 debug("ioremap failed\n");
1260 err = -1;
1261 goto out_unmap1;
1262 }
1263
1264 enable_mmio();
1265
1266 /* setup framebuffer memory */
1267 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1268 tridentfb_fix.smem_len = get_memsize();
1269
1270 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1271 debug("request_mem_region failed!\n");
1272 disable_mmio();
1273 err = -1;
1274 goto out_unmap1;
1275 }
1276
1277 fb_info.screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1278 tridentfb_fix.smem_len);
1279
1280 if (!fb_info.screen_base) {
1281 debug("ioremap failed\n");
1282 err = -1;
1283 goto out_unmap2;
1284 }
1285
1286 output("%s board found\n", pci_name(dev));
1287 displaytype = get_displaytype();
1288
1289 if (flatpanel)
1290 nativex = get_nativex();
1291
1292 fb_info.fix = tridentfb_fix;
1293 fb_info.fbops = &tridentfb_ops;
1294
1295
1296 fb_info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1297 #ifdef CONFIG_FB_TRIDENT_ACCEL
1298 fb_info.flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1299 #endif
1300 fb_info.pseudo_palette = pseudo_pal;
1301
1302 if (!fb_find_mode(&default_var, &fb_info,
1303 mode_option, NULL, 0, NULL, bpp)) {
1304 err = -EINVAL;
1305 goto out_unmap2;
1306 }
1307 err = fb_alloc_cmap(&fb_info.cmap, 256, 0);
1308 if (err < 0)
1309 goto out_unmap2;
1310
1311 if (defaultaccel && acc)
1312 default_var.accel_flags |= FB_ACCELF_TEXT;
1313 else
1314 default_var.accel_flags &= ~FB_ACCELF_TEXT;
1315 default_var.activate |= FB_ACTIVATE_NOW;
1316 fb_info.var = default_var;
1317 fb_info.device = &dev->dev;
1318 if (register_framebuffer(&fb_info) < 0) {
1319 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1320 fb_dealloc_cmap(&fb_info.cmap);
1321 err = -EINVAL;
1322 goto out_unmap2;
1323 }
1324 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1325 fb_info.node, fb_info.fix.id, default_var.xres,
1326 default_var.yres, default_var.bits_per_pixel);
1327 return 0;
1328
1329 out_unmap2:
1330 if (fb_info.screen_base)
1331 iounmap(fb_info.screen_base);
1332 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1333 disable_mmio();
1334 out_unmap1:
1335 if (default_par.io_virt)
1336 iounmap(default_par.io_virt);
1337 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1338 return err;
1339 }
1340
1341 static void __devexit trident_pci_remove(struct pci_dev *dev)
1342 {
1343 struct tridentfb_par *par = (struct tridentfb_par*)fb_info.par;
1344 unregister_framebuffer(&fb_info);
1345 iounmap(par->io_virt);
1346 iounmap(fb_info.screen_base);
1347 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1348 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1349 }
1350
1351 /* List of boards that we are trying to support */
1352 static struct pci_device_id trident_devices[] = {
1353 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1354 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1355 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1356 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1357 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1358 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1359 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1360 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1361 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1362 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1363 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1364 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1365 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1366 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1367 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1368 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1369 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1370 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1371 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1372 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1373 {0,}
1374 };
1375
1376 MODULE_DEVICE_TABLE(pci, trident_devices);
1377
1378 static struct pci_driver tridentfb_pci_driver = {
1379 .name = "tridentfb",
1380 .id_table = trident_devices,
1381 .probe = trident_pci_probe,
1382 .remove = __devexit_p(trident_pci_remove)
1383 };
1384
1385 /*
1386 * Parse user specified options (`video=trident:')
1387 * example:
1388 * video=trident:800x600,bpp=16,noaccel
1389 */
1390 #ifndef MODULE
1391 static int __init tridentfb_setup(char *options)
1392 {
1393 char *opt;
1394 if (!options || !*options)
1395 return 0;
1396 while ((opt = strsep(&options, ",")) != NULL) {
1397 if (!*opt)
1398 continue;
1399 if (!strncmp(opt, "noaccel", 7))
1400 noaccel = 1;
1401 else if (!strncmp(opt, "fp", 2))
1402 displaytype = DISPLAY_FP;
1403 else if (!strncmp(opt, "crt", 3))
1404 displaytype = DISPLAY_CRT;
1405 else if (!strncmp(opt, "bpp=", 4))
1406 bpp = simple_strtoul(opt + 4, NULL, 0);
1407 else if (!strncmp(opt, "center", 6))
1408 center = 1;
1409 else if (!strncmp(opt, "stretch", 7))
1410 stretch = 1;
1411 else if (!strncmp(opt, "memsize=", 8))
1412 memsize = simple_strtoul(opt + 8, NULL, 0);
1413 else if (!strncmp(opt, "memdiff=", 8))
1414 memdiff = simple_strtoul(opt + 8, NULL, 0);
1415 else if (!strncmp(opt, "nativex=", 8))
1416 nativex = simple_strtoul(opt + 8, NULL, 0);
1417 else
1418 mode_option = opt;
1419 }
1420 return 0;
1421 }
1422 #endif
1423
1424 static int __init tridentfb_init(void)
1425 {
1426 #ifndef MODULE
1427 char *option = NULL;
1428
1429 if (fb_get_options("tridentfb", &option))
1430 return -ENODEV;
1431 tridentfb_setup(option);
1432 #endif
1433 output("Trident framebuffer %s initializing\n", VERSION);
1434 return pci_register_driver(&tridentfb_pci_driver);
1435 }
1436
1437 static void __exit tridentfb_exit(void)
1438 {
1439 pci_unregister_driver(&tridentfb_pci_driver);
1440 }
1441
1442 module_init(tridentfb_init);
1443 module_exit(tridentfb_exit);
1444
1445 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1446 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1447 MODULE_LICENSE("GPL");
1448
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