Linux 2.6.26-rc5
[linux-2.6/openmoko-kernel/knife-kernel.git] / include / asm-blackfin / mach-bf548 / mem_init.h
blobab0b863eee66c49a851daf24e90790eda302fdbf
1 /*
2 * File: include/asm-blackfin/mach-bf548/mem_init.h
3 * Based on:
4 * Author:
6 * Created:
7 * Description:
9 * Rev:
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32 #define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
33 #define DDR_CLK_HZ(x) (1000*1000*1000/x)
35 #if (CONFIG_MEM_MT46V32M16_6T)
36 #define DDR_SIZE DEVSZ_512
37 #define DDR_WIDTH DEVWD_16
38 #define DDR_MAX_tCK 13
40 #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
41 #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
42 #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
43 #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
44 #define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
46 #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
47 #define DDR_tWTR DDR_TWTR(1)
48 #define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
49 #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
50 #endif
52 #if (CONFIG_MEM_MT46V32M16_5B)
53 #define DDR_SIZE DEVSZ_512
54 #define DDR_WIDTH DEVWD_16
55 #define DDR_MAX_tCK 13
57 #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
58 #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
59 #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
60 #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
61 #define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
63 #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
64 #define DDR_tWTR DDR_TWTR(2)
65 #define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
66 #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
67 #endif
69 #if (CONFIG_MEM_GENERIC_BOARD)
70 #define DDR_SIZE DEVSZ_512
71 #define DDR_WIDTH DEVWD_16
72 #define DDR_MAX_tCK 13
74 #define DDR_tRCD DDR_TRCD(3)
75 #define DDR_tWTR DDR_TWTR(2)
76 #define DDR_tWR DDR_TWR(2)
77 #define DDR_tMRD DDR_TMRD(2)
78 #define DDR_tRP DDR_TRP(3)
79 #define DDR_tRAS DDR_TRAS(7)
80 #define DDR_tRC DDR_TRC(10)
81 #define DDR_tRFC DDR_TRFC(12)
82 #define DDR_tREFI DDR_TREFI(1288)
83 #endif
85 #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
86 # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
87 #elif(CONFIG_SCLK_HZ <= 133333333)
88 # define DDR_CL CL_2
89 #else
90 # error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
91 #endif
94 #define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
95 #define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
96 | DDR_tMRD | DDR_tWR | DDR_tRCD)
97 #define mem_DDRCTL2 DDR_CL
100 #if defined CONFIG_CLKIN_HALF
101 #define CLKIN_HALF 1
102 #else
103 #define CLKIN_HALF 0
104 #endif
106 #if defined CONFIG_PLL_BYPASS
107 #define PLL_BYPASS 1
108 #else
109 #define PLL_BYPASS 0
110 #endif
112 /***************************************Currently Not Being Used *********************************/
113 #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
114 #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
115 #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
116 #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
117 #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
119 #if (flash_EBIU_AMBCTL_TT > 3)
120 #define flash_EBIU_AMBCTL0_TT B0TT_4
121 #endif
122 #if (flash_EBIU_AMBCTL_TT == 3)
123 #define flash_EBIU_AMBCTL0_TT B0TT_3
124 #endif
125 #if (flash_EBIU_AMBCTL_TT == 2)
126 #define flash_EBIU_AMBCTL0_TT B0TT_2
127 #endif
128 #if (flash_EBIU_AMBCTL_TT < 2)
129 #define flash_EBIU_AMBCTL0_TT B0TT_1
130 #endif
132 #if (flash_EBIU_AMBCTL_ST > 3)
133 #define flash_EBIU_AMBCTL0_ST B0ST_4
134 #endif
135 #if (flash_EBIU_AMBCTL_ST == 3)
136 #define flash_EBIU_AMBCTL0_ST B0ST_3
137 #endif
138 #if (flash_EBIU_AMBCTL_ST == 2)
139 #define flash_EBIU_AMBCTL0_ST B0ST_2
140 #endif
141 #if (flash_EBIU_AMBCTL_ST < 2)
142 #define flash_EBIU_AMBCTL0_ST B0ST_1
143 #endif
145 #if (flash_EBIU_AMBCTL_HT > 2)
146 #define flash_EBIU_AMBCTL0_HT B0HT_3
147 #endif
148 #if (flash_EBIU_AMBCTL_HT == 2)
149 #define flash_EBIU_AMBCTL0_HT B0HT_2
150 #endif
151 #if (flash_EBIU_AMBCTL_HT == 1)
152 #define flash_EBIU_AMBCTL0_HT B0HT_1
153 #endif
154 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
155 #define flash_EBIU_AMBCTL0_HT B0HT_0
156 #endif
157 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
158 #define flash_EBIU_AMBCTL0_HT B0HT_1
159 #endif
161 #if (flash_EBIU_AMBCTL_WAT > 14)
162 #define flash_EBIU_AMBCTL0_WAT B0WAT_15
163 #endif
164 #if (flash_EBIU_AMBCTL_WAT == 14)
165 #define flash_EBIU_AMBCTL0_WAT B0WAT_14
166 #endif
167 #if (flash_EBIU_AMBCTL_WAT == 13)
168 #define flash_EBIU_AMBCTL0_WAT B0WAT_13
169 #endif
170 #if (flash_EBIU_AMBCTL_WAT == 12)
171 #define flash_EBIU_AMBCTL0_WAT B0WAT_12
172 #endif
173 #if (flash_EBIU_AMBCTL_WAT == 11)
174 #define flash_EBIU_AMBCTL0_WAT B0WAT_11
175 #endif
176 #if (flash_EBIU_AMBCTL_WAT == 10)
177 #define flash_EBIU_AMBCTL0_WAT B0WAT_10
178 #endif
179 #if (flash_EBIU_AMBCTL_WAT == 9)
180 #define flash_EBIU_AMBCTL0_WAT B0WAT_9
181 #endif
182 #if (flash_EBIU_AMBCTL_WAT == 8)
183 #define flash_EBIU_AMBCTL0_WAT B0WAT_8
184 #endif
185 #if (flash_EBIU_AMBCTL_WAT == 7)
186 #define flash_EBIU_AMBCTL0_WAT B0WAT_7
187 #endif
188 #if (flash_EBIU_AMBCTL_WAT == 6)
189 #define flash_EBIU_AMBCTL0_WAT B0WAT_6
190 #endif
191 #if (flash_EBIU_AMBCTL_WAT == 5)
192 #define flash_EBIU_AMBCTL0_WAT B0WAT_5
193 #endif
194 #if (flash_EBIU_AMBCTL_WAT == 4)
195 #define flash_EBIU_AMBCTL0_WAT B0WAT_4
196 #endif
197 #if (flash_EBIU_AMBCTL_WAT == 3)
198 #define flash_EBIU_AMBCTL0_WAT B0WAT_3
199 #endif
200 #if (flash_EBIU_AMBCTL_WAT == 2)
201 #define flash_EBIU_AMBCTL0_WAT B0WAT_2
202 #endif
203 #if (flash_EBIU_AMBCTL_WAT == 1)
204 #define flash_EBIU_AMBCTL0_WAT B0WAT_1
205 #endif
207 #if (flash_EBIU_AMBCTL_RAT > 14)
208 #define flash_EBIU_AMBCTL0_RAT B0RAT_15
209 #endif
210 #if (flash_EBIU_AMBCTL_RAT == 14)
211 #define flash_EBIU_AMBCTL0_RAT B0RAT_14
212 #endif
213 #if (flash_EBIU_AMBCTL_RAT == 13)
214 #define flash_EBIU_AMBCTL0_RAT B0RAT_13
215 #endif
216 #if (flash_EBIU_AMBCTL_RAT == 12)
217 #define flash_EBIU_AMBCTL0_RAT B0RAT_12
218 #endif
219 #if (flash_EBIU_AMBCTL_RAT == 11)
220 #define flash_EBIU_AMBCTL0_RAT B0RAT_11
221 #endif
222 #if (flash_EBIU_AMBCTL_RAT == 10)
223 #define flash_EBIU_AMBCTL0_RAT B0RAT_10
224 #endif
225 #if (flash_EBIU_AMBCTL_RAT == 9)
226 #define flash_EBIU_AMBCTL0_RAT B0RAT_9
227 #endif
228 #if (flash_EBIU_AMBCTL_RAT == 8)
229 #define flash_EBIU_AMBCTL0_RAT B0RAT_8
230 #endif
231 #if (flash_EBIU_AMBCTL_RAT == 7)
232 #define flash_EBIU_AMBCTL0_RAT B0RAT_7
233 #endif
234 #if (flash_EBIU_AMBCTL_RAT == 6)
235 #define flash_EBIU_AMBCTL0_RAT B0RAT_6
236 #endif
237 #if (flash_EBIU_AMBCTL_RAT == 5)
238 #define flash_EBIU_AMBCTL0_RAT B0RAT_5
239 #endif
240 #if (flash_EBIU_AMBCTL_RAT == 4)
241 #define flash_EBIU_AMBCTL0_RAT B0RAT_4
242 #endif
243 #if (flash_EBIU_AMBCTL_RAT == 3)
244 #define flash_EBIU_AMBCTL0_RAT B0RAT_3
245 #endif
246 #if (flash_EBIU_AMBCTL_RAT == 2)
247 #define flash_EBIU_AMBCTL0_RAT B0RAT_2
248 #endif
249 #if (flash_EBIU_AMBCTL_RAT == 1)
250 #define flash_EBIU_AMBCTL0_RAT B0RAT_1
251 #endif
253 #define flash_EBIU_AMBCTL0 \
254 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
255 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)