2 * File: include/asm-blackfin/mach-bf561/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 /* This file shoule be up to date with:
10 * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
13 #ifndef _MACH_ANOMALY_H_
14 #define _MACH_ANOMALY_H_
16 /* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
17 #if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
18 # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
21 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
22 #define ANOMALY_05000074 (1)
23 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
24 #define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
25 /* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
26 #define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
27 /* Testset instructions restricted to 32-bit aligned memory locations */
28 #define ANOMALY_05000120 (1)
29 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30 #define ANOMALY_05000122 (1)
31 /* Erroneous exception when enabling cache */
32 #define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
33 /* Signbits instruction not functional under certain conditions */
34 #define ANOMALY_05000127 (1)
35 /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
36 #define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
37 /* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
38 #define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
39 /* Stall in multi-unit DMA operations */
40 #define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
41 /* Allowing the SPORT RX FIFO to fill will cause an overflow */
42 #define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
43 /* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
44 #define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
45 /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
46 #define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
47 /* DMA and TESTSET conflict when both are accessing external memory */
48 #define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
49 /* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
50 #define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
51 /* MDMA may lose the first few words of a descriptor chain */
52 #define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
53 /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
54 #define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
55 /* IMDMA S1/D1 channel may stall */
56 #define ANOMALY_05000149 (1)
57 /* DMA engine may lose data due to incorrect handshaking */
58 #define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
59 /* DMA stalls when all three controllers read data from the same source */
60 #define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
61 /* Execution stall when executing in L2 and doing external accesses */
62 #define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
63 /* Frame Delay in SPORT Multichannel Mode */
64 #define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
65 /* SPORT TFS signal stays active in multichannel mode outside of valid channels */
66 #define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
67 /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
68 #define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
69 /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
70 #define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
71 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
72 #define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
73 /* A read from external memory may return a wrong value with data cache enabled */
74 #define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
75 /* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
76 #define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
77 /* DMEM_CONTROL<12> is not set on Reset */
78 #define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
79 /* SPORT transmit data is not gated by external frame sync in certain conditions */
80 #define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
81 /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
82 #define ANOMALY_05000166 (1)
83 /* Turning Serial Ports on with External Frame Syncs */
84 #define ANOMALY_05000167 (1)
85 /* SDRAM auto-refresh and subsequent Power Ups */
86 #define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
87 /* DATA CPLB page miss can result in lost write-through cache data writes */
88 #define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
89 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
90 #define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
91 /* DSPID register values incorrect */
92 #define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
93 /* DMA vs Core accesses to external memory */
94 #define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
95 /* Cache Fill Buffer Data lost */
96 #define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
97 /* Overlapping Sequencer and Memory Stalls */
98 #define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
99 /* Multiplication of (-1) by (-1) followed by an accumulator saturation */
100 #define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
101 /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
102 #define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
103 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
104 #define ANOMALY_05000180 (1)
105 /* Disabling the PPI resets the PPI configuration registers */
106 #define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
107 /* IMDMA does not operate to full speed for 600MHz and higher devices */
108 #define ANOMALY_05000182 (1)
109 /* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
110 #define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
111 /* PPI TX Mode with 2 External Frame Syncs */
112 #define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
113 /* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
114 #define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
115 /* IMDMA Corrupted Data after a Halt */
116 #define ANOMALY_05000187 (1)
117 /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
118 #define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
119 /* False Protection Exceptions */
120 #define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
121 /* PPI not functional at core voltage < 1Volt */
122 #define ANOMALY_05000190 (1)
123 /* PPI does not invert the Driving PPICLK edge in Transmit Modes */
124 #define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
125 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
126 #define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
127 /* Restarting SPORT in Specific Modes May Cause Data Corruption */
128 #define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
129 /* Failing MMR Accesses When Stalled by Preceding Memory Read */
130 #define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
131 /* Current DMA Address Shows Wrong Value During Carry Fix */
132 #define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
133 /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
134 #define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
135 /* Possible Infinite Stall with Specific Dual-DAG Situation */
136 #define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
137 /* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
138 #define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
139 /* Specific sequence that can cause DMA error or DMA stopping */
140 #define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
141 /* Recovery from "Brown-Out" Condition */
142 #define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
143 /* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
144 #define ANOMALY_05000208 (1)
145 /* Speed Path in Computational Unit Affects Certain Instructions */
146 #define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
147 /* UART TX Interrupt Masked Erroneously */
148 #define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
149 /* NMI Event at Boot Time Results in Unpredictable State */
150 #define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
151 /* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
152 #define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
153 /* Incorrect Pulse-Width of UART Start Bit */
154 #define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
155 /* Scratchpad Memory Bank Reads May Return Incorrect Data */
156 #define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
157 /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
158 #define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
159 /* UART STB Bit Incorrectly Affects Receiver Setting */
160 #define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
161 /* SPORT data transmit lines are incorrectly driven in multichannel mode */
162 #define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
163 /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
164 #define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
165 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
166 #define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
167 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
168 #define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
169 /* TESTSET operation forces stall on the other core */
170 #define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
171 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
172 #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
173 /* Exception Not Generated for MMR Accesses in Reserved Region */
174 #define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
175 /* Maximum External Clock Speed for Timers */
176 #define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
177 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
178 #define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
179 /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
180 #define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
181 /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
182 #define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
183 /* ICPLB_STATUS MMR Register May Be Corrupted */
184 #define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
185 /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
186 #define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
187 /* Stores To Data Cache May Be Lost */
188 #define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
189 /* Hardware Loop Corrupted When Taking an ICPLB Exception */
190 #define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
191 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
192 #define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
193 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
194 #define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
195 /* IMDMA destination IRQ status must be read prior to using IMDMA */
196 #define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
197 /* IMDMA may corrupt data under certain conditions */
198 #define ANOMALY_05000267 (1)
199 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
200 #define ANOMALY_05000269 (1)
201 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
202 #define ANOMALY_05000270 (1)
203 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
204 #define ANOMALY_05000272 (1)
205 /* Data cache write back to external synchronous memory may be lost */
206 #define ANOMALY_05000274 (1)
207 /* PPI Timing and Sampling Information Updates */
208 #define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210 #define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
211 /* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
212 #define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
213 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
214 #define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
215 /* False Hardware Error Exception When ISR Context Is Not Restored */
216 #define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
217 /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
218 #define ANOMALY_05000283 (1)
219 /* A read will receive incorrect data under certain conditions */
220 #define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
221 /* SPORTs May Receive Bad Data If FIFOs Fill Up */
222 #define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
223 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
224 #define ANOMALY_05000301 (1)
225 /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
226 #define ANOMALY_05000302 (1)
227 /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
228 #define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
229 /* SCKELOW Bit Does Not Maintain State Through Hibernate */
230 #define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
231 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
232 #define ANOMALY_05000310 (1)
233 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
234 #define ANOMALY_05000312 (1)
235 /* PPI Is Level-Sensitive on First Transfer */
236 #define ANOMALY_05000313 (1)
237 /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
238 #define ANOMALY_05000315 (1)
239 /* PF2 Output Remains Asserted After SPI Master Boot */
240 #define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
241 /* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
242 #define ANOMALY_05000323 (1)
243 /* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
244 #define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
245 /* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
246 #define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
247 /* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
248 #define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
249 /* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
250 #define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
251 /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
252 #define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253 /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254 #define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
255 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
256 #define ANOMALY_05000357 (1)
257 /* Conflicting Column Address Widths Causes SDRAM Errors */
258 #define ANOMALY_05000362 (1)
259 /* UART Break Signal Issues */
260 #define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
261 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
262 #define ANOMALY_05000366 (1)
263 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
264 #define ANOMALY_05000371 (1)
265 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266 #define ANOMALY_05000403 (1)
268 /* Anomalies that don't exist on this proc */
269 #define ANOMALY_05000158 (0)
270 #define ANOMALY_05000183 (0)
271 #define ANOMALY_05000273 (0)
272 #define ANOMALY_05000311 (0)