Linux 2.6.26-rc5
[linux-2.6/openmoko-kernel/knife-kernel.git] / include / asm-blackfin / mach-bf561 / mem_init.h
blob439a5895b346d3c0a8b31bd6aa3ff4ccd771bee7
1 /*
2 * File: include/asm-blackfin/mach-bf561/mem_init.h
3 * Based on:
4 * Author:
6 * Created:
7 * Description:
9 * Rev:
11 * Modified:
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
32 #if (CONFIG_SCLK_HZ > 119402985)
33 #define SDRAM_tRP TRP_2
34 #define SDRAM_tRP_num 2
35 #define SDRAM_tRAS TRAS_7
36 #define SDRAM_tRAS_num 7
37 #define SDRAM_tRCD TRCD_2
38 #define SDRAM_tWR TWR_2
39 #endif
40 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
41 #define SDRAM_tRP TRP_2
42 #define SDRAM_tRP_num 2
43 #define SDRAM_tRAS TRAS_6
44 #define SDRAM_tRAS_num 6
45 #define SDRAM_tRCD TRCD_2
46 #define SDRAM_tWR TWR_2
47 #endif
48 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
49 #define SDRAM_tRP TRP_2
50 #define SDRAM_tRP_num 2
51 #define SDRAM_tRAS TRAS_5
52 #define SDRAM_tRAS_num 5
53 #define SDRAM_tRCD TRCD_2
54 #define SDRAM_tWR TWR_2
55 #endif
56 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
57 #define SDRAM_tRP TRP_2
58 #define SDRAM_tRP_num 2
59 #define SDRAM_tRAS TRAS_4
60 #define SDRAM_tRAS_num 4
61 #define SDRAM_tRCD TRCD_2
62 #define SDRAM_tWR TWR_2
63 #endif
64 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
65 #define SDRAM_tRP TRP_2
66 #define SDRAM_tRP_num 2
67 #define SDRAM_tRAS TRAS_3
68 #define SDRAM_tRAS_num 3
69 #define SDRAM_tRCD TRCD_2
70 #define SDRAM_tWR TWR_2
71 #endif
72 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
73 #define SDRAM_tRP TRP_1
74 #define SDRAM_tRP_num 1
75 #define SDRAM_tRAS TRAS_4
76 #define SDRAM_tRAS_num 3
77 #define SDRAM_tRCD TRCD_1
78 #define SDRAM_tWR TWR_2
79 #endif
80 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
81 #define SDRAM_tRP TRP_1
82 #define SDRAM_tRP_num 1
83 #define SDRAM_tRAS TRAS_3
84 #define SDRAM_tRAS_num 3
85 #define SDRAM_tRCD TRCD_1
86 #define SDRAM_tWR TWR_2
87 #endif
88 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
89 #define SDRAM_tRP TRP_1
90 #define SDRAM_tRP_num 1
91 #define SDRAM_tRAS TRAS_2
92 #define SDRAM_tRAS_num 2
93 #define SDRAM_tRCD TRCD_1
94 #define SDRAM_tWR TWR_2
95 #endif
96 #if (CONFIG_SCLK_HZ <= 29850746)
97 #define SDRAM_tRP TRP_1
98 #define SDRAM_tRP_num 1
99 #define SDRAM_tRAS TRAS_1
100 #define SDRAM_tRAS_num 1
101 #define SDRAM_tRCD TRCD_1
102 #define SDRAM_tWR TWR_2
103 #endif
104 #endif
106 #if (CONFIG_MEM_MT48LC16M16A2TG_75)
107 /*SDRAM INFORMATION: */
108 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
109 #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
110 #define SDRAM_CL CL_3
111 #endif
113 #if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114 /*SDRAM INFORMATION: */
115 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
116 #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
117 #define SDRAM_CL CL_3
118 #endif
120 #if (CONFIG_MEM_MT48LC8M32B2B5_7)
121 /*SDRAM INFORMATION: */
122 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
123 #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124 #define SDRAM_CL CL_3
125 #endif
127 #if (CONFIG_MEM_GENERIC_BOARD)
128 /*SDRAM INFORMATION: Modify this for your board */
129 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
130 #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
131 #define SDRAM_CL CL_3
132 #endif
134 #if (CONFIG_MEM_SIZE == 128)
135 #define SDRAM_SIZE EB0_SZ_128
136 #endif
137 #if (CONFIG_MEM_SIZE == 64)
138 #define SDRAM_SIZE EB0_SZ_64
139 #endif
140 #if ( CONFIG_MEM_SIZE == 32)
141 #define SDRAM_SIZE EB0_SZ_32
142 #endif
143 #if (CONFIG_MEM_SIZE == 16)
144 #define SDRAM_SIZE EB0_SZ_16
145 #endif
146 #if (CONFIG_MEM_ADD_WIDTH == 11)
147 #define SDRAM_WIDTH EB0_CAW_11
148 #endif
149 #if (CONFIG_MEM_ADD_WIDTH == 10)
150 #define SDRAM_WIDTH EB0_CAW_10
151 #endif
152 #if (CONFIG_MEM_ADD_WIDTH == 9)
153 #define SDRAM_WIDTH EB0_CAW_9
154 #endif
155 #if (CONFIG_MEM_ADD_WIDTH == 8)
156 #define SDRAM_WIDTH EB0_CAW_8
157 #endif
159 #define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EB0_E)
161 /* Equation from section 17 (p17-46) of BF533 HRM */
162 #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
164 /* Enable SCLK Out */
165 #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
167 #if defined CONFIG_CLKIN_HALF
168 #define CLKIN_HALF 1
169 #else
170 #define CLKIN_HALF 0
171 #endif
173 #if defined CONFIG_PLL_BYPASS
174 #define PLL_BYPASS 1
175 #else
176 #define PLL_BYPASS 0
177 #endif
179 /***************************************Currently Not Being Used *********************************/
180 #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
181 #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
182 #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
183 #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
184 #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
186 #if (flash_EBIU_AMBCTL_TT > 3)
187 #define flash_EBIU_AMBCTL0_TT B0TT_4
188 #endif
189 #if (flash_EBIU_AMBCTL_TT == 3)
190 #define flash_EBIU_AMBCTL0_TT B0TT_3
191 #endif
192 #if (flash_EBIU_AMBCTL_TT == 2)
193 #define flash_EBIU_AMBCTL0_TT B0TT_2
194 #endif
195 #if (flash_EBIU_AMBCTL_TT < 2)
196 #define flash_EBIU_AMBCTL0_TT B0TT_1
197 #endif
199 #if (flash_EBIU_AMBCTL_ST > 3)
200 #define flash_EBIU_AMBCTL0_ST B0ST_4
201 #endif
202 #if (flash_EBIU_AMBCTL_ST == 3)
203 #define flash_EBIU_AMBCTL0_ST B0ST_3
204 #endif
205 #if (flash_EBIU_AMBCTL_ST == 2)
206 #define flash_EBIU_AMBCTL0_ST B0ST_2
207 #endif
208 #if (flash_EBIU_AMBCTL_ST < 2)
209 #define flash_EBIU_AMBCTL0_ST B0ST_1
210 #endif
212 #if (flash_EBIU_AMBCTL_HT > 2)
213 #define flash_EBIU_AMBCTL0_HT B0HT_3
214 #endif
215 #if (flash_EBIU_AMBCTL_HT == 2)
216 #define flash_EBIU_AMBCTL0_HT B0HT_2
217 #endif
218 #if (flash_EBIU_AMBCTL_HT == 1)
219 #define flash_EBIU_AMBCTL0_HT B0HT_1
220 #endif
221 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
222 #define flash_EBIU_AMBCTL0_HT B0HT_0
223 #endif
224 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
225 #define flash_EBIU_AMBCTL0_HT B0HT_1
226 #endif
228 #if (flash_EBIU_AMBCTL_WAT > 14)
229 #define flash_EBIU_AMBCTL0_WAT B0WAT_15
230 #endif
231 #if (flash_EBIU_AMBCTL_WAT == 14)
232 #define flash_EBIU_AMBCTL0_WAT B0WAT_14
233 #endif
234 #if (flash_EBIU_AMBCTL_WAT == 13)
235 #define flash_EBIU_AMBCTL0_WAT B0WAT_13
236 #endif
237 #if (flash_EBIU_AMBCTL_WAT == 12)
238 #define flash_EBIU_AMBCTL0_WAT B0WAT_12
239 #endif
240 #if (flash_EBIU_AMBCTL_WAT == 11)
241 #define flash_EBIU_AMBCTL0_WAT B0WAT_11
242 #endif
243 #if (flash_EBIU_AMBCTL_WAT == 10)
244 #define flash_EBIU_AMBCTL0_WAT B0WAT_10
245 #endif
246 #if (flash_EBIU_AMBCTL_WAT == 9)
247 #define flash_EBIU_AMBCTL0_WAT B0WAT_9
248 #endif
249 #if (flash_EBIU_AMBCTL_WAT == 8)
250 #define flash_EBIU_AMBCTL0_WAT B0WAT_8
251 #endif
252 #if (flash_EBIU_AMBCTL_WAT == 7)
253 #define flash_EBIU_AMBCTL0_WAT B0WAT_7
254 #endif
255 #if (flash_EBIU_AMBCTL_WAT == 6)
256 #define flash_EBIU_AMBCTL0_WAT B0WAT_6
257 #endif
258 #if (flash_EBIU_AMBCTL_WAT == 5)
259 #define flash_EBIU_AMBCTL0_WAT B0WAT_5
260 #endif
261 #if (flash_EBIU_AMBCTL_WAT == 4)
262 #define flash_EBIU_AMBCTL0_WAT B0WAT_4
263 #endif
264 #if (flash_EBIU_AMBCTL_WAT == 3)
265 #define flash_EBIU_AMBCTL0_WAT B0WAT_3
266 #endif
267 #if (flash_EBIU_AMBCTL_WAT == 2)
268 #define flash_EBIU_AMBCTL0_WAT B0WAT_2
269 #endif
270 #if (flash_EBIU_AMBCTL_WAT == 1)
271 #define flash_EBIU_AMBCTL0_WAT B0WAT_1
272 #endif
274 #if (flash_EBIU_AMBCTL_RAT > 14)
275 #define flash_EBIU_AMBCTL0_RAT B0RAT_15
276 #endif
277 #if (flash_EBIU_AMBCTL_RAT == 14)
278 #define flash_EBIU_AMBCTL0_RAT B0RAT_14
279 #endif
280 #if (flash_EBIU_AMBCTL_RAT == 13)
281 #define flash_EBIU_AMBCTL0_RAT B0RAT_13
282 #endif
283 #if (flash_EBIU_AMBCTL_RAT == 12)
284 #define flash_EBIU_AMBCTL0_RAT B0RAT_12
285 #endif
286 #if (flash_EBIU_AMBCTL_RAT == 11)
287 #define flash_EBIU_AMBCTL0_RAT B0RAT_11
288 #endif
289 #if (flash_EBIU_AMBCTL_RAT == 10)
290 #define flash_EBIU_AMBCTL0_RAT B0RAT_10
291 #endif
292 #if (flash_EBIU_AMBCTL_RAT == 9)
293 #define flash_EBIU_AMBCTL0_RAT B0RAT_9
294 #endif
295 #if (flash_EBIU_AMBCTL_RAT == 8)
296 #define flash_EBIU_AMBCTL0_RAT B0RAT_8
297 #endif
298 #if (flash_EBIU_AMBCTL_RAT == 7)
299 #define flash_EBIU_AMBCTL0_RAT B0RAT_7
300 #endif
301 #if (flash_EBIU_AMBCTL_RAT == 6)
302 #define flash_EBIU_AMBCTL0_RAT B0RAT_6
303 #endif
304 #if (flash_EBIU_AMBCTL_RAT == 5)
305 #define flash_EBIU_AMBCTL0_RAT B0RAT_5
306 #endif
307 #if (flash_EBIU_AMBCTL_RAT == 4)
308 #define flash_EBIU_AMBCTL0_RAT B0RAT_4
309 #endif
310 #if (flash_EBIU_AMBCTL_RAT == 3)
311 #define flash_EBIU_AMBCTL0_RAT B0RAT_3
312 #endif
313 #if (flash_EBIU_AMBCTL_RAT == 2)
314 #define flash_EBIU_AMBCTL0_RAT B0RAT_2
315 #endif
316 #if (flash_EBIU_AMBCTL_RAT == 1)
317 #define flash_EBIU_AMBCTL0_RAT B0RAT_1
318 #endif
320 #define flash_EBIU_AMBCTL0 \
321 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
322 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)