include/asm-x86/mpspec_def.h

   1 #ifndef __ASM_MPSPEC_DEF_H
   2 #define __ASM_MPSPEC_DEF_H
   3
   4 /*
   5  * Structure definitions for SMP machines following the
   6  * Intel Multiprocessing Specification 1.1 and 1.4.
   7  */
   8
   9 /*
  10  * This tag identifies where the SMP configuration
  11  * information is.
  12  */
  13
  14 #define SMP_MAGIC_IDENT (('_'<<24) | ('P'<<16) | ('M'<<8) | '_')
  15
  16 #ifdef CONFIG_X86_32
  17 # define MAX_MPC_ENTRY 1024
  18 # define MAX_APICS      256
  19 #else
  20 /*
  21  * A maximum of 255 APICs with the current APIC ID architecture.
  22  */
  23 # define MAX_APICS 255
  24 #endif
  25
  26 struct intel_mp_floating {
  27         char mpf_signature[4];          /* "_MP_"                       */
  28         unsigned int mpf_physptr;       /* Configuration table address  */
  29         unsigned char mpf_length;       /* Our length (paragraphs)      */
  30         unsigned char mpf_specification;/* Specification version        */
  31         unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
  32         unsigned char mpf_feature1;     /* Standard or configuration ?  */
  33         unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
  34         unsigned char mpf_feature3;     /* Unused (0)                   */
  35         unsigned char mpf_feature4;     /* Unused (0)                   */
  36         unsigned char mpf_feature5;     /* Unused (0)                   */
  37 };
  38
  39 #define MPC_SIGNATURE "PCMP"
  40
  41 struct mp_config_table {
  42         char mpc_signature[4];
  43         unsigned short mpc_length;      /* Size of table */
  44         char mpc_spec;                  /* 0x01 */
  45         char mpc_checksum;
  46         char mpc_oem[8];
  47         char mpc_productid[12];
  48         unsigned int mpc_oemptr;        /* 0 if not present */
  49         unsigned short mpc_oemsize;     /* 0 if not present */
  50         unsigned short mpc_oemcount;
  51         unsigned int mpc_lapic; /* APIC address */
  52         unsigned int reserved;
  53 };
  54
  55 /* Followed by entries */
  56
  57 #define MP_PROCESSOR            0
  58 #define MP_BUS                  1
  59 #define MP_IOAPIC               2
  60 #define MP_INTSRC               3
  61 #define MP_LINTSRC              4
  62 /* Used by IBM NUMA-Q to describe node locality */
  63 #define MP_TRANSLATION          192
  64
  65 #define CPU_ENABLED             1       /* Processor is available */
  66 #define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
  67
  68 #define CPU_STEPPING_MASK       0x000F
  69 #define CPU_MODEL_MASK          0x00F0
  70 #define CPU_FAMILY_MASK         0x0F00
  71
  72 struct mpc_config_processor {
  73         unsigned char mpc_type;
  74         unsigned char mpc_apicid;       /* Local APIC number */
  75         unsigned char mpc_apicver;      /* Its versions */
  76         unsigned char mpc_cpuflag;
  77         unsigned int mpc_cpufeature;
  78         unsigned int mpc_featureflag;   /* CPUID feature value */
  79         unsigned int mpc_reserved[2];
  80 };
  81
  82 struct mpc_config_bus {
  83         unsigned char mpc_type;
  84         unsigned char mpc_busid;
  85         unsigned char mpc_bustype[6];
  86 };
  87
  88 /* List of Bus Type string values, Intel MP Spec. */
  89 #define BUSTYPE_EISA    "EISA"
  90 #define BUSTYPE_ISA     "ISA"
  91 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
  92 #define BUSTYPE_MCA     "MCA"
  93 #define BUSTYPE_VL      "VL"            /* Local bus */
  94 #define BUSTYPE_PCI     "PCI"
  95 #define BUSTYPE_PCMCIA  "PCMCIA"
  96 #define BUSTYPE_CBUS    "CBUS"
  97 #define BUSTYPE_CBUSII  "CBUSII"
  98 #define BUSTYPE_FUTURE  "FUTURE"
  99 #define BUSTYPE_MBI     "MBI"
 100 #define BUSTYPE_MBII    "MBII"
 101 #define BUSTYPE_MPI     "MPI"
 102 #define BUSTYPE_MPSA    "MPSA"
 103 #define BUSTYPE_NUBUS   "NUBUS"
 104 #define BUSTYPE_TC      "TC"
 105 #define BUSTYPE_VME     "VME"
 106 #define BUSTYPE_XPRESS  "XPRESS"
 107
 108 #define MPC_APIC_USABLE         0x01
 109
 110 struct mpc_config_ioapic {
 111         unsigned char mpc_type;
 112         unsigned char mpc_apicid;
 113         unsigned char mpc_apicver;
 114         unsigned char mpc_flags;
 115         unsigned int mpc_apicaddr;
 116 };
 117
 118 struct mpc_config_intsrc {
 119         unsigned char mpc_type;
 120         unsigned char mpc_irqtype;
 121         unsigned short mpc_irqflag;
 122         unsigned char mpc_srcbus;
 123         unsigned char mpc_srcbusirq;
 124         unsigned char mpc_dstapic;
 125         unsigned char mpc_dstirq;
 126 };
 127
 128 enum mp_irq_source_types {
 129         mp_INT = 0,
 130         mp_NMI = 1,
 131         mp_SMI = 2,
 132         mp_ExtINT = 3
 133 };
 134
 135 #define MP_IRQDIR_DEFAULT       0
 136 #define MP_IRQDIR_HIGH          1
 137 #define MP_IRQDIR_LOW           3
 138
 139 #define MP_APIC_ALL     0xFF
 140
 141 struct mpc_config_lintsrc {
 142         unsigned char mpc_type;
 143         unsigned char mpc_irqtype;
 144         unsigned short mpc_irqflag;
 145         unsigned char mpc_srcbusid;
 146         unsigned char mpc_srcbusirq;
 147         unsigned char mpc_destapic;
 148         unsigned char mpc_destapiclint;
 149 };
 150
 151 #define MPC_OEM_SIGNATURE "_OEM"
 152
 153 struct mp_config_oemtable {
 154         char oem_signature[4];
 155         unsigned short oem_length;      /* Size of table */
 156         char  oem_rev;                  /* 0x01 */
 157         char  oem_checksum;
 158         char  mpc_oem[8];
 159 };
 160
 161 /*
 162  *      Default configurations
 163  *
 164  *      1       2 CPU ISA 82489DX
 165  *      2       2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
 166  *      3       2 CPU EISA 82489DX
 167  *      4       2 CPU MCA 82489DX
 168  *      5       2 CPU ISA+PCI
 169  *      6       2 CPU EISA+PCI
 170  *      7       2 CPU MCA+PCI
 171  */
 172
 173 enum mp_bustype {
 174         MP_BUS_ISA = 1,
 175         MP_BUS_EISA,
 176         MP_BUS_PCI,
 177         MP_BUS_MCA,
 178 };
 179 #endif