include/asm-arm/arch-mxc/board-mx31ads.h

   1 /*
   2  * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
  12 #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
  13
  14 /*!
  15  * @name PBC Controller parameters
  16  */
  17 /*! @{ */
  18 /*!
  19  * Base address of PBC controller
  20  */
  21 #define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
  22 /* Offsets for the PBC Controller register */
  23 /*!
  24  * PBC Board status register offset
  25  */
  26 #define PBC_BSTAT               0x000002
  27 /*!
  28  * PBC Board control register 1 set address.
  29  */
  30 #define PBC_BCTRL1_SET          0x000004
  31 /*!
  32  * PBC Board control register 1 clear address.
  33  */
  34 #define PBC_BCTRL1_CLEAR        0x000006
  35 /*!
  36  * PBC Board control register 2 set address.
  37  */
  38 #define PBC_BCTRL2_SET          0x000008
  39 /*!
  40  * PBC Board control register 2 clear address.
  41  */
  42 #define PBC_BCTRL2_CLEAR        0x00000A
  43 /*!
  44  * PBC Board control register 3 set address.
  45  */
  46 #define PBC_BCTRL3_SET          0x00000C
  47 /*!
  48  * PBC Board control register 3 clear address.
  49  */
  50 #define PBC_BCTRL3_CLEAR        0x00000E
  51 /*!
  52  * PBC Board control register 4 set address.
  53  */
  54 #define PBC_BCTRL4_SET          0x000010
  55 /*!
  56  * PBC Board control register 4 clear address.
  57  */
  58 #define PBC_BCTRL4_CLEAR        0x000012
  59 /*!
  60  * PBC Board status register 1.
  61  */
  62 #define PBC_BSTAT1              0x000014
  63 /*!
  64  * PBC Board interrupt status register.
  65  */
  66 #define PBC_INTSTATUS           0x000016
  67 /*!
  68  * PBC Board interrupt current status register.
  69  */
  70 #define PBC_INTCURR_STATUS      0x000018
  71 /*!
  72  * PBC Interrupt mask register set address.
  73  */
  74 #define PBC_INTMASK_SET         0x00001A
  75 /*!
  76  * PBC Interrupt mask register clear address.
  77  */
  78 #define PBC_INTMASK_CLEAR       0x00001C
  79
  80 /*!
  81  * External UART A.
  82  */
  83 #define PBC_SC16C652_UARTA      0x010000
  84 /*!
  85  * External UART B.
  86  */
  87 #define PBC_SC16C652_UARTB      0x010010
  88 /*!
  89  * Ethernet Controller IO base address.
  90  */
  91 #define PBC_CS8900A_IOBASE      0x020000
  92 /*!
  93  * Ethernet Controller Memory base address.
  94  */
  95 #define PBC_CS8900A_MEMBASE     0x021000
  96 /*!
  97  * Ethernet Controller DMA base address.
  98  */
  99 #define PBC_CS8900A_DMABASE     0x022000
 100 /*!
 101  * External chip select 0.
 102  */
 103 #define PBC_XCS0                0x040000
 104 /*!
 105  * LCD Display enable.
 106  */
 107 #define PBC_LCD_EN_B            0x060000
 108 /*!
 109  * Code test debug enable.
 110  */
 111 #define PBC_CODE_B              0x070000
 112 /*!
 113  * PSRAM memory select.
 114  */
 115 #define PBC_PSRAM_B             0x5000000
 116
 117 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
 118 #define PBC_INTCURR_STATUS_REG  (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
 119 #define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
 120 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
 121 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 122
 123 #define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
 124 #define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
 125 #define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
 126 #define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
 127 #define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
 128 #define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
 129 #define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
 130 #define EXPIO_INT_RES7          (MXC_EXP_IO_BASE + 7)
 131 #define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
 132 #define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
 133 #define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
 134 #define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
 135 #define EXPIO_INT_SYNTH_IRQ     (MXC_EXP_IO_BASE + 12)
 136 #define EXPIO_INT_CE_INT1       (MXC_EXP_IO_BASE + 13)
 137 #define EXPIO_INT_CE_INT2       (MXC_EXP_IO_BASE + 14)
 138 #define EXPIO_INT_RES15         (MXC_EXP_IO_BASE + 15)
 139
 140 #define MXC_MAX_EXP_IO_LINES    16
 141
 142 #endif                          /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */