| blob | 745aa841b31ae8824739edc5678a8b4141650db2 |
1 /*
2 * linux/include/asm-arm/arch-versatile/irqs.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
22 #include <asm/arch/platform.h>
24 /*
25 * IRQ interrupts definitions are the same the INT definitions
26 * held within platform.h
27 */
28 #define IRQ_VIC_START 0
29 #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT)
30 #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT)
31 #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx)
32 #define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx)
33 #define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1)
34 #define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3)
35 #define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0)
36 #define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1)
37 #define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2)
38 #define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3)
39 #define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT)
40 #define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT)
41 #define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0)
42 #define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1)
43 #define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2)
44 #define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT)
45 #define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT)
46 #define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT)
47 #define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT)
48 #define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT)
49 #define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT)
50 #define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21)
51 #define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22)
52 #define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23)
53 #define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24)
54 #define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25)
55 #define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26)
56 #define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27)
57 #define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28)
58 #define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29)
59 #define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30)
60 #define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31)
61 #define IRQ_VIC_END (IRQ_VIC_START + 31)
63 #define IRQMASK_WDOGINT INTMASK_WDOGINT
64 #define IRQMASK_SOFTINT INTMASK_SOFTINT
65 #define IRQMASK_COMMRx INTMASK_COMMRx
66 #define IRQMASK_COMMTx INTMASK_COMMTx
67 #define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
68 #define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
69 #define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
70 #define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
71 #define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
72 #define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
73 #define IRQMASK_RTCINT INTMASK_RTCINT
74 #define IRQMASK_SSPINT INTMASK_SSPINT
75 #define IRQMASK_UARTINT0 INTMASK_UARTINT0
76 #define IRQMASK_UARTINT1 INTMASK_UARTINT1
77 #define IRQMASK_UARTINT2 INTMASK_UARTINT2
78 #define IRQMASK_SCIINT INTMASK_SCIINT
79 #define IRQMASK_CLCDINT INTMASK_CLCDINT
80 #define IRQMASK_DMAINT INTMASK_DMAINT
81 #define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
82 #define IRQMASK_MBXINT INTMASK_MBXINT
83 #define IRQMASK_GNDINT INTMASK_GNDINT
84 #define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21
85 #define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22
86 #define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23
87 #define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24
88 #define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25
89 #define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26
90 #define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27
91 #define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28
92 #define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29
93 #define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30
94 #define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31
96 /*
97 * FIQ interrupts definitions are the same the INT definitions.
98 */
99 #define FIQ_WDOGINT INT_WDOGINT
100 #define FIQ_SOFTINT INT_SOFTINT
101 #define FIQ_COMMRx INT_COMMRx
102 #define FIQ_COMMTx INT_COMMTx
103 #define FIQ_TIMERINT0_1 INT_TIMERINT0_1
104 #define FIQ_TIMERINT2_3 INT_TIMERINT2_3
105 #define FIQ_GPIOINT0 INT_GPIOINT0
106 #define FIQ_GPIOINT1 INT_GPIOINT1
107 #define FIQ_GPIOINT2 INT_GPIOINT2
108 #define FIQ_GPIOINT3 INT_GPIOINT3
109 #define FIQ_RTCINT INT_RTCINT
110 #define FIQ_SSPINT INT_SSPINT
111 #define FIQ_UARTINT0 INT_UARTINT0
112 #define FIQ_UARTINT1 INT_UARTINT1
113 #define FIQ_UARTINT2 INT_UARTINT2
114 #define FIQ_SCIINT INT_SCIINT
115 #define FIQ_CLCDINT INT_CLCDINT
116 #define FIQ_DMAINT INT_DMAINT
117 #define FIQ_PWRFAILINT INT_PWRFAILINT
118 #define FIQ_MBXINT INT_MBXINT
119 #define FIQ_GNDINT INT_GNDINT
120 #define FIQ_VICSOURCE21 INT_VICSOURCE21
121 #define FIQ_VICSOURCE22 INT_VICSOURCE22
122 #define FIQ_VICSOURCE23 INT_VICSOURCE23
123 #define FIQ_VICSOURCE24 INT_VICSOURCE24
124 #define FIQ_VICSOURCE25 INT_VICSOURCE25
125 #define FIQ_VICSOURCE26 INT_VICSOURCE26
126 #define FIQ_VICSOURCE27 INT_VICSOURCE27
127 #define FIQ_VICSOURCE28 INT_VICSOURCE28
128 #define FIQ_VICSOURCE29 INT_VICSOURCE29
129 #define FIQ_VICSOURCE30 INT_VICSOURCE30
130 #define FIQ_VICSOURCE31 INT_VICSOURCE31
133 #define FIQMASK_WDOGINT INTMASK_WDOGINT
134 #define FIQMASK_SOFTINT INTMASK_SOFTINT
135 #define FIQMASK_COMMRx INTMASK_COMMRx
136 #define FIQMASK_COMMTx INTMASK_COMMTx
137 #define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
138 #define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
139 #define FIQMASK_GPIOINT0 INTMASK_GPIOINT0
140 #define FIQMASK_GPIOINT1 INTMASK_GPIOINT1
141 #define FIQMASK_GPIOINT2 INTMASK_GPIOINT2
142 #define FIQMASK_GPIOINT3 INTMASK_GPIOINT3
143 #define FIQMASK_RTCINT INTMASK_RTCINT
144 #define FIQMASK_SSPINT INTMASK_SSPINT
145 #define FIQMASK_UARTINT0 INTMASK_UARTINT0
146 #define FIQMASK_UARTINT1 INTMASK_UARTINT1
147 #define FIQMASK_UARTINT2 INTMASK_UARTINT2
148 #define FIQMASK_SCIINT INTMASK_SCIINT
149 #define FIQMASK_CLCDINT INTMASK_CLCDINT
150 #define FIQMASK_DMAINT INTMASK_DMAINT
151 #define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT
152 #define FIQMASK_MBXINT INTMASK_MBXINT
153 #define FIQMASK_GNDINT INTMASK_GNDINT
154 #define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21
155 #define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22
156 #define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23
157 #define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24
158 #define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25
159 #define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26
160 #define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27
161 #define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28
162 #define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29
163 #define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30
164 #define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31
166 /*
167 * Secondary interrupt controller
168 */
169 #define IRQ_SIC_START 32
170 #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B)
171 #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B)
172 #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0)
173 #define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1)
174 #define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3)
175 #define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3)
176 #define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD)
177 #define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH)
178 #define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD)
179 #define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC)
180 #define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A)
181 #define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A)
182 #define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI)
183 #define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH)
184 #define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB)
185 #define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0)
186 #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1)
187 #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2)
188 #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
189 #define IRQ_SIC_END 63
191 #define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B
192 #define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B
193 #define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0
194 #define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1
195 #define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3
196 #define SIC_IRQMASK_UART3 SIC_INTMASK_UART3
197 #define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD
198 #define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH
199 #define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD
200 #define SIC_IRQMASK_DoC SIC_INTMASK_DoC
201 #define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A
202 #define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A
203 #define SIC_IRQMASK_AACI SIC_INTMASK_AACI
204 #define SIC_IRQMASK_ETH SIC_INTMASK_ETH
205 #define SIC_IRQMASK_USB SIC_INTMASK_USB
206 #define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0
207 #define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1
208 #define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2
209 #define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3
211 #define NR_IRQS 64