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KVM: s390: arch backend for the kvm kernel module
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / infiniband / hw / mthca / mthca_cq.c
blob20401d2ba6b2cdd3ee961ecd4963f8043f96117e
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
37 */
38
39 #include <linux/hardirq.h>
40 #include <linux/sched.h>
41
42 #include <asm/io.h>
43
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49
50 enum {
51 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
52 };
53
54 enum {
55 MTHCA_CQ_ENTRY_SIZE = 0x20
56 };
57
58 enum {
59 MTHCA_ATOMIC_BYTE_LEN = 8
60 };
61
62 /*
63 * Must be packed because start is 64 bits but only aligned to 32 bits.
64 */
65 struct mthca_cq_context {
66 __be32 flags;
67 __be64 start;
68 __be32 logsize_usrpage;
69 __be32 error_eqn; /* Tavor only */
70 __be32 comp_eqn;
71 __be32 pd;
72 __be32 lkey;
73 __be32 last_notified_index;
74 __be32 solicit_producer_index;
75 __be32 consumer_index;
76 __be32 producer_index;
77 __be32 cqn;
78 __be32 ci_db; /* Arbel only */
79 __be32 state_db; /* Arbel only */
80 u32 reserved;
81 } __attribute__((packed));
82
83 #define MTHCA_CQ_STATUS_OK ( 0 << 28)
84 #define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28)
85 #define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28)
86 #define MTHCA_CQ_FLAG_TR ( 1 << 18)
87 #define MTHCA_CQ_FLAG_OI ( 1 << 17)
88 #define MTHCA_CQ_STATE_DISARMED ( 0 << 8)
89 #define MTHCA_CQ_STATE_ARMED ( 1 << 8)
90 #define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8)
91 #define MTHCA_EQ_STATE_FIRED (10 << 8)
92
93 enum {
94 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
95 };
96
97 enum {
98 SYNDROME_LOCAL_LENGTH_ERR = 0x01,
99 SYNDROME_LOCAL_QP_OP_ERR = 0x02,
100 SYNDROME_LOCAL_EEC_OP_ERR = 0x03,
101 SYNDROME_LOCAL_PROT_ERR = 0x04,
102 SYNDROME_WR_FLUSH_ERR = 0x05,
103 SYNDROME_MW_BIND_ERR = 0x06,
104 SYNDROME_BAD_RESP_ERR = 0x10,
105 SYNDROME_LOCAL_ACCESS_ERR = 0x11,
106 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
107 SYNDROME_REMOTE_ACCESS_ERR = 0x13,
108 SYNDROME_REMOTE_OP_ERR = 0x14,
109 SYNDROME_RETRY_EXC_ERR = 0x15,
110 SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
111 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20,
112 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
113 SYNDROME_REMOTE_ABORTED_ERR = 0x22,
114 SYNDROME_INVAL_EECN_ERR = 0x23,
115 SYNDROME_INVAL_EEC_STATE_ERR = 0x24
116 };
117
118 struct mthca_cqe {
119 __be32 my_qpn;
120 __be32 my_ee;
121 __be32 rqpn;
122 u8 sl_ipok;
123 u8 g_mlpath;
124 __be16 rlid;
125 __be32 imm_etype_pkey_eec;
126 __be32 byte_cnt;
127 __be32 wqe;
128 u8 opcode;
129 u8 is_send;
130 u8 reserved;
131 u8 owner;
132 };
133
134 struct mthca_err_cqe {
135 __be32 my_qpn;
136 u32 reserved1[3];
137 u8 syndrome;
138 u8 vendor_err;
139 __be16 db_cnt;
140 u32 reserved2;
141 __be32 wqe;
142 u8 opcode;
143 u8 reserved3[2];
144 u8 owner;
145 };
146
147 #define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
148 #define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7)
149
150 #define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24)
151 #define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24)
152 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24)
153 #define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24)
154 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
155
156 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24)
157 #define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24)
158 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
159
160 static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf,
161 int entry)
162 {
163 if (buf->is_direct)
164 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
165 else
166 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
167 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
168 }
169
170 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
171 {
172 return get_cqe_from_buf(&cq->buf, entry);
173 }
174
175 static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe)
176 {
177 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
178 }
179
180 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
181 {
182 return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe));
183 }
184
185 static inline void set_cqe_hw(struct mthca_cqe *cqe)
186 {
187 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
188 }
189
190 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
191 {
192 __be32 *cqe = cqe_ptr;
193
194 (void) cqe; /* avoid warning if mthca_dbg compiled away... */
195 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
196 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
197 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
198 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
199 }
200
201 /*
202 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
203 * should be correct before calling update_cons_index().
204 */
205 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
206 int incr)
207 {
208 if (mthca_is_memfree(dev)) {
209 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
210 wmb();
211 } else {
212 mthca_write64(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn, incr - 1,
213 dev->kar + MTHCA_CQ_DOORBELL,
214 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
215 /*
216 * Make sure doorbells don't leak out of CQ spinlock
217 * and reach the HCA out of order:
218 */
219 mmiowb();
220 }
221 }
222
223 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
224 {
225 struct mthca_cq *cq;
226
227 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
228
229 if (!cq) {
230 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
231 return;
232 }
233
234 ++cq->arm_sn;
235
236 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
237 }
238
239 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
240 enum ib_event_type event_type)
241 {
242 struct mthca_cq *cq;
243 struct ib_event event;
244
245 spin_lock(&dev->cq_table.lock);
246
247 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
248 if (cq)
249 ++cq->refcount;
250
251 spin_unlock(&dev->cq_table.lock);
252
253 if (!cq) {
254 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn);
255 return;
256 }
257
258 event.device = &dev->ib_dev;
259 event.event = event_type;
260 event.element.cq = &cq->ibcq;
261 if (cq->ibcq.event_handler)
262 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
263
264 spin_lock(&dev->cq_table.lock);
265 if (!--cq->refcount)
266 wake_up(&cq->wait);
267 spin_unlock(&dev->cq_table.lock);
268 }
269
270 static inline int is_recv_cqe(struct mthca_cqe *cqe)
271 {
272 if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
273 MTHCA_ERROR_CQE_OPCODE_MASK)
274 return !(cqe->opcode & 0x01);
275 else
276 return !(cqe->is_send & 0x80);
277 }
278
279 void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,
280 struct mthca_srq *srq)
281 {
282 struct mthca_cqe *cqe;
283 u32 prod_index;
284 int i, nfreed = 0;
285
286 spin_lock_irq(&cq->lock);
287
288 /*
289 * First we need to find the current producer index, so we
290 * know where to start cleaning from. It doesn't matter if HW
291 * adds new entries after this loop -- the QP we're worried
292 * about is already in RESET, so the new entries won't come
293 * from our QP and therefore don't need to be checked.
294 */
295 for (prod_index = cq->cons_index;
296 cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe));
297 ++prod_index)
298 if (prod_index == cq->cons_index + cq->ibcq.cqe)
299 break;
300
301 if (0)
302 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
303 qpn, cq->cqn, cq->cons_index, prod_index);
304
305 /*
306 * Now sweep backwards through the CQ, removing CQ entries
307 * that match our QP by copying older entries on top of them.
308 */
309 while ((int) --prod_index - (int) cq->cons_index >= 0) {
310 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
311 if (cqe->my_qpn == cpu_to_be32(qpn)) {
312 if (srq && is_recv_cqe(cqe))
313 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
314 ++nfreed;
315 } else if (nfreed)
316 memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
317 cqe, MTHCA_CQ_ENTRY_SIZE);
318 }
319
320 if (nfreed) {
321 for (i = 0; i < nfreed; ++i)
322 set_cqe_hw(get_cqe(cq, (cq->cons_index + i) & cq->ibcq.cqe));
323 wmb();
324 cq->cons_index += nfreed;
325 update_cons_index(dev, cq, nfreed);
326 }
327
328 spin_unlock_irq(&cq->lock);
329 }
330
331 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq)
332 {
333 int i;
334
335 /*
336 * In Tavor mode, the hardware keeps the consumer and producer
337 * indices mod the CQ size. Since we might be making the CQ
338 * bigger, we need to deal with the case where the producer
339 * index wrapped around before the CQ was resized.
340 */
341 if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) &&
342 cq->ibcq.cqe < cq->resize_buf->cqe) {
343 cq->cons_index &= cq->ibcq.cqe;
344 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe)))
345 cq->cons_index -= cq->ibcq.cqe + 1;
346 }
347
348 for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i)
349 memcpy(get_cqe_from_buf(&cq->resize_buf->buf,
350 i & cq->resize_buf->cqe),
351 get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE);
352 }
353
354 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent)
355 {
356 int ret;
357 int i;
358
359 ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE,
360 MTHCA_MAX_DIRECT_CQ_SIZE,
361 &buf->queue, &buf->is_direct,
362 &dev->driver_pd, 1, &buf->mr);
363 if (ret)
364 return ret;
365
366 for (i = 0; i < nent; ++i)
367 set_cqe_hw(get_cqe_from_buf(buf, i));
368
369 return 0;
370 }
371
372 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe)
373 {
374 mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue,
375 buf->is_direct, &buf->mr);
376 }
377
378 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
379 struct mthca_qp *qp, int wqe_index, int is_send,
380 struct mthca_err_cqe *cqe,
381 struct ib_wc *entry, int *free_cqe)
382 {
383 int dbd;
384 __be32 new_wqe;
385
386 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
387 mthca_dbg(dev, "local QP operation err "
388 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
389 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
390 cq->cqn, cq->cons_index);
391 dump_cqe(dev, cqe);
392 }
393
394 /*
395 * For completions in error, only work request ID, status, vendor error
396 * (and freed resource count for RD) have to be set.
397 */
398 switch (cqe->syndrome) {
399 case SYNDROME_LOCAL_LENGTH_ERR:
400 entry->status = IB_WC_LOC_LEN_ERR;
401 break;
402 case SYNDROME_LOCAL_QP_OP_ERR:
403 entry->status = IB_WC_LOC_QP_OP_ERR;
404 break;
405 case SYNDROME_LOCAL_EEC_OP_ERR:
406 entry->status = IB_WC_LOC_EEC_OP_ERR;
407 break;
408 case SYNDROME_LOCAL_PROT_ERR:
409 entry->status = IB_WC_LOC_PROT_ERR;
410 break;
411 case SYNDROME_WR_FLUSH_ERR:
412 entry->status = IB_WC_WR_FLUSH_ERR;
413 break;
414 case SYNDROME_MW_BIND_ERR:
415 entry->status = IB_WC_MW_BIND_ERR;
416 break;
417 case SYNDROME_BAD_RESP_ERR:
418 entry->status = IB_WC_BAD_RESP_ERR;
419 break;
420 case SYNDROME_LOCAL_ACCESS_ERR:
421 entry->status = IB_WC_LOC_ACCESS_ERR;
422 break;
423 case SYNDROME_REMOTE_INVAL_REQ_ERR:
424 entry->status = IB_WC_REM_INV_REQ_ERR;
425 break;
426 case SYNDROME_REMOTE_ACCESS_ERR:
427 entry->status = IB_WC_REM_ACCESS_ERR;
428 break;
429 case SYNDROME_REMOTE_OP_ERR:
430 entry->status = IB_WC_REM_OP_ERR;
431 break;
432 case SYNDROME_RETRY_EXC_ERR:
433 entry->status = IB_WC_RETRY_EXC_ERR;
434 break;
435 case SYNDROME_RNR_RETRY_EXC_ERR:
436 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
437 break;
438 case SYNDROME_LOCAL_RDD_VIOL_ERR:
439 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
440 break;
441 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
442 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
443 break;
444 case SYNDROME_REMOTE_ABORTED_ERR:
445 entry->status = IB_WC_REM_ABORT_ERR;
446 break;
447 case SYNDROME_INVAL_EECN_ERR:
448 entry->status = IB_WC_INV_EECN_ERR;
449 break;
450 case SYNDROME_INVAL_EEC_STATE_ERR:
451 entry->status = IB_WC_INV_EEC_STATE_ERR;
452 break;
453 default:
454 entry->status = IB_WC_GENERAL_ERR;
455 break;
456 }
457
458 entry->vendor_err = cqe->vendor_err;
459
460 /*
461 * Mem-free HCAs always generate one CQE per WQE, even in the
462 * error case, so we don't have to check the doorbell count, etc.
463 */
464 if (mthca_is_memfree(dev))
465 return;
466
467 mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
468
469 /*
470 * If we're at the end of the WQE chain, or we've used up our
471 * doorbell count, free the CQE. Otherwise just update it for
472 * the next poll operation.
473 */
474 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
475 return;
476
477 be16_add_cpu(&cqe->db_cnt, -dbd);
478 cqe->wqe = new_wqe;
479 cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
480
481 *free_cqe = 0;
482 }
483
484 static inline int mthca_poll_one(struct mthca_dev *dev,
485 struct mthca_cq *cq,
486 struct mthca_qp **cur_qp,
487 int *freed,
488 struct ib_wc *entry)
489 {
490 struct mthca_wq *wq;
491 struct mthca_cqe *cqe;
492 int wqe_index;
493 int is_error;
494 int is_send;
495 int free_cqe = 1;
496 int err = 0;
497 u16 checksum;
498
499 cqe = next_cqe_sw(cq);
500 if (!cqe)
501 return -EAGAIN;
502
503 /*
504 * Make sure we read CQ entry contents after we've checked the
505 * ownership bit.
506 */
507 rmb();
508
509 if (0) {
510 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
511 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
512 be32_to_cpu(cqe->wqe));
513 dump_cqe(dev, cqe);
514 }
515
516 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
517 MTHCA_ERROR_CQE_OPCODE_MASK;
518 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
519
520 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
521 /*
522 * We do not have to take the QP table lock here,
523 * because CQs will be locked while QPs are removed
524 * from the table.
525 */
526 *cur_qp = mthca_array_get(&dev->qp_table.qp,
527 be32_to_cpu(cqe->my_qpn) &
528 (dev->limits.num_qps - 1));
529 if (!*cur_qp) {
530 mthca_warn(dev, "CQ entry for unknown QP %06x\n",
531 be32_to_cpu(cqe->my_qpn) & 0xffffff);
532 err = -EINVAL;
533 goto out;
534 }
535 }
536
537 entry->qp = &(*cur_qp)->ibqp;
538
539 if (is_send) {
540 wq = &(*cur_qp)->sq;
541 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
542 >> wq->wqe_shift);
543 entry->wr_id = (*cur_qp)->wrid[wqe_index +
544 (*cur_qp)->rq.max];
545 } else if ((*cur_qp)->ibqp.srq) {
546 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
547 u32 wqe = be32_to_cpu(cqe->wqe);
548 wq = NULL;
549 wqe_index = wqe >> srq->wqe_shift;
550 entry->wr_id = srq->wrid[wqe_index];
551 mthca_free_srq_wqe(srq, wqe);
552 } else {
553 s32 wqe;
554 wq = &(*cur_qp)->rq;
555 wqe = be32_to_cpu(cqe->wqe);
556 wqe_index = wqe >> wq->wqe_shift;
557 /*
558 * WQE addr == base - 1 might be reported in receive completion
559 * with error instead of (rq size - 1) by Sinai FW 1.0.800 and
560 * Arbel FW 5.1.400. This bug should be fixed in later FW revs.
561 */
562 if (unlikely(wqe_index < 0))
563 wqe_index = wq->max - 1;
564 entry->wr_id = (*cur_qp)->wrid[wqe_index];
565 }
566
567 if (wq) {
568 if (wq->last_comp < wqe_index)
569 wq->tail += wqe_index - wq->last_comp;
570 else
571 wq->tail += wqe_index + wq->max - wq->last_comp;
572
573 wq->last_comp = wqe_index;
574 }
575
576 if (is_error) {
577 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
578 (struct mthca_err_cqe *) cqe,
579 entry, &free_cqe);
580 goto out;
581 }
582
583 if (is_send) {
584 entry->wc_flags = 0;
585 switch (cqe->opcode) {
586 case MTHCA_OPCODE_RDMA_WRITE:
587 entry->opcode = IB_WC_RDMA_WRITE;
588 break;
589 case MTHCA_OPCODE_RDMA_WRITE_IMM:
590 entry->opcode = IB_WC_RDMA_WRITE;
591 entry->wc_flags |= IB_WC_WITH_IMM;
592 break;
593 case MTHCA_OPCODE_SEND:
594 entry->opcode = IB_WC_SEND;
595 break;
596 case MTHCA_OPCODE_SEND_IMM:
597 entry->opcode = IB_WC_SEND;
598 entry->wc_flags |= IB_WC_WITH_IMM;
599 break;
600 case MTHCA_OPCODE_RDMA_READ:
601 entry->opcode = IB_WC_RDMA_READ;
602 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
603 break;
604 case MTHCA_OPCODE_ATOMIC_CS:
605 entry->opcode = IB_WC_COMP_SWAP;
606 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN;
607 break;
608 case MTHCA_OPCODE_ATOMIC_FA:
609 entry->opcode = IB_WC_FETCH_ADD;
610 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN;
611 break;
612 case MTHCA_OPCODE_BIND_MW:
613 entry->opcode = IB_WC_BIND_MW;
614 break;
615 default:
616 entry->opcode = MTHCA_OPCODE_INVALID;
617 break;
618 }
619 } else {
620 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
621 switch (cqe->opcode & 0x1f) {
622 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
623 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
624 entry->wc_flags = IB_WC_WITH_IMM;
625 entry->imm_data = cqe->imm_etype_pkey_eec;
626 entry->opcode = IB_WC_RECV;
627 break;
628 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
629 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
630 entry->wc_flags = IB_WC_WITH_IMM;
631 entry->imm_data = cqe->imm_etype_pkey_eec;
632 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
633 break;
634 default:
635 entry->wc_flags = 0;
636 entry->opcode = IB_WC_RECV;
637 break;
638 }
639 entry->slid = be16_to_cpu(cqe->rlid);
640 entry->sl = cqe->sl_ipok >> 4;
641 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff;
642 entry->dlid_path_bits = cqe->g_mlpath & 0x7f;
643 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
644 entry->wc_flags |= cqe->g_mlpath & 0x80 ? IB_WC_GRH : 0;
645 checksum = (be32_to_cpu(cqe->rqpn) >> 24) |
646 ((be32_to_cpu(cqe->my_ee) >> 16) & 0xff00);
647 entry->csum_ok = (cqe->sl_ipok & 1 && checksum == 0xffff);
648 }
649
650 entry->status = IB_WC_SUCCESS;
651
652 out:
653 if (likely(free_cqe)) {
654 set_cqe_hw(cqe);
655 ++(*freed);
656 ++cq->cons_index;
657 }
658
659 return err;
660 }
661
662 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
663 struct ib_wc *entry)
664 {
665 struct mthca_dev *dev = to_mdev(ibcq->device);
666 struct mthca_cq *cq = to_mcq(ibcq);
667 struct mthca_qp *qp = NULL;
668 unsigned long flags;
669 int err = 0;
670 int freed = 0;
671 int npolled;
672
673 spin_lock_irqsave(&cq->lock, flags);
674
675 npolled = 0;
676 repoll:
677 while (npolled < num_entries) {
678 err = mthca_poll_one(dev, cq, &qp,
679 &freed, entry + npolled);
680 if (err)
681 break;
682 ++npolled;
683 }
684
685 if (freed) {
686 wmb();
687 update_cons_index(dev, cq, freed);
688 }
689
690 /*
691 * If a CQ resize is in progress and we discovered that the
692 * old buffer is empty, then peek in the new buffer, and if
693 * it's not empty, switch to the new buffer and continue
694 * polling there.
695 */
696 if (unlikely(err == -EAGAIN && cq->resize_buf &&
697 cq->resize_buf->state == CQ_RESIZE_READY)) {
698 /*
699 * In Tavor mode, the hardware keeps the producer
700 * index modulo the CQ size. Since we might be making
701 * the CQ bigger, we need to mask our consumer index
702 * using the size of the old CQ buffer before looking
703 * in the new CQ buffer.
704 */
705 if (!mthca_is_memfree(dev))
706 cq->cons_index &= cq->ibcq.cqe;
707
708 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf,
709 cq->cons_index & cq->resize_buf->cqe))) {
710 struct mthca_cq_buf tbuf;
711 int tcqe;
712
713 tbuf = cq->buf;
714 tcqe = cq->ibcq.cqe;
715 cq->buf = cq->resize_buf->buf;
716 cq->ibcq.cqe = cq->resize_buf->cqe;
717
718 cq->resize_buf->buf = tbuf;
719 cq->resize_buf->cqe = tcqe;
720 cq->resize_buf->state = CQ_RESIZE_SWAPPED;
721
722 goto repoll;
723 }
724 }
725
726 spin_unlock_irqrestore(&cq->lock, flags);
727
728 return err == 0 || err == -EAGAIN ? npolled : err;
729 }
730
731 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags)
732 {
733 u32 dbhi = ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
734 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
735 MTHCA_TAVOR_CQ_DB_REQ_NOT) |
736 to_mcq(cq)->cqn;
737
738 mthca_write64(dbhi, 0xffffffff, to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
739 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
740
741 return 0;
742 }
743
744 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
745 {
746 struct mthca_cq *cq = to_mcq(ibcq);
747 __be32 db_rec[2];
748 u32 dbhi;
749 u32 sn = cq->arm_sn & 3;
750
751 db_rec[0] = cpu_to_be32(cq->cons_index);
752 db_rec[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
753 ((flags & IB_CQ_SOLICITED_MASK) ==
754 IB_CQ_SOLICITED ? 1 : 2));
755
756 mthca_write_db_rec(db_rec, cq->arm_db);
757
758 /*
759 * Make sure that the doorbell record in host memory is
760 * written before ringing the doorbell via PCI MMIO.
761 */
762 wmb();
763
764 dbhi = (sn << 28) |
765 ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
766 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
767 MTHCA_ARBEL_CQ_DB_REQ_NOT) | cq->cqn;
768
769 mthca_write64(dbhi, cq->cons_index,
770 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
771 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
772
773 return 0;
774 }
775
776 int mthca_init_cq(struct mthca_dev *dev, int nent,
777 struct mthca_ucontext *ctx, u32 pdn,
778 struct mthca_cq *cq)
779 {
780 struct mthca_mailbox *mailbox;
781 struct mthca_cq_context *cq_context;
782 int err = -ENOMEM;
783 u8 status;
784
785 cq->ibcq.cqe = nent - 1;
786 cq->is_kernel = !ctx;
787
788 cq->cqn = mthca_alloc(&dev->cq_table.alloc);
789 if (cq->cqn == -1)
790 return -ENOMEM;
791
792 if (mthca_is_memfree(dev)) {
793 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
794 if (err)
795 goto err_out;
796
797 if (cq->is_kernel) {
798 cq->arm_sn = 1;
799
800 err = -ENOMEM;
801
802 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
803 cq->cqn, &cq->set_ci_db);
804 if (cq->set_ci_db_index < 0)
805 goto err_out_icm;
806
807 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
808 cq->cqn, &cq->arm_db);
809 if (cq->arm_db_index < 0)
810 goto err_out_ci;
811 }
812 }
813
814 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
815 if (IS_ERR(mailbox))
816 goto err_out_arm;
817
818 cq_context = mailbox->buf;
819
820 if (cq->is_kernel) {
821 err = mthca_alloc_cq_buf(dev, &cq->buf, nent);
822 if (err)
823 goto err_out_mailbox;
824 }
825
826 spin_lock_init(&cq->lock);
827 cq->refcount = 1;
828 init_waitqueue_head(&cq->wait);
829 mutex_init(&cq->mutex);
830
831 memset(cq_context, 0, sizeof *cq_context);
832 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
833 MTHCA_CQ_STATE_DISARMED |
834 MTHCA_CQ_FLAG_TR);
835 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
836 if (ctx)
837 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
838 else
839 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
840 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
841 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
842 cq_context->pd = cpu_to_be32(pdn);
843 cq_context->lkey = cpu_to_be32(cq->buf.mr.ibmr.lkey);
844 cq_context->cqn = cpu_to_be32(cq->cqn);
845
846 if (mthca_is_memfree(dev)) {
847 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index);
848 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
849 }
850
851 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
852 if (err) {
853 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
854 goto err_out_free_mr;
855 }
856
857 if (status) {
858 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
859 status);
860 err = -EINVAL;
861 goto err_out_free_mr;
862 }
863
864 spin_lock_irq(&dev->cq_table.lock);
865 if (mthca_array_set(&dev->cq_table.cq,
866 cq->cqn & (dev->limits.num_cqs - 1),
867 cq)) {
868 spin_unlock_irq(&dev->cq_table.lock);
869 goto err_out_free_mr;
870 }
871 spin_unlock_irq(&dev->cq_table.lock);
872
873 cq->cons_index = 0;
874
875 mthca_free_mailbox(dev, mailbox);
876
877 return 0;
878
879 err_out_free_mr:
880 if (cq->is_kernel)
881 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
882
883 err_out_mailbox:
884 mthca_free_mailbox(dev, mailbox);
885
886 err_out_arm:
887 if (cq->is_kernel && mthca_is_memfree(dev))
888 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
889
890 err_out_ci:
891 if (cq->is_kernel && mthca_is_memfree(dev))
892 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
893
894 err_out_icm:
895 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
896
897 err_out:
898 mthca_free(&dev->cq_table.alloc, cq->cqn);
899
900 return err;
901 }
902
903 static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq)
904 {
905 int c;
906
907 spin_lock_irq(&dev->cq_table.lock);
908 c = cq->refcount;
909 spin_unlock_irq(&dev->cq_table.lock);
910
911 return c;
912 }
913
914 void mthca_free_cq(struct mthca_dev *dev,
915 struct mthca_cq *cq)
916 {
917 struct mthca_mailbox *mailbox;
918 int err;
919 u8 status;
920
921 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
922 if (IS_ERR(mailbox)) {
923 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
924 return;
925 }
926
927 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
928 if (err)
929 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
930 else if (status)
931 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
932
933 if (0) {
934 __be32 *ctx = mailbox->buf;
935 int j;
936
937 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
938 cq->cqn, cq->cons_index,
939 cq->is_kernel ? !!next_cqe_sw(cq) : 0);
940 for (j = 0; j < 16; ++j)
941 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
942 }
943
944 spin_lock_irq(&dev->cq_table.lock);
945 mthca_array_clear(&dev->cq_table.cq,
946 cq->cqn & (dev->limits.num_cqs - 1));
947 --cq->refcount;
948 spin_unlock_irq(&dev->cq_table.lock);
949
950 if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
951 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
952 else
953 synchronize_irq(dev->pdev->irq);
954
955 wait_event(cq->wait, !get_cq_refcount(dev, cq));
956
957 if (cq->is_kernel) {
958 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
959 if (mthca_is_memfree(dev)) {
960 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
961 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
962 }
963 }
964
965 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
966 mthca_free(&dev->cq_table.alloc, cq->cqn);
967 mthca_free_mailbox(dev, mailbox);
968 }
969
970 int mthca_init_cq_table(struct mthca_dev *dev)
971 {
972 int err;
973
974 spin_lock_init(&dev->cq_table.lock);
975
976 err = mthca_alloc_init(&dev->cq_table.alloc,
977 dev->limits.num_cqs,
978 (1 << 24) - 1,
979 dev->limits.reserved_cqs);
980 if (err)
981 return err;
982
983 err = mthca_array_init(&dev->cq_table.cq,
984 dev->limits.num_cqs);
985 if (err)
986 mthca_alloc_cleanup(&dev->cq_table.alloc);
987
988 return err;
989 }
990
991 void mthca_cleanup_cq_table(struct mthca_dev *dev)
992 {
993 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
994 mthca_alloc_cleanup(&dev->cq_table.alloc);
995 }
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