include/asm-powerpc/mmu-hash32.h

   1 #ifndef _ASM_POWERPC_MMU_HASH32_H_
   2 #define _ASM_POWERPC_MMU_HASH32_H_
   3 /*
   4  * 32-bit hash table MMU support
   5  */
   6
   7 /*
   8  * BATs
   9  */
  10
  11 /* Block size masks */
  12 #define BL_128K 0x000
  13 #define BL_256K 0x001
  14 #define BL_512K 0x003
  15 #define BL_1M   0x007
  16 #define BL_2M   0x00F
  17 #define BL_4M   0x01F
  18 #define BL_8M   0x03F
  19 #define BL_16M  0x07F
  20 #define BL_32M  0x0FF
  21 #define BL_64M  0x1FF
  22 #define BL_128M 0x3FF
  23 #define BL_256M 0x7FF
  24
  25 /* BAT Access Protection */
  26 #define BPP_XX  0x00            /* No access */
  27 #define BPP_RX  0x01            /* Read only */
  28 #define BPP_RW  0x02            /* Read/write */
  29
  30 #ifndef __ASSEMBLY__
  31 struct ppc_bat {
  32         struct {
  33                 unsigned long bepi:15;  /* Effective page index (virtual address) */
  34                 unsigned long :4;       /* Unused */
  35                 unsigned long bl:11;    /* Block size mask */
  36                 unsigned long vs:1;     /* Supervisor valid */
  37                 unsigned long vp:1;     /* User valid */
  38         } batu;                 /* Upper register */
  39         struct {
  40                 unsigned long brpn:15;  /* Real page index (physical address) */
  41                 unsigned long :10;      /* Unused */
  42                 unsigned long w:1;      /* Write-thru cache */
  43                 unsigned long i:1;      /* Cache inhibit */
  44                 unsigned long m:1;      /* Memory coherence */
  45                 unsigned long g:1;      /* Guarded (MBZ in IBAT) */
  46                 unsigned long :1;       /* Unused */
  47                 unsigned long pp:2;     /* Page access protections */
  48         } batl;                 /* Lower register */
  49 };
  50 #endif /* !__ASSEMBLY__ */
  51
  52 /*
  53  * Hash table
  54  */
  55
  56 /* Values for PP (assumes Ks=0, Kp=1) */
  57 #define PP_RWXX 0       /* Supervisor read/write, User none */
  58 #define PP_RWRX 1       /* Supervisor read/write, User read */
  59 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  60 #define PP_RXRX 3       /* Supervisor read,       User read */
  61
  62 #ifndef __ASSEMBLY__
  63
  64 /* Hardware Page Table Entry */
  65 struct hash_pte {
  66         unsigned long v:1;      /* Entry is valid */
  67         unsigned long vsid:24;  /* Virtual segment identifier */
  68         unsigned long h:1;      /* Hash algorithm indicator */
  69         unsigned long api:6;    /* Abbreviated page index */
  70         unsigned long rpn:20;   /* Real (physical) page number */
  71         unsigned long    :3;    /* Unused */
  72         unsigned long r:1;      /* Referenced */
  73         unsigned long c:1;      /* Changed */
  74         unsigned long w:1;      /* Write-thru cache mode */
  75         unsigned long i:1;      /* Cache inhibited */
  76         unsigned long m:1;      /* Memory coherence */
  77         unsigned long g:1;      /* Guarded */
  78         unsigned long  :1;      /* Unused */
  79         unsigned long pp:2;     /* Page protection */
  80 };
  81
  82 typedef struct {
  83         unsigned long id;
  84         unsigned long vdso_base;
  85 } mm_context_t;
  86
  87 typedef unsigned long phys_addr_t;
  88
  89 #endif /* !__ASSEMBLY__ */
  90
  91 #endif /* _ASM_POWERPC_MMU_HASH32_H_ */