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Merge commit 'v2.6.34.7' into dev-df3210-staging
[linux-2.6/parrot-frames.git] / drivers / staging / cx25821 / cx25821-video-upstream-ch2.c
blobcc51618cffa9b419c0deb46631f8293e97df285b
1 /*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include "cx25821-video.h"
24 #include "cx25821-video-upstream-ch2.h"
25
26 #include <linux/fs.h>
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/syscalls.h>
32 #include <linux/file.h>
33 #include <linux/fcntl.h>
34 #include <linux/slab.h>
35 #include <asm/uaccess.h>
36
37 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
38 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
39 MODULE_LICENSE("GPL");
40
41 static int _intr_msk =
42 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
43
44 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
45 __le32 * rp, unsigned int offset,
46 unsigned int bpl, u32 sync_line,
47 unsigned int lines,
48 int fifo_enable, int field_type)
49 {
50 unsigned int line, i;
51 int dist_betwn_starts = bpl * 2;
52
53 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
54
55 if (USE_RISC_NOOP_VIDEO) {
56 for (i = 0; i < NUM_NO_OPS; i++) {
57 *(rp++) = cpu_to_le32(RISC_NOOP);
58 }
59 }
60
61 /* scan lines */
62 for (line = 0; line < lines; line++) {
63 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
64 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
65 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
66
67 if ((lines <= NTSC_FIELD_HEIGHT)
68 || (line < (NTSC_FIELD_HEIGHT - 1))
69 || !(dev->_isNTSC_ch2)) {
70 offset += dist_betwn_starts;
71 }
72 }
73
74 return rp;
75 }
76
77 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
78 __le32 * rp,
79 dma_addr_t databuf_phys_addr,
80 unsigned int offset,
81 u32 sync_line, unsigned int bpl,
82 unsigned int lines,
83 int fifo_enable, int field_type)
84 {
85 unsigned int line, i;
86 struct sram_channel *sram_ch =
87 &dev->sram_channels[dev->_channel2_upstream_select];
88 int dist_betwn_starts = bpl * 2;
89
90 /* sync instruction */
91 if (sync_line != NO_SYNC_LINE) {
92 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
93 }
94
95 if (USE_RISC_NOOP_VIDEO) {
96 for (i = 0; i < NUM_NO_OPS; i++) {
97 *(rp++) = cpu_to_le32(RISC_NOOP);
98 }
99 }
100
101 /* scan lines */
102 for (line = 0; line < lines; line++) {
103 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
104 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
105 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
106
107 if ((lines <= NTSC_FIELD_HEIGHT)
108 || (line < (NTSC_FIELD_HEIGHT - 1))
109 || !(dev->_isNTSC_ch2)) {
110 offset += dist_betwn_starts;
111 }
112
113 // check if we need to enable the FIFO after the first 4 lines
114 // For the upstream video channel, the risc engine will enable the FIFO.
115 if (fifo_enable && line == 3) {
116 *(rp++) = RISC_WRITECR;
117 *(rp++) = sram_ch->dma_ctl;
118 *(rp++) = FLD_VID_FIFO_EN;
119 *(rp++) = 0x00000001;
120 }
121 }
122
123 return rp;
124 }
125
126 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
127 struct pci_dev *pci,
128 unsigned int top_offset, unsigned int bpl,
129 unsigned int lines)
130 {
131 __le32 *rp;
132 int fifo_enable = 0;
133 int singlefield_lines = lines >> 1; //get line count for single field
134 int odd_num_lines = singlefield_lines;
135 int frame = 0;
136 int frame_size = 0;
137 int databuf_offset = 0;
138 int risc_program_size = 0;
139 int risc_flag = RISC_CNT_RESET;
140 unsigned int bottom_offset = bpl;
141 dma_addr_t risc_phys_jump_addr;
142
143 if (dev->_isNTSC_ch2) {
144 odd_num_lines = singlefield_lines + 1;
145 risc_program_size = FRAME1_VID_PROG_SIZE;
146 frame_size =
147 (bpl ==
148 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
149 FRAME_SIZE_NTSC_Y422;
150 } else {
151 risc_program_size = PAL_VID_PROG_SIZE;
152 frame_size =
153 (bpl ==
154 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
155 }
156
157 /* Virtual address of Risc buffer program */
158 rp = dev->_dma_virt_addr_ch2;
159
160 for (frame = 0; frame < NUM_FRAMES; frame++) {
161 databuf_offset = frame_size * frame;
162
163 if (UNSET != top_offset) {
164 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
165 rp = cx25821_risc_field_upstream_ch2(dev, rp,
166 dev->
167 _data_buf_phys_addr_ch2
168 + databuf_offset,
169 top_offset, 0, bpl,
170 odd_num_lines,
171 fifo_enable,
172 ODD_FIELD);
173 }
174
175 fifo_enable = FIFO_DISABLE;
176
177 //Even field
178 rp = cx25821_risc_field_upstream_ch2(dev, rp,
179 dev->
180 _data_buf_phys_addr_ch2 +
181 databuf_offset,
182 bottom_offset, 0x200, bpl,
183 singlefield_lines,
184 fifo_enable, EVEN_FIELD);
185
186 if (frame == 0) {
187 risc_flag = RISC_CNT_RESET;
188 risc_phys_jump_addr =
189 dev->_dma_phys_start_addr_ch2 + risc_program_size;
190 } else {
191 risc_flag = RISC_CNT_INC;
192 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
193 }
194
195 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
196 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
197 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
198 *(rp++) = cpu_to_le32(0);
199 }
200
201 return 0;
202 }
203
204 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
205 {
206 struct sram_channel *sram_ch =
207 &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_J];
208 u32 tmp = 0;
209
210 if (!dev->_is_running_ch2) {
211 printk
212 ("cx25821: No video file is currently running so return!\n");
213 return;
214 }
215 //Disable RISC interrupts
216 tmp = cx_read(sram_ch->int_msk);
217 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
218
219 //Turn OFF risc and fifo
220 tmp = cx_read(sram_ch->dma_ctl);
221 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
222
223 //Clear data buffer memory
224 if (dev->_data_buf_virt_addr_ch2)
225 memset(dev->_data_buf_virt_addr_ch2, 0,
226 dev->_data_buf_size_ch2);
227
228 dev->_is_running_ch2 = 0;
229 dev->_is_first_frame_ch2 = 0;
230 dev->_frame_count_ch2 = 0;
231 dev->_file_status_ch2 = END_OF_FILE;
232
233 if (dev->_irq_queues_ch2) {
234 kfree(dev->_irq_queues_ch2);
235 dev->_irq_queues_ch2 = NULL;
236 }
237
238 if (dev->_filename_ch2 != NULL)
239 kfree(dev->_filename_ch2);
240
241 tmp = cx_read(VID_CH_MODE_SEL);
242 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
243 }
244
245 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
246 {
247 if (dev->_is_running_ch2) {
248 cx25821_stop_upstream_video_ch2(dev);
249 }
250
251 if (dev->_dma_virt_addr_ch2) {
252 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
253 dev->_dma_virt_addr_ch2,
254 dev->_dma_phys_addr_ch2);
255 dev->_dma_virt_addr_ch2 = NULL;
256 }
257
258 if (dev->_data_buf_virt_addr_ch2) {
259 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
260 dev->_data_buf_virt_addr_ch2,
261 dev->_data_buf_phys_addr_ch2);
262 dev->_data_buf_virt_addr_ch2 = NULL;
263 }
264 }
265
266 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
267 {
268 struct file *myfile;
269 int frame_index_temp = dev->_frame_index_ch2;
270 int i = 0;
271 int line_size =
272 (dev->_pixel_format_ch2 ==
273 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
274 int frame_size = 0;
275 int frame_offset = 0;
276 ssize_t vfs_read_retval = 0;
277 char mybuf[line_size];
278 loff_t file_offset;
279 loff_t pos;
280 mm_segment_t old_fs;
281
282 if (dev->_file_status_ch2 == END_OF_FILE)
283 return 0;
284
285 if (dev->_isNTSC_ch2) {
286 frame_size =
287 (line_size ==
288 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
289 FRAME_SIZE_NTSC_Y422;
290 } else {
291 frame_size =
292 (line_size ==
293 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
294 }
295
296 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
297 file_offset = dev->_frame_count_ch2 * frame_size;
298
299 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
300
301 if (IS_ERR(myfile)) {
302 const int open_errno = -PTR_ERR(myfile);
303 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
304 __func__, dev->_filename_ch2, open_errno);
305 return PTR_ERR(myfile);
306 } else {
307 if (!(myfile->f_op)) {
308 printk("%s: File has no file operations registered!",
309 __func__);
310 filp_close(myfile, NULL);
311 return -EIO;
312 }
313
314 if (!myfile->f_op->read) {
315 printk("%s: File has no READ operations registered!",
316 __func__);
317 filp_close(myfile, NULL);
318 return -EIO;
319 }
320
321 pos = myfile->f_pos;
322 old_fs = get_fs();
323 set_fs(KERNEL_DS);
324
325 for (i = 0; i < dev->_lines_count_ch2; i++) {
326 pos = file_offset;
327
328 vfs_read_retval =
329 vfs_read(myfile, mybuf, line_size, &pos);
330
331 if (vfs_read_retval > 0 && vfs_read_retval == line_size
332 && dev->_data_buf_virt_addr_ch2 != NULL) {
333 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
334 frame_offset / 4), mybuf,
335 vfs_read_retval);
336 }
337
338 file_offset += vfs_read_retval;
339 frame_offset += vfs_read_retval;
340
341 if (vfs_read_retval < line_size) {
342 printk(KERN_INFO
343 "Done: exit %s() since no more bytes to read from Video file.\n",
344 __func__);
345 break;
346 }
347 }
348
349 if (i > 0)
350 dev->_frame_count_ch2++;
351
352 dev->_file_status_ch2 =
353 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
354
355 set_fs(old_fs);
356 filp_close(myfile, NULL);
357 }
358
359 return 0;
360 }
361
362 static void cx25821_vidups_handler_ch2(struct work_struct *work)
363 {
364 struct cx25821_dev *dev =
365 container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
366
367 if (!dev) {
368 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
369 __func__);
370 return;
371 }
372
373 cx25821_get_frame_ch2(dev,
374 &dev->sram_channels[dev->
375 _channel2_upstream_select]);
376 }
377
378 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
379 {
380 struct file *myfile;
381 int i = 0, j = 0;
382 int line_size =
383 (dev->_pixel_format_ch2 ==
384 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
385 ssize_t vfs_read_retval = 0;
386 char mybuf[line_size];
387 loff_t pos;
388 loff_t offset = (unsigned long)0;
389 mm_segment_t old_fs;
390
391 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
392
393 if (IS_ERR(myfile)) {
394 const int open_errno = -PTR_ERR(myfile);
395 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
396 __func__, dev->_filename_ch2, open_errno);
397 return PTR_ERR(myfile);
398 } else {
399 if (!(myfile->f_op)) {
400 printk("%s: File has no file operations registered!",
401 __func__);
402 filp_close(myfile, NULL);
403 return -EIO;
404 }
405
406 if (!myfile->f_op->read) {
407 printk
408 ("%s: File has no READ operations registered! Returning.",
409 __func__);
410 filp_close(myfile, NULL);
411 return -EIO;
412 }
413
414 pos = myfile->f_pos;
415 old_fs = get_fs();
416 set_fs(KERNEL_DS);
417
418 for (j = 0; j < NUM_FRAMES; j++) {
419 for (i = 0; i < dev->_lines_count_ch2; i++) {
420 pos = offset;
421
422 vfs_read_retval =
423 vfs_read(myfile, mybuf, line_size, &pos);
424
425 if (vfs_read_retval > 0
426 && vfs_read_retval == line_size
427 && dev->_data_buf_virt_addr_ch2 != NULL) {
428 memcpy((void *)(dev->
429 _data_buf_virt_addr_ch2
430 + offset / 4), mybuf,
431 vfs_read_retval);
432 }
433
434 offset += vfs_read_retval;
435
436 if (vfs_read_retval < line_size) {
437 printk(KERN_INFO
438 "Done: exit %s() since no more bytes to read from Video file.\n",
439 __func__);
440 break;
441 }
442 }
443
444 if (i > 0)
445 dev->_frame_count_ch2++;
446
447 if (vfs_read_retval < line_size) {
448 break;
449 }
450 }
451
452 dev->_file_status_ch2 =
453 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
454
455 set_fs(old_fs);
456 myfile->f_pos = 0;
457 filp_close(myfile, NULL);
458 }
459
460 return 0;
461 }
462
463 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
464 struct sram_channel *sram_ch,
465 int bpl)
466 {
467 int ret = 0;
468 dma_addr_t dma_addr;
469 dma_addr_t data_dma_addr;
470
471 if (dev->_dma_virt_addr_ch2 != NULL) {
472 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
473 dev->_dma_virt_addr_ch2,
474 dev->_dma_phys_addr_ch2);
475 }
476
477 dev->_dma_virt_addr_ch2 =
478 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
479 &dma_addr);
480 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
481 dev->_dma_phys_start_addr_ch2 = dma_addr;
482 dev->_dma_phys_addr_ch2 = dma_addr;
483 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
484
485 if (!dev->_dma_virt_addr_ch2) {
486 printk
487 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
488 return -ENOMEM;
489 }
490
491 //Iniitize at this address until n bytes to 0
492 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
493
494 if (dev->_data_buf_virt_addr_ch2 != NULL) {
495 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
496 dev->_data_buf_virt_addr_ch2,
497 dev->_data_buf_phys_addr_ch2);
498 }
499 //For Video Data buffer allocation
500 dev->_data_buf_virt_addr_ch2 =
501 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
502 &data_dma_addr);
503 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
504 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
505
506 if (!dev->_data_buf_virt_addr_ch2) {
507 printk
508 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
509 return -ENOMEM;
510 }
511
512 //Initialize at this address until n bytes to 0
513 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
514
515 ret = cx25821_openfile_ch2(dev, sram_ch);
516 if (ret < 0)
517 return ret;
518
519 //Creating RISC programs
520 ret =
521 cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
522 dev->_lines_count_ch2);
523 if (ret < 0) {
524 printk(KERN_INFO
525 "cx25821: Failed creating Video Upstream Risc programs! \n");
526 goto error;
527 }
528
529 return 0;
530
531 error:
532 return ret;
533 }
534
535 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
536 u32 status)
537 {
538 u32 int_msk_tmp;
539 struct sram_channel *channel = &dev->sram_channels[chan_num];
540 int singlefield_lines = NTSC_FIELD_HEIGHT;
541 int line_size_in_bytes = Y422_LINE_SZ;
542 int odd_risc_prog_size = 0;
543 dma_addr_t risc_phys_jump_addr;
544 __le32 *rp;
545
546 if (status & FLD_VID_SRC_RISC1) {
547 // We should only process one program per call
548 u32 prog_cnt = cx_read(channel->gpcnt);
549
550 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
551 int_msk_tmp = cx_read(channel->int_msk);
552 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
553 cx_write(channel->int_stat, _intr_msk);
554
555 spin_lock(&dev->slock);
556
557 dev->_frame_index_ch2 = prog_cnt;
558
559 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
560
561 if (dev->_is_first_frame_ch2) {
562 dev->_is_first_frame_ch2 = 0;
563
564 if (dev->_isNTSC_ch2) {
565 singlefield_lines += 1;
566 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
567 } else {
568 singlefield_lines = PAL_FIELD_HEIGHT;
569 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
570 }
571
572 if (dev->_dma_virt_start_addr_ch2 != NULL) {
573 line_size_in_bytes =
574 (dev->_pixel_format_ch2 ==
575 PIXEL_FRMT_411) ? Y411_LINE_SZ :
576 Y422_LINE_SZ;
577 risc_phys_jump_addr =
578 dev->_dma_phys_start_addr_ch2 +
579 odd_risc_prog_size;
580
581 rp = cx25821_update_riscprogram_ch2(dev,
582 dev->
583 _dma_virt_start_addr_ch2,
584 TOP_OFFSET,
585 line_size_in_bytes,
586 0x0,
587 singlefield_lines,
588 FIFO_DISABLE,
589 ODD_FIELD);
590
591 // Jump to Even Risc program of 1st Frame
592 *(rp++) = cpu_to_le32(RISC_JUMP);
593 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
594 *(rp++) = cpu_to_le32(0);
595 }
596 }
597
598 spin_unlock(&dev->slock);
599 }
600
601 if (dev->_file_status_ch2 == END_OF_FILE) {
602 printk("cx25821: EOF Channel 2 Framecount = %d\n",
603 dev->_frame_count_ch2);
604 return -1;
605 }
606 //ElSE, set the interrupt mask register, re-enable irq.
607 int_msk_tmp = cx_read(channel->int_msk);
608 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
609
610 return 0;
611 }
612
613 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
614 {
615 struct cx25821_dev *dev = dev_id;
616 u32 msk_stat, vid_status;
617 int handled = 0;
618 int channel_num = 0;
619 struct sram_channel *sram_ch;
620
621 if (!dev)
622 return -1;
623
624 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
625
626 sram_ch = &dev->sram_channels[channel_num];
627
628 msk_stat = cx_read(sram_ch->int_mstat);
629 vid_status = cx_read(sram_ch->int_stat);
630
631 // Only deal with our interrupt
632 if (vid_status) {
633 handled =
634 cx25821_video_upstream_irq_ch2(dev, channel_num,
635 vid_status);
636 }
637
638 if (handled < 0) {
639 cx25821_stop_upstream_video_ch2(dev);
640 } else {
641 handled += handled;
642 }
643
644 return IRQ_RETVAL(handled);
645 }
646
647 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
648 struct sram_channel *ch, int pix_format)
649 {
650 int width = WIDTH_D1;
651 int height = dev->_lines_count_ch2;
652 int num_lines, odd_num_lines;
653 u32 value;
654 int vip_mode = PIXEL_ENGINE_VIP1;
655
656 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
657 value &= 0xFFFFFFEF;
658 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
659 cx_write(ch->vid_fmt_ctl, value);
660
661 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
662 cx_write(ch->vid_active_ctl1, width);
663
664 num_lines = (height / 2) & 0x3FF;
665 odd_num_lines = num_lines;
666
667 if (dev->_isNTSC_ch2) {
668 odd_num_lines += 1;
669 }
670
671 value = (num_lines << 16) | odd_num_lines;
672
673 // set number of active lines in field 0 (top) and field 1 (bottom)
674 cx_write(ch->vid_active_ctl2, value);
675
676 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
677 }
678
679 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
680 struct sram_channel *sram_ch)
681 {
682 u32 tmp = 0;
683 int err = 0;
684
685 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
686 tmp = cx_read(VID_CH_MODE_SEL);
687 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
688
689 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
690 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
691 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
692
693 /* reset counter */
694 cx_write(sram_ch->gpcnt_ctl, 3);
695
696 // Clear our bits from the interrupt status register.
697 cx_write(sram_ch->int_stat, _intr_msk);
698
699 //Set the interrupt mask register, enable irq.
700 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
701 tmp = cx_read(sram_ch->int_msk);
702 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
703
704 err =
705 request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
706 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
707 if (err < 0) {
708 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
709 dev->pci->irq);
710 goto fail_irq;
711 }
712 // Start the DMA engine
713 tmp = cx_read(sram_ch->dma_ctl);
714 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
715
716 dev->_is_running_ch2 = 1;
717 dev->_is_first_frame_ch2 = 1;
718
719 return 0;
720
721 fail_irq:
722 cx25821_dev_unregister(dev);
723 return err;
724 }
725
726 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
727 int pixel_format)
728 {
729 struct sram_channel *sram_ch;
730 u32 tmp;
731 int retval = 0;
732 int err = 0;
733 int data_frame_size = 0;
734 int risc_buffer_size = 0;
735 int str_length = 0;
736
737 if (dev->_is_running_ch2) {
738 printk("Video Channel is still running so return!\n");
739 return 0;
740 }
741
742 dev->_channel2_upstream_select = channel_select;
743 sram_ch = &dev->sram_channels[channel_select];
744
745 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
746 dev->_irq_queues_ch2 =
747 create_singlethread_workqueue("cx25821_workqueue2");
748
749 if (!dev->_irq_queues_ch2) {
750 printk
751 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
752 return -ENOMEM;
753 }
754 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
755 tmp = cx_read(VID_CH_MODE_SEL);
756 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
757
758 dev->_is_running_ch2 = 0;
759 dev->_frame_count_ch2 = 0;
760 dev->_file_status_ch2 = RESET_STATUS;
761 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
762 dev->_pixel_format_ch2 = pixel_format;
763 dev->_line_size_ch2 =
764 (dev->_pixel_format_ch2 ==
765 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
766 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
767 risc_buffer_size =
768 dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
769
770 if (dev->input_filename_ch2) {
771 str_length = strlen(dev->input_filename_ch2);
772 dev->_filename_ch2 =
773 (char *)kmalloc(str_length + 1, GFP_KERNEL);
774
775 if (!dev->_filename_ch2)
776 goto error;
777
778 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
779 str_length + 1);
780 } else {
781 str_length = strlen(dev->_defaultname_ch2);
782 dev->_filename_ch2 =
783 (char *)kmalloc(str_length + 1, GFP_KERNEL);
784
785 if (!dev->_filename_ch2)
786 goto error;
787
788 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
789 str_length + 1);
790 }
791
792 //Default if filename is empty string
793 if (strcmp(dev->input_filename_ch2, "") == 0) {
794 if (dev->_isNTSC_ch2) {
795 dev->_filename_ch2 =
796 (dev->_pixel_format_ch2 ==
797 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
798 "/root/vidtest.yuv";
799 } else {
800 dev->_filename_ch2 =
801 (dev->_pixel_format_ch2 ==
802 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
803 "/root/pal422.yuv";
804 }
805 }
806
807 retval =
808 cx25821_sram_channel_setup_upstream(dev, sram_ch,
809 dev->_line_size_ch2, 0);
810
811 /* setup fifo + format */
812 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
813
814 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
815 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
816
817 //Allocating buffers and prepare RISC program
818 retval =
819 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
820 dev->_line_size_ch2);
821 if (retval < 0) {
822 printk(KERN_ERR
823 "%s: Failed to set up Video upstream buffers!\n",
824 dev->name);
825 goto error;
826 }
827
828 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
829
830 return 0;
831
832 error:
833 cx25821_dev_unregister(dev);
834
835 return err;
836 }
Linux on s3c2412 based picture frames