AT91: Added a generic way to setup AT91 serial ports in Kconfig
[linux-2.6/pdupreez.git] / arch / arm / mach-at91 / board-yl-9200.c
blob2e6d5c7ffcb856b9f12f5b24bbf3650298c4741e
1 /*
2 * linux/arch/arm/mach-at91/board-yl-9200.c
4 * Adapted from various board files in arch/arm/mach-at91
6 * Modifications for YL-9200 platform:
7 * Copyright (C) 2007 S. Birtles
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/types.h>
25 #include <linux/init.h>
26 #include <linux/mm.h>
27 #include <linux/module.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/platform_device.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/ads7846.h>
32 #include <linux/mtd/physmap.h>
33 #include <linux/gpio_keys.h>
34 #include <linux/input.h>
36 #include <mach/hardware.h>
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/irq.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/irq.h>
45 #include <mach/board.h>
46 #include <mach/gpio.h>
47 #include <mach/at91rm9200_mc.h>
49 #include "generic.h"
52 static void __init yl9200_map_io(void)
54 /* Initialize processor: 18.432 MHz crystal */
55 at91rm9200_initialize(18432000, AT91RM9200_PQFP);
57 /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
58 at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
60 /* Setup the serial ports and console */
61 at91_init_uarts();
64 static void __init yl9200_init_irq(void)
66 at91rm9200_init_interrupts(NULL);
71 * LEDs
73 static struct gpio_led yl9200_leds[] = {
74 { /* D2 */
75 .name = "led2",
76 .gpio = AT91_PIN_PB17,
77 .active_low = 1,
78 .default_trigger = "timer",
80 { /* D3 */
81 .name = "led3",
82 .gpio = AT91_PIN_PB16,
83 .active_low = 1,
84 .default_trigger = "heartbeat",
86 { /* D4 */
87 .name = "led4",
88 .gpio = AT91_PIN_PB15,
89 .active_low = 1,
91 { /* D5 */
92 .name = "led5",
93 .gpio = AT91_PIN_PB8,
94 .active_low = 1,
99 * Ethernet
101 static struct at91_eth_data __initdata yl9200_eth_data = {
102 .phy_irq_pin = AT91_PIN_PB28,
103 .is_rmii = 1,
107 * USB Host
109 static struct at91_usbh_data __initdata yl9200_usbh_data = {
110 .ports = 1, /* PQFP version of AT91RM9200 */
114 * USB Device
116 static struct at91_udc_data __initdata yl9200_udc_data = {
117 .pullup_pin = AT91_PIN_PC4,
118 .vbus_pin = AT91_PIN_PC5,
119 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
124 * MMC
126 static struct at91_mmc_data __initdata yl9200_mmc_data = {
127 .det_pin = AT91_PIN_PB9,
128 // .wp_pin = ... not connected
129 .wire4 = 1,
133 * NAND Flash
135 static struct mtd_partition __initdata yl9200_nand_partition[] = {
137 .name = "AT91 NAND partition 1, boot",
138 .offset = 0,
139 .size = 1 * SZ_256K
142 .name = "AT91 NAND partition 2, kernel",
143 .offset = 1 * SZ_256K,
144 .size = 2 * SZ_1M - 1 * SZ_256K
147 .name = "AT91 NAND partition 3, filesystem",
148 .offset = 2 * SZ_1M,
149 .size = 14 * SZ_1M
152 .name = "AT91 NAND partition 4, storage",
153 .offset = 16 * SZ_1M,
154 .size = 16 * SZ_1M
157 .name = "AT91 NAND partition 5, ext-fs",
158 .offset = 32 * SZ_1M,
159 .size = 32 * SZ_1M
163 static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
165 *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
166 return yl9200_nand_partition;
169 static struct atmel_nand_data __initdata yl9200_nand_data = {
170 .ale = 6,
171 .cle = 7,
172 // .det_pin = ... not connected
173 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
174 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
175 .partition_info = nand_partitions,
179 * NOR Flash
181 #define YL9200_FLASH_BASE AT91_CHIPSELECT_0
182 #define YL9200_FLASH_SIZE 0x1000000
184 static struct mtd_partition yl9200_flash_partitions[] = {
186 .name = "Bootloader",
187 .size = 0x00040000,
188 .offset = 0,
189 .mask_flags = MTD_WRITEABLE, /* force read-only */
192 .name = "Kernel",
193 .size = 0x001C0000,
194 .offset = 0x00040000,
197 .name = "Filesystem",
198 .size = MTDPART_SIZ_FULL,
199 .offset = 0x00200000
203 static struct physmap_flash_data yl9200_flash_data = {
204 .width = 2,
205 .parts = yl9200_flash_partitions,
206 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
209 static struct resource yl9200_flash_resources[] = {
211 .start = YL9200_FLASH_BASE,
212 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
213 .flags = IORESOURCE_MEM,
217 static struct platform_device yl9200_flash = {
218 .name = "physmap-flash",
219 .id = 0,
220 .dev = {
221 .platform_data = &yl9200_flash_data,
223 .resource = yl9200_flash_resources,
224 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
228 * I2C (TWI)
230 static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
231 { /* EEPROM */
232 I2C_BOARD_INFO("24c128", 0x50),
237 * GPIO Buttons
239 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
240 static struct gpio_keys_button yl9200_buttons[] = {
242 .gpio = AT91_PIN_PA24,
243 .code = BTN_2,
244 .desc = "SW2",
245 .active_low = 1,
246 .wakeup = 1,
249 .gpio = AT91_PIN_PB1,
250 .code = BTN_3,
251 .desc = "SW3",
252 .active_low = 1,
253 .wakeup = 1,
256 .gpio = AT91_PIN_PB2,
257 .code = BTN_4,
258 .desc = "SW4",
259 .active_low = 1,
260 .wakeup = 1,
263 .gpio = AT91_PIN_PB6,
264 .code = BTN_5,
265 .desc = "SW5",
266 .active_low = 1,
267 .wakeup = 1,
271 static struct gpio_keys_platform_data yl9200_button_data = {
272 .buttons = yl9200_buttons,
273 .nbuttons = ARRAY_SIZE(yl9200_buttons),
276 static struct platform_device yl9200_button_device = {
277 .name = "gpio-keys",
278 .id = -1,
279 .num_resources = 0,
280 .dev = {
281 .platform_data = &yl9200_button_data,
285 static void __init yl9200_add_device_buttons(void)
287 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
288 at91_set_deglitch(AT91_PIN_PA24, 1);
289 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
290 at91_set_deglitch(AT91_PIN_PB1, 1);
291 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
292 at91_set_deglitch(AT91_PIN_PB2, 1);
293 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
294 at91_set_deglitch(AT91_PIN_PB6, 1);
296 /* Enable buttons (Sheet 5) */
297 at91_set_gpio_output(AT91_PIN_PB7, 1);
299 platform_device_register(&yl9200_button_device);
301 #else
302 static void __init yl9200_add_device_buttons(void) {}
303 #endif
306 * Touchscreen
308 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
309 static int ads7843_pendown_state(void)
311 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
314 static struct ads7846_platform_data ads_info = {
315 .model = 7843,
316 .x_min = 150,
317 .x_max = 3830,
318 .y_min = 190,
319 .y_max = 3830,
320 .vref_delay_usecs = 100,
322 /* For a 8" touch-screen */
323 // .x_plate_ohms = 603,
324 // .y_plate_ohms = 332,
326 /* For a 10.4" touch-screen */
327 // .x_plate_ohms = 611,
328 // .y_plate_ohms = 325,
330 .x_plate_ohms = 576,
331 .y_plate_ohms = 366,
333 .pressure_max = 15000, /* generally nonsense on the 7843 */
334 .debounce_max = 1,
335 .debounce_rep = 0,
336 .debounce_tol = (~0),
337 .get_pendown_state = ads7843_pendown_state,
340 static void __init yl9200_add_device_ts(void)
342 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
343 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
345 #else
346 static void __init yl9200_add_device_ts(void) {}
347 #endif
350 * SPI devices
352 static struct spi_board_info yl9200_spi_devices[] = {
353 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
354 { /* Touchscreen */
355 .modalias = "ads7846",
356 .chip_select = 0,
357 .max_speed_hz = 5000 * 26,
358 .platform_data = &ads_info,
359 .irq = AT91_PIN_PB11,
361 #endif
362 { /* CAN */
363 .modalias = "mcp2510",
364 .chip_select = 1,
365 .max_speed_hz = 25000 * 26,
366 .irq = AT91_PIN_PC0,
371 * LCD / VGA
373 * EPSON S1D13806 FB (discontinued chip)
374 * EPSON S1D13506 FB
376 #if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
377 #include <video/s1d13xxxfb.h>
379 #define AT91_FB_REG_BASE 0x80000000L
380 #define AT91_FB_REG_SIZE 0x200
381 #define AT91_FB_VMEM_BASE 0x80200000L
382 #define AT91_FB_VMEM_SIZE 0x200000L
384 static void __init yl9200_init_video(void)
386 /* NWAIT Signal */
387 at91_set_A_periph(AT91_PIN_PC6, 0);
389 /* Initialization of the Static Memory Controller for Chip Select 2 */
390 at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
391 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
392 | AT91_SMC_TDF_(0x100) /* float time */
396 static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
398 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
399 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
400 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
401 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
402 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
403 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
404 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
405 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
406 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
407 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
408 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
409 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
410 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
411 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
412 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
413 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
414 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
415 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
416 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
417 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
418 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
419 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
420 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
421 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
422 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
423 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
424 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
425 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
426 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
427 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
428 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
429 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
430 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
431 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
432 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
433 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
434 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
435 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
436 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
437 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
438 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
439 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
440 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
441 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
442 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
443 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
444 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
445 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
446 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
447 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
448 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
449 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
450 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
451 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
452 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
453 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
454 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
455 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
456 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
457 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
458 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
459 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
460 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
461 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
462 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
463 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
464 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
465 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
466 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
467 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
468 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
469 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
470 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
471 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
472 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
473 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
474 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
475 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
476 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
477 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
478 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
479 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
480 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
481 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
482 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
483 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
484 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
485 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
486 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
487 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
488 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
489 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
490 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
491 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
492 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
493 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
494 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
495 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
496 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
497 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
498 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
499 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
500 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
501 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
502 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
505 static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
507 static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
508 .initregs = yl9200_s1dfb_initregs,
509 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
510 .platform_init_video = yl9200_init_video,
513 static struct resource yl9200_s1dfb_resource[] = {
514 [0] = { /* video mem */
515 .name = "s1d13xxxfb memory",
516 .start = AT91_FB_VMEM_BASE,
517 .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
518 .flags = IORESOURCE_MEM,
520 [1] = { /* video registers */
521 .name = "s1d13xxxfb registers",
522 .start = AT91_FB_REG_BASE,
523 .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
524 .flags = IORESOURCE_MEM,
528 static struct platform_device yl9200_s1dfb_device = {
529 .name = "s1d13806fb",
530 .id = -1,
531 .dev = {
532 .dma_mask = &s1dfb_dmamask,
533 .coherent_dma_mask = DMA_BIT_MASK(32),
534 .platform_data = &yl9200_s1dfb_pdata,
536 .resource = yl9200_s1dfb_resource,
537 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
540 void __init yl9200_add_device_video(void)
542 platform_device_register(&yl9200_s1dfb_device);
544 #else
545 void __init yl9200_add_device_video(void) {}
546 #endif
549 static void __init yl9200_board_init(void)
551 /* Serial */
552 at91_add_device_serial();
553 /* Ethernet */
554 at91_add_device_eth(&yl9200_eth_data);
555 /* USB Host */
556 at91_add_device_usbh(&yl9200_usbh_data);
557 /* USB Device */
558 at91_add_device_udc(&yl9200_udc_data);
559 /* I2C */
560 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
561 /* MMC */
562 at91_add_device_mmc(0, &yl9200_mmc_data);
563 /* NAND */
564 at91_add_device_nand(&yl9200_nand_data);
565 /* NOR Flash */
566 platform_device_register(&yl9200_flash);
567 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
568 /* SPI */
569 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
570 /* Touchscreen */
571 yl9200_add_device_ts();
572 #endif
573 /* LEDs. */
574 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
575 /* Push Buttons */
576 yl9200_add_device_buttons();
577 /* VGA */
578 yl9200_add_device_video();
581 MACHINE_START(YL9200, "uCdragon YL-9200")
582 /* Maintainer: S.Birtles */
583 .phys_io = AT91_BASE_SYS,
584 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
585 .boot_params = AT91_SDRAM_BASE + 0x100,
586 .timer = &at91rm9200_timer,
587 .map_io = yl9200_map_io,
588 .init_irq = yl9200_init_irq,
589 .init_machine = yl9200_board_init,
590 MACHINE_END