arch/avr32/mach-at32ap/include/mach/at32ap700x.h

   1 /*
   2  * Pin definitions for AT32AP7000.
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef __ASM_ARCH_AT32AP700X_H__
  11 #define __ASM_ARCH_AT32AP700X_H__
  12
  13 #define GPIO_PERIPH_A   0
  14 #define GPIO_PERIPH_B   1
  15
  16 /*
  17  * Pin numbers identifying specific GPIO pins on the chip. They can
  18  * also be converted to IRQ numbers by passing them through
  19  * gpio_to_irq().
  20  */
  21 #define GPIO_PIOA_BASE  (0)
  22 #define GPIO_PIOB_BASE  (GPIO_PIOA_BASE + 32)
  23 #define GPIO_PIOC_BASE  (GPIO_PIOB_BASE + 32)
  24 #define GPIO_PIOD_BASE  (GPIO_PIOC_BASE + 32)
  25 #define GPIO_PIOE_BASE  (GPIO_PIOD_BASE + 32)
  26
  27 #define GPIO_PIN_PA(N)  (GPIO_PIOA_BASE + (N))
  28 #define GPIO_PIN_PB(N)  (GPIO_PIOB_BASE + (N))
  29 #define GPIO_PIN_PC(N)  (GPIO_PIOC_BASE + (N))
  30 #define GPIO_PIN_PD(N)  (GPIO_PIOD_BASE + (N))
  31 #define GPIO_PIN_PE(N)  (GPIO_PIOE_BASE + (N))
  32
  33
  34 /*
  35  * DMAC peripheral hardware handshaking interfaces, used with dw_dmac
  36  */
  37 #define DMAC_MCI_RX             0
  38 #define DMAC_MCI_TX             1
  39 #define DMAC_DAC_TX             2
  40 #define DMAC_AC97_A_RX          3
  41 #define DMAC_AC97_A_TX          4
  42 #define DMAC_AC97_B_RX          5
  43 #define DMAC_AC97_B_TX          6
  44 #define DMAC_DMAREQ_0           7
  45 #define DMAC_DMAREQ_1           8
  46 #define DMAC_DMAREQ_2           9
  47 #define DMAC_DMAREQ_3           10
  48
  49 /* HSB master IDs */
  50 #define HMATRIX_MASTER_CPU_DCACHE               0
  51 #define HMATRIX_MASTER_CPU_ICACHE               1
  52 #define HMATRIX_MASTER_PDC                      2
  53 #define HMATRIX_MASTER_ISI                      3
  54 #define HMATRIX_MASTER_USBA                     4
  55 #define HMATRIX_MASTER_LCDC                     5
  56 #define HMATRIX_MASTER_MACB0                    6
  57 #define HMATRIX_MASTER_MACB1                    7
  58 #define HMATRIX_MASTER_DMACA_M0                 8
  59 #define HMATRIX_MASTER_DMACA_M1                 9
  60
  61 /* HSB slave IDs */
  62 #define HMATRIX_SLAVE_SRAM0                     0
  63 #define HMATRIX_SLAVE_SRAM1                     1
  64 #define HMATRIX_SLAVE_PBA                       2
  65 #define HMATRIX_SLAVE_PBB                       3
  66 #define HMATRIX_SLAVE_EBI                       4
  67 #define HMATRIX_SLAVE_USBA                      5
  68 #define HMATRIX_SLAVE_LCDC                      6
  69 #define HMATRIX_SLAVE_DMACA                     7
  70
  71 /* Bits in HMATRIX SFR4 (EBI) */
  72 #define HMATRIX_EBI_SDRAM_ENABLE                (1 << 1)
  73 #define HMATRIX_EBI_NAND_ENABLE                 (1 << 3)
  74 #define HMATRIX_EBI_CF0_ENABLE                  (1 << 4)
  75 #define HMATRIX_EBI_CF1_ENABLE                  (1 << 5)
  76 #define HMATRIX_EBI_PULLUP_DISABLE              (1 << 8)
  77
  78 /*
  79  * Base addresses of controllers that may be accessed early by
  80  * platform code.
  81  */
  82 #define PM_BASE         0xfff00000
  83 #define HMATRIX_BASE    0xfff00800
  84 #define SDRAMC_BASE     0xfff03800
  85
  86 #endif /* __ASM_ARCH_AT32AP700X_H__ */