arch/mips/kernel/spram.c

   1 /*
   2  * MIPS SPRAM support
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  *
   9  * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/ptrace.h>
  14 #include <linux/stddef.h>
  15
  16 #include <asm/cpu.h>
  17 #include <asm/fpu.h>
  18 #include <asm/mipsregs.h>
  19 #include <asm/system.h>
  20 #include <asm/r4kcache.h>
  21 #include <asm/hazards.h>
  22
  23 /*
  24  * These definitions are correct for the 24K/34K/74K SPRAM sample
  25  * implementation. The 4KS interpreted the tags differently...
  26  */
  27 #define SPRAM_TAG0_ENABLE       0x00000080
  28 #define SPRAM_TAG0_PA_MASK      0xfffff000
  29 #define SPRAM_TAG1_SIZE_MASK    0xfffff000
  30
  31 #define SPRAM_TAG_STRIDE        8
  32
  33 #define ERRCTL_SPRAM            (1 << 28)
  34
  35 /* errctl access */
  36 #define read_c0_errctl(x) read_c0_ecc(x)
  37 #define write_c0_errctl(x) write_c0_ecc(x)
  38
  39 /*
  40  * Different semantics to the set_c0_* function built by __BUILD_SET_C0
  41  */
  42 static __cpuinit unsigned int bis_c0_errctl(unsigned int set)
  43 {
  44         unsigned int res;
  45         res = read_c0_errctl();
  46         write_c0_errctl(res | set);
  47         return res;
  48 }
  49
  50 static __cpuinit void ispram_store_tag(unsigned int offset, unsigned int data)
  51 {
  52         unsigned int errctl;
  53
  54         /* enable SPRAM tag access */
  55         errctl = bis_c0_errctl(ERRCTL_SPRAM);
  56         ehb();
  57
  58         write_c0_taglo(data);
  59         ehb();
  60
  61         cache_op(Index_Store_Tag_I, CKSEG0|offset);
  62         ehb();
  63
  64         write_c0_errctl(errctl);
  65         ehb();
  66 }
  67
  68
  69 static __cpuinit unsigned int ispram_load_tag(unsigned int offset)
  70 {
  71         unsigned int data;
  72         unsigned int errctl;
  73
  74         /* enable SPRAM tag access */
  75         errctl = bis_c0_errctl(ERRCTL_SPRAM);
  76         ehb();
  77         cache_op(Index_Load_Tag_I, CKSEG0 | offset);
  78         ehb();
  79         data = read_c0_taglo();
  80         ehb();
  81         write_c0_errctl(errctl);
  82         ehb();
  83
  84         return data;
  85 }
  86
  87 static __cpuinit void dspram_store_tag(unsigned int offset, unsigned int data)
  88 {
  89         unsigned int errctl;
  90
  91         /* enable SPRAM tag access */
  92         errctl = bis_c0_errctl(ERRCTL_SPRAM);
  93         ehb();
  94         write_c0_dtaglo(data);
  95         ehb();
  96         cache_op(Index_Store_Tag_D, CKSEG0 | offset);
  97         ehb();
  98         write_c0_errctl(errctl);
  99         ehb();
 100 }
 101
 102
 103 static __cpuinit unsigned int dspram_load_tag(unsigned int offset)
 104 {
 105         unsigned int data;
 106         unsigned int errctl;
 107
 108         errctl = bis_c0_errctl(ERRCTL_SPRAM);
 109         ehb();
 110         cache_op(Index_Load_Tag_D, CKSEG0 | offset);
 111         ehb();
 112         data = read_c0_dtaglo();
 113         ehb();
 114         write_c0_errctl(errctl);
 115         ehb();
 116
 117         return data;
 118 }
 119
 120 static __cpuinit void probe_spram(char *type,
 121             unsigned int base,
 122             unsigned int (*read)(unsigned int),
 123             void (*write)(unsigned int, unsigned int))
 124 {
 125         unsigned int firstsize = 0, lastsize = 0;
 126         unsigned int firstpa = 0, lastpa = 0, pa = 0;
 127         unsigned int offset = 0;
 128         unsigned int size, tag0, tag1;
 129         unsigned int enabled;
 130         int i;
 131
 132         /*
 133          * The limit is arbitrary but avoids the loop running away if
 134          * the SPRAM tags are implemented differently
 135          */
 136
 137         for (i = 0; i < 8; i++) {
 138                 tag0 = read(offset);
 139                 tag1 = read(offset+SPRAM_TAG_STRIDE);
 140                 pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
 141                          type, i, tag0, tag1);
 142
 143                 size = tag1 & SPRAM_TAG1_SIZE_MASK;
 144
 145                 if (size == 0)
 146                         break;
 147
 148                 if (i != 0) {
 149                         /* tags may repeat... */
 150                         if ((pa == firstpa && size == firstsize) ||
 151                             (pa == lastpa && size == lastsize))
 152                                 break;
 153                 }
 154
 155                 /* Align base with size */
 156                 base = (base + size - 1) & ~(size-1);
 157
 158                 /* reprogram the base address base address and enable */
 159                 tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
 160                 write(offset, tag0);
 161
 162                 base += size;
 163
 164                 /* reread the tag */
 165                 tag0 = read(offset);
 166                 pa = tag0 & SPRAM_TAG0_PA_MASK;
 167                 enabled = tag0 & SPRAM_TAG0_ENABLE;
 168
 169                 if (i == 0) {
 170                         firstpa = pa;
 171                         firstsize = size;
 172                 }
 173
 174                 lastpa = pa;
 175                 lastsize = size;
 176
 177                 if (strcmp(type, "DSPRAM") == 0) {
 178                         unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
 179                         unsigned int v;
 180 #define TDAT    0x5a5aa5a5
 181                         vp[0] = TDAT;
 182                         vp[1] = ~TDAT;
 183
 184                         mb();
 185
 186                         v = vp[0];
 187                         if (v != TDAT)
 188                                 printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
 189                                        vp, TDAT, v);
 190                         v = vp[1];
 191                         if (v != ~TDAT)
 192                                 printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
 193                                        vp+1, ~TDAT, v);
 194                 }
 195
 196                 pr_info("%s%d: PA=%08x,Size=%08x%s\n",
 197                         type, i, pa, size, enabled ? ",enabled" : "");
 198                 offset += 2 * SPRAM_TAG_STRIDE;
 199         }
 200 }
 201
 202 __cpuinit void spram_config(void)
 203 {
 204         struct cpuinfo_mips *c = &current_cpu_data;
 205         unsigned int config0;
 206
 207         switch (c->cputype) {
 208         case CPU_24K:
 209         case CPU_34K:
 210         case CPU_74K:
 211                 config0 = read_c0_config();
 212                 /* FIXME: addresses are Malta specific */
 213                 if (config0 & (1<<24)) {
 214                         probe_spram("ISPRAM", 0x1c000000,
 215                                     &ispram_load_tag, &ispram_store_tag);
 216                 }
 217                 if (config0 & (1<<23))
 218                         probe_spram("DSPRAM", 0x1c100000,
 219                                     &dspram_load_tag, &dspram_store_tag);
 220         }
 221 }