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AT91: Added a generic way to setup AT91 serial ports in Kconfig
[linux-2.6/pdupreez.git] / arch / mips / kernel / traps.c
blobb602ac6eb47d8a41454d0bd5e48b7931d6f4ee7f
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28
29 #include <asm/bootinfo.h>
30 #include <asm/branch.h>
31 #include <asm/break.h>
32 #include <asm/cpu.h>
33 #include <asm/dsp.h>
34 #include <asm/fpu.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mipsmtregs.h>
37 #include <asm/module.h>
38 #include <asm/pgtable.h>
39 #include <asm/ptrace.h>
40 #include <asm/sections.h>
41 #include <asm/system.h>
42 #include <asm/tlbdebug.h>
43 #include <asm/traps.h>
44 #include <asm/uaccess.h>
45 #include <asm/mmu_context.h>
46 #include <asm/types.h>
47 #include <asm/stacktrace.h>
48
49 extern void check_wait(void);
50 extern asmlinkage void r4k_wait(void);
51 extern asmlinkage void rollback_handle_int(void);
52 extern asmlinkage void handle_int(void);
53 extern asmlinkage void handle_tlbm(void);
54 extern asmlinkage void handle_tlbl(void);
55 extern asmlinkage void handle_tlbs(void);
56 extern asmlinkage void handle_adel(void);
57 extern asmlinkage void handle_ades(void);
58 extern asmlinkage void handle_ibe(void);
59 extern asmlinkage void handle_dbe(void);
60 extern asmlinkage void handle_sys(void);
61 extern asmlinkage void handle_bp(void);
62 extern asmlinkage void handle_ri(void);
63 extern asmlinkage void handle_ri_rdhwr_vivt(void);
64 extern asmlinkage void handle_ri_rdhwr(void);
65 extern asmlinkage void handle_cpu(void);
66 extern asmlinkage void handle_ov(void);
67 extern asmlinkage void handle_tr(void);
68 extern asmlinkage void handle_fpe(void);
69 extern asmlinkage void handle_mdmx(void);
70 extern asmlinkage void handle_watch(void);
71 extern asmlinkage void handle_mt(void);
72 extern asmlinkage void handle_dsp(void);
73 extern asmlinkage void handle_mcheck(void);
74 extern asmlinkage void handle_reserved(void);
75
76 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
77 struct mips_fpu_struct *ctx, int has_fpu);
78
79 void (*board_be_init)(void);
80 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
81 void (*board_nmi_handler_setup)(void);
82 void (*board_ejtag_handler_setup)(void);
83 void (*board_bind_eic_interrupt)(int irq, int regset);
84
85
86 static void show_raw_backtrace(unsigned long reg29)
87 {
88 unsigned long *sp = (unsigned long *)(reg29 & ~3);
89 unsigned long addr;
90
91 printk("Call Trace:");
92 #ifdef CONFIG_KALLSYMS
93 printk("\n");
94 #endif
95 while (!kstack_end(sp)) {
96 unsigned long __user *p =
97 (unsigned long __user *)(unsigned long)sp++;
98 if (__get_user(addr, p)) {
99 printk(" (Bad stack address)");
100 break;
101 }
102 if (__kernel_text_address(addr))
103 print_ip_sym(addr);
104 }
105 printk("\n");
106 }
107
108 #ifdef CONFIG_KALLSYMS
109 int raw_show_trace;
110 static int __init set_raw_show_trace(char *str)
111 {
112 raw_show_trace = 1;
113 return 1;
114 }
115 __setup("raw_show_trace", set_raw_show_trace);
116 #endif
117
118 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
119 {
120 unsigned long sp = regs->regs[29];
121 unsigned long ra = regs->regs[31];
122 unsigned long pc = regs->cp0_epc;
123
124 if (raw_show_trace || !__kernel_text_address(pc)) {
125 show_raw_backtrace(sp);
126 return;
127 }
128 printk("Call Trace:\n");
129 do {
130 print_ip_sym(pc);
131 pc = unwind_stack(task, &sp, pc, &ra);
132 } while (pc);
133 printk("\n");
134 }
135
136 /*
137 * This routine abuses get_user()/put_user() to reference pointers
138 * with at least a bit of error checking ...
139 */
140 static void show_stacktrace(struct task_struct *task,
141 const struct pt_regs *regs)
142 {
143 const int field = 2 * sizeof(unsigned long);
144 long stackdata;
145 int i;
146 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
147
148 printk("Stack :");
149 i = 0;
150 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
151 if (i && ((i % (64 / field)) == 0))
152 printk("\n ");
153 if (i > 39) {
154 printk(" ...");
155 break;
156 }
157
158 if (__get_user(stackdata, sp++)) {
159 printk(" (Bad stack address)");
160 break;
161 }
162
163 printk(" %0*lx", field, stackdata);
164 i++;
165 }
166 printk("\n");
167 show_backtrace(task, regs);
168 }
169
170 void show_stack(struct task_struct *task, unsigned long *sp)
171 {
172 struct pt_regs regs;
173 if (sp) {
174 regs.regs[29] = (unsigned long)sp;
175 regs.regs[31] = 0;
176 regs.cp0_epc = 0;
177 } else {
178 if (task && task != current) {
179 regs.regs[29] = task->thread.reg29;
180 regs.regs[31] = 0;
181 regs.cp0_epc = task->thread.reg31;
182 } else {
183 prepare_frametrace(&regs);
184 }
185 }
186 show_stacktrace(task, &regs);
187 }
188
189 /*
190 * The architecture-independent dump_stack generator
191 */
192 void dump_stack(void)
193 {
194 struct pt_regs regs;
195
196 prepare_frametrace(&regs);
197 show_backtrace(current, &regs);
198 }
199
200 EXPORT_SYMBOL(dump_stack);
201
202 static void show_code(unsigned int __user *pc)
203 {
204 long i;
205 unsigned short __user *pc16 = NULL;
206
207 printk("\nCode:");
208
209 if ((unsigned long)pc & 1)
210 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
211 for(i = -3 ; i < 6 ; i++) {
212 unsigned int insn;
213 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
214 printk(" (Bad address in epc)\n");
215 break;
216 }
217 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
218 }
219 }
220
221 static void __show_regs(const struct pt_regs *regs)
222 {
223 const int field = 2 * sizeof(unsigned long);
224 unsigned int cause = regs->cp0_cause;
225 int i;
226
227 printk("Cpu %d\n", smp_processor_id());
228
229 /*
230 * Saved main processor registers
231 */
232 for (i = 0; i < 32; ) {
233 if ((i % 4) == 0)
234 printk("$%2d :", i);
235 if (i == 0)
236 printk(" %0*lx", field, 0UL);
237 else if (i == 26 || i == 27)
238 printk(" %*s", field, "");
239 else
240 printk(" %0*lx", field, regs->regs[i]);
241
242 i++;
243 if ((i % 4) == 0)
244 printk("\n");
245 }
246
247 #ifdef CONFIG_CPU_HAS_SMARTMIPS
248 printk("Acx : %0*lx\n", field, regs->acx);
249 #endif
250 printk("Hi : %0*lx\n", field, regs->hi);
251 printk("Lo : %0*lx\n", field, regs->lo);
252
253 /*
254 * Saved cp0 registers
255 */
256 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
257 (void *) regs->cp0_epc);
258 printk(" %s\n", print_tainted());
259 printk("ra : %0*lx %pS\n", field, regs->regs[31],
260 (void *) regs->regs[31]);
261
262 printk("Status: %08x ", (uint32_t) regs->cp0_status);
263
264 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
265 if (regs->cp0_status & ST0_KUO)
266 printk("KUo ");
267 if (regs->cp0_status & ST0_IEO)
268 printk("IEo ");
269 if (regs->cp0_status & ST0_KUP)
270 printk("KUp ");
271 if (regs->cp0_status & ST0_IEP)
272 printk("IEp ");
273 if (regs->cp0_status & ST0_KUC)
274 printk("KUc ");
275 if (regs->cp0_status & ST0_IEC)
276 printk("IEc ");
277 } else {
278 if (regs->cp0_status & ST0_KX)
279 printk("KX ");
280 if (regs->cp0_status & ST0_SX)
281 printk("SX ");
282 if (regs->cp0_status & ST0_UX)
283 printk("UX ");
284 switch (regs->cp0_status & ST0_KSU) {
285 case KSU_USER:
286 printk("USER ");
287 break;
288 case KSU_SUPERVISOR:
289 printk("SUPERVISOR ");
290 break;
291 case KSU_KERNEL:
292 printk("KERNEL ");
293 break;
294 default:
295 printk("BAD_MODE ");
296 break;
297 }
298 if (regs->cp0_status & ST0_ERL)
299 printk("ERL ");
300 if (regs->cp0_status & ST0_EXL)
301 printk("EXL ");
302 if (regs->cp0_status & ST0_IE)
303 printk("IE ");
304 }
305 printk("\n");
306
307 printk("Cause : %08x\n", cause);
308
309 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
310 if (1 <= cause && cause <= 5)
311 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
312
313 printk("PrId : %08x (%s)\n", read_c0_prid(),
314 cpu_name_string());
315 }
316
317 /*
318 * FIXME: really the generic show_regs should take a const pointer argument.
319 */
320 void show_regs(struct pt_regs *regs)
321 {
322 __show_regs((struct pt_regs *)regs);
323 }
324
325 void show_registers(const struct pt_regs *regs)
326 {
327 const int field = 2 * sizeof(unsigned long);
328
329 __show_regs(regs);
330 print_modules();
331 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
332 current->comm, current->pid, current_thread_info(), current,
333 field, current_thread_info()->tp_value);
334 if (cpu_has_userlocal) {
335 unsigned long tls;
336
337 tls = read_c0_userlocal();
338 if (tls != current_thread_info()->tp_value)
339 printk("*HwTLS: %0*lx\n", field, tls);
340 }
341
342 show_stacktrace(current, regs);
343 show_code((unsigned int __user *) regs->cp0_epc);
344 printk("\n");
345 }
346
347 static DEFINE_SPINLOCK(die_lock);
348
349 void __noreturn die(const char * str, const struct pt_regs * regs)
350 {
351 static int die_counter;
352 #ifdef CONFIG_MIPS_MT_SMTC
353 unsigned long dvpret = dvpe();
354 #endif /* CONFIG_MIPS_MT_SMTC */
355
356 console_verbose();
357 spin_lock_irq(&die_lock);
358 bust_spinlocks(1);
359 #ifdef CONFIG_MIPS_MT_SMTC
360 mips_mt_regdump(dvpret);
361 #endif /* CONFIG_MIPS_MT_SMTC */
362 printk("%s[#%d]:\n", str, ++die_counter);
363 show_registers(regs);
364 add_taint(TAINT_DIE);
365 spin_unlock_irq(&die_lock);
366
367 if (in_interrupt())
368 panic("Fatal exception in interrupt");
369
370 if (panic_on_oops) {
371 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
372 ssleep(5);
373 panic("Fatal exception");
374 }
375
376 do_exit(SIGSEGV);
377 }
378
379 extern struct exception_table_entry __start___dbe_table[];
380 extern struct exception_table_entry __stop___dbe_table[];
381
382 __asm__(
383 " .section __dbe_table, \"a\"\n"
384 " .previous \n");
385
386 /* Given an address, look for it in the exception tables. */
387 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
388 {
389 const struct exception_table_entry *e;
390
391 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
392 if (!e)
393 e = search_module_dbetables(addr);
394 return e;
395 }
396
397 asmlinkage void do_be(struct pt_regs *regs)
398 {
399 const int field = 2 * sizeof(unsigned long);
400 const struct exception_table_entry *fixup = NULL;
401 int data = regs->cp0_cause & 4;
402 int action = MIPS_BE_FATAL;
403
404 /* XXX For now. Fixme, this searches the wrong table ... */
405 if (data && !user_mode(regs))
406 fixup = search_dbe_tables(exception_epc(regs));
407
408 if (fixup)
409 action = MIPS_BE_FIXUP;
410
411 if (board_be_handler)
412 action = board_be_handler(regs, fixup != NULL);
413
414 switch (action) {
415 case MIPS_BE_DISCARD:
416 return;
417 case MIPS_BE_FIXUP:
418 if (fixup) {
419 regs->cp0_epc = fixup->nextinsn;
420 return;
421 }
422 break;
423 default:
424 break;
425 }
426
427 /*
428 * Assume it would be too dangerous to continue ...
429 */
430 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
431 data ? "Data" : "Instruction",
432 field, regs->cp0_epc, field, regs->regs[31]);
433 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0)
434 == NOTIFY_STOP)
435 return;
436
437 die_if_kernel("Oops", regs);
438 force_sig(SIGBUS, current);
439 }
440
441 /*
442 * ll/sc, rdhwr, sync emulation
443 */
444
445 #define OPCODE 0xfc000000
446 #define BASE 0x03e00000
447 #define RT 0x001f0000
448 #define OFFSET 0x0000ffff
449 #define LL 0xc0000000
450 #define SC 0xe0000000
451 #define SPEC0 0x00000000
452 #define SPEC3 0x7c000000
453 #define RD 0x0000f800
454 #define FUNC 0x0000003f
455 #define SYNC 0x0000000f
456 #define RDHWR 0x0000003b
457
458 /*
459 * The ll_bit is cleared by r*_switch.S
460 */
461
462 unsigned long ll_bit;
463
464 static struct task_struct *ll_task = NULL;
465
466 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
467 {
468 unsigned long value, __user *vaddr;
469 long offset;
470
471 /*
472 * analyse the ll instruction that just caused a ri exception
473 * and put the referenced address to addr.
474 */
475
476 /* sign extend offset */
477 offset = opcode & OFFSET;
478 offset <<= 16;
479 offset >>= 16;
480
481 vaddr = (unsigned long __user *)
482 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
483
484 if ((unsigned long)vaddr & 3)
485 return SIGBUS;
486 if (get_user(value, vaddr))
487 return SIGSEGV;
488
489 preempt_disable();
490
491 if (ll_task == NULL || ll_task == current) {
492 ll_bit = 1;
493 } else {
494 ll_bit = 0;
495 }
496 ll_task = current;
497
498 preempt_enable();
499
500 regs->regs[(opcode & RT) >> 16] = value;
501
502 return 0;
503 }
504
505 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
506 {
507 unsigned long __user *vaddr;
508 unsigned long reg;
509 long offset;
510
511 /*
512 * analyse the sc instruction that just caused a ri exception
513 * and put the referenced address to addr.
514 */
515
516 /* sign extend offset */
517 offset = opcode & OFFSET;
518 offset <<= 16;
519 offset >>= 16;
520
521 vaddr = (unsigned long __user *)
522 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
523 reg = (opcode & RT) >> 16;
524
525 if ((unsigned long)vaddr & 3)
526 return SIGBUS;
527
528 preempt_disable();
529
530 if (ll_bit == 0 || ll_task != current) {
531 regs->regs[reg] = 0;
532 preempt_enable();
533 return 0;
534 }
535
536 preempt_enable();
537
538 if (put_user(regs->regs[reg], vaddr))
539 return SIGSEGV;
540
541 regs->regs[reg] = 1;
542
543 return 0;
544 }
545
546 /*
547 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
548 * opcodes are supposed to result in coprocessor unusable exceptions if
549 * executed on ll/sc-less processors. That's the theory. In practice a
550 * few processors such as NEC's VR4100 throw reserved instruction exceptions
551 * instead, so we're doing the emulation thing in both exception handlers.
552 */
553 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
554 {
555 if ((opcode & OPCODE) == LL)
556 return simulate_ll(regs, opcode);
557 if ((opcode & OPCODE) == SC)
558 return simulate_sc(regs, opcode);
559
560 return -1; /* Must be something else ... */
561 }
562
563 /*
564 * Simulate trapping 'rdhwr' instructions to provide user accessible
565 * registers not implemented in hardware.
566 */
567 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
568 {
569 struct thread_info *ti = task_thread_info(current);
570
571 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
572 int rd = (opcode & RD) >> 11;
573 int rt = (opcode & RT) >> 16;
574 switch (rd) {
575 case 0: /* CPU number */
576 regs->regs[rt] = smp_processor_id();
577 return 0;
578 case 1: /* SYNCI length */
579 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
580 current_cpu_data.icache.linesz);
581 return 0;
582 case 2: /* Read count register */
583 regs->regs[rt] = read_c0_count();
584 return 0;
585 case 3: /* Count register resolution */
586 switch (current_cpu_data.cputype) {
587 case CPU_20KC:
588 case CPU_25KF:
589 regs->regs[rt] = 1;
590 break;
591 default:
592 regs->regs[rt] = 2;
593 }
594 return 0;
595 case 29:
596 regs->regs[rt] = ti->tp_value;
597 return 0;
598 default:
599 return -1;
600 }
601 }
602
603 /* Not ours. */
604 return -1;
605 }
606
607 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
608 {
609 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
610 return 0;
611
612 return -1; /* Must be something else ... */
613 }
614
615 asmlinkage void do_ov(struct pt_regs *regs)
616 {
617 siginfo_t info;
618
619 die_if_kernel("Integer overflow", regs);
620
621 info.si_code = FPE_INTOVF;
622 info.si_signo = SIGFPE;
623 info.si_errno = 0;
624 info.si_addr = (void __user *) regs->cp0_epc;
625 force_sig_info(SIGFPE, &info, current);
626 }
627
628 /*
629 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
630 */
631 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
632 {
633 siginfo_t info;
634
635 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0)
636 == NOTIFY_STOP)
637 return;
638 die_if_kernel("FP exception in kernel code", regs);
639
640 if (fcr31 & FPU_CSR_UNI_X) {
641 int sig;
642
643 /*
644 * Unimplemented operation exception. If we've got the full
645 * software emulator on-board, let's use it...
646 *
647 * Force FPU to dump state into task/thread context. We're
648 * moving a lot of data here for what is probably a single
649 * instruction, but the alternative is to pre-decode the FP
650 * register operands before invoking the emulator, which seems
651 * a bit extreme for what should be an infrequent event.
652 */
653 /* Ensure 'resume' not overwrite saved fp context again. */
654 lose_fpu(1);
655
656 /* Run the emulator */
657 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
658
659 /*
660 * We can't allow the emulated instruction to leave any of
661 * the cause bit set in $fcr31.
662 */
663 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
664
665 /* Restore the hardware register state */
666 own_fpu(1); /* Using the FPU again. */
667
668 /* If something went wrong, signal */
669 if (sig)
670 force_sig(sig, current);
671
672 return;
673 } else if (fcr31 & FPU_CSR_INV_X)
674 info.si_code = FPE_FLTINV;
675 else if (fcr31 & FPU_CSR_DIV_X)
676 info.si_code = FPE_FLTDIV;
677 else if (fcr31 & FPU_CSR_OVF_X)
678 info.si_code = FPE_FLTOVF;
679 else if (fcr31 & FPU_CSR_UDF_X)
680 info.si_code = FPE_FLTUND;
681 else if (fcr31 & FPU_CSR_INE_X)
682 info.si_code = FPE_FLTRES;
683 else
684 info.si_code = __SI_FAULT;
685 info.si_signo = SIGFPE;
686 info.si_errno = 0;
687 info.si_addr = (void __user *) regs->cp0_epc;
688 force_sig_info(SIGFPE, &info, current);
689 }
690
691 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
692 const char *str)
693 {
694 siginfo_t info;
695 char b[40];
696
697 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
698 return;
699
700 /*
701 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
702 * insns, even for trap and break codes that indicate arithmetic
703 * failures. Weird ...
704 * But should we continue the brokenness??? --macro
705 */
706 switch (code) {
707 case BRK_OVERFLOW:
708 case BRK_DIVZERO:
709 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
710 die_if_kernel(b, regs);
711 if (code == BRK_DIVZERO)
712 info.si_code = FPE_INTDIV;
713 else
714 info.si_code = FPE_INTOVF;
715 info.si_signo = SIGFPE;
716 info.si_errno = 0;
717 info.si_addr = (void __user *) regs->cp0_epc;
718 force_sig_info(SIGFPE, &info, current);
719 break;
720 case BRK_BUG:
721 die_if_kernel("Kernel bug detected", regs);
722 force_sig(SIGTRAP, current);
723 break;
724 default:
725 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
726 die_if_kernel(b, regs);
727 force_sig(SIGTRAP, current);
728 }
729 }
730
731 asmlinkage void do_bp(struct pt_regs *regs)
732 {
733 unsigned int opcode, bcode;
734
735 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
736 goto out_sigsegv;
737
738 /*
739 * There is the ancient bug in the MIPS assemblers that the break
740 * code starts left to bit 16 instead to bit 6 in the opcode.
741 * Gas is bug-compatible, but not always, grrr...
742 * We handle both cases with a simple heuristics. --macro
743 */
744 bcode = ((opcode >> 6) & ((1 << 20) - 1));
745 if (bcode >= (1 << 10))
746 bcode >>= 10;
747
748 do_trap_or_bp(regs, bcode, "Break");
749 return;
750
751 out_sigsegv:
752 force_sig(SIGSEGV, current);
753 }
754
755 asmlinkage void do_tr(struct pt_regs *regs)
756 {
757 unsigned int opcode, tcode = 0;
758
759 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
760 goto out_sigsegv;
761
762 /* Immediate versions don't provide a code. */
763 if (!(opcode & OPCODE))
764 tcode = ((opcode >> 6) & ((1 << 10) - 1));
765
766 do_trap_or_bp(regs, tcode, "Trap");
767 return;
768
769 out_sigsegv:
770 force_sig(SIGSEGV, current);
771 }
772
773 asmlinkage void do_ri(struct pt_regs *regs)
774 {
775 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
776 unsigned long old_epc = regs->cp0_epc;
777 unsigned int opcode = 0;
778 int status = -1;
779
780 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0)
781 == NOTIFY_STOP)
782 return;
783
784 die_if_kernel("Reserved instruction in kernel code", regs);
785
786 if (unlikely(compute_return_epc(regs) < 0))
787 return;
788
789 if (unlikely(get_user(opcode, epc) < 0))
790 status = SIGSEGV;
791
792 if (!cpu_has_llsc && status < 0)
793 status = simulate_llsc(regs, opcode);
794
795 if (status < 0)
796 status = simulate_rdhwr(regs, opcode);
797
798 if (status < 0)
799 status = simulate_sync(regs, opcode);
800
801 if (status < 0)
802 status = SIGILL;
803
804 if (unlikely(status > 0)) {
805 regs->cp0_epc = old_epc; /* Undo skip-over. */
806 force_sig(status, current);
807 }
808 }
809
810 /*
811 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
812 * emulated more than some threshold number of instructions, force migration to
813 * a "CPU" that has FP support.
814 */
815 static void mt_ase_fp_affinity(void)
816 {
817 #ifdef CONFIG_MIPS_MT_FPAFF
818 if (mt_fpemul_threshold > 0 &&
819 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
820 /*
821 * If there's no FPU present, or if the application has already
822 * restricted the allowed set to exclude any CPUs with FPUs,
823 * we'll skip the procedure.
824 */
825 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
826 cpumask_t tmask;
827
828 current->thread.user_cpus_allowed
829 = current->cpus_allowed;
830 cpus_and(tmask, current->cpus_allowed,
831 mt_fpu_cpumask);
832 set_cpus_allowed(current, tmask);
833 set_thread_flag(TIF_FPUBOUND);
834 }
835 }
836 #endif /* CONFIG_MIPS_MT_FPAFF */
837 }
838
839 asmlinkage void do_cpu(struct pt_regs *regs)
840 {
841 unsigned int __user *epc;
842 unsigned long old_epc;
843 unsigned int opcode;
844 unsigned int cpid;
845 int status;
846
847 die_if_kernel("do_cpu invoked from kernel context!", regs);
848
849 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
850
851 switch (cpid) {
852 case 0:
853 epc = (unsigned int __user *)exception_epc(regs);
854 old_epc = regs->cp0_epc;
855 opcode = 0;
856 status = -1;
857
858 if (unlikely(compute_return_epc(regs) < 0))
859 return;
860
861 if (unlikely(get_user(opcode, epc) < 0))
862 status = SIGSEGV;
863
864 if (!cpu_has_llsc && status < 0)
865 status = simulate_llsc(regs, opcode);
866
867 if (status < 0)
868 status = simulate_rdhwr(regs, opcode);
869
870 if (status < 0)
871 status = SIGILL;
872
873 if (unlikely(status > 0)) {
874 regs->cp0_epc = old_epc; /* Undo skip-over. */
875 force_sig(status, current);
876 }
877
878 return;
879
880 case 1:
881 if (used_math()) /* Using the FPU again. */
882 own_fpu(1);
883 else { /* First time FPU user. */
884 init_fpu();
885 set_used_math();
886 }
887
888 if (!raw_cpu_has_fpu) {
889 int sig;
890 sig = fpu_emulator_cop1Handler(regs,
891 &current->thread.fpu, 0);
892 if (sig)
893 force_sig(sig, current);
894 else
895 mt_ase_fp_affinity();
896 }
897
898 return;
899
900 case 2:
901 case 3:
902 break;
903 }
904
905 force_sig(SIGILL, current);
906 }
907
908 asmlinkage void do_mdmx(struct pt_regs *regs)
909 {
910 force_sig(SIGILL, current);
911 }
912
913 asmlinkage void do_watch(struct pt_regs *regs)
914 {
915 /*
916 * We use the watch exception where available to detect stack
917 * overflows.
918 */
919 dump_tlb_all();
920 show_regs(regs);
921 panic("Caught WATCH exception - probably caused by stack overflow.");
922 }
923
924 asmlinkage void do_mcheck(struct pt_regs *regs)
925 {
926 const int field = 2 * sizeof(unsigned long);
927 int multi_match = regs->cp0_status & ST0_TS;
928
929 show_regs(regs);
930
931 if (multi_match) {
932 printk("Index : %0x\n", read_c0_index());
933 printk("Pagemask: %0x\n", read_c0_pagemask());
934 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
935 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
936 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
937 printk("\n");
938 dump_tlb_all();
939 }
940
941 show_code((unsigned int __user *) regs->cp0_epc);
942
943 /*
944 * Some chips may have other causes of machine check (e.g. SB1
945 * graduation timer)
946 */
947 panic("Caught Machine Check exception - %scaused by multiple "
948 "matching entries in the TLB.",
949 (multi_match) ? "" : "not ");
950 }
951
952 asmlinkage void do_mt(struct pt_regs *regs)
953 {
954 int subcode;
955
956 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
957 >> VPECONTROL_EXCPT_SHIFT;
958 switch (subcode) {
959 case 0:
960 printk(KERN_DEBUG "Thread Underflow\n");
961 break;
962 case 1:
963 printk(KERN_DEBUG "Thread Overflow\n");
964 break;
965 case 2:
966 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
967 break;
968 case 3:
969 printk(KERN_DEBUG "Gating Storage Exception\n");
970 break;
971 case 4:
972 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
973 break;
974 case 5:
975 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
976 break;
977 default:
978 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
979 subcode);
980 break;
981 }
982 die_if_kernel("MIPS MT Thread exception in kernel", regs);
983
984 force_sig(SIGILL, current);
985 }
986
987
988 asmlinkage void do_dsp(struct pt_regs *regs)
989 {
990 if (cpu_has_dsp)
991 panic("Unexpected DSP exception\n");
992
993 force_sig(SIGILL, current);
994 }
995
996 asmlinkage void do_reserved(struct pt_regs *regs)
997 {
998 /*
999 * Game over - no way to handle this if it ever occurs. Most probably
1000 * caused by a new unknown cpu type or after another deadly
1001 * hard/software error.
1002 */
1003 show_regs(regs);
1004 panic("Caught reserved exception %ld - should not happen.",
1005 (regs->cp0_cause & 0x7f) >> 2);
1006 }
1007
1008 static int __initdata l1parity = 1;
1009 static int __init nol1parity(char *s)
1010 {
1011 l1parity = 0;
1012 return 1;
1013 }
1014 __setup("nol1par", nol1parity);
1015 static int __initdata l2parity = 1;
1016 static int __init nol2parity(char *s)
1017 {
1018 l2parity = 0;
1019 return 1;
1020 }
1021 __setup("nol2par", nol2parity);
1022
1023 /*
1024 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1025 * it different ways.
1026 */
1027 static inline void parity_protection_init(void)
1028 {
1029 switch (current_cpu_type()) {
1030 case CPU_24K:
1031 case CPU_34K:
1032 case CPU_74K:
1033 case CPU_1004K:
1034 {
1035 #define ERRCTL_PE 0x80000000
1036 #define ERRCTL_L2P 0x00800000
1037 unsigned long errctl;
1038 unsigned int l1parity_present, l2parity_present;
1039
1040 errctl = read_c0_ecc();
1041 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1042
1043 /* probe L1 parity support */
1044 write_c0_ecc(errctl | ERRCTL_PE);
1045 back_to_back_c0_hazard();
1046 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1047
1048 /* probe L2 parity support */
1049 write_c0_ecc(errctl|ERRCTL_L2P);
1050 back_to_back_c0_hazard();
1051 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1052
1053 if (l1parity_present && l2parity_present) {
1054 if (l1parity)
1055 errctl |= ERRCTL_PE;
1056 if (l1parity ^ l2parity)
1057 errctl |= ERRCTL_L2P;
1058 } else if (l1parity_present) {
1059 if (l1parity)
1060 errctl |= ERRCTL_PE;
1061 } else if (l2parity_present) {
1062 if (l2parity)
1063 errctl |= ERRCTL_L2P;
1064 } else {
1065 /* No parity available */
1066 }
1067
1068 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1069
1070 write_c0_ecc(errctl);
1071 back_to_back_c0_hazard();
1072 errctl = read_c0_ecc();
1073 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1074
1075 if (l1parity_present)
1076 printk(KERN_INFO "Cache parity protection %sabled\n",
1077 (errctl & ERRCTL_PE) ? "en" : "dis");
1078
1079 if (l2parity_present) {
1080 if (l1parity_present && l1parity)
1081 errctl ^= ERRCTL_L2P;
1082 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1083 (errctl & ERRCTL_L2P) ? "en" : "dis");
1084 }
1085 }
1086 break;
1087
1088 case CPU_5KC:
1089 write_c0_ecc(0x80000000);
1090 back_to_back_c0_hazard();
1091 /* Set the PE bit (bit 31) in the c0_errctl register. */
1092 printk(KERN_INFO "Cache parity protection %sabled\n",
1093 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1094 break;
1095 case CPU_20KC:
1096 case CPU_25KF:
1097 /* Clear the DE bit (bit 16) in the c0_status register. */
1098 printk(KERN_INFO "Enable cache parity protection for "
1099 "MIPS 20KC/25KF CPUs.\n");
1100 clear_c0_status(ST0_DE);
1101 break;
1102 default:
1103 break;
1104 }
1105 }
1106
1107 asmlinkage void cache_parity_error(void)
1108 {
1109 const int field = 2 * sizeof(unsigned long);
1110 unsigned int reg_val;
1111
1112 /* For the moment, report the problem and hang. */
1113 printk("Cache error exception:\n");
1114 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1115 reg_val = read_c0_cacheerr();
1116 printk("c0_cacheerr == %08x\n", reg_val);
1117
1118 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1119 reg_val & (1<<30) ? "secondary" : "primary",
1120 reg_val & (1<<31) ? "data" : "insn");
1121 printk("Error bits: %s%s%s%s%s%s%s\n",
1122 reg_val & (1<<29) ? "ED " : "",
1123 reg_val & (1<<28) ? "ET " : "",
1124 reg_val & (1<<26) ? "EE " : "",
1125 reg_val & (1<<25) ? "EB " : "",
1126 reg_val & (1<<24) ? "EI " : "",
1127 reg_val & (1<<23) ? "E1 " : "",
1128 reg_val & (1<<22) ? "E0 " : "");
1129 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1130
1131 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1132 if (reg_val & (1<<22))
1133 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1134
1135 if (reg_val & (1<<23))
1136 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1137 #endif
1138
1139 panic("Can't handle the cache error!");
1140 }
1141
1142 /*
1143 * SDBBP EJTAG debug exception handler.
1144 * We skip the instruction and return to the next instruction.
1145 */
1146 void ejtag_exception_handler(struct pt_regs *regs)
1147 {
1148 const int field = 2 * sizeof(unsigned long);
1149 unsigned long depc, old_epc;
1150 unsigned int debug;
1151
1152 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1153 depc = read_c0_depc();
1154 debug = read_c0_debug();
1155 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1156 if (debug & 0x80000000) {
1157 /*
1158 * In branch delay slot.
1159 * We cheat a little bit here and use EPC to calculate the
1160 * debug return address (DEPC). EPC is restored after the
1161 * calculation.
1162 */
1163 old_epc = regs->cp0_epc;
1164 regs->cp0_epc = depc;
1165 __compute_return_epc(regs);
1166 depc = regs->cp0_epc;
1167 regs->cp0_epc = old_epc;
1168 } else
1169 depc += 4;
1170 write_c0_depc(depc);
1171
1172 #if 0
1173 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1174 write_c0_debug(debug | 0x100);
1175 #endif
1176 }
1177
1178 /*
1179 * NMI exception handler.
1180 */
1181 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1182 {
1183 bust_spinlocks(1);
1184 printk("NMI taken!!!!\n");
1185 die("NMI", regs);
1186 }
1187
1188 #define VECTORSPACING 0x100 /* for EI/VI mode */
1189
1190 unsigned long ebase;
1191 unsigned long exception_handlers[32];
1192 unsigned long vi_handlers[64];
1193
1194 /*
1195 * As a side effect of the way this is implemented we're limited
1196 * to interrupt handlers in the address range from
1197 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1198 */
1199 void *set_except_vector(int n, void *addr)
1200 {
1201 unsigned long handler = (unsigned long) addr;
1202 unsigned long old_handler = exception_handlers[n];
1203
1204 exception_handlers[n] = handler;
1205 if (n == 0 && cpu_has_divec) {
1206 *(u32 *)(ebase + 0x200) = 0x08000000 |
1207 (0x03ffffff & (handler >> 2));
1208 local_flush_icache_range(ebase + 0x200, ebase + 0x204);
1209 }
1210 return (void *)old_handler;
1211 }
1212
1213 static asmlinkage void do_default_vi(void)
1214 {
1215 show_regs(get_irq_regs());
1216 panic("Caught unexpected vectored interrupt.");
1217 }
1218
1219 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1220 {
1221 unsigned long handler;
1222 unsigned long old_handler = vi_handlers[n];
1223 int srssets = current_cpu_data.srsets;
1224 u32 *w;
1225 unsigned char *b;
1226
1227 if (!cpu_has_veic && !cpu_has_vint)
1228 BUG();
1229
1230 if (addr == NULL) {
1231 handler = (unsigned long) do_default_vi;
1232 srs = 0;
1233 } else
1234 handler = (unsigned long) addr;
1235 vi_handlers[n] = (unsigned long) addr;
1236
1237 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1238
1239 if (srs >= srssets)
1240 panic("Shadow register set %d not supported", srs);
1241
1242 if (cpu_has_veic) {
1243 if (board_bind_eic_interrupt)
1244 board_bind_eic_interrupt(n, srs);
1245 } else if (cpu_has_vint) {
1246 /* SRSMap is only defined if shadow sets are implemented */
1247 if (srssets > 1)
1248 change_c0_srsmap(0xf << n*4, srs << n*4);
1249 }
1250
1251 if (srs == 0) {
1252 /*
1253 * If no shadow set is selected then use the default handler
1254 * that does normal register saving and a standard interrupt exit
1255 */
1256
1257 extern char except_vec_vi, except_vec_vi_lui;
1258 extern char except_vec_vi_ori, except_vec_vi_end;
1259 extern char rollback_except_vec_vi;
1260 char *vec_start = (cpu_wait == r4k_wait) ?
1261 &rollback_except_vec_vi : &except_vec_vi;
1262 #ifdef CONFIG_MIPS_MT_SMTC
1263 /*
1264 * We need to provide the SMTC vectored interrupt handler
1265 * not only with the address of the handler, but with the
1266 * Status.IM bit to be masked before going there.
1267 */
1268 extern char except_vec_vi_mori;
1269 const int mori_offset = &except_vec_vi_mori - vec_start;
1270 #endif /* CONFIG_MIPS_MT_SMTC */
1271 const int handler_len = &except_vec_vi_end - vec_start;
1272 const int lui_offset = &except_vec_vi_lui - vec_start;
1273 const int ori_offset = &except_vec_vi_ori - vec_start;
1274
1275 if (handler_len > VECTORSPACING) {
1276 /*
1277 * Sigh... panicing won't help as the console
1278 * is probably not configured :(
1279 */
1280 panic("VECTORSPACING too small");
1281 }
1282
1283 memcpy(b, vec_start, handler_len);
1284 #ifdef CONFIG_MIPS_MT_SMTC
1285 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1286
1287 w = (u32 *)(b + mori_offset);
1288 *w = (*w & 0xffff0000) | (0x100 << n);
1289 #endif /* CONFIG_MIPS_MT_SMTC */
1290 w = (u32 *)(b + lui_offset);
1291 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1292 w = (u32 *)(b + ori_offset);
1293 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1294 local_flush_icache_range((unsigned long)b,
1295 (unsigned long)(b+handler_len));
1296 }
1297 else {
1298 /*
1299 * In other cases jump directly to the interrupt handler
1300 *
1301 * It is the handlers responsibility to save registers if required
1302 * (eg hi/lo) and return from the exception using "eret"
1303 */
1304 w = (u32 *)b;
1305 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1306 *w = 0;
1307 local_flush_icache_range((unsigned long)b,
1308 (unsigned long)(b+8));
1309 }
1310
1311 return (void *)old_handler;
1312 }
1313
1314 void *set_vi_handler(int n, vi_handler_t addr)
1315 {
1316 return set_vi_srs_handler(n, addr, 0);
1317 }
1318
1319 /*
1320 * This is used by native signal handling
1321 */
1322 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1323 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1324
1325 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1326 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1327
1328 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1329 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1330
1331 #ifdef CONFIG_SMP
1332 static int smp_save_fp_context(struct sigcontext __user *sc)
1333 {
1334 return raw_cpu_has_fpu
1335 ? _save_fp_context(sc)
1336 : fpu_emulator_save_context(sc);
1337 }
1338
1339 static int smp_restore_fp_context(struct sigcontext __user *sc)
1340 {
1341 return raw_cpu_has_fpu
1342 ? _restore_fp_context(sc)
1343 : fpu_emulator_restore_context(sc);
1344 }
1345 #endif
1346
1347 static inline void signal_init(void)
1348 {
1349 #ifdef CONFIG_SMP
1350 /* For now just do the cpu_has_fpu check when the functions are invoked */
1351 save_fp_context = smp_save_fp_context;
1352 restore_fp_context = smp_restore_fp_context;
1353 #else
1354 if (cpu_has_fpu) {
1355 save_fp_context = _save_fp_context;
1356 restore_fp_context = _restore_fp_context;
1357 } else {
1358 save_fp_context = fpu_emulator_save_context;
1359 restore_fp_context = fpu_emulator_restore_context;
1360 }
1361 #endif
1362 }
1363
1364 #ifdef CONFIG_MIPS32_COMPAT
1365
1366 /*
1367 * This is used by 32-bit signal stuff on the 64-bit kernel
1368 */
1369 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1370 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1371
1372 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1373 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1374
1375 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1376 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1377
1378 static inline void signal32_init(void)
1379 {
1380 if (cpu_has_fpu) {
1381 save_fp_context32 = _save_fp_context32;
1382 restore_fp_context32 = _restore_fp_context32;
1383 } else {
1384 save_fp_context32 = fpu_emulator_save_context32;
1385 restore_fp_context32 = fpu_emulator_restore_context32;
1386 }
1387 }
1388 #endif
1389
1390 extern void cpu_cache_init(void);
1391 extern void tlb_init(void);
1392 extern void flush_tlb_handlers(void);
1393
1394 /*
1395 * Timer interrupt
1396 */
1397 int cp0_compare_irq;
1398
1399 /*
1400 * Performance counter IRQ or -1 if shared with timer
1401 */
1402 int cp0_perfcount_irq;
1403 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1404
1405 static int __cpuinitdata noulri;
1406
1407 static int __init ulri_disable(char *s)
1408 {
1409 pr_info("Disabling ulri\n");
1410 noulri = 1;
1411
1412 return 1;
1413 }
1414 __setup("noulri", ulri_disable);
1415
1416 void __cpuinit per_cpu_trap_init(void)
1417 {
1418 unsigned int cpu = smp_processor_id();
1419 unsigned int status_set = ST0_CU0;
1420 #ifdef CONFIG_MIPS_MT_SMTC
1421 int secondaryTC = 0;
1422 int bootTC = (cpu == 0);
1423
1424 /*
1425 * Only do per_cpu_trap_init() for first TC of Each VPE.
1426 * Note that this hack assumes that the SMTC init code
1427 * assigns TCs consecutively and in ascending order.
1428 */
1429
1430 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1431 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1432 secondaryTC = 1;
1433 #endif /* CONFIG_MIPS_MT_SMTC */
1434
1435 /*
1436 * Disable coprocessors and select 32-bit or 64-bit addressing
1437 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1438 * flag that some firmware may have left set and the TS bit (for
1439 * IP27). Set XX for ISA IV code to work.
1440 */
1441 #ifdef CONFIG_64BIT
1442 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1443 #endif
1444 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1445 status_set |= ST0_XX;
1446 if (cpu_has_dsp)
1447 status_set |= ST0_MX;
1448
1449 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1450 status_set);
1451
1452 if (cpu_has_mips_r2) {
1453 unsigned int enable = 0x0000000f;
1454
1455 if (!noulri && cpu_has_userlocal)
1456 enable |= (1 << 29);
1457
1458 write_c0_hwrena(enable);
1459 }
1460
1461 #ifdef CONFIG_MIPS_MT_SMTC
1462 if (!secondaryTC) {
1463 #endif /* CONFIG_MIPS_MT_SMTC */
1464
1465 if (cpu_has_veic || cpu_has_vint) {
1466 write_c0_ebase(ebase);
1467 /* Setting vector spacing enables EI/VI mode */
1468 change_c0_intctl(0x3e0, VECTORSPACING);
1469 }
1470 if (cpu_has_divec) {
1471 if (cpu_has_mipsmt) {
1472 unsigned int vpflags = dvpe();
1473 set_c0_cause(CAUSEF_IV);
1474 evpe(vpflags);
1475 } else
1476 set_c0_cause(CAUSEF_IV);
1477 }
1478
1479 /*
1480 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1481 *
1482 * o read IntCtl.IPTI to determine the timer interrupt
1483 * o read IntCtl.IPPCI to determine the performance counter interrupt
1484 */
1485 if (cpu_has_mips_r2) {
1486 cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1487 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1488 if (cp0_perfcount_irq == cp0_compare_irq)
1489 cp0_perfcount_irq = -1;
1490 } else {
1491 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1492 cp0_perfcount_irq = -1;
1493 }
1494
1495 #ifdef CONFIG_MIPS_MT_SMTC
1496 }
1497 #endif /* CONFIG_MIPS_MT_SMTC */
1498
1499 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1500 TLBMISS_HANDLER_SETUP();
1501
1502 atomic_inc(&init_mm.mm_count);
1503 current->active_mm = &init_mm;
1504 BUG_ON(current->mm);
1505 enter_lazy_tlb(&init_mm, current);
1506
1507 #ifdef CONFIG_MIPS_MT_SMTC
1508 if (bootTC) {
1509 #endif /* CONFIG_MIPS_MT_SMTC */
1510 cpu_cache_init();
1511 tlb_init();
1512 #ifdef CONFIG_MIPS_MT_SMTC
1513 } else if (!secondaryTC) {
1514 /*
1515 * First TC in non-boot VPE must do subset of tlb_init()
1516 * for MMU countrol registers.
1517 */
1518 write_c0_pagemask(PM_DEFAULT_MASK);
1519 write_c0_wired(0);
1520 }
1521 #endif /* CONFIG_MIPS_MT_SMTC */
1522 }
1523
1524 /* Install CPU exception handler */
1525 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1526 {
1527 memcpy((void *)(ebase + offset), addr, size);
1528 local_flush_icache_range(ebase + offset, ebase + offset + size);
1529 }
1530
1531 static char panic_null_cerr[] __cpuinitdata =
1532 "Trying to set NULL cache error exception handler";
1533
1534 /* Install uncached CPU exception handler */
1535 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1536 unsigned long size)
1537 {
1538 #ifdef CONFIG_32BIT
1539 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1540 #endif
1541 #ifdef CONFIG_64BIT
1542 unsigned long uncached_ebase = TO_UNCAC(ebase);
1543 #endif
1544
1545 if (!addr)
1546 panic(panic_null_cerr);
1547
1548 memcpy((void *)(uncached_ebase + offset), addr, size);
1549 }
1550
1551 static int __initdata rdhwr_noopt;
1552 static int __init set_rdhwr_noopt(char *str)
1553 {
1554 rdhwr_noopt = 1;
1555 return 1;
1556 }
1557
1558 __setup("rdhwr_noopt", set_rdhwr_noopt);
1559
1560 void __init trap_init(void)
1561 {
1562 extern char except_vec3_generic, except_vec3_r4000;
1563 extern char except_vec4;
1564 unsigned long i;
1565 int rollback;
1566
1567 check_wait();
1568 rollback = (cpu_wait == r4k_wait);
1569
1570 #if defined(CONFIG_KGDB)
1571 if (kgdb_early_setup)
1572 return; /* Already done */
1573 #endif
1574
1575 if (cpu_has_veic || cpu_has_vint)
1576 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1577 else
1578 ebase = CAC_BASE;
1579
1580 per_cpu_trap_init();
1581
1582 /*
1583 * Copy the generic exception handlers to their final destination.
1584 * This will be overriden later as suitable for a particular
1585 * configuration.
1586 */
1587 set_handler(0x180, &except_vec3_generic, 0x80);
1588
1589 /*
1590 * Setup default vectors
1591 */
1592 for (i = 0; i <= 31; i++)
1593 set_except_vector(i, handle_reserved);
1594
1595 /*
1596 * Copy the EJTAG debug exception vector handler code to it's final
1597 * destination.
1598 */
1599 if (cpu_has_ejtag && board_ejtag_handler_setup)
1600 board_ejtag_handler_setup();
1601
1602 /*
1603 * Only some CPUs have the watch exceptions.
1604 */
1605 if (cpu_has_watch)
1606 set_except_vector(23, handle_watch);
1607
1608 /*
1609 * Initialise interrupt handlers
1610 */
1611 if (cpu_has_veic || cpu_has_vint) {
1612 int nvec = cpu_has_veic ? 64 : 8;
1613 for (i = 0; i < nvec; i++)
1614 set_vi_handler(i, NULL);
1615 }
1616 else if (cpu_has_divec)
1617 set_handler(0x200, &except_vec4, 0x8);
1618
1619 /*
1620 * Some CPUs can enable/disable for cache parity detection, but does
1621 * it different ways.
1622 */
1623 parity_protection_init();
1624
1625 /*
1626 * The Data Bus Errors / Instruction Bus Errors are signaled
1627 * by external hardware. Therefore these two exceptions
1628 * may have board specific handlers.
1629 */
1630 if (board_be_init)
1631 board_be_init();
1632
1633 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1634 set_except_vector(1, handle_tlbm);
1635 set_except_vector(2, handle_tlbl);
1636 set_except_vector(3, handle_tlbs);
1637
1638 set_except_vector(4, handle_adel);
1639 set_except_vector(5, handle_ades);
1640
1641 set_except_vector(6, handle_ibe);
1642 set_except_vector(7, handle_dbe);
1643
1644 set_except_vector(8, handle_sys);
1645 set_except_vector(9, handle_bp);
1646 set_except_vector(10, rdhwr_noopt ? handle_ri :
1647 (cpu_has_vtag_icache ?
1648 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1649 set_except_vector(11, handle_cpu);
1650 set_except_vector(12, handle_ov);
1651 set_except_vector(13, handle_tr);
1652
1653 if (current_cpu_type() == CPU_R6000 ||
1654 current_cpu_type() == CPU_R6000A) {
1655 /*
1656 * The R6000 is the only R-series CPU that features a machine
1657 * check exception (similar to the R4000 cache error) and
1658 * unaligned ldc1/sdc1 exception. The handlers have not been
1659 * written yet. Well, anyway there is no R6000 machine on the
1660 * current list of targets for Linux/MIPS.
1661 * (Duh, crap, there is someone with a triple R6k machine)
1662 */
1663 //set_except_vector(14, handle_mc);
1664 //set_except_vector(15, handle_ndc);
1665 }
1666
1667
1668 if (board_nmi_handler_setup)
1669 board_nmi_handler_setup();
1670
1671 if (cpu_has_fpu && !cpu_has_nofpuex)
1672 set_except_vector(15, handle_fpe);
1673
1674 set_except_vector(22, handle_mdmx);
1675
1676 if (cpu_has_mcheck)
1677 set_except_vector(24, handle_mcheck);
1678
1679 if (cpu_has_mipsmt)
1680 set_except_vector(25, handle_mt);
1681
1682 set_except_vector(26, handle_dsp);
1683
1684 if (cpu_has_vce)
1685 /* Special exception: R4[04]00 uses also the divec space. */
1686 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1687 else if (cpu_has_4kex)
1688 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1689 else
1690 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1691
1692 signal_init();
1693 #ifdef CONFIG_MIPS32_COMPAT
1694 signal32_init();
1695 #endif
1696
1697 local_flush_icache_range(ebase, ebase + 0x400);
1698 flush_tlb_handlers();
1699
1700 sort_extable(__start___dbe_table, __stop___dbe_table);
1701 }
Linux branches of Pieter du Preez