arch/x86/pci/irq.c

   1 /*
   2  *      Low-Level PCI Support for PC -- Routing of Interrupts
   3  *
   4  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   5  */
   6
   7 #include <linux/types.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pci.h>
  10 #include <linux/init.h>
  11 #include <linux/slab.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/dmi.h>
  14 #include <linux/io.h>
  15 #include <linux/smp.h>
  16 #include <asm/io_apic.h>
  17 #include <linux/irq.h>
  18 #include <linux/acpi.h>
  19
  20 #include "pci.h"
  21
  22 #define PIRQ_SIGNATURE  (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
  23 #define PIRQ_VERSION 0x0100
  24
  25 static int broken_hp_bios_irq9;
  26 static int acer_tm360_irqrouting;
  27
  28 static struct irq_routing_table *pirq_table;
  29
  30 static int pirq_enable_irq(struct pci_dev *dev);
  31
  32 /*
  33  * Never use: 0, 1, 2 (timer, keyboard, and cascade)
  34  * Avoid using: 13, 14 and 15 (FP error and IDE).
  35  * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
  36  */
  37 unsigned int pcibios_irq_mask = 0xfff8;
  38
  39 static int pirq_penalty[16] = {
  40         1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
  41         0, 0, 0, 0, 1000, 100000, 100000, 100000
  42 };
  43
  44 struct irq_router {
  45         char *name;
  46         u16 vendor, device;
  47         int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
  48         int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
  49                 int new);
  50 };
  51
  52 struct irq_router_handler {
  53         u16 vendor;
  54         int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
  55 };
  56
  57 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
  58 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
  59
  60 /*
  61  *  Check passed address for the PCI IRQ Routing Table signature
  62  *  and perform checksum verification.
  63  */
  64
  65 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
  66 {
  67         struct irq_routing_table *rt;
  68         int i;
  69         u8 sum;
  70
  71         rt = (struct irq_routing_table *) addr;
  72         if (rt->signature != PIRQ_SIGNATURE ||
  73             rt->version != PIRQ_VERSION ||
  74             rt->size % 16 ||
  75             rt->size < sizeof(struct irq_routing_table))
  76                 return NULL;
  77         sum = 0;
  78         for (i = 0; i < rt->size; i++)
  79                 sum += addr[i];
  80         if (!sum) {
  81                 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
  82                         rt);
  83                 return rt;
  84         }
  85         return NULL;
  86 }
  87
  88
  89
  90 /*
  91  *  Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
  92  */
  93
  94 static struct irq_routing_table * __init pirq_find_routing_table(void)
  95 {
  96         u8 *addr;
  97         struct irq_routing_table *rt;
  98
  99         if (pirq_table_addr) {
 100                 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
 101                 if (rt)
 102                         return rt;
 103                 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
 104         }
 105         for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
 106                 rt = pirq_check_routing_table(addr);
 107                 if (rt)
 108                         return rt;
 109         }
 110         return NULL;
 111 }
 112
 113 /*
 114  *  If we have a IRQ routing table, use it to search for peer host
 115  *  bridges.  It's a gross hack, but since there are no other known
 116  *  ways how to get a list of buses, we have to go this way.
 117  */
 118
 119 static void __init pirq_peer_trick(void)
 120 {
 121         struct irq_routing_table *rt = pirq_table;
 122         u8 busmap[256];
 123         int i;
 124         struct irq_info *e;
 125
 126         memset(busmap, 0, sizeof(busmap));
 127         for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
 128                 e = &rt->slots[i];
 129 #ifdef DEBUG
 130                 {
 131                         int j;
 132                         DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
 133                         for (j = 0; j < 4; j++)
 134                                 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
 135                         DBG("\n");
 136                 }
 137 #endif
 138                 busmap[e->bus] = 1;
 139         }
 140         for (i = 1; i < 256; i++) {
 141                 int node;
 142                 if (!busmap[i] || pci_find_bus(0, i))
 143                         continue;
 144                 node = get_mp_bus_to_node(i);
 145                 if (pci_scan_bus_on_node(i, &pci_root_ops, node))
 146                         printk(KERN_INFO "PCI: Discovered primary peer "
 147                                "bus %02x [IRQ]\n", i);
 148         }
 149         pcibios_last_bus = -1;
 150 }
 151
 152 /*
 153  *  Code for querying and setting of IRQ routes on various interrupt routers.
 154  */
 155
 156 void eisa_set_level_irq(unsigned int irq)
 157 {
 158         unsigned char mask = 1 << (irq & 7);
 159         unsigned int port = 0x4d0 + (irq >> 3);
 160         unsigned char val;
 161         static u16 eisa_irq_mask;
 162
 163         if (irq >= 16 || (1 << irq) & eisa_irq_mask)
 164                 return;
 165
 166         eisa_irq_mask |= (1 << irq);
 167         printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
 168         val = inb(port);
 169         if (!(val & mask)) {
 170                 DBG(KERN_DEBUG " -> edge");
 171                 outb(val | mask, port);
 172         }
 173 }
 174
 175 /*
 176  * Common IRQ routing practice: nibbles in config space,
 177  * offset by some magic constant.
 178  */
 179 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
 180 {
 181         u8 x;
 182         unsigned reg = offset + (nr >> 1);
 183
 184         pci_read_config_byte(router, reg, &x);
 185         return (nr & 1) ? (x >> 4) : (x & 0xf);
 186 }
 187
 188 static void write_config_nybble(struct pci_dev *router, unsigned offset,
 189         unsigned nr, unsigned int val)
 190 {
 191         u8 x;
 192         unsigned reg = offset + (nr >> 1);
 193
 194         pci_read_config_byte(router, reg, &x);
 195         x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
 196         pci_write_config_byte(router, reg, x);
 197 }
 198
 199 /*
 200  * ALI pirq entries are damn ugly, and completely undocumented.
 201  * This has been figured out from pirq tables, and it's not a pretty
 202  * picture.
 203  */
 204 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 205 {
 206         static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
 207
 208         WARN_ON_ONCE(pirq > 16);
 209         return irqmap[read_config_nybble(router, 0x48, pirq-1)];
 210 }
 211
 212 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 213 {
 214         static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
 215         unsigned int val = irqmap[irq];
 216
 217         WARN_ON_ONCE(pirq > 16);
 218         if (val) {
 219                 write_config_nybble(router, 0x48, pirq-1, val);
 220                 return 1;
 221         }
 222         return 0;
 223 }
 224
 225 /*
 226  * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
 227  * just a pointer to the config space.
 228  */
 229 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 230 {
 231         u8 x;
 232
 233         pci_read_config_byte(router, pirq, &x);
 234         return (x < 16) ? x : 0;
 235 }
 236
 237 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 238 {
 239         pci_write_config_byte(router, pirq, irq);
 240         return 1;
 241 }
 242
 243 /*
 244  * The VIA pirq rules are nibble-based, like ALI,
 245  * but without the ugly irq number munging.
 246  * However, PIRQD is in the upper instead of lower 4 bits.
 247  */
 248 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 249 {
 250         return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
 251 }
 252
 253 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 254 {
 255         write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
 256         return 1;
 257 }
 258
 259 /*
 260  * The VIA pirq rules are nibble-based, like ALI,
 261  * but without the ugly irq number munging.
 262  * However, for 82C586, nibble map is different .
 263  */
 264 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 265 {
 266         static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
 267
 268         WARN_ON_ONCE(pirq > 5);
 269         return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
 270 }
 271
 272 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 273 {
 274         static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
 275
 276         WARN_ON_ONCE(pirq > 5);
 277         write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
 278         return 1;
 279 }
 280
 281 /*
 282  * ITE 8330G pirq rules are nibble-based
 283  * FIXME: pirqmap may be { 1, 0, 3, 2 },
 284  *        2+3 are both mapped to irq 9 on my system
 285  */
 286 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 287 {
 288         static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 289
 290         WARN_ON_ONCE(pirq > 4);
 291         return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
 292 }
 293
 294 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 295 {
 296         static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 297
 298         WARN_ON_ONCE(pirq > 4);
 299         write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
 300         return 1;
 301 }
 302
 303 /*
 304  * OPTI: high four bits are nibble pointer..
 305  * I wonder what the low bits do?
 306  */
 307 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 308 {
 309         return read_config_nybble(router, 0xb8, pirq >> 4);
 310 }
 311
 312 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 313 {
 314         write_config_nybble(router, 0xb8, pirq >> 4, irq);
 315         return 1;
 316 }
 317
 318 /*
 319  * Cyrix: nibble offset 0x5C
 320  * 0x5C bits 7:4 is INTB bits 3:0 is INTA
 321  * 0x5D bits 7:4 is INTD bits 3:0 is INTC
 322  */
 323 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 324 {
 325         return read_config_nybble(router, 0x5C, (pirq-1)^1);
 326 }
 327
 328 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 329 {
 330         write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
 331         return 1;
 332 }
 333
 334 /*
 335  *      PIRQ routing for SiS 85C503 router used in several SiS chipsets.
 336  *      We have to deal with the following issues here:
 337  *      - vendors have different ideas about the meaning of link values
 338  *      - some onboard devices (integrated in the chipset) have special
 339  *        links and are thus routed differently (i.e. not via PCI INTA-INTD)
 340  *      - different revision of the router have a different layout for
 341  *        the routing registers, particularly for the onchip devices
 342  *
 343  *      For all routing registers the common thing is we have one byte
 344  *      per routeable link which is defined as:
 345  *               bit 7      IRQ mapping enabled (0) or disabled (1)
 346  *               bits [6:4] reserved (sometimes used for onchip devices)
 347  *               bits [3:0] IRQ to map to
 348  *                   allowed: 3-7, 9-12, 14-15
 349  *                   reserved: 0, 1, 2, 8, 13
 350  *
 351  *      The config-space registers located at 0x41/0x42/0x43/0x44 are
 352  *      always used to route the normal PCI INT A/B/C/D respectively.
 353  *      Apparently there are systems implementing PCI routing table using
 354  *      link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
 355  *      We try our best to handle both link mappings.
 356  *
 357  *      Currently (2003-05-21) it appears most SiS chipsets follow the
 358  *      definition of routing registers from the SiS-5595 southbridge.
 359  *      According to the SiS 5595 datasheets the revision id's of the
 360  *      router (ISA-bridge) should be 0x01 or 0xb0.
 361  *
 362  *      Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
 363  *      Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
 364  *      They seem to work with the current routing code. However there is
 365  *      some concern because of the two USB-OHCI HCs (original SiS 5595
 366  *      had only one). YMMV.
 367  *
 368  *      Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
 369  *
 370  *      0x61:   IDEIRQ:
 371  *              bits [6:5] must be written 01
 372  *              bit 4 channel-select primary (0), secondary (1)
 373  *
 374  *      0x62:   USBIRQ:
 375  *              bit 6 OHCI function disabled (0), enabled (1)
 376  *
 377  *      0x6a:   ACPI/SCI IRQ: bits 4-6 reserved
 378  *
 379  *      0x7e:   Data Acq. Module IRQ - bits 4-6 reserved
 380  *
 381  *      We support USBIRQ (in addition to INTA-INTD) and keep the
 382  *      IDE, ACPI and DAQ routing untouched as set by the BIOS.
 383  *
 384  *      Currently the only reported exception is the new SiS 65x chipset
 385  *      which includes the SiS 69x southbridge. Here we have the 85C503
 386  *      router revision 0x04 and there are changes in the register layout
 387  *      mostly related to the different USB HCs with USB 2.0 support.
 388  *
 389  *      Onchip routing for router rev-id 0x04 (try-and-error observation)
 390  *
 391  *      0x60/0x61/0x62/0x63:    1xEHCI and 3xOHCI (companion) USB-HCs
 392  *                              bit 6-4 are probably unused, not like 5595
 393  */
 394
 395 #define PIRQ_SIS_IRQ_MASK       0x0f
 396 #define PIRQ_SIS_IRQ_DISABLE    0x80
 397 #define PIRQ_SIS_USB_ENABLE     0x40
 398
 399 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 400 {
 401         u8 x;
 402         int reg;
 403
 404         reg = pirq;
 405         if (reg >= 0x01 && reg <= 0x04)
 406                 reg += 0x40;
 407         pci_read_config_byte(router, reg, &x);
 408         return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
 409 }
 410
 411 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 412 {
 413         u8 x;
 414         int reg;
 415
 416         reg = pirq;
 417         if (reg >= 0x01 && reg <= 0x04)
 418                 reg += 0x40;
 419         pci_read_config_byte(router, reg, &x);
 420         x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
 421         x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
 422         pci_write_config_byte(router, reg, x);
 423         return 1;
 424 }
 425
 426
 427 /*
 428  * VLSI: nibble offset 0x74 - educated guess due to routing table and
 429  *       config space of VLSI 82C534 PCI-bridge/router (1004:0102)
 430  *       Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
 431  *       devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
 432  *       for the busbridge to the docking station.
 433  */
 434
 435 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 436 {
 437         WARN_ON_ONCE(pirq >= 9);
 438         if (pirq > 8) {
 439                 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
 440                 return 0;
 441         }
 442         return read_config_nybble(router, 0x74, pirq-1);
 443 }
 444
 445 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 446 {
 447         WARN_ON_ONCE(pirq >= 9);
 448         if (pirq > 8) {
 449                 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
 450                 return 0;
 451         }
 452         write_config_nybble(router, 0x74, pirq-1, irq);
 453         return 1;
 454 }
 455
 456 /*
 457  * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
 458  * and Redirect I/O registers (0x0c00 and 0x0c01).  The Index register
 459  * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a.  The Redirect
 460  * register is a straight binary coding of desired PIC IRQ (low nibble).
 461  *
 462  * The 'link' value in the PIRQ table is already in the correct format
 463  * for the Index register.  There are some special index values:
 464  * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
 465  * and 0x03 for SMBus.
 466  */
 467 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 468 {
 469         outb(pirq, 0xc00);
 470         return inb(0xc01) & 0xf;
 471 }
 472
 473 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
 474         int pirq, int irq)
 475 {
 476         outb(pirq, 0xc00);
 477         outb(irq, 0xc01);
 478         return 1;
 479 }
 480
 481 /* Support for AMD756 PCI IRQ Routing
 482  * Jhon H. Caicedo <jhcaiced@osso.org.co>
 483  * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
 484  * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
 485  * The AMD756 pirq rules are nibble-based
 486  * offset 0x56 0-3 PIRQA  4-7  PIRQB
 487  * offset 0x57 0-3 PIRQC  4-7  PIRQD
 488  */
 489 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 490 {
 491         u8 irq;
 492         irq = 0;
 493         if (pirq <= 4)
 494                 irq = read_config_nybble(router, 0x56, pirq - 1);
 495         dev_info(&dev->dev,
 496                  "AMD756: dev [%04x/%04x], router PIRQ %d get IRQ %d\n",
 497                  dev->vendor, dev->device, pirq, irq);
 498         return irq;
 499 }
 500
 501 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 502 {
 503         dev_info(&dev->dev,
 504                  "AMD756: dev [%04x/%04x], router PIRQ %d set IRQ %d\n",
 505                  dev->vendor, dev->device, pirq, irq);
 506         if (pirq <= 4)
 507                 write_config_nybble(router, 0x56, pirq - 1, irq);
 508         return 1;
 509 }
 510
 511 /*
 512  * PicoPower PT86C523
 513  */
 514 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 515 {
 516         outb(0x10 + ((pirq - 1) >> 1), 0x24);
 517         return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
 518 }
 519
 520 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
 521                         int irq)
 522 {
 523         unsigned int x;
 524         outb(0x10 + ((pirq - 1) >> 1), 0x24);
 525         x = inb(0x26);
 526         x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
 527         outb(x, 0x26);
 528         return 1;
 529 }
 530
 531 #ifdef CONFIG_PCI_BIOS
 532
 533 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 534 {
 535         struct pci_dev *bridge;
 536         int pin = pci_get_interrupt_pin(dev, &bridge);
 537         return pcibios_set_irq_routing(bridge, pin, irq);
 538 }
 539
 540 #endif
 541
 542 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 543 {
 544         static struct pci_device_id __initdata pirq_440gx[] = {
 545                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
 546                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
 547                 { },
 548         };
 549
 550         /* 440GX has a proprietary PIRQ router -- don't use it */
 551         if (pci_dev_present(pirq_440gx))
 552                 return 0;
 553
 554         switch (device) {
 555         case PCI_DEVICE_ID_INTEL_82371FB_0:
 556         case PCI_DEVICE_ID_INTEL_82371SB_0:
 557         case PCI_DEVICE_ID_INTEL_82371AB_0:
 558         case PCI_DEVICE_ID_INTEL_82371MX:
 559         case PCI_DEVICE_ID_INTEL_82443MX_0:
 560         case PCI_DEVICE_ID_INTEL_82801AA_0:
 561         case PCI_DEVICE_ID_INTEL_82801AB_0:
 562         case PCI_DEVICE_ID_INTEL_82801BA_0:
 563         case PCI_DEVICE_ID_INTEL_82801BA_10:
 564         case PCI_DEVICE_ID_INTEL_82801CA_0:
 565         case PCI_DEVICE_ID_INTEL_82801CA_12:
 566         case PCI_DEVICE_ID_INTEL_82801DB_0:
 567         case PCI_DEVICE_ID_INTEL_82801E_0:
 568         case PCI_DEVICE_ID_INTEL_82801EB_0:
 569         case PCI_DEVICE_ID_INTEL_ESB_1:
 570         case PCI_DEVICE_ID_INTEL_ICH6_0:
 571         case PCI_DEVICE_ID_INTEL_ICH6_1:
 572         case PCI_DEVICE_ID_INTEL_ICH7_0:
 573         case PCI_DEVICE_ID_INTEL_ICH7_1:
 574         case PCI_DEVICE_ID_INTEL_ICH7_30:
 575         case PCI_DEVICE_ID_INTEL_ICH7_31:
 576         case PCI_DEVICE_ID_INTEL_ESB2_0:
 577         case PCI_DEVICE_ID_INTEL_ICH8_0:
 578         case PCI_DEVICE_ID_INTEL_ICH8_1:
 579         case PCI_DEVICE_ID_INTEL_ICH8_2:
 580         case PCI_DEVICE_ID_INTEL_ICH8_3:
 581         case PCI_DEVICE_ID_INTEL_ICH8_4:
 582         case PCI_DEVICE_ID_INTEL_ICH9_0:
 583         case PCI_DEVICE_ID_INTEL_ICH9_1:
 584         case PCI_DEVICE_ID_INTEL_ICH9_2:
 585         case PCI_DEVICE_ID_INTEL_ICH9_3:
 586         case PCI_DEVICE_ID_INTEL_ICH9_4:
 587         case PCI_DEVICE_ID_INTEL_ICH9_5:
 588         case PCI_DEVICE_ID_INTEL_TOLAPAI_0:
 589         case PCI_DEVICE_ID_INTEL_ICH10_0:
 590         case PCI_DEVICE_ID_INTEL_ICH10_1:
 591         case PCI_DEVICE_ID_INTEL_ICH10_2:
 592         case PCI_DEVICE_ID_INTEL_ICH10_3:
 593         case PCI_DEVICE_ID_INTEL_PCH_0:
 594         case PCI_DEVICE_ID_INTEL_PCH_1:
 595                 r->name = "PIIX/ICH";
 596                 r->get = pirq_piix_get;
 597                 r->set = pirq_piix_set;
 598                 return 1;
 599         }
 600         return 0;
 601 }
 602
 603 static __init int via_router_probe(struct irq_router *r,
 604                                 struct pci_dev *router, u16 device)
 605 {
 606         /* FIXME: We should move some of the quirk fixup stuff here */
 607
 608         /*
 609          * workarounds for some buggy BIOSes
 610          */
 611         if (device == PCI_DEVICE_ID_VIA_82C586_0) {
 612                 switch (router->device) {
 613                 case PCI_DEVICE_ID_VIA_82C686:
 614                         /*
 615                          * Asus k7m bios wrongly reports 82C686A
 616                          * as 586-compatible
 617                          */
 618                         device = PCI_DEVICE_ID_VIA_82C686;
 619                         break;
 620                 case PCI_DEVICE_ID_VIA_8235:
 621                         /**
 622                          * Asus a7v-x bios wrongly reports 8235
 623                          * as 586-compatible
 624                          */
 625                         device = PCI_DEVICE_ID_VIA_8235;
 626                         break;
 627                 case PCI_DEVICE_ID_VIA_8237:
 628                         /**
 629                          * Asus a7v600 bios wrongly reports 8237
 630                          * as 586-compatible
 631                          */
 632                         device = PCI_DEVICE_ID_VIA_8237;
 633                         break;
 634                 }
 635         }
 636
 637         switch (device) {
 638         case PCI_DEVICE_ID_VIA_82C586_0:
 639                 r->name = "VIA";
 640                 r->get = pirq_via586_get;
 641                 r->set = pirq_via586_set;
 642                 return 1;
 643         case PCI_DEVICE_ID_VIA_82C596:
 644         case PCI_DEVICE_ID_VIA_82C686:
 645         case PCI_DEVICE_ID_VIA_8231:
 646         case PCI_DEVICE_ID_VIA_8233A:
 647         case PCI_DEVICE_ID_VIA_8235:
 648         case PCI_DEVICE_ID_VIA_8237:
 649                 /* FIXME: add new ones for 8233/5 */
 650                 r->name = "VIA";
 651                 r->get = pirq_via_get;
 652                 r->set = pirq_via_set;
 653                 return 1;
 654         }
 655         return 0;
 656 }
 657
 658 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 659 {
 660         switch (device) {
 661         case PCI_DEVICE_ID_VLSI_82C534:
 662                 r->name = "VLSI 82C534";
 663                 r->get = pirq_vlsi_get;
 664                 r->set = pirq_vlsi_set;
 665                 return 1;
 666         }
 667         return 0;
 668 }
 669
 670
 671 static __init int serverworks_router_probe(struct irq_router *r,
 672                 struct pci_dev *router, u16 device)
 673 {
 674         switch (device) {
 675         case PCI_DEVICE_ID_SERVERWORKS_OSB4:
 676         case PCI_DEVICE_ID_SERVERWORKS_CSB5:
 677                 r->name = "ServerWorks";
 678                 r->get = pirq_serverworks_get;
 679                 r->set = pirq_serverworks_set;
 680                 return 1;
 681         }
 682         return 0;
 683 }
 684
 685 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 686 {
 687         if (device != PCI_DEVICE_ID_SI_503)
 688                 return 0;
 689
 690         r->name = "SIS";
 691         r->get = pirq_sis_get;
 692         r->set = pirq_sis_set;
 693         return 1;
 694 }
 695
 696 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 697 {
 698         switch (device) {
 699         case PCI_DEVICE_ID_CYRIX_5520:
 700                 r->name = "NatSemi";
 701                 r->get = pirq_cyrix_get;
 702                 r->set = pirq_cyrix_set;
 703                 return 1;
 704         }
 705         return 0;
 706 }
 707
 708 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 709 {
 710         switch (device) {
 711         case PCI_DEVICE_ID_OPTI_82C700:
 712                 r->name = "OPTI";
 713                 r->get = pirq_opti_get;
 714                 r->set = pirq_opti_set;
 715                 return 1;
 716         }
 717         return 0;
 718 }
 719
 720 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 721 {
 722         switch (device) {
 723         case PCI_DEVICE_ID_ITE_IT8330G_0:
 724                 r->name = "ITE";
 725                 r->get = pirq_ite_get;
 726                 r->set = pirq_ite_set;
 727                 return 1;
 728         }
 729         return 0;
 730 }
 731
 732 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 733 {
 734         switch (device) {
 735         case PCI_DEVICE_ID_AL_M1533:
 736         case PCI_DEVICE_ID_AL_M1563:
 737                 r->name = "ALI";
 738                 r->get = pirq_ali_get;
 739                 r->set = pirq_ali_set;
 740                 return 1;
 741         }
 742         return 0;
 743 }
 744
 745 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 746 {
 747         switch (device) {
 748         case PCI_DEVICE_ID_AMD_VIPER_740B:
 749                 r->name = "AMD756";
 750                 break;
 751         case PCI_DEVICE_ID_AMD_VIPER_7413:
 752                 r->name = "AMD766";
 753                 break;
 754         case PCI_DEVICE_ID_AMD_VIPER_7443:
 755                 r->name = "AMD768";
 756                 break;
 757         default:
 758                 return 0;
 759         }
 760         r->get = pirq_amd756_get;
 761         r->set = pirq_amd756_set;
 762         return 1;
 763 }
 764
 765 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 766 {
 767         switch (device) {
 768         case PCI_DEVICE_ID_PICOPOWER_PT86C523:
 769                 r->name = "PicoPower PT86C523";
 770                 r->get = pirq_pico_get;
 771                 r->set = pirq_pico_set;
 772                 return 1;
 773
 774         case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
 775                 r->name = "PicoPower PT86C523 rev. BB+";
 776                 r->get = pirq_pico_get;
 777                 r->set = pirq_pico_set;
 778                 return 1;
 779         }
 780         return 0;
 781 }
 782
 783 static __initdata struct irq_router_handler pirq_routers[] = {
 784         { PCI_VENDOR_ID_INTEL, intel_router_probe },
 785         { PCI_VENDOR_ID_AL, ali_router_probe },
 786         { PCI_VENDOR_ID_ITE, ite_router_probe },
 787         { PCI_VENDOR_ID_VIA, via_router_probe },
 788         { PCI_VENDOR_ID_OPTI, opti_router_probe },
 789         { PCI_VENDOR_ID_SI, sis_router_probe },
 790         { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
 791         { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
 792         { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
 793         { PCI_VENDOR_ID_AMD, amd_router_probe },
 794         { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
 795         /* Someone with docs needs to add the ATI Radeon IGP */
 796         { 0, NULL }
 797 };
 798 static struct irq_router pirq_router;
 799 static struct pci_dev *pirq_router_dev;
 800
 801
 802 /*
 803  *      FIXME: should we have an option to say "generic for
 804  *      chipset" ?
 805  */
 806
 807 static void __init pirq_find_router(struct irq_router *r)
 808 {
 809         struct irq_routing_table *rt = pirq_table;
 810         struct irq_router_handler *h;
 811
 812 #ifdef CONFIG_PCI_BIOS
 813         if (!rt->signature) {
 814                 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
 815                 r->set = pirq_bios_set;
 816                 r->name = "BIOS";
 817                 return;
 818         }
 819 #endif
 820
 821         /* Default unless a driver reloads it */
 822         r->name = "default";
 823         r->get = NULL;
 824         r->set = NULL;
 825
 826         DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for %04x:%04x\n",
 827             rt->rtr_vendor, rt->rtr_device);
 828
 829         pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn);
 830         if (!pirq_router_dev) {
 831                 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
 832                         "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
 833                 return;
 834         }
 835
 836         for (h = pirq_routers; h->vendor; h++) {
 837                 /* First look for a router match */
 838                 if (rt->rtr_vendor == h->vendor &&
 839                         h->probe(r, pirq_router_dev, rt->rtr_device))
 840                         break;
 841                 /* Fall back to a device match */
 842                 if (pirq_router_dev->vendor == h->vendor &&
 843                         h->probe(r, pirq_router_dev, pirq_router_dev->device))
 844                         break;
 845         }
 846         dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x/%04x]\n",
 847                  pirq_router.name,
 848                  pirq_router_dev->vendor, pirq_router_dev->device);
 849
 850         /* The device remains referenced for the kernel lifetime */
 851 }
 852
 853 static struct irq_info *pirq_get_info(struct pci_dev *dev)
 854 {
 855         struct irq_routing_table *rt = pirq_table;
 856         int entries = (rt->size - sizeof(struct irq_routing_table)) /
 857                 sizeof(struct irq_info);
 858         struct irq_info *info;
 859
 860         for (info = rt->slots; entries--; info++)
 861                 if (info->bus == dev->bus->number &&
 862                         PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
 863                         return info;
 864         return NULL;
 865 }
 866
 867 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
 868 {
 869         u8 pin;
 870         struct irq_info *info;
 871         int i, pirq, newirq;
 872         int irq = 0;
 873         u32 mask;
 874         struct irq_router *r = &pirq_router;
 875         struct pci_dev *dev2 = NULL;
 876         char *msg = NULL;
 877
 878         /* Find IRQ pin */
 879         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
 880         if (!pin) {
 881                 dev_dbg(&dev->dev, "no interrupt pin\n");
 882                 return 0;
 883         }
 884         pin = pin - 1;
 885
 886         /* Find IRQ routing entry */
 887
 888         if (!pirq_table)
 889                 return 0;
 890
 891         info = pirq_get_info(dev);
 892         if (!info) {
 893                 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
 894                         'A' + pin);
 895                 return 0;
 896         }
 897         pirq = info->irq[pin].link;
 898         mask = info->irq[pin].bitmap;
 899         if (!pirq) {
 900                 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin);
 901                 return 0;
 902         }
 903         dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
 904                 'A' + pin, pirq, mask, pirq_table->exclusive_irqs);
 905         mask &= pcibios_irq_mask;
 906
 907         /* Work around broken HP Pavilion Notebooks which assign USB to
 908            IRQ 9 even though it is actually wired to IRQ 11 */
 909
 910         if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
 911                 dev->irq = 11;
 912                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
 913                 r->set(pirq_router_dev, dev, pirq, 11);
 914         }
 915
 916         /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
 917         if (acer_tm360_irqrouting && dev->irq == 11 &&
 918                 dev->vendor == PCI_VENDOR_ID_O2) {
 919                 pirq = 0x68;
 920                 mask = 0x400;
 921                 dev->irq = r->get(pirq_router_dev, dev, pirq);
 922                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 923         }
 924
 925         /*
 926          * Find the best IRQ to assign: use the one
 927          * reported by the device if possible.
 928          */
 929         newirq = dev->irq;
 930         if (newirq && !((1 << newirq) & mask)) {
 931                 if (pci_probe & PCI_USE_PIRQ_MASK)
 932                         newirq = 0;
 933                 else
 934                         dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
 935                                  "%#x; try pci=usepirqmask\n", newirq, mask);
 936         }
 937         if (!newirq && assign) {
 938                 for (i = 0; i < 16; i++) {
 939                         if (!(mask & (1 << i)))
 940                                 continue;
 941                         if (pirq_penalty[i] < pirq_penalty[newirq] &&
 942                                 can_request_irq(i, IRQF_SHARED))
 943                                 newirq = i;
 944                 }
 945         }
 946         dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin, newirq);
 947
 948         /* Check if it is hardcoded */
 949         if ((pirq & 0xf0) == 0xf0) {
 950                 irq = pirq & 0xf;
 951                 msg = "hardcoded";
 952         } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
 953         ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
 954                 msg = "found";
 955                 eisa_set_level_irq(irq);
 956         } else if (newirq && r->set &&
 957                 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
 958                 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
 959                         eisa_set_level_irq(newirq);
 960                         msg = "assigned";
 961                         irq = newirq;
 962                 }
 963         }
 964
 965         if (!irq) {
 966                 if (newirq && mask == (1 << newirq)) {
 967                         msg = "guessed";
 968                         irq = newirq;
 969                 } else {
 970                         dev_dbg(&dev->dev, "can't route interrupt\n");
 971                         return 0;
 972                 }
 973         }
 974         dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin, irq);
 975
 976         /* Update IRQ for all devices with the same pirq value */
 977         while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
 978                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
 979                 if (!pin)
 980                         continue;
 981                 pin--;
 982                 info = pirq_get_info(dev2);
 983                 if (!info)
 984                         continue;
 985                 if (info->irq[pin].link == pirq) {
 986                         /*
 987                          * We refuse to override the dev->irq
 988                          * information. Give a warning!
 989                          */
 990                         if (dev2->irq && dev2->irq != irq && \
 991                         (!(pci_probe & PCI_USE_PIRQ_MASK) || \
 992                         ((1 << dev2->irq) & mask))) {
 993 #ifndef CONFIG_PCI_MSI
 994                                 dev_info(&dev2->dev, "IRQ routing conflict: "
 995                                          "have IRQ %d, want IRQ %d\n",
 996                                          dev2->irq, irq);
 997 #endif
 998                                 continue;
 999                         }
1000                         dev2->irq = irq;
1001                         pirq_penalty[irq]++;
1002                         if (dev != dev2)
1003                                 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1004                                          irq, pci_name(dev2));
1005                 }
1006         }
1007         return 1;
1008 }
1009
1010 static void __init pcibios_fixup_irqs(void)
1011 {
1012         struct pci_dev *dev = NULL;
1013         u8 pin;
1014
1015         DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1016         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1017                 /*
1018                  * If the BIOS has set an out of range IRQ number, just
1019                  * ignore it.  Also keep track of which IRQ's are
1020                  * already in use.
1021                  */
1022                 if (dev->irq >= 16) {
1023                         dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1024                         dev->irq = 0;
1025                 }
1026                 /*
1027                  * If the IRQ is already assigned to a PCI device,
1028                  * ignore its ISA use penalty
1029                  */
1030                 if (pirq_penalty[dev->irq] >= 100 &&
1031                                 pirq_penalty[dev->irq] < 100000)
1032                         pirq_penalty[dev->irq] = 0;
1033                 pirq_penalty[dev->irq]++;
1034         }
1035
1036         dev = NULL;
1037         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1038                 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1039 #ifdef CONFIG_X86_IO_APIC
1040                 /*
1041                  * Recalculate IRQ numbers if we use the I/O APIC.
1042                  */
1043                 if (io_apic_assign_pci_irqs) {
1044                         int irq;
1045
1046                         if (pin) {
1047                                 /*
1048                                  * interrupt pins are numbered starting
1049                                  * from 1
1050                                  */
1051                                 pin--;
1052                                 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1053                                         PCI_SLOT(dev->devfn), pin);
1054         /*
1055          * Busses behind bridges are typically not listed in the MP-table.
1056          * In this case we have to look up the IRQ based on the parent bus,
1057          * parent slot, and pin number. The SMP code detects such bridged
1058          * busses itself so we should get into this branch reliably.
1059          */
1060                                 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1061                                         struct pci_dev *bridge = dev->bus->self;
1062
1063                                         pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1064                                         irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1065                                                         PCI_SLOT(bridge->devfn), pin);
1066                                         if (irq >= 0)
1067                                                 dev_warn(&dev->dev, "using bridge %s INT %c to get IRQ %d\n",
1068                                                          pci_name(bridge),
1069                                                          'A' + pin, irq);
1070                                 }
1071                                 if (irq >= 0) {
1072                                         dev_info(&dev->dev, "PCI->APIC IRQ transform: INT %c -> IRQ %d\n", 'A' + pin, irq);
1073                                         dev->irq = irq;
1074                                 }
1075                         }
1076                 }
1077 #endif
1078                 /*
1079                  * Still no IRQ? Try to lookup one...
1080                  */
1081                 if (pin && !dev->irq)
1082                         pcibios_lookup_irq(dev, 0);
1083         }
1084 }
1085
1086 /*
1087  * Work around broken HP Pavilion Notebooks which assign USB to
1088  * IRQ 9 even though it is actually wired to IRQ 11
1089  */
1090 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1091 {
1092         if (!broken_hp_bios_irq9) {
1093                 broken_hp_bios_irq9 = 1;
1094                 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1095                         d->ident);
1096         }
1097         return 0;
1098 }
1099
1100 /*
1101  * Work around broken Acer TravelMate 360 Notebooks which assign
1102  * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1103  */
1104 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1105 {
1106         if (!acer_tm360_irqrouting) {
1107                 acer_tm360_irqrouting = 1;
1108                 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1109                         d->ident);
1110         }
1111         return 0;
1112 }
1113
1114 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1115         {
1116                 .callback = fix_broken_hp_bios_irq9,
1117                 .ident = "HP Pavilion N5400 Series Laptop",
1118                 .matches = {
1119                         DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1120                         DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1121                         DMI_MATCH(DMI_PRODUCT_VERSION,
1122                                 "HP Pavilion Notebook Model GE"),
1123                         DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1124                 },
1125         },
1126         {
1127                 .callback = fix_acer_tm360_irqrouting,
1128                 .ident = "Acer TravelMate 36x Laptop",
1129                 .matches = {
1130                         DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1131                         DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1132                 },
1133         },
1134         { }
1135 };
1136
1137 int __init pcibios_irq_init(void)
1138 {
1139         DBG(KERN_DEBUG "PCI: IRQ init\n");
1140
1141         if (pcibios_enable_irq || raw_pci_ops == NULL)
1142                 return 0;
1143
1144         dmi_check_system(pciirq_dmi_table);
1145
1146         pirq_table = pirq_find_routing_table();
1147
1148 #ifdef CONFIG_PCI_BIOS
1149         if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1150                 pirq_table = pcibios_get_irq_routing_table();
1151 #endif
1152         if (pirq_table) {
1153                 pirq_peer_trick();
1154                 pirq_find_router(&pirq_router);
1155                 if (pirq_table->exclusive_irqs) {
1156                         int i;
1157                         for (i = 0; i < 16; i++)
1158                                 if (!(pirq_table->exclusive_irqs & (1 << i)))
1159                                         pirq_penalty[i] += 100;
1160                 }
1161                 /*
1162                  * If we're using the I/O APIC, avoid using the PCI IRQ
1163                  * routing table
1164                  */
1165                 if (io_apic_assign_pci_irqs)
1166                         pirq_table = NULL;
1167         }
1168
1169         pcibios_enable_irq = pirq_enable_irq;
1170
1171         pcibios_fixup_irqs();
1172         return 0;
1173 }
1174
1175 static void pirq_penalize_isa_irq(int irq, int active)
1176 {
1177         /*
1178          *  If any ISAPnP device reports an IRQ in its list of possible
1179          *  IRQ's, we try to avoid assigning it to PCI devices.
1180          */
1181         if (irq < 16) {
1182                 if (active)
1183                         pirq_penalty[irq] += 1000;
1184                 else
1185                         pirq_penalty[irq] += 100;
1186         }
1187 }
1188
1189 void pcibios_penalize_isa_irq(int irq, int active)
1190 {
1191 #ifdef CONFIG_ACPI
1192         if (!acpi_noirq)
1193                 acpi_penalize_isa_irq(irq, active);
1194         else
1195 #endif
1196                 pirq_penalize_isa_irq(irq, active);
1197 }
1198
1199 static int pirq_enable_irq(struct pci_dev *dev)
1200 {
1201         u8 pin;
1202         struct pci_dev *temp_dev;
1203
1204         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1205         if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1206                 char *msg = "";
1207
1208                 pin--; /* interrupt pins are numbered starting from 1 */
1209
1210                 if (io_apic_assign_pci_irqs) {
1211                         int irq;
1212
1213                         irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1214                         /*
1215                          * Busses behind bridges are typically not listed in the MP-table.
1216                          * In this case we have to look up the IRQ based on the parent bus,
1217                          * parent slot, and pin number. The SMP code detects such bridged
1218                          * busses itself so we should get into this branch reliably.
1219                          */
1220                         temp_dev = dev;
1221                         while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1222                                 struct pci_dev *bridge = dev->bus->self;
1223
1224                                 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1225                                 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1226                                                 PCI_SLOT(bridge->devfn), pin);
1227                                 if (irq >= 0)
1228                                         dev_warn(&dev->dev, "using bridge %s "
1229                                                  "INT %c to get IRQ %d\n",
1230                                                  pci_name(bridge), 'A' + pin,
1231                                                  irq);
1232                                 dev = bridge;
1233                         }
1234                         dev = temp_dev;
1235                         if (irq >= 0) {
1236                                 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1237                                          "INT %c -> IRQ %d\n", 'A' + pin, irq);
1238                                 dev->irq = irq;
1239                                 return 0;
1240                         } else
1241                                 msg = "; probably buggy MP table";
1242                 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1243                         msg = "";
1244                 else
1245                         msg = "; please try using pci=biosirq";
1246
1247                 /*
1248                  * With IDE legacy devices the IRQ lookup failure is not
1249                  * a problem..
1250                  */
1251                 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1252                                 !(dev->class & 0x5))
1253                         return 0;
1254
1255                 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1256                          'A' + pin, msg);
1257         }
1258         return 0;
1259 }