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AT91: Added a generic way to setup AT91 serial ports in Kconfig
[linux-2.6/pdupreez.git] / sound / pci / hda / hda_intel.c
blob1c53e337ecb2dce93b833dcce526f64288cc9136
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
51
52
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56 static char *model[SNDRV_CARDS];
57 static int position_fix[SNDRV_CARDS];
58 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
59 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int single_cmd;
61 static int enable_msi;
62
63 module_param_array(index, int, NULL, 0444);
64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
65 module_param_array(id, charp, NULL, 0444);
66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
67 module_param_array(enable, bool, NULL, 0444);
68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
69 module_param_array(model, charp, NULL, 0444);
70 MODULE_PARM_DESC(model, "Use the given board model.");
71 module_param_array(position_fix, int, NULL, 0444);
72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
73 "(0 = auto, 1 = none, 2 = POSBUF).");
74 module_param_array(bdl_pos_adj, int, NULL, 0644);
75 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
76 module_param_array(probe_mask, int, NULL, 0444);
77 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
78 module_param(single_cmd, bool, 0444);
79 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
80 "(for debugging only).");
81 module_param(enable_msi, int, 0444);
82 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
83
84 #ifdef CONFIG_SND_HDA_POWER_SAVE
85 /* power_save option is defined in hda_codec.c */
86
87 /* reset the HD-audio controller in power save mode.
88 * this may give more power-saving, but will take longer time to
89 * wake up.
90 */
91 static int power_save_controller = 1;
92 module_param(power_save_controller, bool, 0644);
93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
94 #endif
95
96 MODULE_LICENSE("GPL");
97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
98 "{Intel, ICH6M},"
99 "{Intel, ICH7},"
100 "{Intel, ESB2},"
101 "{Intel, ICH8},"
102 "{Intel, ICH9},"
103 "{Intel, ICH10},"
104 "{Intel, PCH},"
105 "{Intel, SCH},"
106 "{ATI, SB450},"
107 "{ATI, SB600},"
108 "{ATI, RS600},"
109 "{ATI, RS690},"
110 "{ATI, RS780},"
111 "{ATI, R600},"
112 "{ATI, RV630},"
113 "{ATI, RV610},"
114 "{ATI, RV670},"
115 "{ATI, RV635},"
116 "{ATI, RV620},"
117 "{ATI, RV770},"
118 "{VIA, VT8251},"
119 "{VIA, VT8237A},"
120 "{SiS, SIS966},"
121 "{ULI, M5461}}");
122 MODULE_DESCRIPTION("Intel HDA driver");
123
124 #define SFX "hda-intel: "
125
126
127 /*
128 * registers
129 */
130 #define ICH6_REG_GCAP 0x00
131 #define ICH6_REG_VMIN 0x02
132 #define ICH6_REG_VMAJ 0x03
133 #define ICH6_REG_OUTPAY 0x04
134 #define ICH6_REG_INPAY 0x06
135 #define ICH6_REG_GCTL 0x08
136 #define ICH6_REG_WAKEEN 0x0c
137 #define ICH6_REG_STATESTS 0x0e
138 #define ICH6_REG_GSTS 0x10
139 #define ICH6_REG_INTCTL 0x20
140 #define ICH6_REG_INTSTS 0x24
141 #define ICH6_REG_WALCLK 0x30
142 #define ICH6_REG_SYNC 0x34
143 #define ICH6_REG_CORBLBASE 0x40
144 #define ICH6_REG_CORBUBASE 0x44
145 #define ICH6_REG_CORBWP 0x48
146 #define ICH6_REG_CORBRP 0x4A
147 #define ICH6_REG_CORBCTL 0x4c
148 #define ICH6_REG_CORBSTS 0x4d
149 #define ICH6_REG_CORBSIZE 0x4e
150
151 #define ICH6_REG_RIRBLBASE 0x50
152 #define ICH6_REG_RIRBUBASE 0x54
153 #define ICH6_REG_RIRBWP 0x58
154 #define ICH6_REG_RINTCNT 0x5a
155 #define ICH6_REG_RIRBCTL 0x5c
156 #define ICH6_REG_RIRBSTS 0x5d
157 #define ICH6_REG_RIRBSIZE 0x5e
158
159 #define ICH6_REG_IC 0x60
160 #define ICH6_REG_IR 0x64
161 #define ICH6_REG_IRS 0x68
162 #define ICH6_IRS_VALID (1<<1)
163 #define ICH6_IRS_BUSY (1<<0)
164
165 #define ICH6_REG_DPLBASE 0x70
166 #define ICH6_REG_DPUBASE 0x74
167 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
168
169 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
170 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
171
172 /* stream register offsets from stream base */
173 #define ICH6_REG_SD_CTL 0x00
174 #define ICH6_REG_SD_STS 0x03
175 #define ICH6_REG_SD_LPIB 0x04
176 #define ICH6_REG_SD_CBL 0x08
177 #define ICH6_REG_SD_LVI 0x0c
178 #define ICH6_REG_SD_FIFOW 0x0e
179 #define ICH6_REG_SD_FIFOSIZE 0x10
180 #define ICH6_REG_SD_FORMAT 0x12
181 #define ICH6_REG_SD_BDLPL 0x18
182 #define ICH6_REG_SD_BDLPU 0x1c
183
184 /* PCI space */
185 #define ICH6_PCIREG_TCSEL 0x44
186
187 /*
188 * other constants
189 */
190
191 /* max number of SDs */
192 /* ICH, ATI and VIA have 4 playback and 4 capture */
193 #define ICH6_NUM_CAPTURE 4
194 #define ICH6_NUM_PLAYBACK 4
195
196 /* ULI has 6 playback and 5 capture */
197 #define ULI_NUM_CAPTURE 5
198 #define ULI_NUM_PLAYBACK 6
199
200 /* ATI HDMI has 1 playback and 0 capture */
201 #define ATIHDMI_NUM_CAPTURE 0
202 #define ATIHDMI_NUM_PLAYBACK 1
203
204 /* TERA has 4 playback and 3 capture */
205 #define TERA_NUM_CAPTURE 3
206 #define TERA_NUM_PLAYBACK 4
207
208 /* this number is statically defined for simplicity */
209 #define MAX_AZX_DEV 16
210
211 /* max number of fragments - we may use more if allocating more pages for BDL */
212 #define BDL_SIZE 4096
213 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
214 #define AZX_MAX_FRAG 32
215 /* max buffer size - no h/w limit, you can increase as you like */
216 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
217 /* max number of PCM devics per card */
218 #define AZX_MAX_PCMS 8
219
220 /* RIRB int mask: overrun[2], response[0] */
221 #define RIRB_INT_RESPONSE 0x01
222 #define RIRB_INT_OVERRUN 0x04
223 #define RIRB_INT_MASK 0x05
224
225 /* STATESTS int mask: SD2,SD1,SD0 */
226 #define AZX_MAX_CODECS 3
227 #define STATESTS_INT_MASK 0x07
228
229 /* SD_CTL bits */
230 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
231 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
232 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
233 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
234 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
235 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
236 #define SD_CTL_STREAM_TAG_SHIFT 20
237
238 /* SD_CTL and SD_STS */
239 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
240 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
241 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
242 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
243 SD_INT_COMPLETE)
244
245 /* SD_STS */
246 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
247
248 /* INTCTL and INTSTS */
249 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
250 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
251 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
252
253 /* GCTL unsolicited response enable bit */
254 #define ICH6_GCTL_UREN (1<<8)
255
256 /* GCTL reset bit */
257 #define ICH6_GCTL_RESET (1<<0)
258
259 /* CORB/RIRB control, read/write pointer */
260 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
261 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
262 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
263 /* below are so far hardcoded - should read registers in future */
264 #define ICH6_MAX_CORB_ENTRIES 256
265 #define ICH6_MAX_RIRB_ENTRIES 256
266
267 /* position fix mode */
268 enum {
269 POS_FIX_AUTO,
270 POS_FIX_LPIB,
271 POS_FIX_POSBUF,
272 };
273
274 /* Defines for ATI HD Audio support in SB450 south bridge */
275 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
276 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
277
278 /* Defines for Nvidia HDA support */
279 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
280 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
281 #define NVIDIA_HDA_ISTRM_COH 0x4d
282 #define NVIDIA_HDA_OSTRM_COH 0x4c
283 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
284
285 /* Defines for Intel SCH HDA snoop control */
286 #define INTEL_SCH_HDA_DEVC 0x78
287 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
288
289
290 /*
291 */
292
293 struct azx_dev {
294 struct snd_dma_buffer bdl; /* BDL buffer */
295 u32 *posbuf; /* position buffer pointer */
296
297 unsigned int bufsize; /* size of the play buffer in bytes */
298 unsigned int period_bytes; /* size of the period in bytes */
299 unsigned int frags; /* number for period in the play buffer */
300 unsigned int fifo_size; /* FIFO size */
301
302 void __iomem *sd_addr; /* stream descriptor pointer */
303
304 u32 sd_int_sta_mask; /* stream int status mask */
305
306 /* pcm support */
307 struct snd_pcm_substream *substream; /* assigned substream,
308 * set in PCM open
309 */
310 unsigned int format_val; /* format value to be set in the
311 * controller and the codec
312 */
313 unsigned char stream_tag; /* assigned stream */
314 unsigned char index; /* stream index */
315
316 unsigned int opened :1;
317 unsigned int running :1;
318 unsigned int irq_pending :1;
319 unsigned int irq_ignore :1;
320 };
321
322 /* CORB/RIRB */
323 struct azx_rb {
324 u32 *buf; /* CORB/RIRB buffer
325 * Each CORB entry is 4byte, RIRB is 8byte
326 */
327 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
328 /* for RIRB */
329 unsigned short rp, wp; /* read/write pointers */
330 int cmds; /* number of pending requests */
331 u32 res; /* last read value */
332 };
333
334 struct azx {
335 struct snd_card *card;
336 struct pci_dev *pci;
337 int dev_index;
338
339 /* chip type specific */
340 int driver_type;
341 int playback_streams;
342 int playback_index_offset;
343 int capture_streams;
344 int capture_index_offset;
345 int num_streams;
346
347 /* pci resources */
348 unsigned long addr;
349 void __iomem *remap_addr;
350 int irq;
351
352 /* locks */
353 spinlock_t reg_lock;
354 struct mutex open_mutex;
355
356 /* streams (x num_streams) */
357 struct azx_dev *azx_dev;
358
359 /* PCM */
360 struct snd_pcm *pcm[AZX_MAX_PCMS];
361
362 /* HD codec */
363 unsigned short codec_mask;
364 struct hda_bus *bus;
365
366 /* CORB/RIRB */
367 struct azx_rb corb;
368 struct azx_rb rirb;
369
370 /* CORB/RIRB and position buffers */
371 struct snd_dma_buffer rb;
372 struct snd_dma_buffer posbuf;
373
374 /* flags */
375 int position_fix;
376 unsigned int running :1;
377 unsigned int initialized :1;
378 unsigned int single_cmd :1;
379 unsigned int polling_mode :1;
380 unsigned int msi :1;
381 unsigned int irq_pending_warned :1;
382
383 /* for debugging */
384 unsigned int last_cmd; /* last issued command (to sync) */
385
386 /* for pending irqs */
387 struct work_struct irq_pending_work;
388 };
389
390 /* driver types */
391 enum {
392 AZX_DRIVER_ICH,
393 AZX_DRIVER_SCH,
394 AZX_DRIVER_ATI,
395 AZX_DRIVER_ATIHDMI,
396 AZX_DRIVER_VIA,
397 AZX_DRIVER_SIS,
398 AZX_DRIVER_ULI,
399 AZX_DRIVER_NVIDIA,
400 AZX_DRIVER_TERA,
401 };
402
403 static char *driver_short_names[] __devinitdata = {
404 [AZX_DRIVER_ICH] = "HDA Intel",
405 [AZX_DRIVER_SCH] = "HDA Intel MID",
406 [AZX_DRIVER_ATI] = "HDA ATI SB",
407 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
408 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
409 [AZX_DRIVER_SIS] = "HDA SIS966",
410 [AZX_DRIVER_ULI] = "HDA ULI M5461",
411 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
412 [AZX_DRIVER_TERA] = "HDA Teradici",
413 };
414
415 /*
416 * macros for easy use
417 */
418 #define azx_writel(chip,reg,value) \
419 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
420 #define azx_readl(chip,reg) \
421 readl((chip)->remap_addr + ICH6_REG_##reg)
422 #define azx_writew(chip,reg,value) \
423 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
424 #define azx_readw(chip,reg) \
425 readw((chip)->remap_addr + ICH6_REG_##reg)
426 #define azx_writeb(chip,reg,value) \
427 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
428 #define azx_readb(chip,reg) \
429 readb((chip)->remap_addr + ICH6_REG_##reg)
430
431 #define azx_sd_writel(dev,reg,value) \
432 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
433 #define azx_sd_readl(dev,reg) \
434 readl((dev)->sd_addr + ICH6_REG_##reg)
435 #define azx_sd_writew(dev,reg,value) \
436 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
437 #define azx_sd_readw(dev,reg) \
438 readw((dev)->sd_addr + ICH6_REG_##reg)
439 #define azx_sd_writeb(dev,reg,value) \
440 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
441 #define azx_sd_readb(dev,reg) \
442 readb((dev)->sd_addr + ICH6_REG_##reg)
443
444 /* for pcm support */
445 #define get_azx_dev(substream) (substream->runtime->private_data)
446
447 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
448
449 /*
450 * Interface for HD codec
451 */
452
453 /*
454 * CORB / RIRB interface
455 */
456 static int azx_alloc_cmd_io(struct azx *chip)
457 {
458 int err;
459
460 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
461 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
462 snd_dma_pci_data(chip->pci),
463 PAGE_SIZE, &chip->rb);
464 if (err < 0) {
465 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
466 return err;
467 }
468 return 0;
469 }
470
471 static void azx_init_cmd_io(struct azx *chip)
472 {
473 /* CORB set up */
474 chip->corb.addr = chip->rb.addr;
475 chip->corb.buf = (u32 *)chip->rb.area;
476 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
477 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
478
479 /* set the corb size to 256 entries (ULI requires explicitly) */
480 azx_writeb(chip, CORBSIZE, 0x02);
481 /* set the corb write pointer to 0 */
482 azx_writew(chip, CORBWP, 0);
483 /* reset the corb hw read pointer */
484 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
485 /* enable corb dma */
486 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
487
488 /* RIRB set up */
489 chip->rirb.addr = chip->rb.addr + 2048;
490 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
491 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
492 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
493
494 /* set the rirb size to 256 entries (ULI requires explicitly) */
495 azx_writeb(chip, RIRBSIZE, 0x02);
496 /* reset the rirb hw write pointer */
497 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
498 /* set N=1, get RIRB response interrupt for new entry */
499 azx_writew(chip, RINTCNT, 1);
500 /* enable rirb dma and response irq */
501 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
502 chip->rirb.rp = chip->rirb.cmds = 0;
503 }
504
505 static void azx_free_cmd_io(struct azx *chip)
506 {
507 /* disable ringbuffer DMAs */
508 azx_writeb(chip, RIRBCTL, 0);
509 azx_writeb(chip, CORBCTL, 0);
510 }
511
512 /* send a command */
513 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
514 {
515 struct azx *chip = codec->bus->private_data;
516 unsigned int wp;
517
518 /* add command to corb */
519 wp = azx_readb(chip, CORBWP);
520 wp++;
521 wp %= ICH6_MAX_CORB_ENTRIES;
522
523 spin_lock_irq(&chip->reg_lock);
524 chip->rirb.cmds++;
525 chip->corb.buf[wp] = cpu_to_le32(val);
526 azx_writel(chip, CORBWP, wp);
527 spin_unlock_irq(&chip->reg_lock);
528
529 return 0;
530 }
531
532 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
533
534 /* retrieve RIRB entry - called from interrupt handler */
535 static void azx_update_rirb(struct azx *chip)
536 {
537 unsigned int rp, wp;
538 u32 res, res_ex;
539
540 wp = azx_readb(chip, RIRBWP);
541 if (wp == chip->rirb.wp)
542 return;
543 chip->rirb.wp = wp;
544
545 while (chip->rirb.rp != wp) {
546 chip->rirb.rp++;
547 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
548
549 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
550 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
551 res = le32_to_cpu(chip->rirb.buf[rp]);
552 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
553 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
554 else if (chip->rirb.cmds) {
555 chip->rirb.res = res;
556 smp_wmb();
557 chip->rirb.cmds--;
558 }
559 }
560 }
561
562 /* receive a response */
563 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
564 {
565 struct azx *chip = codec->bus->private_data;
566 unsigned long timeout;
567
568 again:
569 timeout = jiffies + msecs_to_jiffies(1000);
570 for (;;) {
571 if (chip->polling_mode) {
572 spin_lock_irq(&chip->reg_lock);
573 azx_update_rirb(chip);
574 spin_unlock_irq(&chip->reg_lock);
575 }
576 if (!chip->rirb.cmds) {
577 smp_rmb();
578 return chip->rirb.res; /* the last value */
579 }
580 if (time_after(jiffies, timeout))
581 break;
582 if (codec->bus->needs_damn_long_delay)
583 msleep(2); /* temporary workaround */
584 else {
585 udelay(10);
586 cond_resched();
587 }
588 }
589
590 if (chip->msi) {
591 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
592 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
593 free_irq(chip->irq, chip);
594 chip->irq = -1;
595 pci_disable_msi(chip->pci);
596 chip->msi = 0;
597 if (azx_acquire_irq(chip, 1) < 0)
598 return -1;
599 goto again;
600 }
601
602 if (!chip->polling_mode) {
603 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
604 "switching to polling mode: last cmd=0x%08x\n",
605 chip->last_cmd);
606 chip->polling_mode = 1;
607 goto again;
608 }
609
610 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
611 "switching to single_cmd mode: last cmd=0x%08x\n",
612 chip->last_cmd);
613 chip->rirb.rp = azx_readb(chip, RIRBWP);
614 chip->rirb.cmds = 0;
615 /* switch to single_cmd mode */
616 chip->single_cmd = 1;
617 azx_free_cmd_io(chip);
618 return -1;
619 }
620
621 /*
622 * Use the single immediate command instead of CORB/RIRB for simplicity
623 *
624 * Note: according to Intel, this is not preferred use. The command was
625 * intended for the BIOS only, and may get confused with unsolicited
626 * responses. So, we shouldn't use it for normal operation from the
627 * driver.
628 * I left the codes, however, for debugging/testing purposes.
629 */
630
631 /* send a command */
632 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
633 {
634 struct azx *chip = codec->bus->private_data;
635 int timeout = 50;
636
637 while (timeout--) {
638 /* check ICB busy bit */
639 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
640 /* Clear IRV valid bit */
641 azx_writew(chip, IRS, azx_readw(chip, IRS) |
642 ICH6_IRS_VALID);
643 azx_writel(chip, IC, val);
644 azx_writew(chip, IRS, azx_readw(chip, IRS) |
645 ICH6_IRS_BUSY);
646 return 0;
647 }
648 udelay(1);
649 }
650 if (printk_ratelimit())
651 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
652 azx_readw(chip, IRS), val);
653 return -EIO;
654 }
655
656 /* receive a response */
657 static unsigned int azx_single_get_response(struct hda_codec *codec)
658 {
659 struct azx *chip = codec->bus->private_data;
660 int timeout = 50;
661
662 while (timeout--) {
663 /* check IRV busy bit */
664 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
665 return azx_readl(chip, IR);
666 udelay(1);
667 }
668 if (printk_ratelimit())
669 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
670 azx_readw(chip, IRS));
671 return (unsigned int)-1;
672 }
673
674 /*
675 * The below are the main callbacks from hda_codec.
676 *
677 * They are just the skeleton to call sub-callbacks according to the
678 * current setting of chip->single_cmd.
679 */
680
681 /* send a command */
682 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
683 int direct, unsigned int verb,
684 unsigned int para)
685 {
686 struct azx *chip = codec->bus->private_data;
687 u32 val;
688
689 val = (u32)(codec->addr & 0x0f) << 28;
690 val |= (u32)direct << 27;
691 val |= (u32)nid << 20;
692 val |= verb << 8;
693 val |= para;
694 chip->last_cmd = val;
695
696 if (chip->single_cmd)
697 return azx_single_send_cmd(codec, val);
698 else
699 return azx_corb_send_cmd(codec, val);
700 }
701
702 /* get a response */
703 static unsigned int azx_get_response(struct hda_codec *codec)
704 {
705 struct azx *chip = codec->bus->private_data;
706 if (chip->single_cmd)
707 return azx_single_get_response(codec);
708 else
709 return azx_rirb_get_response(codec);
710 }
711
712 #ifdef CONFIG_SND_HDA_POWER_SAVE
713 static void azx_power_notify(struct hda_codec *codec);
714 #endif
715
716 /* reset codec link */
717 static int azx_reset(struct azx *chip)
718 {
719 int count;
720
721 /* clear STATESTS */
722 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
723
724 /* reset controller */
725 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
726
727 count = 50;
728 while (azx_readb(chip, GCTL) && --count)
729 msleep(1);
730
731 /* delay for >= 100us for codec PLL to settle per spec
732 * Rev 0.9 section 5.5.1
733 */
734 msleep(1);
735
736 /* Bring controller out of reset */
737 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
738
739 count = 50;
740 while (!azx_readb(chip, GCTL) && --count)
741 msleep(1);
742
743 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
744 msleep(1);
745
746 /* check to see if controller is ready */
747 if (!azx_readb(chip, GCTL)) {
748 snd_printd("azx_reset: controller not ready!\n");
749 return -EBUSY;
750 }
751
752 /* Accept unsolicited responses */
753 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
754
755 /* detect codecs */
756 if (!chip->codec_mask) {
757 chip->codec_mask = azx_readw(chip, STATESTS);
758 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
759 }
760
761 return 0;
762 }
763
764
765 /*
766 * Lowlevel interface
767 */
768
769 /* enable interrupts */
770 static void azx_int_enable(struct azx *chip)
771 {
772 /* enable controller CIE and GIE */
773 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
774 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
775 }
776
777 /* disable interrupts */
778 static void azx_int_disable(struct azx *chip)
779 {
780 int i;
781
782 /* disable interrupts in stream descriptor */
783 for (i = 0; i < chip->num_streams; i++) {
784 struct azx_dev *azx_dev = &chip->azx_dev[i];
785 azx_sd_writeb(azx_dev, SD_CTL,
786 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
787 }
788
789 /* disable SIE for all streams */
790 azx_writeb(chip, INTCTL, 0);
791
792 /* disable controller CIE and GIE */
793 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
794 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
795 }
796
797 /* clear interrupts */
798 static void azx_int_clear(struct azx *chip)
799 {
800 int i;
801
802 /* clear stream status */
803 for (i = 0; i < chip->num_streams; i++) {
804 struct azx_dev *azx_dev = &chip->azx_dev[i];
805 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
806 }
807
808 /* clear STATESTS */
809 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
810
811 /* clear rirb status */
812 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
813
814 /* clear int status */
815 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
816 }
817
818 /* start a stream */
819 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
820 {
821 /* enable SIE */
822 azx_writeb(chip, INTCTL,
823 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
824 /* set DMA start and interrupt mask */
825 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
826 SD_CTL_DMA_START | SD_INT_MASK);
827 }
828
829 /* stop a stream */
830 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
831 {
832 /* stop DMA */
833 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
834 ~(SD_CTL_DMA_START | SD_INT_MASK));
835 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
836 /* disable SIE */
837 azx_writeb(chip, INTCTL,
838 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
839 }
840
841
842 /*
843 * reset and start the controller registers
844 */
845 static void azx_init_chip(struct azx *chip)
846 {
847 if (chip->initialized)
848 return;
849
850 /* reset controller */
851 azx_reset(chip);
852
853 /* initialize interrupts */
854 azx_int_clear(chip);
855 azx_int_enable(chip);
856
857 /* initialize the codec command I/O */
858 if (!chip->single_cmd)
859 azx_init_cmd_io(chip);
860
861 /* program the position buffer */
862 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
863 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
864
865 chip->initialized = 1;
866 }
867
868 /*
869 * initialize the PCI registers
870 */
871 /* update bits in a PCI register byte */
872 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
873 unsigned char mask, unsigned char val)
874 {
875 unsigned char data;
876
877 pci_read_config_byte(pci, reg, &data);
878 data &= ~mask;
879 data |= (val & mask);
880 pci_write_config_byte(pci, reg, data);
881 }
882
883 static void azx_init_pci(struct azx *chip)
884 {
885 unsigned short snoop;
886
887 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
888 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
889 * Ensuring these bits are 0 clears playback static on some HD Audio
890 * codecs
891 */
892 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
893
894 switch (chip->driver_type) {
895 case AZX_DRIVER_ATI:
896 /* For ATI SB450 azalia HD audio, we need to enable snoop */
897 update_pci_byte(chip->pci,
898 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
899 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
900 break;
901 case AZX_DRIVER_NVIDIA:
902 /* For NVIDIA HDA, enable snoop */
903 update_pci_byte(chip->pci,
904 NVIDIA_HDA_TRANSREG_ADDR,
905 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
906 update_pci_byte(chip->pci,
907 NVIDIA_HDA_ISTRM_COH,
908 0x01, NVIDIA_HDA_ENABLE_COHBIT);
909 update_pci_byte(chip->pci,
910 NVIDIA_HDA_OSTRM_COH,
911 0x01, NVIDIA_HDA_ENABLE_COHBIT);
912 break;
913 case AZX_DRIVER_SCH:
914 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
915 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
916 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
917 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
918 pci_read_config_word(chip->pci,
919 INTEL_SCH_HDA_DEVC, &snoop);
920 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
921 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
922 ? "Failed" : "OK");
923 }
924 break;
925
926 }
927 }
928
929
930 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
931
932 /*
933 * interrupt handler
934 */
935 static irqreturn_t azx_interrupt(int irq, void *dev_id)
936 {
937 struct azx *chip = dev_id;
938 struct azx_dev *azx_dev;
939 u32 status;
940 int i;
941
942 spin_lock(&chip->reg_lock);
943
944 status = azx_readl(chip, INTSTS);
945 if (status == 0) {
946 spin_unlock(&chip->reg_lock);
947 return IRQ_NONE;
948 }
949
950 for (i = 0; i < chip->num_streams; i++) {
951 azx_dev = &chip->azx_dev[i];
952 if (status & azx_dev->sd_int_sta_mask) {
953 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
954 if (!azx_dev->substream || !azx_dev->running)
955 continue;
956 /* ignore the first dummy IRQ (due to pos_adj) */
957 if (azx_dev->irq_ignore) {
958 azx_dev->irq_ignore = 0;
959 continue;
960 }
961 /* check whether this IRQ is really acceptable */
962 if (azx_position_ok(chip, azx_dev)) {
963 azx_dev->irq_pending = 0;
964 spin_unlock(&chip->reg_lock);
965 snd_pcm_period_elapsed(azx_dev->substream);
966 spin_lock(&chip->reg_lock);
967 } else {
968 /* bogus IRQ, process it later */
969 azx_dev->irq_pending = 1;
970 schedule_work(&chip->irq_pending_work);
971 }
972 }
973 }
974
975 /* clear rirb int */
976 status = azx_readb(chip, RIRBSTS);
977 if (status & RIRB_INT_MASK) {
978 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
979 azx_update_rirb(chip);
980 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
981 }
982
983 #if 0
984 /* clear state status int */
985 if (azx_readb(chip, STATESTS) & 0x04)
986 azx_writeb(chip, STATESTS, 0x04);
987 #endif
988 spin_unlock(&chip->reg_lock);
989
990 return IRQ_HANDLED;
991 }
992
993
994 /*
995 * set up a BDL entry
996 */
997 static int setup_bdle(struct snd_pcm_substream *substream,
998 struct azx_dev *azx_dev, u32 **bdlp,
999 int ofs, int size, int with_ioc)
1000 {
1001 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
1002 u32 *bdl = *bdlp;
1003
1004 while (size > 0) {
1005 dma_addr_t addr;
1006 int chunk;
1007
1008 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1009 return -EINVAL;
1010
1011 addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1012 /* program the address field of the BDL entry */
1013 bdl[0] = cpu_to_le32((u32)addr);
1014 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1015 /* program the size field of the BDL entry */
1016 chunk = PAGE_SIZE - (ofs % PAGE_SIZE);
1017 if (size < chunk)
1018 chunk = size;
1019 bdl[2] = cpu_to_le32(chunk);
1020 /* program the IOC to enable interrupt
1021 * only when the whole fragment is processed
1022 */
1023 size -= chunk;
1024 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1025 bdl += 4;
1026 azx_dev->frags++;
1027 ofs += chunk;
1028 }
1029 *bdlp = bdl;
1030 return ofs;
1031 }
1032
1033 /*
1034 * set up BDL entries
1035 */
1036 static int azx_setup_periods(struct azx *chip,
1037 struct snd_pcm_substream *substream,
1038 struct azx_dev *azx_dev)
1039 {
1040 u32 *bdl;
1041 int i, ofs, periods, period_bytes;
1042 int pos_adj;
1043
1044 /* reset BDL address */
1045 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1046 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1047
1048 period_bytes = snd_pcm_lib_period_bytes(substream);
1049 azx_dev->period_bytes = period_bytes;
1050 periods = azx_dev->bufsize / period_bytes;
1051
1052 /* program the initial BDL entries */
1053 bdl = (u32 *)azx_dev->bdl.area;
1054 ofs = 0;
1055 azx_dev->frags = 0;
1056 azx_dev->irq_ignore = 0;
1057 pos_adj = bdl_pos_adj[chip->dev_index];
1058 if (pos_adj > 0) {
1059 struct snd_pcm_runtime *runtime = substream->runtime;
1060 int pos_align = pos_adj;
1061 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1062 if (!pos_adj)
1063 pos_adj = pos_align;
1064 else
1065 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1066 pos_align;
1067 pos_adj = frames_to_bytes(runtime, pos_adj);
1068 if (pos_adj >= period_bytes) {
1069 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1070 bdl_pos_adj[chip->dev_index]);
1071 pos_adj = 0;
1072 } else {
1073 ofs = setup_bdle(substream, azx_dev,
1074 &bdl, ofs, pos_adj, 1);
1075 if (ofs < 0)
1076 goto error;
1077 azx_dev->irq_ignore = 1;
1078 }
1079 } else
1080 pos_adj = 0;
1081 for (i = 0; i < periods; i++) {
1082 if (i == periods - 1 && pos_adj)
1083 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1084 period_bytes - pos_adj, 0);
1085 else
1086 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1087 period_bytes, 1);
1088 if (ofs < 0)
1089 goto error;
1090 }
1091 return 0;
1092
1093 error:
1094 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1095 azx_dev->bufsize, period_bytes);
1096 /* reset */
1097 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1098 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1099 return -EINVAL;
1100 }
1101
1102 /*
1103 * set up the SD for streaming
1104 */
1105 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1106 {
1107 unsigned char val;
1108 int timeout;
1109
1110 /* make sure the run bit is zero for SD */
1111 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1112 ~SD_CTL_DMA_START);
1113 /* reset stream */
1114 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1115 SD_CTL_STREAM_RESET);
1116 udelay(3);
1117 timeout = 300;
1118 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1119 --timeout)
1120 ;
1121 val &= ~SD_CTL_STREAM_RESET;
1122 azx_sd_writeb(azx_dev, SD_CTL, val);
1123 udelay(3);
1124
1125 timeout = 300;
1126 /* waiting for hardware to report that the stream is out of reset */
1127 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1128 --timeout)
1129 ;
1130
1131 /* program the stream_tag */
1132 azx_sd_writel(azx_dev, SD_CTL,
1133 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1134 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1135
1136 /* program the length of samples in cyclic buffer */
1137 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1138
1139 /* program the stream format */
1140 /* this value needs to be the same as the one programmed */
1141 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1142
1143 /* program the stream LVI (last valid index) of the BDL */
1144 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1145
1146 /* program the BDL address */
1147 /* lower BDL address */
1148 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1149 /* upper BDL address */
1150 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1151
1152 /* enable the position buffer */
1153 if (chip->position_fix == POS_FIX_POSBUF ||
1154 chip->position_fix == POS_FIX_AUTO) {
1155 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1156 azx_writel(chip, DPLBASE,
1157 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1158 }
1159
1160 /* set the interrupt enable bits in the descriptor control register */
1161 azx_sd_writel(azx_dev, SD_CTL,
1162 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1163
1164 return 0;
1165 }
1166
1167
1168 /*
1169 * Codec initialization
1170 */
1171
1172 static unsigned int azx_max_codecs[] __devinitdata = {
1173 [AZX_DRIVER_ICH] = 4, /* Some ICH9 boards use SD3 */
1174 [AZX_DRIVER_SCH] = 3,
1175 [AZX_DRIVER_ATI] = 4,
1176 [AZX_DRIVER_ATIHDMI] = 4,
1177 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1178 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1179 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1180 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1181 [AZX_DRIVER_TERA] = 1,
1182 };
1183
1184 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1185 unsigned int codec_probe_mask)
1186 {
1187 struct hda_bus_template bus_temp;
1188 int c, codecs, audio_codecs, err;
1189
1190 memset(&bus_temp, 0, sizeof(bus_temp));
1191 bus_temp.private_data = chip;
1192 bus_temp.modelname = model;
1193 bus_temp.pci = chip->pci;
1194 bus_temp.ops.command = azx_send_cmd;
1195 bus_temp.ops.get_response = azx_get_response;
1196 #ifdef CONFIG_SND_HDA_POWER_SAVE
1197 bus_temp.ops.pm_notify = azx_power_notify;
1198 #endif
1199
1200 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1201 if (err < 0)
1202 return err;
1203
1204 codecs = audio_codecs = 0;
1205 for (c = 0; c < AZX_MAX_CODECS; c++) {
1206 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1207 struct hda_codec *codec;
1208 err = snd_hda_codec_new(chip->bus, c, &codec);
1209 if (err < 0)
1210 continue;
1211 codecs++;
1212 if (codec->afg)
1213 audio_codecs++;
1214 }
1215 }
1216 if (!audio_codecs) {
1217 /* probe additional slots if no codec is found */
1218 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1219 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1220 err = snd_hda_codec_new(chip->bus, c, NULL);
1221 if (err < 0)
1222 continue;
1223 codecs++;
1224 }
1225 }
1226 }
1227 if (!codecs) {
1228 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1229 return -ENXIO;
1230 }
1231
1232 return 0;
1233 }
1234
1235
1236 /*
1237 * PCM support
1238 */
1239
1240 /* assign a stream for the PCM */
1241 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1242 {
1243 int dev, i, nums;
1244 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1245 dev = chip->playback_index_offset;
1246 nums = chip->playback_streams;
1247 } else {
1248 dev = chip->capture_index_offset;
1249 nums = chip->capture_streams;
1250 }
1251 for (i = 0; i < nums; i++, dev++)
1252 if (!chip->azx_dev[dev].opened) {
1253 chip->azx_dev[dev].opened = 1;
1254 return &chip->azx_dev[dev];
1255 }
1256 return NULL;
1257 }
1258
1259 /* release the assigned stream */
1260 static inline void azx_release_device(struct azx_dev *azx_dev)
1261 {
1262 azx_dev->opened = 0;
1263 }
1264
1265 static struct snd_pcm_hardware azx_pcm_hw = {
1266 .info = (SNDRV_PCM_INFO_MMAP |
1267 SNDRV_PCM_INFO_INTERLEAVED |
1268 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1269 SNDRV_PCM_INFO_MMAP_VALID |
1270 /* No full-resume yet implemented */
1271 /* SNDRV_PCM_INFO_RESUME |*/
1272 SNDRV_PCM_INFO_PAUSE |
1273 SNDRV_PCM_INFO_SYNC_START),
1274 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1275 .rates = SNDRV_PCM_RATE_48000,
1276 .rate_min = 48000,
1277 .rate_max = 48000,
1278 .channels_min = 2,
1279 .channels_max = 2,
1280 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1281 .period_bytes_min = 128,
1282 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1283 .periods_min = 2,
1284 .periods_max = AZX_MAX_FRAG,
1285 .fifo_size = 0,
1286 };
1287
1288 struct azx_pcm {
1289 struct azx *chip;
1290 struct hda_codec *codec;
1291 struct hda_pcm_stream *hinfo[2];
1292 };
1293
1294 static int azx_pcm_open(struct snd_pcm_substream *substream)
1295 {
1296 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1297 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1298 struct azx *chip = apcm->chip;
1299 struct azx_dev *azx_dev;
1300 struct snd_pcm_runtime *runtime = substream->runtime;
1301 unsigned long flags;
1302 int err;
1303
1304 mutex_lock(&chip->open_mutex);
1305 azx_dev = azx_assign_device(chip, substream->stream);
1306 if (azx_dev == NULL) {
1307 mutex_unlock(&chip->open_mutex);
1308 return -EBUSY;
1309 }
1310 runtime->hw = azx_pcm_hw;
1311 runtime->hw.channels_min = hinfo->channels_min;
1312 runtime->hw.channels_max = hinfo->channels_max;
1313 runtime->hw.formats = hinfo->formats;
1314 runtime->hw.rates = hinfo->rates;
1315 snd_pcm_limit_hw_rates(runtime);
1316 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1317 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1318 128);
1319 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1320 128);
1321 snd_hda_power_up(apcm->codec);
1322 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1323 if (err < 0) {
1324 azx_release_device(azx_dev);
1325 snd_hda_power_down(apcm->codec);
1326 mutex_unlock(&chip->open_mutex);
1327 return err;
1328 }
1329 spin_lock_irqsave(&chip->reg_lock, flags);
1330 azx_dev->substream = substream;
1331 azx_dev->running = 0;
1332 spin_unlock_irqrestore(&chip->reg_lock, flags);
1333
1334 runtime->private_data = azx_dev;
1335 snd_pcm_set_sync(substream);
1336 mutex_unlock(&chip->open_mutex);
1337 return 0;
1338 }
1339
1340 static int azx_pcm_close(struct snd_pcm_substream *substream)
1341 {
1342 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1343 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1344 struct azx *chip = apcm->chip;
1345 struct azx_dev *azx_dev = get_azx_dev(substream);
1346 unsigned long flags;
1347
1348 mutex_lock(&chip->open_mutex);
1349 spin_lock_irqsave(&chip->reg_lock, flags);
1350 azx_dev->substream = NULL;
1351 azx_dev->running = 0;
1352 spin_unlock_irqrestore(&chip->reg_lock, flags);
1353 azx_release_device(azx_dev);
1354 hinfo->ops.close(hinfo, apcm->codec, substream);
1355 snd_hda_power_down(apcm->codec);
1356 mutex_unlock(&chip->open_mutex);
1357 return 0;
1358 }
1359
1360 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1361 struct snd_pcm_hw_params *hw_params)
1362 {
1363 return snd_pcm_lib_malloc_pages(substream,
1364 params_buffer_bytes(hw_params));
1365 }
1366
1367 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1368 {
1369 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1370 struct azx_dev *azx_dev = get_azx_dev(substream);
1371 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1372
1373 /* reset BDL address */
1374 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1375 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1376 azx_sd_writel(azx_dev, SD_CTL, 0);
1377
1378 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1379
1380 return snd_pcm_lib_free_pages(substream);
1381 }
1382
1383 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1384 {
1385 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1386 struct azx *chip = apcm->chip;
1387 struct azx_dev *azx_dev = get_azx_dev(substream);
1388 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1389 struct snd_pcm_runtime *runtime = substream->runtime;
1390
1391 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1392 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1393 runtime->channels,
1394 runtime->format,
1395 hinfo->maxbps);
1396 if (!azx_dev->format_val) {
1397 snd_printk(KERN_ERR SFX
1398 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1399 runtime->rate, runtime->channels, runtime->format);
1400 return -EINVAL;
1401 }
1402
1403 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1404 azx_dev->bufsize, azx_dev->format_val);
1405 if (azx_setup_periods(chip, substream, azx_dev) < 0)
1406 return -EINVAL;
1407 azx_setup_controller(chip, azx_dev);
1408 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1409 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1410 else
1411 azx_dev->fifo_size = 0;
1412
1413 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1414 azx_dev->format_val, substream);
1415 }
1416
1417 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1418 {
1419 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1420 struct azx *chip = apcm->chip;
1421 struct azx_dev *azx_dev;
1422 struct snd_pcm_substream *s;
1423 int start, nsync = 0, sbits = 0;
1424 int nwait, timeout;
1425
1426 switch (cmd) {
1427 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1428 case SNDRV_PCM_TRIGGER_RESUME:
1429 case SNDRV_PCM_TRIGGER_START:
1430 start = 1;
1431 break;
1432 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1433 case SNDRV_PCM_TRIGGER_SUSPEND:
1434 case SNDRV_PCM_TRIGGER_STOP:
1435 start = 0;
1436 break;
1437 default:
1438 return -EINVAL;
1439 }
1440
1441 snd_pcm_group_for_each_entry(s, substream) {
1442 if (s->pcm->card != substream->pcm->card)
1443 continue;
1444 azx_dev = get_azx_dev(s);
1445 sbits |= 1 << azx_dev->index;
1446 nsync++;
1447 snd_pcm_trigger_done(s, substream);
1448 }
1449
1450 spin_lock(&chip->reg_lock);
1451 if (nsync > 1) {
1452 /* first, set SYNC bits of corresponding streams */
1453 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1454 }
1455 snd_pcm_group_for_each_entry(s, substream) {
1456 if (s->pcm->card != substream->pcm->card)
1457 continue;
1458 azx_dev = get_azx_dev(s);
1459 if (start)
1460 azx_stream_start(chip, azx_dev);
1461 else
1462 azx_stream_stop(chip, azx_dev);
1463 azx_dev->running = start;
1464 }
1465 spin_unlock(&chip->reg_lock);
1466 if (start) {
1467 if (nsync == 1)
1468 return 0;
1469 /* wait until all FIFOs get ready */
1470 for (timeout = 5000; timeout; timeout--) {
1471 nwait = 0;
1472 snd_pcm_group_for_each_entry(s, substream) {
1473 if (s->pcm->card != substream->pcm->card)
1474 continue;
1475 azx_dev = get_azx_dev(s);
1476 if (!(azx_sd_readb(azx_dev, SD_STS) &
1477 SD_STS_FIFO_READY))
1478 nwait++;
1479 }
1480 if (!nwait)
1481 break;
1482 cpu_relax();
1483 }
1484 } else {
1485 /* wait until all RUN bits are cleared */
1486 for (timeout = 5000; timeout; timeout--) {
1487 nwait = 0;
1488 snd_pcm_group_for_each_entry(s, substream) {
1489 if (s->pcm->card != substream->pcm->card)
1490 continue;
1491 azx_dev = get_azx_dev(s);
1492 if (azx_sd_readb(azx_dev, SD_CTL) &
1493 SD_CTL_DMA_START)
1494 nwait++;
1495 }
1496 if (!nwait)
1497 break;
1498 cpu_relax();
1499 }
1500 }
1501 if (nsync > 1) {
1502 spin_lock(&chip->reg_lock);
1503 /* reset SYNC bits */
1504 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1505 spin_unlock(&chip->reg_lock);
1506 }
1507 return 0;
1508 }
1509
1510 static unsigned int azx_get_position(struct azx *chip,
1511 struct azx_dev *azx_dev)
1512 {
1513 unsigned int pos;
1514
1515 if (chip->position_fix == POS_FIX_POSBUF ||
1516 chip->position_fix == POS_FIX_AUTO) {
1517 /* use the position buffer */
1518 pos = le32_to_cpu(*azx_dev->posbuf);
1519 } else {
1520 /* read LPIB */
1521 pos = azx_sd_readl(azx_dev, SD_LPIB);
1522 }
1523 if (pos >= azx_dev->bufsize)
1524 pos = 0;
1525 return pos;
1526 }
1527
1528 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1529 {
1530 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1531 struct azx *chip = apcm->chip;
1532 struct azx_dev *azx_dev = get_azx_dev(substream);
1533 return bytes_to_frames(substream->runtime,
1534 azx_get_position(chip, azx_dev));
1535 }
1536
1537 /*
1538 * Check whether the current DMA position is acceptable for updating
1539 * periods. Returns non-zero if it's OK.
1540 *
1541 * Many HD-audio controllers appear pretty inaccurate about
1542 * the update-IRQ timing. The IRQ is issued before actually the
1543 * data is processed. So, we need to process it afterwords in a
1544 * workqueue.
1545 */
1546 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1547 {
1548 unsigned int pos;
1549
1550 pos = azx_get_position(chip, azx_dev);
1551 if (chip->position_fix == POS_FIX_AUTO) {
1552 if (!pos) {
1553 printk(KERN_WARNING
1554 "hda-intel: Invalid position buffer, "
1555 "using LPIB read method instead.\n");
1556 chip->position_fix = POS_FIX_LPIB;
1557 pos = azx_get_position(chip, azx_dev);
1558 } else
1559 chip->position_fix = POS_FIX_POSBUF;
1560 }
1561
1562 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1563 return 0; /* NG - it's below the period boundary */
1564 return 1; /* OK, it's fine */
1565 }
1566
1567 /*
1568 * The work for pending PCM period updates.
1569 */
1570 static void azx_irq_pending_work(struct work_struct *work)
1571 {
1572 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1573 int i, pending;
1574
1575 if (!chip->irq_pending_warned) {
1576 printk(KERN_WARNING
1577 "hda-intel: IRQ timing workaround is activated "
1578 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1579 chip->card->number);
1580 chip->irq_pending_warned = 1;
1581 }
1582
1583 for (;;) {
1584 pending = 0;
1585 spin_lock_irq(&chip->reg_lock);
1586 for (i = 0; i < chip->num_streams; i++) {
1587 struct azx_dev *azx_dev = &chip->azx_dev[i];
1588 if (!azx_dev->irq_pending ||
1589 !azx_dev->substream ||
1590 !azx_dev->running)
1591 continue;
1592 if (azx_position_ok(chip, azx_dev)) {
1593 azx_dev->irq_pending = 0;
1594 spin_unlock(&chip->reg_lock);
1595 snd_pcm_period_elapsed(azx_dev->substream);
1596 spin_lock(&chip->reg_lock);
1597 } else
1598 pending++;
1599 }
1600 spin_unlock_irq(&chip->reg_lock);
1601 if (!pending)
1602 return;
1603 cond_resched();
1604 }
1605 }
1606
1607 /* clear irq_pending flags and assure no on-going workq */
1608 static void azx_clear_irq_pending(struct azx *chip)
1609 {
1610 int i;
1611
1612 spin_lock_irq(&chip->reg_lock);
1613 for (i = 0; i < chip->num_streams; i++)
1614 chip->azx_dev[i].irq_pending = 0;
1615 spin_unlock_irq(&chip->reg_lock);
1616 flush_scheduled_work();
1617 }
1618
1619 static struct snd_pcm_ops azx_pcm_ops = {
1620 .open = azx_pcm_open,
1621 .close = azx_pcm_close,
1622 .ioctl = snd_pcm_lib_ioctl,
1623 .hw_params = azx_pcm_hw_params,
1624 .hw_free = azx_pcm_hw_free,
1625 .prepare = azx_pcm_prepare,
1626 .trigger = azx_pcm_trigger,
1627 .pointer = azx_pcm_pointer,
1628 .page = snd_pcm_sgbuf_ops_page,
1629 };
1630
1631 static void azx_pcm_free(struct snd_pcm *pcm)
1632 {
1633 kfree(pcm->private_data);
1634 }
1635
1636 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1637 struct hda_pcm *cpcm)
1638 {
1639 int err;
1640 struct snd_pcm *pcm;
1641 struct azx_pcm *apcm;
1642
1643 /* if no substreams are defined for both playback and capture,
1644 * it's just a placeholder. ignore it.
1645 */
1646 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1647 return 0;
1648
1649 snd_assert(cpcm->name, return -EINVAL);
1650
1651 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1652 cpcm->stream[0].substreams,
1653 cpcm->stream[1].substreams,
1654 &pcm);
1655 if (err < 0)
1656 return err;
1657 strcpy(pcm->name, cpcm->name);
1658 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1659 if (apcm == NULL)
1660 return -ENOMEM;
1661 apcm->chip = chip;
1662 apcm->codec = codec;
1663 apcm->hinfo[0] = &cpcm->stream[0];
1664 apcm->hinfo[1] = &cpcm->stream[1];
1665 pcm->private_data = apcm;
1666 pcm->private_free = azx_pcm_free;
1667 if (cpcm->stream[0].substreams)
1668 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1669 if (cpcm->stream[1].substreams)
1670 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1671 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1672 snd_dma_pci_data(chip->pci),
1673 1024 * 64, 1024 * 1024);
1674 chip->pcm[cpcm->device] = pcm;
1675 return 0;
1676 }
1677
1678 static int __devinit azx_pcm_create(struct azx *chip)
1679 {
1680 static const char *dev_name[HDA_PCM_NTYPES] = {
1681 "Audio", "SPDIF", "HDMI", "Modem"
1682 };
1683 /* starting device index for each PCM type */
1684 static int dev_idx[HDA_PCM_NTYPES] = {
1685 [HDA_PCM_TYPE_AUDIO] = 0,
1686 [HDA_PCM_TYPE_SPDIF] = 1,
1687 [HDA_PCM_TYPE_HDMI] = 3,
1688 [HDA_PCM_TYPE_MODEM] = 6
1689 };
1690 /* normal audio device indices; not linear to keep compatibility */
1691 static int audio_idx[4] = { 0, 2, 4, 5 };
1692 struct hda_codec *codec;
1693 int c, err;
1694 int num_devs[HDA_PCM_NTYPES];
1695
1696 err = snd_hda_build_pcms(chip->bus);
1697 if (err < 0)
1698 return err;
1699
1700 /* create audio PCMs */
1701 memset(num_devs, 0, sizeof(num_devs));
1702 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1703 for (c = 0; c < codec->num_pcms; c++) {
1704 struct hda_pcm *cpcm = &codec->pcm_info[c];
1705 int type = cpcm->pcm_type;
1706 switch (type) {
1707 case HDA_PCM_TYPE_AUDIO:
1708 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1709 snd_printk(KERN_WARNING
1710 "Too many audio devices\n");
1711 continue;
1712 }
1713 cpcm->device = audio_idx[num_devs[type]];
1714 break;
1715 case HDA_PCM_TYPE_SPDIF:
1716 case HDA_PCM_TYPE_HDMI:
1717 case HDA_PCM_TYPE_MODEM:
1718 if (num_devs[type]) {
1719 snd_printk(KERN_WARNING
1720 "%s already defined\n",
1721 dev_name[type]);
1722 continue;
1723 }
1724 cpcm->device = dev_idx[type];
1725 break;
1726 default:
1727 snd_printk(KERN_WARNING
1728 "Invalid PCM type %d\n", type);
1729 continue;
1730 }
1731 num_devs[type]++;
1732 err = create_codec_pcm(chip, codec, cpcm);
1733 if (err < 0)
1734 return err;
1735 }
1736 }
1737 return 0;
1738 }
1739
1740 /*
1741 * mixer creation - all stuff is implemented in hda module
1742 */
1743 static int __devinit azx_mixer_create(struct azx *chip)
1744 {
1745 return snd_hda_build_controls(chip->bus);
1746 }
1747
1748
1749 /*
1750 * initialize SD streams
1751 */
1752 static int __devinit azx_init_stream(struct azx *chip)
1753 {
1754 int i;
1755
1756 /* initialize each stream (aka device)
1757 * assign the starting bdl address to each stream (device)
1758 * and initialize
1759 */
1760 for (i = 0; i < chip->num_streams; i++) {
1761 struct azx_dev *azx_dev = &chip->azx_dev[i];
1762 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1763 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1764 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1765 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1766 azx_dev->sd_int_sta_mask = 1 << i;
1767 /* stream tag: must be non-zero and unique */
1768 azx_dev->index = i;
1769 azx_dev->stream_tag = i + 1;
1770 }
1771
1772 return 0;
1773 }
1774
1775 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1776 {
1777 if (request_irq(chip->pci->irq, azx_interrupt,
1778 chip->msi ? 0 : IRQF_SHARED,
1779 "HDA Intel", chip)) {
1780 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1781 "disabling device\n", chip->pci->irq);
1782 if (do_disconnect)
1783 snd_card_disconnect(chip->card);
1784 return -1;
1785 }
1786 chip->irq = chip->pci->irq;
1787 pci_intx(chip->pci, !chip->msi);
1788 return 0;
1789 }
1790
1791
1792 static void azx_stop_chip(struct azx *chip)
1793 {
1794 if (!chip->initialized)
1795 return;
1796
1797 /* disable interrupts */
1798 azx_int_disable(chip);
1799 azx_int_clear(chip);
1800
1801 /* disable CORB/RIRB */
1802 azx_free_cmd_io(chip);
1803
1804 /* disable position buffer */
1805 azx_writel(chip, DPLBASE, 0);
1806 azx_writel(chip, DPUBASE, 0);
1807
1808 chip->initialized = 0;
1809 }
1810
1811 #ifdef CONFIG_SND_HDA_POWER_SAVE
1812 /* power-up/down the controller */
1813 static void azx_power_notify(struct hda_codec *codec)
1814 {
1815 struct azx *chip = codec->bus->private_data;
1816 struct hda_codec *c;
1817 int power_on = 0;
1818
1819 list_for_each_entry(c, &codec->bus->codec_list, list) {
1820 if (c->power_on) {
1821 power_on = 1;
1822 break;
1823 }
1824 }
1825 if (power_on)
1826 azx_init_chip(chip);
1827 else if (chip->running && power_save_controller)
1828 azx_stop_chip(chip);
1829 }
1830 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1831
1832 #ifdef CONFIG_PM
1833 /*
1834 * power management
1835 */
1836 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1837 {
1838 struct snd_card *card = pci_get_drvdata(pci);
1839 struct azx *chip = card->private_data;
1840 int i;
1841
1842 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1843 azx_clear_irq_pending(chip);
1844 for (i = 0; i < AZX_MAX_PCMS; i++)
1845 snd_pcm_suspend_all(chip->pcm[i]);
1846 if (chip->initialized)
1847 snd_hda_suspend(chip->bus, state);
1848 azx_stop_chip(chip);
1849 if (chip->irq >= 0) {
1850 free_irq(chip->irq, chip);
1851 chip->irq = -1;
1852 }
1853 if (chip->msi)
1854 pci_disable_msi(chip->pci);
1855 pci_disable_device(pci);
1856 pci_save_state(pci);
1857 pci_set_power_state(pci, pci_choose_state(pci, state));
1858 return 0;
1859 }
1860
1861 static int azx_resume(struct pci_dev *pci)
1862 {
1863 struct snd_card *card = pci_get_drvdata(pci);
1864 struct azx *chip = card->private_data;
1865
1866 pci_set_power_state(pci, PCI_D0);
1867 pci_restore_state(pci);
1868 if (pci_enable_device(pci) < 0) {
1869 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1870 "disabling device\n");
1871 snd_card_disconnect(card);
1872 return -EIO;
1873 }
1874 pci_set_master(pci);
1875 if (chip->msi)
1876 if (pci_enable_msi(pci) < 0)
1877 chip->msi = 0;
1878 if (azx_acquire_irq(chip, 1) < 0)
1879 return -EIO;
1880 azx_init_pci(chip);
1881
1882 if (snd_hda_codecs_inuse(chip->bus))
1883 azx_init_chip(chip);
1884
1885 snd_hda_resume(chip->bus);
1886 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1887 return 0;
1888 }
1889 #endif /* CONFIG_PM */
1890
1891
1892 /*
1893 * destructor
1894 */
1895 static int azx_free(struct azx *chip)
1896 {
1897 int i;
1898
1899 if (chip->initialized) {
1900 azx_clear_irq_pending(chip);
1901 for (i = 0; i < chip->num_streams; i++)
1902 azx_stream_stop(chip, &chip->azx_dev[i]);
1903 azx_stop_chip(chip);
1904 }
1905
1906 if (chip->irq >= 0)
1907 free_irq(chip->irq, (void*)chip);
1908 if (chip->msi)
1909 pci_disable_msi(chip->pci);
1910 if (chip->remap_addr)
1911 iounmap(chip->remap_addr);
1912
1913 if (chip->azx_dev) {
1914 for (i = 0; i < chip->num_streams; i++)
1915 if (chip->azx_dev[i].bdl.area)
1916 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1917 }
1918 if (chip->rb.area)
1919 snd_dma_free_pages(&chip->rb);
1920 if (chip->posbuf.area)
1921 snd_dma_free_pages(&chip->posbuf);
1922 pci_release_regions(chip->pci);
1923 pci_disable_device(chip->pci);
1924 kfree(chip->azx_dev);
1925 kfree(chip);
1926
1927 return 0;
1928 }
1929
1930 static int azx_dev_free(struct snd_device *device)
1931 {
1932 return azx_free(device->device_data);
1933 }
1934
1935 /*
1936 * white/black-listing for position_fix
1937 */
1938 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1939 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1940 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1941 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1942 {}
1943 };
1944
1945 static int __devinit check_position_fix(struct azx *chip, int fix)
1946 {
1947 const struct snd_pci_quirk *q;
1948
1949 if (fix == POS_FIX_AUTO) {
1950 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1951 if (q) {
1952 printk(KERN_INFO
1953 "hda_intel: position_fix set to %d "
1954 "for device %04x:%04x\n",
1955 q->value, q->subvendor, q->subdevice);
1956 return q->value;
1957 }
1958 }
1959 return fix;
1960 }
1961
1962 /*
1963 * black-lists for probe_mask
1964 */
1965 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1966 /* Thinkpad often breaks the controller communication when accessing
1967 * to the non-working (or non-existing) modem codec slot.
1968 */
1969 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1970 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1971 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1972 {}
1973 };
1974
1975 static void __devinit check_probe_mask(struct azx *chip, int dev)
1976 {
1977 const struct snd_pci_quirk *q;
1978
1979 if (probe_mask[dev] == -1) {
1980 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1981 if (q) {
1982 printk(KERN_INFO
1983 "hda_intel: probe_mask set to 0x%x "
1984 "for device %04x:%04x\n",
1985 q->value, q->subvendor, q->subdevice);
1986 probe_mask[dev] = q->value;
1987 }
1988 }
1989 }
1990
1991
1992 /*
1993 * constructor
1994 */
1995 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1996 int dev, int driver_type,
1997 struct azx **rchip)
1998 {
1999 struct azx *chip;
2000 int i, err;
2001 unsigned short gcap;
2002 static struct snd_device_ops ops = {
2003 .dev_free = azx_dev_free,
2004 };
2005
2006 *rchip = NULL;
2007
2008 err = pci_enable_device(pci);
2009 if (err < 0)
2010 return err;
2011
2012 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2013 if (!chip) {
2014 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2015 pci_disable_device(pci);
2016 return -ENOMEM;
2017 }
2018
2019 spin_lock_init(&chip->reg_lock);
2020 mutex_init(&chip->open_mutex);
2021 chip->card = card;
2022 chip->pci = pci;
2023 chip->irq = -1;
2024 chip->driver_type = driver_type;
2025 chip->msi = enable_msi;
2026 chip->dev_index = dev;
2027 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2028
2029 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2030 check_probe_mask(chip, dev);
2031
2032 chip->single_cmd = single_cmd;
2033
2034 if (bdl_pos_adj[dev] < 0) {
2035 switch (chip->driver_type) {
2036 case AZX_DRIVER_ICH:
2037 bdl_pos_adj[dev] = 1;
2038 break;
2039 default:
2040 bdl_pos_adj[dev] = 32;
2041 break;
2042 }
2043 }
2044
2045 #if BITS_PER_LONG != 64
2046 /* Fix up base address on ULI M5461 */
2047 if (chip->driver_type == AZX_DRIVER_ULI) {
2048 u16 tmp3;
2049 pci_read_config_word(pci, 0x40, &tmp3);
2050 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2051 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2052 }
2053 #endif
2054
2055 err = pci_request_regions(pci, "ICH HD audio");
2056 if (err < 0) {
2057 kfree(chip);
2058 pci_disable_device(pci);
2059 return err;
2060 }
2061
2062 chip->addr = pci_resource_start(pci, 0);
2063 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2064 if (chip->remap_addr == NULL) {
2065 snd_printk(KERN_ERR SFX "ioremap error\n");
2066 err = -ENXIO;
2067 goto errout;
2068 }
2069
2070 if (chip->msi)
2071 if (pci_enable_msi(pci) < 0)
2072 chip->msi = 0;
2073
2074 if (azx_acquire_irq(chip, 0) < 0) {
2075 err = -EBUSY;
2076 goto errout;
2077 }
2078
2079 pci_set_master(pci);
2080 synchronize_irq(chip->irq);
2081
2082 gcap = azx_readw(chip, GCAP);
2083 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2084
2085 /* allow 64bit DMA address if supported by H/W */
2086 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2087 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2088
2089 /* read number of streams from GCAP register instead of using
2090 * hardcoded value
2091 */
2092 chip->capture_streams = (gcap >> 8) & 0x0f;
2093 chip->playback_streams = (gcap >> 12) & 0x0f;
2094 if (!chip->playback_streams && !chip->capture_streams) {
2095 /* gcap didn't give any info, switching to old method */
2096
2097 switch (chip->driver_type) {
2098 case AZX_DRIVER_ULI:
2099 chip->playback_streams = ULI_NUM_PLAYBACK;
2100 chip->capture_streams = ULI_NUM_CAPTURE;
2101 break;
2102 case AZX_DRIVER_ATIHDMI:
2103 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2104 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2105 break;
2106 default:
2107 chip->playback_streams = ICH6_NUM_PLAYBACK;
2108 chip->capture_streams = ICH6_NUM_CAPTURE;
2109 break;
2110 }
2111 }
2112 chip->capture_index_offset = 0;
2113 chip->playback_index_offset = chip->capture_streams;
2114 chip->num_streams = chip->playback_streams + chip->capture_streams;
2115 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2116 GFP_KERNEL);
2117 if (!chip->azx_dev) {
2118 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2119 goto errout;
2120 }
2121
2122 for (i = 0; i < chip->num_streams; i++) {
2123 /* allocate memory for the BDL for each stream */
2124 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2125 snd_dma_pci_data(chip->pci),
2126 BDL_SIZE, &chip->azx_dev[i].bdl);
2127 if (err < 0) {
2128 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2129 goto errout;
2130 }
2131 }
2132 /* allocate memory for the position buffer */
2133 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2134 snd_dma_pci_data(chip->pci),
2135 chip->num_streams * 8, &chip->posbuf);
2136 if (err < 0) {
2137 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2138 goto errout;
2139 }
2140 /* allocate CORB/RIRB */
2141 if (!chip->single_cmd) {
2142 err = azx_alloc_cmd_io(chip);
2143 if (err < 0)
2144 goto errout;
2145 }
2146
2147 /* initialize streams */
2148 azx_init_stream(chip);
2149
2150 /* initialize chip */
2151 azx_init_pci(chip);
2152 azx_init_chip(chip);
2153
2154 /* codec detection */
2155 if (!chip->codec_mask) {
2156 snd_printk(KERN_ERR SFX "no codecs found!\n");
2157 err = -ENODEV;
2158 goto errout;
2159 }
2160
2161 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2162 if (err <0) {
2163 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2164 goto errout;
2165 }
2166
2167 strcpy(card->driver, "HDA-Intel");
2168 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2169 sprintf(card->longname, "%s at 0x%lx irq %i",
2170 card->shortname, chip->addr, chip->irq);
2171
2172 *rchip = chip;
2173 return 0;
2174
2175 errout:
2176 azx_free(chip);
2177 return err;
2178 }
2179
2180 static void power_down_all_codecs(struct azx *chip)
2181 {
2182 #ifdef CONFIG_SND_HDA_POWER_SAVE
2183 /* The codecs were powered up in snd_hda_codec_new().
2184 * Now all initialization done, so turn them down if possible
2185 */
2186 struct hda_codec *codec;
2187 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2188 snd_hda_power_down(codec);
2189 }
2190 #endif
2191 }
2192
2193 static int __devinit azx_probe(struct pci_dev *pci,
2194 const struct pci_device_id *pci_id)
2195 {
2196 static int dev;
2197 struct snd_card *card;
2198 struct azx *chip;
2199 int err;
2200
2201 if (dev >= SNDRV_CARDS)
2202 return -ENODEV;
2203 if (!enable[dev]) {
2204 dev++;
2205 return -ENOENT;
2206 }
2207
2208 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2209 if (!card) {
2210 snd_printk(KERN_ERR SFX "Error creating card!\n");
2211 return -ENOMEM;
2212 }
2213
2214 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2215 if (err < 0) {
2216 snd_card_free(card);
2217 return err;
2218 }
2219 card->private_data = chip;
2220
2221 /* create codec instances */
2222 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2223 if (err < 0) {
2224 snd_card_free(card);
2225 return err;
2226 }
2227
2228 /* create PCM streams */
2229 err = azx_pcm_create(chip);
2230 if (err < 0) {
2231 snd_card_free(card);
2232 return err;
2233 }
2234
2235 /* create mixer controls */
2236 err = azx_mixer_create(chip);
2237 if (err < 0) {
2238 snd_card_free(card);
2239 return err;
2240 }
2241
2242 snd_card_set_dev(card, &pci->dev);
2243
2244 err = snd_card_register(card);
2245 if (err < 0) {
2246 snd_card_free(card);
2247 return err;
2248 }
2249
2250 pci_set_drvdata(pci, card);
2251 chip->running = 1;
2252 power_down_all_codecs(chip);
2253
2254 dev++;
2255 return err;
2256 }
2257
2258 static void __devexit azx_remove(struct pci_dev *pci)
2259 {
2260 snd_card_free(pci_get_drvdata(pci));
2261 pci_set_drvdata(pci, NULL);
2262 }
2263
2264 /* PCI IDs */
2265 static struct pci_device_id azx_ids[] = {
2266 /* ICH 6..10 */
2267 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2268 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2269 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2270 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2271 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2272 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2273 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2274 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2275 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2276 /* PCH */
2277 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2278 /* SCH */
2279 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2280 /* ATI SB 450/600 */
2281 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2282 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2283 /* ATI HDMI */
2284 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2285 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2286 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2287 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2288 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2289 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2290 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2291 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2292 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2293 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2294 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2295 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2296 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2297 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2298 /* VIA VT8251/VT8237A */
2299 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2300 /* SIS966 */
2301 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2302 /* ULI M5461 */
2303 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2304 /* NVIDIA MCP */
2305 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2306 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2307 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2308 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2309 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2310 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2311 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2312 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2313 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2314 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2315 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2316 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2317 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2318 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2319 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2320 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2321 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2322 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2323 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2324 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2325 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2326 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2327 /* Teradici */
2328 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2329 { 0, }
2330 };
2331 MODULE_DEVICE_TABLE(pci, azx_ids);
2332
2333 /* pci_driver definition */
2334 static struct pci_driver driver = {
2335 .name = "HDA Intel",
2336 .id_table = azx_ids,
2337 .probe = azx_probe,
2338 .remove = __devexit_p(azx_remove),
2339 #ifdef CONFIG_PM
2340 .suspend = azx_suspend,
2341 .resume = azx_resume,
2342 #endif
2343 };
2344
2345 static int __init alsa_card_azx_init(void)
2346 {
2347 return pci_register_driver(&driver);
2348 }
2349
2350 static void __exit alsa_card_azx_exit(void)
2351 {
2352 pci_unregister_driver(&driver);
2353 }
2354
2355 module_init(alsa_card_azx_init)
2356 module_exit(alsa_card_azx_exit)
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