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Complete the renaming to TuxOnIce with function names, vars etc.
[linux-2.6/suspend2-head.git] / drivers / net / sky2.h
blobdce4d276d4435e685232c7073ae98d26b9e1f818
1 /*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4 #ifndef _SKY2_H
5 #define _SKY2_H
6
7 #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */
8
9 /* PCI config registers */
10 enum {
11 PCI_DEV_REG1 = 0x40,
12 PCI_DEV_REG2 = 0x44,
13 PCI_DEV_STATUS = 0x7c,
14 PCI_DEV_REG3 = 0x80,
15 PCI_DEV_REG4 = 0x84,
16 PCI_DEV_REG5 = 0x88,
17 PCI_CFG_REG_0 = 0x90,
18 PCI_CFG_REG_1 = 0x94,
19 };
20
21 enum {
22 PEX_DEV_CAP = 0xe4,
23 PEX_DEV_CTRL = 0xe8,
24 PEX_DEV_STA = 0xea,
25 PEX_LNK_STAT = 0xf2,
26 PEX_UNC_ERR_STAT= 0x104,
27 };
28
29 /* Yukon-2 */
30 enum pci_dev_reg_1 {
31 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
32 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
33 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
34 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
35 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
37 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
38 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
39 };
40
41 enum pci_dev_reg_2 {
42 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
43 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
44 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
45
46 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
47 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
48 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
49 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
50
51 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
52 };
53
54 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
55 enum pci_dev_reg_4 {
56 /* (Link Training & Status State Machine) */
57 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
58 /* (Active State Power Management) */
59 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
60 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
61 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
62 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
63
64 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
65 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
66 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
67 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
68 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
69 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
70 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
71 };
72
73 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
74 enum pci_dev_reg_5 {
75 /* Bit 31..27: for A3 & later */
76 P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
77 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
78 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
79 P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
80 /* Bit 26..16: Release Clock on Event */
81 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
82 P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */
83 P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */
84 P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */
85 P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */
86 P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */
87 P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */
88 P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */
89 P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */
90 P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
91 P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */
92
93 /* Bit 10.. 0: Mask for Gate Clock */
94 P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
95 P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */
96 P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */
97 P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */
98 P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */
99 P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */
100 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
101 P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */
102 P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */
103 P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
104 P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */
105
106 PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
107 P_REL_INT_FIFO_N_EMPTY |
108 P_REL_PCIE_EXIT_L1_ST |
109 P_REL_PCIE_RX_EX_IDLE |
110 P_GAT_GPHY_N_REC_PACKET |
111 P_GAT_INT_FIFO_EMPTY |
112 P_GAT_PCIE_ENTER_L1_ST |
113 P_GAT_PCIE_RX_EL_IDLE,
114 };
115
116 #/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
117 enum pci_cfg_reg1 {
118 P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
119 /* Bit 23..21: Release Clock on Event */
120 P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */
121 P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */
122 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
123 /* Bit 20..18: Gate Clock on Event */
124 P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */
125 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
126 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
127 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
128 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
129
130 P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */
131
132 P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
133 P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
134
135 PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
136 P_CF1_REL_LDR_NOT_FIN |
137 P_CF1_REL_VMAIN_AVLBL |
138 P_CF1_REL_PCIE_RESET |
139 P_CF1_GAT_LDR_NOT_FIN |
140 P_CF1_GAT_PCIE_RESET |
141 P_CF1_PRST_PHY_CLKREQ |
142 P_CF1_ENA_CFG_LDR_DONE |
143 P_CF1_ENA_TXBMU_RD_IDLE |
144 P_CF1_ENA_TXBMU_WR_IDLE,
145 };
146
147
148 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
149 PCI_STATUS_SIG_SYSTEM_ERROR | \
150 PCI_STATUS_REC_MASTER_ABORT | \
151 PCI_STATUS_REC_TARGET_ABORT | \
152 PCI_STATUS_PARITY)
153
154 enum pex_dev_ctrl {
155 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
156 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
157 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
158 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
159 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
160 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
161 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
162 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
163 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
164 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
165 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
166 };
167 #define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
168
169 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
170 enum pex_err {
171 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
172
173 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
174
175 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
176
177 PEX_COMP_TO = 1<<14, /* Completion Timeout */
178 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
179 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
180
181 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
182 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
183 };
184
185
186 enum csr_regs {
187 B0_RAP = 0x0000,
188 B0_CTST = 0x0004,
189 B0_Y2LED = 0x0005,
190 B0_POWER_CTRL = 0x0007,
191 B0_ISRC = 0x0008,
192 B0_IMSK = 0x000c,
193 B0_HWE_ISRC = 0x0010,
194 B0_HWE_IMSK = 0x0014,
195
196 /* Special ISR registers (Yukon-2 only) */
197 B0_Y2_SP_ISRC2 = 0x001c,
198 B0_Y2_SP_ISRC3 = 0x0020,
199 B0_Y2_SP_EISR = 0x0024,
200 B0_Y2_SP_LISR = 0x0028,
201 B0_Y2_SP_ICR = 0x002c,
202
203 B2_MAC_1 = 0x0100,
204 B2_MAC_2 = 0x0108,
205 B2_MAC_3 = 0x0110,
206 B2_CONN_TYP = 0x0118,
207 B2_PMD_TYP = 0x0119,
208 B2_MAC_CFG = 0x011a,
209 B2_CHIP_ID = 0x011b,
210 B2_E_0 = 0x011c,
211
212 B2_Y2_CLK_GATE = 0x011d,
213 B2_Y2_HW_RES = 0x011e,
214 B2_E_3 = 0x011f,
215 B2_Y2_CLK_CTRL = 0x0120,
216
217 B2_TI_INI = 0x0130,
218 B2_TI_VAL = 0x0134,
219 B2_TI_CTRL = 0x0138,
220 B2_TI_TEST = 0x0139,
221
222 B2_TST_CTRL1 = 0x0158,
223 B2_TST_CTRL2 = 0x0159,
224 B2_GP_IO = 0x015c,
225
226 B2_I2C_CTRL = 0x0160,
227 B2_I2C_DATA = 0x0164,
228 B2_I2C_IRQ = 0x0168,
229 B2_I2C_SW = 0x016c,
230
231 B3_RAM_ADDR = 0x0180,
232 B3_RAM_DATA_LO = 0x0184,
233 B3_RAM_DATA_HI = 0x0188,
234
235 /* RAM Interface Registers */
236 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
237 /*
238 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
239 * not usable in SW. Please notice these are NOT real timeouts, these are
240 * the number of qWords transferred continuously.
241 */
242 #define RAM_BUFFER(port, reg) (reg | (port <<6))
243
244 B3_RI_WTO_R1 = 0x0190,
245 B3_RI_WTO_XA1 = 0x0191,
246 B3_RI_WTO_XS1 = 0x0192,
247 B3_RI_RTO_R1 = 0x0193,
248 B3_RI_RTO_XA1 = 0x0194,
249 B3_RI_RTO_XS1 = 0x0195,
250 B3_RI_WTO_R2 = 0x0196,
251 B3_RI_WTO_XA2 = 0x0197,
252 B3_RI_WTO_XS2 = 0x0198,
253 B3_RI_RTO_R2 = 0x0199,
254 B3_RI_RTO_XA2 = 0x019a,
255 B3_RI_RTO_XS2 = 0x019b,
256 B3_RI_TO_VAL = 0x019c,
257 B3_RI_CTRL = 0x01a0,
258 B3_RI_TEST = 0x01a2,
259 B3_MA_TOINI_RX1 = 0x01b0,
260 B3_MA_TOINI_RX2 = 0x01b1,
261 B3_MA_TOINI_TX1 = 0x01b2,
262 B3_MA_TOINI_TX2 = 0x01b3,
263 B3_MA_TOVAL_RX1 = 0x01b4,
264 B3_MA_TOVAL_RX2 = 0x01b5,
265 B3_MA_TOVAL_TX1 = 0x01b6,
266 B3_MA_TOVAL_TX2 = 0x01b7,
267 B3_MA_TO_CTRL = 0x01b8,
268 B3_MA_TO_TEST = 0x01ba,
269 B3_MA_RCINI_RX1 = 0x01c0,
270 B3_MA_RCINI_RX2 = 0x01c1,
271 B3_MA_RCINI_TX1 = 0x01c2,
272 B3_MA_RCINI_TX2 = 0x01c3,
273 B3_MA_RCVAL_RX1 = 0x01c4,
274 B3_MA_RCVAL_RX2 = 0x01c5,
275 B3_MA_RCVAL_TX1 = 0x01c6,
276 B3_MA_RCVAL_TX2 = 0x01c7,
277 B3_MA_RC_CTRL = 0x01c8,
278 B3_MA_RC_TEST = 0x01ca,
279 B3_PA_TOINI_RX1 = 0x01d0,
280 B3_PA_TOINI_RX2 = 0x01d4,
281 B3_PA_TOINI_TX1 = 0x01d8,
282 B3_PA_TOINI_TX2 = 0x01dc,
283 B3_PA_TOVAL_RX1 = 0x01e0,
284 B3_PA_TOVAL_RX2 = 0x01e4,
285 B3_PA_TOVAL_TX1 = 0x01e8,
286 B3_PA_TOVAL_TX2 = 0x01ec,
287 B3_PA_CTRL = 0x01f0,
288 B3_PA_TEST = 0x01f2,
289
290 Y2_CFG_SPC = 0x1c00,
291 };
292
293 /* B0_CTST 16 bit Control/Status register */
294 enum {
295 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
296 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
297 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
298 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
299 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
300 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
301 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
302 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
303 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
304 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
305
306 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
307 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
308 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
309 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
310 CS_MRST_CLR = 1<<3, /* Clear Master reset */
311 CS_MRST_SET = 1<<2, /* Set Master reset */
312 CS_RST_CLR = 1<<1, /* Clear Software reset */
313 CS_RST_SET = 1, /* Set Software reset */
314 };
315
316 /* B0_LED 8 Bit LED register */
317 enum {
318 /* Bit 7.. 2: reserved */
319 LED_STAT_ON = 1<<1, /* Status LED on */
320 LED_STAT_OFF = 1, /* Status LED off */
321 };
322
323 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
324 enum {
325 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
326 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
327 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
328 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
329 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
330 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
331 PC_VCC_ON = 1<<1, /* Switch VCC On */
332 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
333 };
334
335 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
336
337 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
338 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
339 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
340 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
341 enum {
342 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
343 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
344 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
345
346 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
347 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
348 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
349 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
350
351 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
352 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
353 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
354 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
355 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
356
357 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
358 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
359 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
360 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
361 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
362
363 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
364 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
365 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
366 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
367 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
368 Y2_IS_ERROR = Y2_IS_HW_ERR |
369 Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
370 Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
371 };
372
373 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
374 enum {
375 IS_ERR_MSK = 0x00003fff,/* All Error bits */
376
377 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
378 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
379 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
380 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
381 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
382 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
383 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
384 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
385 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
386 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
387 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
388 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
389 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
390 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
391 };
392
393 /* Hardware error interrupt mask for Yukon 2 */
394 enum {
395 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
396 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
397 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
398 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
399 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
400 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
401 /* Link 2 */
402 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
403 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
404 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
405 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
406 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
407 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
408 /* Link 1 */
409 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
410 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
411 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
412 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
413 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
414 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
415
416 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
417 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
418 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
419 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
420
421 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
422 Y2_IS_PCI_EXP |
423 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
424 };
425
426 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
427 enum {
428 DPT_START = 1<<1,
429 DPT_STOP = 1<<0,
430 };
431
432 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
433 enum {
434 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
435 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
436 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
437 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
438 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
439 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
440 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
441 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
442 };
443
444 /* B2_GPIO */
445 enum {
446 GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
447 GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
448
449 GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
450 GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
451 GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
452 GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
453 GLB_GPIO_TEST_SEL_BASE = 1<<11,
454 GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
455 GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
456 };
457
458 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
459 enum {
460 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
461 /* Bit 3.. 2: reserved */
462 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
463 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
464 };
465
466 /* B2_CHIP_ID 8 bit Chip Identification Number */
467 enum {
468 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
469 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
470 CHIP_ID_YUKON_EX = 0xb5, /* Chip ID for YUKON-2 Extreme */
471 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
472 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
473
474 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
475 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
476 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
477
478 CHIP_REV_YU_EC_U_A0 = 1,
479 CHIP_REV_YU_EC_U_A1 = 2,
480 CHIP_REV_YU_EC_U_B0 = 3,
481
482 CHIP_REV_YU_FE_A1 = 1,
483 CHIP_REV_YU_FE_A2 = 2,
484
485 };
486 enum yukon_ex_rev {
487 CHIP_REV_YU_EX_A0 = 1,
488 CHIP_REV_YU_EX_B0 = 2,
489 };
490
491
492 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
493 enum {
494 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
495 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
496 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
497 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
498 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
499 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
500 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
501 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
502 };
503
504 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
505 enum {
506 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
507 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
508 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
509 };
510 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
511 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
512
513
514 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
515 enum {
516 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
517 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
518 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
519 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
520 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
521 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
522 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
523 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
524 };
525
526 /* B2_TI_CTRL 8 bit Timer control */
527 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
528 enum {
529 TIM_START = 1<<2, /* Start Timer */
530 TIM_STOP = 1<<1, /* Stop Timer */
531 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
532 };
533
534 /* B2_TI_TEST 8 Bit Timer Test */
535 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
536 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
537 enum {
538 TIM_T_ON = 1<<2, /* Test mode on */
539 TIM_T_OFF = 1<<1, /* Test mode off */
540 TIM_T_STEP = 1<<0, /* Test step */
541 };
542
543 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
544 /* Bit 31..19: reserved */
545 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
546 /* RAM Interface Registers */
547
548 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
549 enum {
550 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
551 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
552
553 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
554 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
555 };
556
557 #define SK_RI_TO_53 36 /* RAM interface timeout */
558
559
560 /* Port related registers FIFO, and Arbiter */
561 #define SK_REG(port,reg) (((port)<<7)+(reg))
562
563 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
564 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
565 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
566 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
567 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
568
569 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
570
571 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
572 enum {
573 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
574 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
575 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
576 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
577 TXA_START_RC = 1<<3, /* Start sync Rate Control */
578 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
579 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
580 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
581 };
582
583 /*
584 * Bank 4 - 5
585 */
586 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
587 enum {
588 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
589 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
590 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
591 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
592 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
593 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
594 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
595 };
596
597
598 enum {
599 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
600 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
601 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
602 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
603 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
604 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
605 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
606 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
607 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
608 };
609
610 /* Queue Register Offsets, use Q_ADDR() to access */
611 enum {
612 B8_Q_REGS = 0x0400, /* base of Queue registers */
613 Q_D = 0x00, /* 8*32 bit Current Descriptor */
614 Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
615 Q_DONE = 0x24, /* 16 bit Done Index */
616 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
617 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
618 Q_BC = 0x30, /* 32 bit Current Byte Counter */
619 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
620 Q_TEST = 0x38, /* 32 bit Test/Control Register */
621
622 /* Yukon-2 */
623 Q_WM = 0x40, /* 16 bit FIFO Watermark */
624 Q_AL = 0x42, /* 8 bit FIFO Alignment */
625 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
626 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
627 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
628 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
629 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
630 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
631 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
632 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
633 };
634 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
635
636 /* Q_TEST 32 bit Test Register */
637 enum {
638 /* Transmit */
639 F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
640 F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
641
642 /* Receive */
643 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
644
645 /* Hardware testbits not used */
646 };
647
648 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
649 enum {
650 Y2_B8_PREF_REGS = 0x0450,
651
652 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
653 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
654 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
655 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
656 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
657 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
658 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
659 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
660 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
661 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
662
663 PREF_UNIT_MASK_IDX = 0x0fff,
664 };
665 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
666
667 /* RAM Buffer Register Offsets */
668 enum {
669
670 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
671 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
672 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
673 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
674 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
675 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
676 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
677 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
678 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
679 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
680 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
681 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
682 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
683 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
684 };
685
686 /* Receive and Transmit Queues */
687 enum {
688 Q_R1 = 0x0000, /* Receive Queue 1 */
689 Q_R2 = 0x0080, /* Receive Queue 2 */
690 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
691 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
692 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
693 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
694 };
695
696 /* Different PHY Types */
697 enum {
698 PHY_ADDR_MARV = 0,
699 };
700
701 #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
702
703
704 enum {
705 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
706 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
707 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
708 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
709
710 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
711
712 /* Receive GMAC FIFO (YUKON and Yukon-2) */
713
714 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
715 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
716 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
717 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
718 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
719 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
720 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
721 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
722 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
723 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
724
725 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
726
727 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
728
729 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
730 };
731
732
733 /* Q_BC 32 bit Current Byte Counter */
734
735 /* BMU Control Status Registers */
736 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
737 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
738 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
739 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
740 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
741 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
742 /* Q_CSR 32 bit BMU Control/Status Register */
743
744 /* Rx BMU Control / Status Registers (Yukon-2) */
745 enum {
746 BMU_IDLE = 1<<31, /* BMU Idle State */
747 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
748 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
749
750 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
751 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
752 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
753 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
754 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
755 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
756 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
757 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
758 BMU_START = 1<<8, /* Start Rx/Tx Queue */
759 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
760 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
761 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
762 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
763 BMU_OP_ON = 1<<3, /* BMU Operational On */
764 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
765 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
766 BMU_RST_SET = 1<<0, /* Set BMU Reset */
767
768 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
769 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
770 BMU_FIFO_ENA | BMU_OP_ON,
771
772 BMU_WM_DEFAULT = 0x600,
773 BMU_WM_PEX = 0x80,
774 };
775
776 /* Tx BMU Control / Status Registers (Yukon-2) */
777 /* Bit 31: same as for Rx */
778 enum {
779 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
780 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
781 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
782 };
783
784 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
785 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
786 enum {
787 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
788 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
789 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
790 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
791 };
792
793 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
794 /* RB_START 32 bit RAM Buffer Start Address */
795 /* RB_END 32 bit RAM Buffer End Address */
796 /* RB_WP 32 bit RAM Buffer Write Pointer */
797 /* RB_RP 32 bit RAM Buffer Read Pointer */
798 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
799 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
800 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
801 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
802 /* RB_PC 32 bit RAM Buffer Packet Counter */
803 /* RB_LEV 32 bit RAM Buffer Level Register */
804
805 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
806 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
807 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
808
809 /* RB_CTRL 8 bit RAM Buffer Control Register */
810 enum {
811 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
812 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
813 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
814 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
815 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
816 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
817 };
818
819
820 /* Transmit GMAC FIFO (YUKON only) */
821 enum {
822 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
823 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
824 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
825
826 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
827 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
828 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
829
830 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
831 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
832 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
833
834 /* Threshold values for Yukon-EC Ultra and Extreme */
835 ECU_AE_THR = 0x0070, /* Almost Empty Threshold */
836 ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */
837 ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */
838 };
839
840 /* Descriptor Poll Timer Registers */
841 enum {
842 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
843 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
844 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
845
846 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
847 };
848
849 /* Time Stamp Timer Registers (YUKON only) */
850 enum {
851 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
852 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
853 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
854 };
855
856 /* Polling Unit Registers (Yukon-2 only) */
857 enum {
858 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
859 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
860
861 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
862 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
863 };
864
865 enum {
866 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
867 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
868 };
869
870 enum {
871 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
872 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
873 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
874 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
875 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
876 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
877 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
878 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
879 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
880 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
881 };
882
883 /* ASF Subsystem Registers (Yukon-2 only) */
884 enum {
885 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
886 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
887 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
888
889 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
890 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
891 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
892 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
893 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
894 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
895 };
896
897 /* Status BMU Registers (Yukon-2 only)*/
898 enum {
899 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
900 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
901
902 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
903 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
904 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
905 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
906 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
907 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
908 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
909 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
910
911 /* FIFO Control/Status Registers (Yukon-2 only)*/
912 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
913 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
914 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
915 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
916 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
917 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
918 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
919
920 /* Level and ISR Timer Registers (Yukon-2 only)*/
921 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
922 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
923 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
924 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
925 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
926 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
927 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
928 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
929 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
930 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
931 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
932 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
933 };
934
935 enum {
936 LINKLED_OFF = 0x01,
937 LINKLED_ON = 0x02,
938 LINKLED_LINKSYNC_OFF = 0x04,
939 LINKLED_LINKSYNC_ON = 0x08,
940 LINKLED_BLINK_OFF = 0x10,
941 LINKLED_BLINK_ON = 0x20,
942 };
943
944 /* GMAC and GPHY Control Registers (YUKON only) */
945 enum {
946 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
947 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
948 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
949 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
950 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
951
952 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
953 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
954 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
955 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
956 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
957 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
958
959 /* WOL Pattern Length Registers (YUKON only) */
960 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
961 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
962
963 /* WOL Pattern Counter Registers (YUKON only) */
964 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
965 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
966 };
967 #define WOL_REGS(port, x) (x + (port)*0x80)
968
969 enum {
970 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
971 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
972 };
973 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
974
975 enum {
976 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
977 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
978 };
979
980 /*
981 * Marvel-PHY Registers, indirect addressed over GMAC
982 */
983 enum {
984 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
985 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
986 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
987 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
988 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
989 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
990 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
991 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
992 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
993 /* Marvel-specific registers */
994 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
995 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
996 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
997 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
998 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
999 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1000 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1001 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1002 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1003 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1004 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1005 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1006 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1007 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1008 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1009 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1010 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1011 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1012
1013 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1014 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1015 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1016 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1017 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1018 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1019 };
1020
1021 enum {
1022 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1023 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1024 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1025 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1026 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1027 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1028 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1029 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1030 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1031 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1032 };
1033
1034 enum {
1035 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1036 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1037 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1038 };
1039
1040 enum {
1041 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1042
1043 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1044 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1045 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1046 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1047 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1048 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1049 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1050 };
1051
1052 enum {
1053 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1054 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1055 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1056 };
1057
1058 /* different Marvell PHY Ids */
1059 enum {
1060 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1061
1062 PHY_BCOM_ID1_A1 = 0x6041,
1063 PHY_BCOM_ID1_B2 = 0x6043,
1064 PHY_BCOM_ID1_C0 = 0x6044,
1065 PHY_BCOM_ID1_C5 = 0x6047,
1066
1067 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1068 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1069 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1070 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1071 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1072 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1073 };
1074
1075 /* Advertisement register bits */
1076 enum {
1077 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1078 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1079 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1080
1081 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1082 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1083 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1084 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1085 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1086 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1087 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1088 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1089 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1090 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1091 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1092 PHY_AN_100HALF | PHY_AN_100FULL,
1093 };
1094
1095 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1096 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1097 enum {
1098 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1099 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1100 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1101 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1102 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1103 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1104 /* Bit 9..8: reserved */
1105 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1106 };
1107
1108 /** Marvell-Specific */
1109 enum {
1110 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1111 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1112 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1113
1114 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1115 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1116 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1117 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1118 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1119 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1120 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1121 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1122 };
1123
1124 /* special defines for FIBER (88E1011S only) */
1125 enum {
1126 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1127 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1128 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1129 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1130 };
1131
1132 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1133 enum {
1134 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1135 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1136 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1137 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1138 };
1139
1140 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1141 enum {
1142 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1143 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1144 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1145 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1146 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1147 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1148 };
1149
1150 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1151 enum {
1152 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1153 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1154 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1155 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1156 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1157 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1158 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1159 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1160 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1161 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1162 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1163 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1164 };
1165
1166 enum {
1167 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1168 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1169 };
1170
1171 #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
1172
1173 enum {
1174 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1175 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1176 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1177 };
1178
1179 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1180 enum {
1181 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1182 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1183 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1184 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1185 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1186
1187 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1188 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1189
1190 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1191 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1192 };
1193
1194 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1195 enum {
1196 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1197 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1198 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1199 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1200 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1201 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1202 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1203 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1204 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1205 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1206 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1207 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1208 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1209 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1210 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1211 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1212 };
1213
1214 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1215
1216 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1217 enum {
1218 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1219 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1220 };
1221
1222 enum {
1223 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1224 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1225 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1226 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1227 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1228 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1229 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1230 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1231 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1232 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1233 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1234 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1235
1236 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1237 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1238 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1239
1240 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1241 | PHY_M_IS_DUP_CHANGE,
1242 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1243 };
1244
1245
1246 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1247 enum {
1248 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1249 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1250
1251 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1252 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1253 /* (88E1011 only) */
1254 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1255 /* (88E1011 only) */
1256 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1257 /* (88E1111 only) */
1258 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1259 /* !!! Errata in spec. (1 = disable) */
1260 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1261 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1262 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1263 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1264 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1265 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1266
1267 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
1268 /* 00=1x; 01=2x; 10=3x; 11=4x */
1269 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
1270 /* 00=dis; 01=1x; 10=2x; 11=3x */
1271 #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
1272 /* 000=1x; 001=2x; 010=3x; 011=4x */
1273 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
1274 /* 01X=0; 110=2.5; 111=25 (MHz) */
1275
1276 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1277 enum {
1278 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1279 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1280 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1281 };
1282 /* !!! Errata in spec. (1 = disable) */
1283
1284 #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
1285 /* 100=5x; 101=6x; 110=7x; 111=8x */
1286 enum {
1287 MAC_TX_CLK_0_MHZ = 2,
1288 MAC_TX_CLK_2_5_MHZ = 6,
1289 MAC_TX_CLK_25_MHZ = 7,
1290 };
1291
1292 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1293 enum {
1294 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1295 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1296 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1297 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1298 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1299 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1300 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1301 /* (88E1111 only) */
1302 };
1303
1304 enum {
1305 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1306 /* (88E1011 only) */
1307 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1308 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1309 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1310 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1311 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1312 };
1313
1314 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1315
1316 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1317 enum {
1318 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1319 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1320 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1321 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1322 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1323 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1324 };
1325
1326 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1327 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1328 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1329 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1330 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1331 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1332
1333 enum {
1334 PULS_NO_STR = 0,/* no pulse stretching */
1335 PULS_21MS = 1,/* 21 ms to 42 ms */
1336 PULS_42MS = 2,/* 42 ms to 84 ms */
1337 PULS_84MS = 3,/* 84 ms to 170 ms */
1338 PULS_170MS = 4,/* 170 ms to 340 ms */
1339 PULS_340MS = 5,/* 340 ms to 670 ms */
1340 PULS_670MS = 6,/* 670 ms to 1.3 s */
1341 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1342 };
1343
1344 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1345
1346 enum {
1347 BLINK_42MS = 0,/* 42 ms */
1348 BLINK_84MS = 1,/* 84 ms */
1349 BLINK_170MS = 2,/* 170 ms */
1350 BLINK_340MS = 3,/* 340 ms */
1351 BLINK_670MS = 4,/* 670 ms */
1352 };
1353
1354 /**** PHY_MARV_LED_OVER 16 bit r/w LED control */
1355 enum {
1356 PHY_M_LED_MO_DUP = 3<<10,/* Bit 11..10: Duplex */
1357 PHY_M_LED_MO_10 = 3<<8, /* Bit 9.. 8: Link 10 */
1358 PHY_M_LED_MO_100 = 3<<6, /* Bit 7.. 6: Link 100 */
1359 PHY_M_LED_MO_1000 = 3<<4, /* Bit 5.. 4: Link 1000 */
1360 PHY_M_LED_MO_RX = 3<<2, /* Bit 3.. 2: Rx */
1361 PHY_M_LED_MO_TX = 3<<0, /* Bit 1.. 0: Tx */
1362
1363 PHY_M_LED_ALL = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10
1364 | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000
1365 | PHY_M_LED_MO_RX,
1366 };
1367
1368 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1369 enum {
1370 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1371 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1372 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1373 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1374 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1375 };
1376
1377 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1378 enum {
1379 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1380 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1381 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1382 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1383 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1384 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1385 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1386 /* (88E1111 only) */
1387
1388 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1389 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1390 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1391 };
1392
1393 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1394 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1395 /* Bit 15..12: reserved (used internally) */
1396 enum {
1397 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1398 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1399 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1400 };
1401
1402 #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
1403 #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
1404 #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
1405
1406 enum {
1407 LED_PAR_CTRL_COLX = 0x00,
1408 LED_PAR_CTRL_ERROR = 0x01,
1409 LED_PAR_CTRL_DUPLEX = 0x02,
1410 LED_PAR_CTRL_DP_COL = 0x03,
1411 LED_PAR_CTRL_SPEED = 0x04,
1412 LED_PAR_CTRL_LINK = 0x05,
1413 LED_PAR_CTRL_TX = 0x06,
1414 LED_PAR_CTRL_RX = 0x07,
1415 LED_PAR_CTRL_ACT = 0x08,
1416 LED_PAR_CTRL_LNK_RX = 0x09,
1417 LED_PAR_CTRL_LNK_AC = 0x0a,
1418 LED_PAR_CTRL_ACT_BL = 0x0b,
1419 LED_PAR_CTRL_TX_BL = 0x0c,
1420 LED_PAR_CTRL_RX_BL = 0x0d,
1421 LED_PAR_CTRL_COL_BL = 0x0e,
1422 LED_PAR_CTRL_INACT = 0x0f
1423 };
1424
1425 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1426 enum {
1427 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1428 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1429 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1430 };
1431
1432 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1433 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1434 enum {
1435 PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */
1436 PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */
1437 PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */
1438 };
1439
1440 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1441 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1442 enum {
1443 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1444 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1445 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1446 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1447 };
1448 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1449
1450 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1451 enum {
1452 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1453 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1454 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1455 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1456 };
1457
1458 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1459 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1460 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1461 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1462
1463 /* GMAC registers */
1464 /* Port Registers */
1465 enum {
1466 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1467 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1468 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1469 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1470 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1471 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1472 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1473 /* Source Address Registers */
1474 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1475 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1476 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1477 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1478 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1479 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1480
1481 /* Multicast Address Hash Registers */
1482 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1483 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1484 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1485 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1486
1487 /* Interrupt Source Registers */
1488 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1489 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1490 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1491
1492 /* Interrupt Mask Registers */
1493 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1494 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1495 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1496
1497 /* Serial Management Interface (SMI) Registers */
1498 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1499 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1500 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1501 /* MIB Counters */
1502 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
1503 GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
1504 };
1505
1506
1507 /*
1508 * MIB Counters base address definitions (low word) -
1509 * use offset 4 for access to high word (32 bit r/o)
1510 */
1511 enum {
1512 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1513 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1514 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1515 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1516 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1517
1518 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1519 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1520 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1521 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1522 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1523 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1524 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1525 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1526 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1527 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1528 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1529 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1530 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1531 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1532 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1533
1534 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1535 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1536 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1537 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1538 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1539 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1540 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1541 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1542 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1543 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1544 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1545 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1546 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1547 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1548
1549 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1550 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1551 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1552 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1553 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1554 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1555 };
1556
1557 /* GMAC Bit Definitions */
1558 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1559 enum {
1560 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1561 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1562 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1563 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1564 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1565 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1566 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1567 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1568
1569 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1570 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1571 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1572 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1573 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1574 };
1575
1576 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1577 enum {
1578 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1579 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1580 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1581 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1582 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1583 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1584 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1585 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1586 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1587 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1588 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1589 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1590 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1591 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1592 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1593 };
1594
1595 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1596 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1597
1598 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1599 enum {
1600 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1601 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1602 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1603 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1604 };
1605
1606 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1607 #define TX_COL_DEF 0x04
1608
1609 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1610 enum {
1611 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1612 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1613 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1614 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1615 };
1616
1617 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1618 enum {
1619 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1620 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1621 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1622 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1623
1624 TX_JAM_LEN_DEF = 0x03,
1625 TX_JAM_IPG_DEF = 0x0b,
1626 TX_IPG_JAM_DEF = 0x1c,
1627 TX_BOF_LIM_DEF = 0x04,
1628 };
1629
1630 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1631 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1632 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1633 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1634
1635
1636 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1637 enum {
1638 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1639 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1640 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1641 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1642 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1643 };
1644
1645 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1646 #define DATA_BLIND_DEF 0x04
1647
1648 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1649 #define IPG_DATA_DEF 0x1e
1650
1651 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1652 enum {
1653 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1654 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1655 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1656 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1657 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1658 };
1659
1660 #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
1661 #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
1662
1663 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1664 enum {
1665 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1666 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1667 };
1668
1669 /* Receive Frame Status Encoding */
1670 enum {
1671 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1672 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1673 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1674 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1675 GMR_FS_MC = 1<<10, /* Multicast Packet */
1676 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1677 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1678 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1679 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1680 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1681 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1682 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1683
1684 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1685 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1686
1687 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1688 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1689 GMR_FS_MII_ERR | GMR_FS_BAD_FC |
1690 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1691 };
1692
1693 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1694 enum {
1695 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1696 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1697 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1698 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1699
1700 RX_MACSEC_FLUSH_ON = 1<<23,
1701 RX_MACSEC_FLUSH_OFF = 1<<22,
1702 RX_MACSEC_ASF_FLUSH_ON = 1<<21,
1703 RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
1704
1705 GMF_RX_OVER_ON = 1<<19, /* enable flushing on receive overrun */
1706 GMF_RX_OVER_OFF = 1<<18, /* disable flushing on receive overrun */
1707 GMF_ASF_RX_OVER_ON = 1<<17, /* enable flushing of ASF when overrun */
1708 GMF_ASF_RX_OVER_OFF = 1<<16, /* disable flushing of ASF when overrun */
1709
1710 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1711 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1712 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1713
1714 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1715 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1716 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1717 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1718 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1719 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1720 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1721
1722 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1723 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1724 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1725 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1726
1727 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1728
1729 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1730 };
1731
1732
1733 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1734 enum {
1735 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1736 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1737
1738 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1739 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1740
1741 TX_JUMBO_ENA = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1742 TX_JUMBO_DIS = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1743
1744 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1745 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1746 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1747
1748 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1749 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1750 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1751 };
1752
1753 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1754 enum {
1755 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1756 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1757 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1758 };
1759
1760 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1761 enum {
1762 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1763 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1764 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1765 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1766 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1767
1768 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1769 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1770 };
1771
1772 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1773 enum {
1774 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1775 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1776 };
1777 /* HCU_CCSR CPU Control and Status Register */
1778 enum {
1779 HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
1780 HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */
1781 /* Clock Stretching Timeout */
1782 HCU_CCSR_CS_TO = 1<<25,
1783 HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */
1784
1785 HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */
1786 HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */
1787
1788 HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */
1789 HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */
1790
1791 HCU_CCSR_SET_SYNC_CPU = 1<<5,
1792 HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
1793 HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
1794 HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */
1795 /* Microcontroller State */
1796 HCU_CCSR_UC_STATE_MSK = 3,
1797 HCU_CCSR_UC_STATE_BASE = 1<<0,
1798 HCU_CCSR_ASF_RESET = 0,
1799 HCU_CCSR_ASF_HALTED = 1<<1,
1800 HCU_CCSR_ASF_RUNNING = 1<<0,
1801 };
1802
1803 /* HCU_HCSR Host Control and Status Register */
1804 enum {
1805 HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */
1806
1807 HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */
1808 HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */
1809 };
1810
1811 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1812 enum {
1813 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1814 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1815 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1816 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1817 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1818 };
1819
1820 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1821 enum {
1822 GMC_SET_RST = 1<<15,/* MAC SEC RST */
1823 GMC_SEC_RST_OFF = 1<<14,/* MAC SEC RSt OFF */
1824 GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
1825 GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
1826 GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
1827 GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX off*/
1828 GMC_BYP_RETR_ON = 1<<9, /* Bypass retransmit FIFO On */
1829 GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */
1830
1831 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1832 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1833 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1834 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1835 GMC_PAUSE_ON = 1<<3, /* Pause On */
1836 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1837 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1838 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1839 };
1840
1841 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1842 enum {
1843 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1844 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1845 };
1846
1847 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1848 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1849 enum {
1850 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1851 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1852 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1853 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1854 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1855 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1856
1857 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1858 };
1859
1860 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1861 enum { /* Bits 15.. 2: reserved */
1862 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1863 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1864 };
1865
1866
1867 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1868 enum {
1869 WOL_CTL_LINK_CHG_OCC = 1<<15,
1870 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1871 WOL_CTL_PATTERN_OCC = 1<<13,
1872 WOL_CTL_CLEAR_RESULT = 1<<12,
1873 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1874 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1875 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1876 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1877 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1878 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1879 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1880 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1881 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1882 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1883 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1884 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1885 };
1886
1887
1888 /* Control flags */
1889 enum {
1890 UDPTCP = 1<<0,
1891 CALSUM = 1<<1,
1892 WR_SUM = 1<<2,
1893 INIT_SUM= 1<<3,
1894 LOCK_SUM= 1<<4,
1895 INS_VLAN= 1<<5,
1896 EOP = 1<<7,
1897 };
1898
1899 enum {
1900 HW_OWNER = 1<<7,
1901 OP_TCPWRITE = 0x11,
1902 OP_TCPSTART = 0x12,
1903 OP_TCPINIT = 0x14,
1904 OP_TCPLCK = 0x18,
1905 OP_TCPCHKSUM = OP_TCPSTART,
1906 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1907 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1908 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1909 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1910
1911 OP_ADDR64 = 0x21,
1912 OP_VLAN = 0x22,
1913 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1914 OP_LRGLEN = 0x24,
1915 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1916 OP_MSS = 0x28,
1917 OP_MSSVLAN = OP_MSS | OP_VLAN,
1918
1919 OP_BUFFER = 0x40,
1920 OP_PACKET = 0x41,
1921 OP_LARGESEND = 0x43,
1922 OP_LSOV2 = 0x45,
1923
1924 /* YUKON-2 STATUS opcodes defines */
1925 OP_RXSTAT = 0x60,
1926 OP_RXTIMESTAMP = 0x61,
1927 OP_RXVLAN = 0x62,
1928 OP_RXCHKS = 0x64,
1929 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1930 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1931 OP_RSS_HASH = 0x65,
1932 OP_TXINDEXLE = 0x68,
1933 OP_MACSEC = 0x6c,
1934 OP_PUTIDX = 0x70,
1935 };
1936
1937 enum status_css {
1938 CSS_TCPUDPCSOK = 1<<7, /* TCP / UDP checksum is ok */
1939 CSS_ISUDP = 1<<6, /* packet is a UDP packet */
1940 CSS_ISTCP = 1<<5, /* packet is a TCP packet */
1941 CSS_ISIPFRAG = 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
1942 CSS_ISIPV6 = 1<<3, /* packet is a IPv6 packet */
1943 CSS_IPV4CSUMOK = 1<<2, /* IP v4: TCP header checksum is ok */
1944 CSS_ISIPV4 = 1<<1, /* packet is a IPv4 packet */
1945 CSS_LINK_BIT = 1<<0, /* port number (legacy) */
1946 };
1947
1948 /* Yukon 2 hardware interface */
1949 struct sky2_tx_le {
1950 __le32 addr;
1951 __le16 length; /* also vlan tag or checksum start */
1952 u8 ctrl;
1953 u8 opcode;
1954 } __attribute((packed));
1955
1956 struct sky2_rx_le {
1957 __le32 addr;
1958 __le16 length;
1959 u8 ctrl;
1960 u8 opcode;
1961 } __attribute((packed));
1962
1963 struct sky2_status_le {
1964 __le32 status; /* also checksum */
1965 __le16 length; /* also vlan tag */
1966 u8 css;
1967 u8 opcode;
1968 } __attribute((packed));
1969
1970 struct tx_ring_info {
1971 struct sk_buff *skb;
1972 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1973 DECLARE_PCI_UNMAP_ADDR(maplen);
1974 };
1975
1976 struct rx_ring_info {
1977 struct sk_buff *skb;
1978 dma_addr_t data_addr;
1979 DECLARE_PCI_UNMAP_ADDR(data_size);
1980 dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
1981 };
1982
1983 enum flow_control {
1984 FC_NONE = 0,
1985 FC_TX = 1,
1986 FC_RX = 2,
1987 FC_BOTH = 3,
1988 };
1989
1990 struct sky2_port {
1991 struct sky2_hw *hw;
1992 struct net_device *netdev;
1993 unsigned port;
1994 u32 msg_enable;
1995 spinlock_t phy_lock;
1996
1997 struct tx_ring_info *tx_ring;
1998 struct sky2_tx_le *tx_le;
1999 u16 tx_cons; /* next le to check */
2000 u16 tx_prod; /* next le to use */
2001 u16 tx_next; /* debug only */
2002 u32 tx_addr64;
2003 u16 tx_pending;
2004 u16 tx_last_mss;
2005 u32 tx_tcpsum;
2006
2007 struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp;
2008 struct sky2_rx_le *rx_le;
2009 u32 rx_addr64;
2010 u16 rx_next; /* next re to check */
2011 u16 rx_put; /* next le index to use */
2012 u16 rx_pending;
2013 u16 rx_data_size;
2014 u16 rx_nfrags;
2015
2016 #ifdef SKY2_VLAN_TAG_USED
2017 u16 rx_tag;
2018 struct vlan_group *vlgrp;
2019 #endif
2020
2021 dma_addr_t rx_le_map;
2022 dma_addr_t tx_le_map;
2023 u16 advertising; /* ADVERTISED_ bits */
2024 u16 speed; /* SPEED_1000, SPEED_100, ... */
2025 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2026 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2027 u8 rx_csum;
2028 u8 wol;
2029 enum flow_control flow_mode;
2030 enum flow_control flow_status;
2031
2032 #ifdef CONFIG_SKY2_DEBUG
2033 struct dentry *debugfs;
2034 #endif
2035 struct net_device_stats net_stats;
2036
2037 };
2038
2039 struct sky2_hw {
2040 void __iomem *regs;
2041 struct pci_dev *pdev;
2042 struct net_device *dev[2];
2043
2044 u8 chip_id;
2045 u8 chip_rev;
2046 u8 pmd_type;
2047 u8 ports;
2048
2049 struct sky2_status_le *st_le;
2050 u32 st_idx;
2051 dma_addr_t st_dma;
2052
2053 struct timer_list idle_timer;
2054 struct work_struct restart_work;
2055 int msi;
2056 wait_queue_head_t msi_wait;
2057 };
2058
2059 static inline int sky2_is_copper(const struct sky2_hw *hw)
2060 {
2061 return !(hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P');
2062 }
2063
2064 /* Register accessor for memory mapped device */
2065 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
2066 {
2067 return readl(hw->regs + reg);
2068 }
2069
2070 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
2071 {
2072 return readw(hw->regs + reg);
2073 }
2074
2075 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
2076 {
2077 return readb(hw->regs + reg);
2078 }
2079
2080 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
2081 {
2082 writel(val, hw->regs + reg);
2083 }
2084
2085 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
2086 {
2087 writew(val, hw->regs + reg);
2088 }
2089
2090 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
2091 {
2092 writeb(val, hw->regs + reg);
2093 }
2094
2095 /* Yukon PHY related registers */
2096 #define SK_GMAC_REG(port,reg) \
2097 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2098 #define GM_PHY_RETRIES 100
2099
2100 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
2101 {
2102 return sky2_read16(hw, SK_GMAC_REG(port,reg));
2103 }
2104
2105 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
2106 {
2107 unsigned base = SK_GMAC_REG(port, reg);
2108 return (u32) sky2_read16(hw, base)
2109 | (u32) sky2_read16(hw, base+4) << 16;
2110 }
2111
2112 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
2113 {
2114 sky2_write16(hw, SK_GMAC_REG(port,r), v);
2115 }
2116
2117 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
2118 const u8 *addr)
2119 {
2120 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2121 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2122 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2123 }
2124
2125 /* PCI config space access */
2126 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
2127 {
2128 return sky2_read32(hw, Y2_CFG_SPC + reg);
2129 }
2130
2131 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
2132 {
2133 return sky2_read16(hw, Y2_CFG_SPC + reg);
2134 }
2135
2136 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
2137 {
2138 sky2_write32(hw, Y2_CFG_SPC + reg, val);
2139 }
2140
2141 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
2142 {
2143 sky2_write16(hw, Y2_CFG_SPC + reg, val);
2144 }
2145 #endif
Software Suspend 2 for Linus's 2.6 head (mirror)