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Complete the renaming to TuxOnIce with function names, vars etc.
[linux-2.6/suspend2-head.git] / drivers / net / sun3lance.c
blobf1548c033327d9a3ae3d9c50438de721d7663906
1 /* sun3lance.c: Ethernet driver for SUN3 Lance chip */
2 /*
3
4 Sun3 Lance ethernet driver, by Sam Creasey (sammy@users.qual.net).
5 This driver is a part of the linux kernel, and is thus distributed
6 under the GNU General Public License.
7
8 The values used in LANCE_OBIO and LANCE_IRQ seem to be empirically
9 true for the correct IRQ and address of the lance registers. They
10 have not been widely tested, however. What we probably need is a
11 "proper" way to search for a device in the sun3's prom, but, alas,
12 linux has no such thing.
13
14 This driver is largely based on atarilance.c, by Roman Hodek. Other
15 sources of inspiration were the NetBSD sun3 am7990 driver, and the
16 linux sparc lance driver (sunlance.c).
17
18 There are more assumptions made throughout this driver, it almost
19 certainly still needs work, but it does work at least for RARP/BOOTP and
20 mounting the root NFS filesystem.
21
22 */
23
24 static char *version = "sun3lance.c: v1.2 1/12/2001 Sam Creasey (sammy@sammy.net)\n";
25
26 #include <linux/module.h>
27 #include <linux/stddef.h>
28 #include <linux/kernel.h>
29 #include <linux/string.h>
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/ioport.h>
35 #include <linux/delay.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/bitops.h>
40
41 #include <asm/cacheflush.h>
42 #include <asm/setup.h>
43 #include <asm/irq.h>
44 #include <asm/io.h>
45 #include <asm/pgtable.h>
46 #include <asm/dvma.h>
47 #include <asm/idprom.h>
48 #include <asm/machines.h>
49
50 #ifdef CONFIG_SUN3
51 #include <asm/sun3mmu.h>
52 #else
53 #include <asm/sun3xprom.h>
54 #endif
55
56 /* sun3/60 addr/irq for the lance chip. If your sun is different,
57 change this. */
58 #define LANCE_OBIO 0x120000
59 #define LANCE_IRQ IRQ_AUTO_3
60
61 /* Debug level:
62 * 0 = silent, print only serious errors
63 * 1 = normal, print error messages
64 * 2 = debug, print debug infos
65 * 3 = debug, print even more debug infos (packet data)
66 */
67
68 #define LANCE_DEBUG 0
69
70 #ifdef LANCE_DEBUG
71 static int lance_debug = LANCE_DEBUG;
72 #else
73 static int lance_debug = 1;
74 #endif
75 module_param(lance_debug, int, 0);
76 MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)");
77 MODULE_LICENSE("GPL");
78
79 #define DPRINTK(n,a) \
80 do { \
81 if (lance_debug >= n) \
82 printk a; \
83 } while( 0 )
84
85
86 /* we're only using 32k of memory, so we use 4 TX
87 buffers and 16 RX buffers. These values are expressed as log2. */
88
89 #define TX_LOG_RING_SIZE 3
90 #define RX_LOG_RING_SIZE 5
91
92 /* These are the derived values */
93
94 #define TX_RING_SIZE (1 << TX_LOG_RING_SIZE)
95 #define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5)
96 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
97
98 #define RX_RING_SIZE (1 << RX_LOG_RING_SIZE)
99 #define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5)
100 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
101
102 /* Definitions for packet buffer access: */
103 #define PKT_BUF_SZ 1544
104
105 /* Get the address of a packet buffer corresponding to a given buffer head */
106 #define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base)
107
108
109 /* The LANCE Rx and Tx ring descriptors. */
110 struct lance_rx_head {
111 unsigned short base; /* Low word of base addr */
112 volatile unsigned char flag;
113 unsigned char base_hi; /* High word of base addr (unused) */
114 short buf_length; /* This length is 2s complement! */
115 volatile short msg_length; /* This length is "normal". */
116 };
117
118 struct lance_tx_head {
119 unsigned short base; /* Low word of base addr */
120 volatile unsigned char flag;
121 unsigned char base_hi; /* High word of base addr (unused) */
122 short length; /* Length is 2s complement! */
123 volatile short misc;
124 };
125
126 /* The LANCE initialization block, described in databook. */
127 struct lance_init_block {
128 unsigned short mode; /* Pre-set mode */
129 unsigned char hwaddr[6]; /* Physical ethernet address */
130 unsigned int filter[2]; /* Multicast filter (unused). */
131 /* Receive and transmit ring base, along with length bits. */
132 unsigned short rdra;
133 unsigned short rlen;
134 unsigned short tdra;
135 unsigned short tlen;
136 unsigned short pad[4]; /* is thie needed? */
137 };
138
139 /* The whole layout of the Lance shared memory */
140 struct lance_memory {
141 struct lance_init_block init;
142 struct lance_tx_head tx_head[TX_RING_SIZE];
143 struct lance_rx_head rx_head[RX_RING_SIZE];
144 char rx_data[RX_RING_SIZE][PKT_BUF_SZ];
145 char tx_data[TX_RING_SIZE][PKT_BUF_SZ];
146 };
147
148 /* The driver's private device structure */
149
150 struct lance_private {
151 volatile unsigned short *iobase;
152 struct lance_memory *mem;
153 int new_rx, new_tx; /* The next free ring entry */
154 int old_tx, old_rx; /* ring entry to be processed */
155 struct net_device_stats stats;
156 /* These two must be longs for set_bit() */
157 long tx_full;
158 long lock;
159 };
160
161 /* I/O register access macros */
162
163 #define MEM lp->mem
164 #define DREG lp->iobase[0]
165 #define AREG lp->iobase[1]
166 #define REGA(a) (*( AREG = (a), &DREG ))
167
168 /* Definitions for the Lance */
169
170 /* tx_head flags */
171 #define TMD1_ENP 0x01 /* end of packet */
172 #define TMD1_STP 0x02 /* start of packet */
173 #define TMD1_DEF 0x04 /* deferred */
174 #define TMD1_ONE 0x08 /* one retry needed */
175 #define TMD1_MORE 0x10 /* more than one retry needed */
176 #define TMD1_ERR 0x40 /* error summary */
177 #define TMD1_OWN 0x80 /* ownership (set: chip owns) */
178
179 #define TMD1_OWN_CHIP TMD1_OWN
180 #define TMD1_OWN_HOST 0
181
182 /* tx_head misc field */
183 #define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */
184 #define TMD3_RTRY 0x0400 /* failed after 16 retries */
185 #define TMD3_LCAR 0x0800 /* carrier lost */
186 #define TMD3_LCOL 0x1000 /* late collision */
187 #define TMD3_UFLO 0x4000 /* underflow (late memory) */
188 #define TMD3_BUFF 0x8000 /* buffering error (no ENP) */
189
190 /* rx_head flags */
191 #define RMD1_ENP 0x01 /* end of packet */
192 #define RMD1_STP 0x02 /* start of packet */
193 #define RMD1_BUFF 0x04 /* buffer error */
194 #define RMD1_CRC 0x08 /* CRC error */
195 #define RMD1_OFLO 0x10 /* overflow */
196 #define RMD1_FRAM 0x20 /* framing error */
197 #define RMD1_ERR 0x40 /* error summary */
198 #define RMD1_OWN 0x80 /* ownership (set: ship owns) */
199
200 #define RMD1_OWN_CHIP RMD1_OWN
201 #define RMD1_OWN_HOST 0
202
203 /* register names */
204 #define CSR0 0 /* mode/status */
205 #define CSR1 1 /* init block addr (low) */
206 #define CSR2 2 /* init block addr (high) */
207 #define CSR3 3 /* misc */
208 #define CSR8 8 /* address filter */
209 #define CSR15 15 /* promiscuous mode */
210
211 /* CSR0 */
212 /* (R=readable, W=writeable, S=set on write, C=clear on write) */
213 #define CSR0_INIT 0x0001 /* initialize (RS) */
214 #define CSR0_STRT 0x0002 /* start (RS) */
215 #define CSR0_STOP 0x0004 /* stop (RS) */
216 #define CSR0_TDMD 0x0008 /* transmit demand (RS) */
217 #define CSR0_TXON 0x0010 /* transmitter on (R) */
218 #define CSR0_RXON 0x0020 /* receiver on (R) */
219 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */
220 #define CSR0_INTR 0x0080 /* interrupt active (R) */
221 #define CSR0_IDON 0x0100 /* initialization done (RC) */
222 #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */
223 #define CSR0_RINT 0x0400 /* receiver interrupt (RC) */
224 #define CSR0_MERR 0x0800 /* memory error (RC) */
225 #define CSR0_MISS 0x1000 /* missed frame (RC) */
226 #define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */
227 #define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */
228 #define CSR0_ERR 0x8000 /* error (RC) */
229
230 /* CSR3 */
231 #define CSR3_BCON 0x0001 /* byte control */
232 #define CSR3_ACON 0x0002 /* ALE control */
233 #define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */
234
235 /***************************** Prototypes *****************************/
236
237 static int lance_probe( struct net_device *dev);
238 static int lance_open( struct net_device *dev );
239 static void lance_init_ring( struct net_device *dev );
240 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev );
241 static irqreturn_t lance_interrupt( int irq, void *dev_id);
242 static int lance_rx( struct net_device *dev );
243 static int lance_close( struct net_device *dev );
244 static struct net_device_stats *lance_get_stats( struct net_device *dev );
245 static void set_multicast_list( struct net_device *dev );
246
247 /************************* End of Prototypes **************************/
248
249 struct net_device * __init sun3lance_probe(int unit)
250 {
251 struct net_device *dev;
252 static int found;
253 int err = -ENODEV;
254
255 /* check that this machine has an onboard lance */
256 switch(idprom->id_machtype) {
257 case SM_SUN3|SM_3_50:
258 case SM_SUN3|SM_3_60:
259 case SM_SUN3X|SM_3_80:
260 /* these machines have lance */
261 break;
262
263 default:
264 return ERR_PTR(-ENODEV);
265 }
266
267 if (found)
268 return ERR_PTR(-ENODEV);
269
270 dev = alloc_etherdev(sizeof(struct lance_private));
271 if (!dev)
272 return ERR_PTR(-ENOMEM);
273 if (unit >= 0) {
274 sprintf(dev->name, "eth%d", unit);
275 netdev_boot_setup_check(dev);
276 }
277 SET_MODULE_OWNER(dev);
278
279 if (!lance_probe(dev))
280 goto out;
281
282 err = register_netdev(dev);
283 if (err)
284 goto out1;
285 found = 1;
286 return dev;
287
288 out1:
289 #ifdef CONFIG_SUN3
290 iounmap((void __iomem *)dev->base_addr);
291 #endif
292 out:
293 free_netdev(dev);
294 return ERR_PTR(err);
295 }
296
297 static int __init lance_probe( struct net_device *dev)
298 {
299 unsigned long ioaddr;
300
301 struct lance_private *lp;
302 int i;
303 static int did_version;
304 volatile unsigned short *ioaddr_probe;
305 unsigned short tmp1, tmp2;
306
307 #ifdef CONFIG_SUN3
308 ioaddr = (unsigned long)ioremap(LANCE_OBIO, PAGE_SIZE);
309 if (!ioaddr)
310 return 0;
311 #else
312 ioaddr = SUN3X_LANCE;
313 #endif
314
315 /* test to see if there's really a lance here */
316 /* (CSRO_INIT shouldn't be readable) */
317
318 ioaddr_probe = (volatile unsigned short *)ioaddr;
319 tmp1 = ioaddr_probe[0];
320 tmp2 = ioaddr_probe[1];
321
322 ioaddr_probe[1] = CSR0;
323 ioaddr_probe[0] = CSR0_INIT | CSR0_STOP;
324
325 if(ioaddr_probe[0] != CSR0_STOP) {
326 ioaddr_probe[0] = tmp1;
327 ioaddr_probe[1] = tmp2;
328
329 #ifdef CONFIG_SUN3
330 iounmap((void __iomem *)ioaddr);
331 #endif
332 return 0;
333 }
334
335 lp = netdev_priv(dev);
336
337 /* XXX - leak? */
338 MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000);
339 if (MEM == NULL) {
340 #ifdef CONFIG_SUN3
341 iounmap((void __iomem *)ioaddr);
342 #endif
343 printk(KERN_WARNING "SUN3 Lance couldn't allocate DVMA memory\n");
344 return 0;
345 }
346
347 lp->iobase = (volatile unsigned short *)ioaddr;
348 dev->base_addr = (unsigned long)ioaddr; /* informational only */
349
350 REGA(CSR0) = CSR0_STOP;
351
352 if (request_irq(LANCE_IRQ, lance_interrupt, IRQF_DISABLED, "SUN3 Lance", dev) < 0) {
353 #ifdef CONFIG_SUN3
354 iounmap((void __iomem *)ioaddr);
355 #endif
356 dvma_free((void *)MEM);
357 printk(KERN_WARNING "SUN3 Lance unable to allocate IRQ\n");
358 return 0;
359 }
360 dev->irq = (unsigned short)LANCE_IRQ;
361
362
363 printk("%s: SUN3 Lance at io %#lx, mem %#lx, irq %d, hwaddr ",
364 dev->name,
365 (unsigned long)ioaddr,
366 (unsigned long)MEM,
367 dev->irq);
368
369 /* copy in the ethernet address from the prom */
370 for(i = 0; i < 6 ; i++)
371 dev->dev_addr[i] = idprom->id_ethaddr[i];
372
373 /* tell the card it's ether address, bytes swapped */
374 MEM->init.hwaddr[0] = dev->dev_addr[1];
375 MEM->init.hwaddr[1] = dev->dev_addr[0];
376 MEM->init.hwaddr[2] = dev->dev_addr[3];
377 MEM->init.hwaddr[3] = dev->dev_addr[2];
378 MEM->init.hwaddr[4] = dev->dev_addr[5];
379 MEM->init.hwaddr[5] = dev->dev_addr[4];
380
381 for( i = 0; i < 6; ++i )
382 printk( "%02x%s", dev->dev_addr[i], (i < 5) ? ":" : "\n" );
383
384 MEM->init.mode = 0x0000;
385 MEM->init.filter[0] = 0x00000000;
386 MEM->init.filter[1] = 0x00000000;
387 MEM->init.rdra = dvma_vtob(MEM->rx_head);
388 MEM->init.rlen = (RX_LOG_RING_SIZE << 13) |
389 (dvma_vtob(MEM->rx_head) >> 16);
390 MEM->init.tdra = dvma_vtob(MEM->tx_head);
391 MEM->init.tlen = (TX_LOG_RING_SIZE << 13) |
392 (dvma_vtob(MEM->tx_head) >> 16);
393
394 DPRINTK(2, ("initaddr: %08lx rx_ring: %08lx tx_ring: %08lx\n",
395 dvma_vtob(&(MEM->init)), dvma_vtob(MEM->rx_head),
396 (dvma_vtob(MEM->tx_head))));
397
398 if (did_version++ == 0)
399 printk( version );
400
401 /* The LANCE-specific entries in the device structure. */
402 dev->open = &lance_open;
403 dev->hard_start_xmit = &lance_start_xmit;
404 dev->stop = &lance_close;
405 dev->get_stats = &lance_get_stats;
406 dev->set_multicast_list = &set_multicast_list;
407 dev->set_mac_address = NULL;
408 // KLUDGE -- REMOVE ME
409 set_bit(__LINK_STATE_PRESENT, &dev->state);
410
411
412 memset( &lp->stats, 0, sizeof(lp->stats) );
413
414 return 1;
415 }
416
417 static int lance_open( struct net_device *dev )
418 {
419 struct lance_private *lp = netdev_priv(dev);
420 int i;
421
422 DPRINTK( 2, ( "%s: lance_open()\n", dev->name ));
423
424 REGA(CSR0) = CSR0_STOP;
425
426 lance_init_ring(dev);
427
428 /* From now on, AREG is kept to point to CSR0 */
429 REGA(CSR0) = CSR0_INIT;
430
431 i = 1000000;
432 while (--i > 0)
433 if (DREG & CSR0_IDON)
434 break;
435 if (i < 0 || (DREG & CSR0_ERR)) {
436 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n",
437 dev->name, i, DREG ));
438 DREG = CSR0_STOP;
439 return( -EIO );
440 }
441
442 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA;
443
444 netif_start_queue(dev);
445
446 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG ));
447
448 return( 0 );
449 }
450
451
452 /* Initialize the LANCE Rx and Tx rings. */
453
454 static void lance_init_ring( struct net_device *dev )
455 {
456 struct lance_private *lp = netdev_priv(dev);
457 int i;
458
459 lp->lock = 0;
460 lp->tx_full = 0;
461 lp->new_rx = lp->new_tx = 0;
462 lp->old_rx = lp->old_tx = 0;
463
464 for( i = 0; i < TX_RING_SIZE; i++ ) {
465 MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]);
466 MEM->tx_head[i].flag = 0;
467 MEM->tx_head[i].base_hi =
468 (dvma_vtob(MEM->tx_data[i])) >>16;
469 MEM->tx_head[i].length = 0;
470 MEM->tx_head[i].misc = 0;
471 }
472
473 for( i = 0; i < RX_RING_SIZE; i++ ) {
474 MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]);
475 MEM->rx_head[i].flag = RMD1_OWN_CHIP;
476 MEM->rx_head[i].base_hi =
477 (dvma_vtob(MEM->rx_data[i])) >> 16;
478 MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000;
479 MEM->rx_head[i].msg_length = 0;
480 }
481
482 /* tell the card it's ether address, bytes swapped */
483 MEM->init.hwaddr[0] = dev->dev_addr[1];
484 MEM->init.hwaddr[1] = dev->dev_addr[0];
485 MEM->init.hwaddr[2] = dev->dev_addr[3];
486 MEM->init.hwaddr[3] = dev->dev_addr[2];
487 MEM->init.hwaddr[4] = dev->dev_addr[5];
488 MEM->init.hwaddr[5] = dev->dev_addr[4];
489
490 MEM->init.mode = 0x0000;
491 MEM->init.filter[0] = 0x00000000;
492 MEM->init.filter[1] = 0x00000000;
493 MEM->init.rdra = dvma_vtob(MEM->rx_head);
494 MEM->init.rlen = (RX_LOG_RING_SIZE << 13) |
495 (dvma_vtob(MEM->rx_head) >> 16);
496 MEM->init.tdra = dvma_vtob(MEM->tx_head);
497 MEM->init.tlen = (TX_LOG_RING_SIZE << 13) |
498 (dvma_vtob(MEM->tx_head) >> 16);
499
500
501 /* tell the lance the address of its init block */
502 REGA(CSR1) = dvma_vtob(&(MEM->init));
503 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
504
505 #ifdef CONFIG_SUN3X
506 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON;
507 #else
508 REGA(CSR3) = CSR3_BSWP;
509 #endif
510
511 }
512
513
514 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev )
515 {
516 struct lance_private *lp = netdev_priv(dev);
517 int entry, len;
518 struct lance_tx_head *head;
519 unsigned long flags;
520
521 DPRINTK( 1, ( "%s: transmit start.\n",
522 dev->name));
523
524 /* Transmitter timeout, serious problems. */
525 if (netif_queue_stopped(dev)) {
526 int tickssofar = jiffies - dev->trans_start;
527 if (tickssofar < 20)
528 return( 1 );
529
530 DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n",
531 dev->name, DREG ));
532 DREG = CSR0_STOP;
533 /*
534 * Always set BSWP after a STOP as STOP puts it back into
535 * little endian mode.
536 */
537 REGA(CSR3) = CSR3_BSWP;
538 lp->stats.tx_errors++;
539
540 if(lance_debug >= 2) {
541 int i;
542 printk("Ring data: old_tx %d new_tx %d%s new_rx %d\n",
543 lp->old_tx, lp->new_tx,
544 lp->tx_full ? " (full)" : "",
545 lp->new_rx );
546 for( i = 0 ; i < RX_RING_SIZE; i++ )
547 printk( "rx #%d: base=%04x blen=%04x mlen=%04x\n",
548 i, MEM->rx_head[i].base,
549 -MEM->rx_head[i].buf_length,
550 MEM->rx_head[i].msg_length);
551 for( i = 0 ; i < TX_RING_SIZE; i++ )
552 printk("tx #%d: base=%04x len=%04x misc=%04x\n",
553 i, MEM->tx_head[i].base,
554 -MEM->tx_head[i].length,
555 MEM->tx_head[i].misc );
556 }
557
558 lance_init_ring(dev);
559 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
560
561 netif_start_queue(dev);
562 dev->trans_start = jiffies;
563
564 return 0;
565 }
566
567
568 /* Block a timer-based transmit from overlapping. This could better be
569 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
570
571 /* Block a timer-based transmit from overlapping with us by
572 stopping the queue for a bit... */
573
574 netif_stop_queue(dev);
575
576 if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) {
577 printk( "%s: tx queue lock!.\n", dev->name);
578 /* don't clear dev->tbusy flag. */
579 return 1;
580 }
581
582 AREG = CSR0;
583 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n",
584 dev->name, DREG ));
585
586 #ifdef CONFIG_SUN3X
587 /* this weirdness doesn't appear on sun3... */
588 if(!(DREG & CSR0_INIT)) {
589 DPRINTK( 1, ("INIT not set, reinitializing...\n"));
590 REGA( CSR0 ) = CSR0_STOP;
591 lance_init_ring(dev);
592 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT;
593 }
594 #endif
595
596 /* Fill in a Tx ring entry */
597 #if 0
598 if (lance_debug >= 2) {
599 u_char *p;
600 int i;
601 printk( "%s: TX pkt %d type 0x%04x from ", dev->name,
602 lp->new_tx, ((u_short *)skb->data)[6]);
603 for( p = &((u_char *)skb->data)[6], i = 0; i < 6; i++ )
604 printk("%02x%s", *p++, i != 5 ? ":" : "" );
605 printk(" to ");
606 for( p = (u_char *)skb->data, i = 0; i < 6; i++ )
607 printk("%02x%s", *p++, i != 5 ? ":" : "" );
608 printk(" data at 0x%08x len %d\n", (int)skb->data,
609 (int)skb->len );
610 }
611 #endif
612 /* We're not prepared for the int until the last flags are set/reset.
613 * And the int may happen already after setting the OWN_CHIP... */
614 local_irq_save(flags);
615
616 /* Mask to ring buffer boundary. */
617 entry = lp->new_tx;
618 head = &(MEM->tx_head[entry]);
619
620 /* Caution: the write order is important here, set the "ownership" bits
621 * last.
622 */
623
624 /* the sun3's lance needs it's buffer padded to the minimum
625 size */
626 len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
627
628 // head->length = -len;
629 head->length = (-len) | 0xf000;
630 head->misc = 0;
631
632 skb_copy_from_linear_data(skb, PKTBUF_ADDR(head), skb->len);
633 if (len != skb->len)
634 memset(PKTBUF_ADDR(head) + skb->len, 0, len-skb->len);
635
636 head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP;
637 lp->new_tx = (lp->new_tx + 1) & TX_RING_MOD_MASK;
638 lp->stats.tx_bytes += skb->len;
639
640 /* Trigger an immediate send poll. */
641 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT;
642 AREG = CSR0;
643 DPRINTK( 2, ( "%s: lance_start_xmit() exiting, csr0 %4.4x.\n",
644 dev->name, DREG ));
645 dev->trans_start = jiffies;
646 dev_kfree_skb( skb );
647
648 lp->lock = 0;
649 if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
650 TMD1_OWN_HOST)
651 netif_start_queue(dev);
652
653 local_irq_restore(flags);
654
655 return 0;
656 }
657
658 /* The LANCE interrupt handler. */
659
660 static irqreturn_t lance_interrupt( int irq, void *dev_id)
661 {
662 struct net_device *dev = dev_id;
663 struct lance_private *lp = netdev_priv(dev);
664 int csr0;
665 static int in_interrupt;
666
667 if (dev == NULL) {
668 DPRINTK( 1, ( "lance_interrupt(): invalid dev_id\n" ));
669 return IRQ_NONE;
670 }
671
672 if (in_interrupt)
673 DPRINTK( 2, ( "%s: Re-entering the interrupt handler.\n", dev->name ));
674 in_interrupt = 1;
675
676 still_more:
677 flush_cache_all();
678
679 AREG = CSR0;
680 csr0 = DREG;
681
682 /* ack interrupts */
683 DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON);
684
685 /* clear errors */
686 if(csr0 & CSR0_ERR)
687 DREG = CSR0_BABL | CSR0_MERR | CSR0_CERR | CSR0_MISS;
688
689
690 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n",
691 dev->name, csr0, DREG ));
692
693 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */
694 int old_tx = lp->old_tx;
695
696 // if(lance_debug >= 3) {
697 // int i;
698 //
699 // printk("%s: tx int\n", dev->name);
700 //
701 // for(i = 0; i < TX_RING_SIZE; i++)
702 // printk("ring %d flag=%04x\n", i,
703 // MEM->tx_head[i].flag);
704 // }
705
706 while( old_tx != lp->new_tx) {
707 struct lance_tx_head *head = &(MEM->tx_head[old_tx]);
708
709 DPRINTK(3, ("on tx_ring %d\n", old_tx));
710
711 if (head->flag & TMD1_OWN_CHIP)
712 break; /* It still hasn't been Txed */
713
714 if (head->flag & TMD1_ERR) {
715 int status = head->misc;
716 lp->stats.tx_errors++;
717 if (status & TMD3_RTRY) lp->stats.tx_aborted_errors++;
718 if (status & TMD3_LCAR) lp->stats.tx_carrier_errors++;
719 if (status & TMD3_LCOL) lp->stats.tx_window_errors++;
720 if (status & (TMD3_UFLO | TMD3_BUFF)) {
721 lp->stats.tx_fifo_errors++;
722 printk("%s: Tx FIFO error\n",
723 dev->name);
724 REGA(CSR0) = CSR0_STOP;
725 REGA(CSR3) = CSR3_BSWP;
726 lance_init_ring(dev);
727 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
728 return IRQ_HANDLED;
729 }
730 } else if(head->flag & (TMD1_ENP | TMD1_STP)) {
731
732 head->flag &= ~(TMD1_ENP | TMD1_STP);
733 if(head->flag & (TMD1_ONE | TMD1_MORE))
734 lp->stats.collisions++;
735
736 lp->stats.tx_packets++;
737 DPRINTK(3, ("cleared tx ring %d\n", old_tx));
738 }
739 old_tx = (old_tx +1) & TX_RING_MOD_MASK;
740 }
741
742 lp->old_tx = old_tx;
743 }
744
745
746 if (netif_queue_stopped(dev)) {
747 /* The ring is no longer full, clear tbusy. */
748 netif_start_queue(dev);
749 netif_wake_queue(dev);
750 }
751
752 if (csr0 & CSR0_RINT) /* Rx interrupt */
753 lance_rx( dev );
754
755 /* Log misc errors. */
756 if (csr0 & CSR0_BABL) lp->stats.tx_errors++; /* Tx babble. */
757 if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */
758 if (csr0 & CSR0_MERR) {
759 DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), "
760 "status %04x.\n", dev->name, csr0 ));
761 /* Restart the chip. */
762 REGA(CSR0) = CSR0_STOP;
763 REGA(CSR3) = CSR3_BSWP;
764 lance_init_ring(dev);
765 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
766 }
767
768
769 /* Clear any other interrupt, and set interrupt enable. */
770 // DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR |
771 // CSR0_IDON | CSR0_INEA;
772
773 REGA(CSR0) = CSR0_INEA;
774
775 if(DREG & (CSR0_RINT | CSR0_TINT)) {
776 DPRINTK(2, ("restarting interrupt, csr0=%#04x\n", DREG));
777 goto still_more;
778 }
779
780 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n",
781 dev->name, DREG ));
782 in_interrupt = 0;
783 return IRQ_HANDLED;
784 }
785
786 /* get packet, toss into skbuff */
787 static int lance_rx( struct net_device *dev )
788 {
789 struct lance_private *lp = netdev_priv(dev);
790 int entry = lp->new_rx;
791
792 /* If we own the next entry, it's a new packet. Send it up. */
793 while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
794 struct lance_rx_head *head = &(MEM->rx_head[entry]);
795 int status = head->flag;
796
797 if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */
798 /* There is a tricky error noted by John Murphy,
799 <murf@perftech.com> to Russ Nelson: Even with
800 full-sized buffers it's possible for a jabber packet to use two
801 buffers, with only the last correctly noting the error. */
802 if (status & RMD1_ENP) /* Only count a general error at the */
803 lp->stats.rx_errors++; /* end of a packet.*/
804 if (status & RMD1_FRAM) lp->stats.rx_frame_errors++;
805 if (status & RMD1_OFLO) lp->stats.rx_over_errors++;
806 if (status & RMD1_CRC) lp->stats.rx_crc_errors++;
807 if (status & RMD1_BUFF) lp->stats.rx_fifo_errors++;
808 head->flag &= (RMD1_ENP|RMD1_STP);
809 } else {
810 /* Malloc up new buffer, compatible with net-3. */
811 // short pkt_len = head->msg_length;// & 0xfff;
812 short pkt_len = (head->msg_length & 0xfff) - 4;
813 struct sk_buff *skb;
814
815 if (pkt_len < 60) {
816 printk( "%s: Runt packet!\n", dev->name );
817 lp->stats.rx_errors++;
818 }
819 else {
820 skb = dev_alloc_skb( pkt_len+2 );
821 if (skb == NULL) {
822 DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n",
823 dev->name ));
824
825 lp->stats.rx_dropped++;
826 head->msg_length = 0;
827 head->flag |= RMD1_OWN_CHIP;
828 lp->new_rx = (lp->new_rx+1) &
829 RX_RING_MOD_MASK;
830 }
831
832 #if 0
833 if (lance_debug >= 3) {
834 u_char *data = PKTBUF_ADDR(head), *p;
835 printk( "%s: RX pkt %d type 0x%04x from ", dev->name, entry, ((u_short *)data)[6]);
836 for( p = &data[6], i = 0; i < 6; i++ )
837 printk("%02x%s", *p++, i != 5 ? ":" : "" );
838 printk(" to ");
839 for( p = data, i = 0; i < 6; i++ )
840 printk("%02x%s", *p++, i != 5 ? ":" : "" );
841 printk(" data %02x %02x %02x %02x %02x %02x %02x %02x "
842 "len %d at %08x\n",
843 data[15], data[16], data[17], data[18],
844 data[19], data[20], data[21], data[22],
845 pkt_len, data);
846 }
847 #endif
848 if (lance_debug >= 3) {
849 u_char *data = PKTBUF_ADDR(head);
850 printk( "%s: RX pkt %d type 0x%04x len %d\n ", dev->name, entry, ((u_short *)data)[6], pkt_len);
851 }
852
853
854 skb_reserve( skb, 2 ); /* 16 byte align */
855 skb_put( skb, pkt_len ); /* Make room */
856 skb_copy_to_linear_data(skb,
857 PKTBUF_ADDR(head),
858 pkt_len);
859
860 skb->protocol = eth_type_trans( skb, dev );
861 netif_rx( skb );
862 dev->last_rx = jiffies;
863 lp->stats.rx_packets++;
864 lp->stats.rx_bytes += pkt_len;
865 }
866 }
867
868 // head->buf_length = -PKT_BUF_SZ | 0xf000;
869 head->msg_length = 0;
870 head->flag = RMD1_OWN_CHIP;
871
872 entry = lp->new_rx = (lp->new_rx +1) & RX_RING_MOD_MASK;
873 }
874
875 /* From lance.c (Donald Becker): */
876 /* We should check that at least two ring entries are free.
877 If not, we should free one and mark stats->rx_dropped++. */
878
879 return 0;
880 }
881
882
883 static int lance_close( struct net_device *dev )
884 {
885 struct lance_private *lp = netdev_priv(dev);
886
887 netif_stop_queue(dev);
888
889 AREG = CSR0;
890
891 DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n",
892 dev->name, DREG ));
893
894 /* We stop the LANCE here -- it occasionally polls
895 memory if we don't. */
896 DREG = CSR0_STOP;
897 return 0;
898 }
899
900
901 static struct net_device_stats *lance_get_stats( struct net_device *dev )
902 {
903 struct lance_private *lp = netdev_priv(dev);
904
905 return &lp->stats;
906 }
907
908
909 /* Set or clear the multicast filter for this adaptor.
910 num_addrs == -1 Promiscuous mode, receive all packets
911 num_addrs == 0 Normal mode, clear multicast list
912 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
913 best-effort filtering.
914 */
915
916 /* completely untested on a sun3 */
917 static void set_multicast_list( struct net_device *dev )
918 {
919 struct lance_private *lp = netdev_priv(dev);
920
921 if(netif_queue_stopped(dev))
922 /* Only possible if board is already started */
923 return;
924
925 /* We take the simple way out and always enable promiscuous mode. */
926 DREG = CSR0_STOP; /* Temporarily stop the lance. */
927
928 if (dev->flags & IFF_PROMISC) {
929 /* Log any net taps. */
930 DPRINTK( 3, ( "%s: Promiscuous mode enabled.\n", dev->name ));
931 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
932 } else {
933 short multicast_table[4];
934 int num_addrs = dev->mc_count;
935 int i;
936 /* We don't use the multicast table, but rely on upper-layer
937 * filtering. */
938 memset( multicast_table, (num_addrs == 0) ? 0 : -1,
939 sizeof(multicast_table) );
940 for( i = 0; i < 4; i++ )
941 REGA( CSR8+i ) = multicast_table[i];
942 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
943 }
944
945 /*
946 * Always set BSWP after a STOP as STOP puts it back into
947 * little endian mode.
948 */
949 REGA( CSR3 ) = CSR3_BSWP;
950
951 /* Resume normal operation and reset AREG to CSR0 */
952 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
953 }
954
955
956 #ifdef MODULE
957
958 static struct net_device *sun3lance_dev;
959
960 int __init init_module(void)
961 {
962 sun3lance_dev = sun3lance_probe(-1);
963 if (IS_ERR(sun3lance_dev))
964 return PTR_ERR(sun3lance_dev);
965 return 0;
966 }
967
968 void __exit cleanup_module(void)
969 {
970 unregister_netdev(sun3lance_dev);
971 #ifdef CONFIG_SUN3
972 iounmap((void __iomem *)sun3lance_dev->base_addr);
973 #endif
974 free_netdev(sun3lance_dev);
975 }
976
977 #endif /* MODULE */
978
Software Suspend 2 for Linus's 2.6 head (mirror)