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Complete the renaming to TuxOnIce with function names, vars etc.
[linux-2.6/suspend2-head.git] / drivers / net / tg3.c
blob32e4037dcb50a3ec73961e2021cac643b9f21034
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.78"
68 #define DRV_MODULE_RELDATE "July 11, 2007"
69
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86 #define TG3_TX_TIMEOUT (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST 6
134
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
209 };
210
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
213 static const struct {
214 const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292 };
293
294 static const struct {
295 const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303 };
304
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306 {
307 writel(val, tp->regs + off);
308 }
309
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
311 {
312 return (readl(tp->regs + off));
313 }
314
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316 {
317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
323 }
324
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326 {
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
329 }
330
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
332 {
333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341 }
342
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344 {
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
356 }
357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371 }
372
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374 {
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383 }
384
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
391 {
392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
408 }
409
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411 {
412 tp->write32_mbox(tp, off, val);
413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
416 }
417
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
419 {
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426 }
427
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429 {
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431 }
432
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434 {
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436 }
437
438 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
443
444 #define tw32(reg,val) tp->write32(tp, reg, val)
445 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg) tp->read32(tp, reg)
448
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450 {
451 unsigned long flags;
452
453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
461
462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
467
468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 }
473
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475 {
476 unsigned long flags;
477
478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
488
489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
499 }
500
501 static void tg3_disable_ints(struct tg3 *tp)
502 {
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
506 }
507
508 static inline void tg3_cond_int(struct tg3 *tp)
509 {
510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
516 }
517
518 static void tg3_enable_ints(struct tg3 *tp)
519 {
520 tp->irq_sync = 0;
521 wmb();
522
523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
530 tg3_cond_int(tp);
531 }
532
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
534 {
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551 }
552
553 /* tg3_restart_ints
554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
556 * which reenables interrupts
557 */
558 static void tg3_restart_ints(struct tg3 *tp)
559 {
560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
562 mmiowb();
563
564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
572 }
573
574 static inline void tg3_netif_stop(struct tg3 *tp)
575 {
576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579 }
580
581 static inline void tg3_netif_start(struct tg3 *tp)
582 {
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
591 }
592
593 static void tg3_switch_clocks(struct tg3 *tp)
594 {
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
599 return;
600
601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
620 }
621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
622 }
623
624 #define PHY_BUSY_LOOPS 5000
625
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627 {
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
645
646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673 }
674
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676 {
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
697
698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722 }
723
724 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
725 {
726 u32 phy;
727
728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
729 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
730 return;
731
732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
733 u32 ephy;
734
735 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
736 tg3_writephy(tp, MII_TG3_EPHY_TEST,
737 ephy | MII_TG3_EPHY_SHADOW_EN);
738 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
739 if (enable)
740 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
741 else
742 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
743 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
744 }
745 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
746 }
747 } else {
748 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
749 MII_TG3_AUXCTL_SHDWSEL_MISC;
750 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
751 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
752 if (enable)
753 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
754 else
755 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
756 phy |= MII_TG3_AUXCTL_MISC_WREN;
757 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
758 }
759 }
760 }
761
762 static void tg3_phy_set_wirespeed(struct tg3 *tp)
763 {
764 u32 val;
765
766 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
767 return;
768
769 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
770 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
771 tg3_writephy(tp, MII_TG3_AUX_CTRL,
772 (val | (1 << 15) | (1 << 4)));
773 }
774
775 static int tg3_bmcr_reset(struct tg3 *tp)
776 {
777 u32 phy_control;
778 int limit, err;
779
780 /* OK, reset it, and poll the BMCR_RESET bit until it
781 * clears or we time out.
782 */
783 phy_control = BMCR_RESET;
784 err = tg3_writephy(tp, MII_BMCR, phy_control);
785 if (err != 0)
786 return -EBUSY;
787
788 limit = 5000;
789 while (limit--) {
790 err = tg3_readphy(tp, MII_BMCR, &phy_control);
791 if (err != 0)
792 return -EBUSY;
793
794 if ((phy_control & BMCR_RESET) == 0) {
795 udelay(40);
796 break;
797 }
798 udelay(10);
799 }
800 if (limit <= 0)
801 return -EBUSY;
802
803 return 0;
804 }
805
806 static int tg3_wait_macro_done(struct tg3 *tp)
807 {
808 int limit = 100;
809
810 while (limit--) {
811 u32 tmp32;
812
813 if (!tg3_readphy(tp, 0x16, &tmp32)) {
814 if ((tmp32 & 0x1000) == 0)
815 break;
816 }
817 }
818 if (limit <= 0)
819 return -EBUSY;
820
821 return 0;
822 }
823
824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
825 {
826 static const u32 test_pat[4][6] = {
827 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
828 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
829 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
830 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
831 };
832 int chan;
833
834 for (chan = 0; chan < 4; chan++) {
835 int i;
836
837 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
838 (chan * 0x2000) | 0x0200);
839 tg3_writephy(tp, 0x16, 0x0002);
840
841 for (i = 0; i < 6; i++)
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
843 test_pat[chan][i]);
844
845 tg3_writephy(tp, 0x16, 0x0202);
846 if (tg3_wait_macro_done(tp)) {
847 *resetp = 1;
848 return -EBUSY;
849 }
850
851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
852 (chan * 0x2000) | 0x0200);
853 tg3_writephy(tp, 0x16, 0x0082);
854 if (tg3_wait_macro_done(tp)) {
855 *resetp = 1;
856 return -EBUSY;
857 }
858
859 tg3_writephy(tp, 0x16, 0x0802);
860 if (tg3_wait_macro_done(tp)) {
861 *resetp = 1;
862 return -EBUSY;
863 }
864
865 for (i = 0; i < 6; i += 2) {
866 u32 low, high;
867
868 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
869 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
870 tg3_wait_macro_done(tp)) {
871 *resetp = 1;
872 return -EBUSY;
873 }
874 low &= 0x7fff;
875 high &= 0x000f;
876 if (low != test_pat[chan][i] ||
877 high != test_pat[chan][i+1]) {
878 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
880 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
881
882 return -EBUSY;
883 }
884 }
885 }
886
887 return 0;
888 }
889
890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
891 {
892 int chan;
893
894 for (chan = 0; chan < 4; chan++) {
895 int i;
896
897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
898 (chan * 0x2000) | 0x0200);
899 tg3_writephy(tp, 0x16, 0x0002);
900 for (i = 0; i < 6; i++)
901 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
902 tg3_writephy(tp, 0x16, 0x0202);
903 if (tg3_wait_macro_done(tp))
904 return -EBUSY;
905 }
906
907 return 0;
908 }
909
910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
911 {
912 u32 reg32, phy9_orig;
913 int retries, do_phy_reset, err;
914
915 retries = 10;
916 do_phy_reset = 1;
917 do {
918 if (do_phy_reset) {
919 err = tg3_bmcr_reset(tp);
920 if (err)
921 return err;
922 do_phy_reset = 0;
923 }
924
925 /* Disable transmitter and interrupt. */
926 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
927 continue;
928
929 reg32 |= 0x3000;
930 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
931
932 /* Set full-duplex, 1000 mbps. */
933 tg3_writephy(tp, MII_BMCR,
934 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
935
936 /* Set to master mode. */
937 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
938 continue;
939
940 tg3_writephy(tp, MII_TG3_CTRL,
941 (MII_TG3_CTRL_AS_MASTER |
942 MII_TG3_CTRL_ENABLE_AS_MASTER));
943
944 /* Enable SM_DSP_CLOCK and 6dB. */
945 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
946
947 /* Block the PHY control access. */
948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
950
951 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
952 if (!err)
953 break;
954 } while (--retries);
955
956 err = tg3_phy_reset_chanpat(tp);
957 if (err)
958 return err;
959
960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
962
963 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
964 tg3_writephy(tp, 0x16, 0x0000);
965
966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
968 /* Set Extended packet length bit for jumbo frames */
969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
970 }
971 else {
972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
973 }
974
975 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
976
977 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
978 reg32 &= ~0x3000;
979 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
980 } else if (!err)
981 err = -EBUSY;
982
983 return err;
984 }
985
986 static void tg3_link_report(struct tg3 *);
987
988 /* This will reset the tigon3 PHY if there is no valid
989 * link unless the FORCE argument is non-zero.
990 */
991 static int tg3_phy_reset(struct tg3 *tp)
992 {
993 u32 phy_status;
994 int err;
995
996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
997 u32 val;
998
999 val = tr32(GRC_MISC_CFG);
1000 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1001 udelay(40);
1002 }
1003 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1004 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1005 if (err != 0)
1006 return -EBUSY;
1007
1008 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1009 netif_carrier_off(tp->dev);
1010 tg3_link_report(tp);
1011 }
1012
1013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1016 err = tg3_phy_reset_5703_4_5(tp);
1017 if (err)
1018 return err;
1019 goto out;
1020 }
1021
1022 err = tg3_bmcr_reset(tp);
1023 if (err)
1024 return err;
1025
1026 out:
1027 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1028 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1032 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1034 }
1035 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1036 tg3_writephy(tp, 0x1c, 0x8d68);
1037 tg3_writephy(tp, 0x1c, 0x8d68);
1038 }
1039 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1040 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1041 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1042 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1044 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1045 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1046 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1047 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1048 }
1049 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1050 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1051 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1052 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1053 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1054 tg3_writephy(tp, MII_TG3_TEST1,
1055 MII_TG3_TEST1_TRIM_EN | 0x4);
1056 } else
1057 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1058 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1059 }
1060 /* Set Extended packet length bit (bit 14) on all chips that */
1061 /* support jumbo frames */
1062 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1063 /* Cannot do read-modify-write on 5401 */
1064 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1065 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1066 u32 phy_reg;
1067
1068 /* Set bit 14 with read-modify-write to preserve other bits */
1069 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1070 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1071 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1072 }
1073
1074 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1075 * jumbo frames transmission.
1076 */
1077 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1078 u32 phy_reg;
1079
1080 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1081 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1082 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1083 }
1084
1085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1086 /* adjust output voltage */
1087 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1088 }
1089
1090 tg3_phy_toggle_automdix(tp, 1);
1091 tg3_phy_set_wirespeed(tp);
1092 return 0;
1093 }
1094
1095 static void tg3_frob_aux_power(struct tg3 *tp)
1096 {
1097 struct tg3 *tp_peer = tp;
1098
1099 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1100 return;
1101
1102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1103 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1104 struct net_device *dev_peer;
1105
1106 dev_peer = pci_get_drvdata(tp->pdev_peer);
1107 /* remove_one() may have been run on the peer. */
1108 if (!dev_peer)
1109 tp_peer = tp;
1110 else
1111 tp_peer = netdev_priv(dev_peer);
1112 }
1113
1114 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1115 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1116 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1117 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1121 (GRC_LCLCTRL_GPIO_OE0 |
1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT0 |
1125 GRC_LCLCTRL_GPIO_OUTPUT1),
1126 100);
1127 } else {
1128 u32 no_gpio2;
1129 u32 grc_local_ctrl = 0;
1130
1131 if (tp_peer != tp &&
1132 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1133 return;
1134
1135 /* Workaround to prevent overdrawing Amps. */
1136 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1137 ASIC_REV_5714) {
1138 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140 grc_local_ctrl, 100);
1141 }
1142
1143 /* On 5753 and variants, GPIO2 cannot be used. */
1144 no_gpio2 = tp->nic_sram_data_cfg &
1145 NIC_SRAM_DATA_CFG_NO_GPIO2;
1146
1147 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1148 GRC_LCLCTRL_GPIO_OE1 |
1149 GRC_LCLCTRL_GPIO_OE2 |
1150 GRC_LCLCTRL_GPIO_OUTPUT1 |
1151 GRC_LCLCTRL_GPIO_OUTPUT2;
1152 if (no_gpio2) {
1153 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1154 GRC_LCLCTRL_GPIO_OUTPUT2);
1155 }
1156 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157 grc_local_ctrl, 100);
1158
1159 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1160
1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1162 grc_local_ctrl, 100);
1163
1164 if (!no_gpio2) {
1165 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1166 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1167 grc_local_ctrl, 100);
1168 }
1169 }
1170 } else {
1171 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1172 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1173 if (tp_peer != tp &&
1174 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1175 return;
1176
1177 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1178 (GRC_LCLCTRL_GPIO_OE1 |
1179 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1180
1181 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1182 GRC_LCLCTRL_GPIO_OE1, 100);
1183
1184 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1185 (GRC_LCLCTRL_GPIO_OE1 |
1186 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1187 }
1188 }
1189 }
1190
1191 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1192 {
1193 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1194 return 1;
1195 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1196 if (speed != SPEED_10)
1197 return 1;
1198 } else if (speed == SPEED_10)
1199 return 1;
1200
1201 return 0;
1202 }
1203
1204 static int tg3_setup_phy(struct tg3 *, int);
1205
1206 #define RESET_KIND_SHUTDOWN 0
1207 #define RESET_KIND_INIT 1
1208 #define RESET_KIND_SUSPEND 2
1209
1210 static void tg3_write_sig_post_reset(struct tg3 *, int);
1211 static int tg3_halt_cpu(struct tg3 *, u32);
1212 static int tg3_nvram_lock(struct tg3 *);
1213 static void tg3_nvram_unlock(struct tg3 *);
1214
1215 static void tg3_power_down_phy(struct tg3 *tp)
1216 {
1217 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1219 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1220 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1221
1222 sg_dig_ctrl |=
1223 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1224 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1225 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1226 }
1227 return;
1228 }
1229
1230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1231 u32 val;
1232
1233 tg3_bmcr_reset(tp);
1234 val = tr32(GRC_MISC_CFG);
1235 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1236 udelay(40);
1237 return;
1238 } else {
1239 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1240 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1241 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1242 }
1243
1244 /* The PHY should not be powered down on some chips because
1245 * of bugs.
1246 */
1247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1249 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1250 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1251 return;
1252 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1253 }
1254
1255 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1256 {
1257 u32 misc_host_ctrl;
1258 u16 power_control, power_caps;
1259 int pm = tp->pm_cap;
1260
1261 /* Make sure register accesses (indirect or otherwise)
1262 * will function correctly.
1263 */
1264 pci_write_config_dword(tp->pdev,
1265 TG3PCI_MISC_HOST_CTRL,
1266 tp->misc_host_ctrl);
1267
1268 pci_read_config_word(tp->pdev,
1269 pm + PCI_PM_CTRL,
1270 &power_control);
1271 power_control |= PCI_PM_CTRL_PME_STATUS;
1272 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1273 switch (state) {
1274 case PCI_D0:
1275 power_control |= 0;
1276 pci_write_config_word(tp->pdev,
1277 pm + PCI_PM_CTRL,
1278 power_control);
1279 udelay(100); /* Delay after power state change */
1280
1281 /* Switch out of Vaux if it is a NIC */
1282 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1283 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1284
1285 return 0;
1286
1287 case PCI_D1:
1288 power_control |= 1;
1289 break;
1290
1291 case PCI_D2:
1292 power_control |= 2;
1293 break;
1294
1295 case PCI_D3hot:
1296 power_control |= 3;
1297 break;
1298
1299 default:
1300 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1301 "requested.\n",
1302 tp->dev->name, state);
1303 return -EINVAL;
1304 };
1305
1306 power_control |= PCI_PM_CTRL_PME_ENABLE;
1307
1308 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1309 tw32(TG3PCI_MISC_HOST_CTRL,
1310 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1311
1312 if (tp->link_config.phy_is_low_power == 0) {
1313 tp->link_config.phy_is_low_power = 1;
1314 tp->link_config.orig_speed = tp->link_config.speed;
1315 tp->link_config.orig_duplex = tp->link_config.duplex;
1316 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1317 }
1318
1319 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1320 tp->link_config.speed = SPEED_10;
1321 tp->link_config.duplex = DUPLEX_HALF;
1322 tp->link_config.autoneg = AUTONEG_ENABLE;
1323 tg3_setup_phy(tp, 0);
1324 }
1325
1326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1327 u32 val;
1328
1329 val = tr32(GRC_VCPU_EXT_CTRL);
1330 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1331 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1332 int i;
1333 u32 val;
1334
1335 for (i = 0; i < 200; i++) {
1336 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1337 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1338 break;
1339 msleep(1);
1340 }
1341 }
1342 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1343 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1344 WOL_DRV_STATE_SHUTDOWN |
1345 WOL_DRV_WOL |
1346 WOL_SET_MAGIC_PKT);
1347
1348 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1349
1350 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1351 u32 mac_mode;
1352
1353 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1354 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1355 udelay(40);
1356
1357 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1358 mac_mode = MAC_MODE_PORT_MODE_GMII;
1359 else
1360 mac_mode = MAC_MODE_PORT_MODE_MII;
1361
1362 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1363 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1364 ASIC_REV_5700) {
1365 u32 speed = (tp->tg3_flags &
1366 TG3_FLAG_WOL_SPEED_100MB) ?
1367 SPEED_100 : SPEED_10;
1368 if (tg3_5700_link_polarity(tp, speed))
1369 mac_mode |= MAC_MODE_LINK_POLARITY;
1370 else
1371 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1372 }
1373 } else {
1374 mac_mode = MAC_MODE_PORT_MODE_TBI;
1375 }
1376
1377 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1378 tw32(MAC_LED_CTRL, tp->led_ctrl);
1379
1380 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1381 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1382 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1383
1384 tw32_f(MAC_MODE, mac_mode);
1385 udelay(100);
1386
1387 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1388 udelay(10);
1389 }
1390
1391 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1392 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1393 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1394 u32 base_val;
1395
1396 base_val = tp->pci_clock_ctrl;
1397 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1398 CLOCK_CTRL_TXCLK_DISABLE);
1399
1400 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1401 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1402 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1403 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1404 /* do nothing */
1405 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1406 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1407 u32 newbits1, newbits2;
1408
1409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1411 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1412 CLOCK_CTRL_TXCLK_DISABLE |
1413 CLOCK_CTRL_ALTCLK);
1414 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1415 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1416 newbits1 = CLOCK_CTRL_625_CORE;
1417 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1418 } else {
1419 newbits1 = CLOCK_CTRL_ALTCLK;
1420 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1421 }
1422
1423 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1424 40);
1425
1426 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1427 40);
1428
1429 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1430 u32 newbits3;
1431
1432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1434 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1435 CLOCK_CTRL_TXCLK_DISABLE |
1436 CLOCK_CTRL_44MHZ_CORE);
1437 } else {
1438 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1439 }
1440
1441 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1442 tp->pci_clock_ctrl | newbits3, 40);
1443 }
1444 }
1445
1446 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1447 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1448 tg3_power_down_phy(tp);
1449
1450 tg3_frob_aux_power(tp);
1451
1452 /* Workaround for unstable PLL clock */
1453 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1454 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1455 u32 val = tr32(0x7d00);
1456
1457 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1458 tw32(0x7d00, val);
1459 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1460 int err;
1461
1462 err = tg3_nvram_lock(tp);
1463 tg3_halt_cpu(tp, RX_CPU_BASE);
1464 if (!err)
1465 tg3_nvram_unlock(tp);
1466 }
1467 }
1468
1469 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1470
1471 /* Finally, set the new power state. */
1472 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1473 udelay(100); /* Delay after power state change */
1474
1475 return 0;
1476 }
1477
1478 static void tg3_link_report(struct tg3 *tp)
1479 {
1480 if (!netif_carrier_ok(tp->dev)) {
1481 if (netif_msg_link(tp))
1482 printk(KERN_INFO PFX "%s: Link is down.\n",
1483 tp->dev->name);
1484 } else if (netif_msg_link(tp)) {
1485 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1486 tp->dev->name,
1487 (tp->link_config.active_speed == SPEED_1000 ?
1488 1000 :
1489 (tp->link_config.active_speed == SPEED_100 ?
1490 100 : 10)),
1491 (tp->link_config.active_duplex == DUPLEX_FULL ?
1492 "full" : "half"));
1493
1494 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1495 "%s for RX.\n",
1496 tp->dev->name,
1497 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1498 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1499 }
1500 }
1501
1502 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1503 {
1504 u32 new_tg3_flags = 0;
1505 u32 old_rx_mode = tp->rx_mode;
1506 u32 old_tx_mode = tp->tx_mode;
1507
1508 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1509
1510 /* Convert 1000BaseX flow control bits to 1000BaseT
1511 * bits before resolving flow control.
1512 */
1513 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1514 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1515 ADVERTISE_PAUSE_ASYM);
1516 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1517
1518 if (local_adv & ADVERTISE_1000XPAUSE)
1519 local_adv |= ADVERTISE_PAUSE_CAP;
1520 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1521 local_adv |= ADVERTISE_PAUSE_ASYM;
1522 if (remote_adv & LPA_1000XPAUSE)
1523 remote_adv |= LPA_PAUSE_CAP;
1524 if (remote_adv & LPA_1000XPAUSE_ASYM)
1525 remote_adv |= LPA_PAUSE_ASYM;
1526 }
1527
1528 if (local_adv & ADVERTISE_PAUSE_CAP) {
1529 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1530 if (remote_adv & LPA_PAUSE_CAP)
1531 new_tg3_flags |=
1532 (TG3_FLAG_RX_PAUSE |
1533 TG3_FLAG_TX_PAUSE);
1534 else if (remote_adv & LPA_PAUSE_ASYM)
1535 new_tg3_flags |=
1536 (TG3_FLAG_RX_PAUSE);
1537 } else {
1538 if (remote_adv & LPA_PAUSE_CAP)
1539 new_tg3_flags |=
1540 (TG3_FLAG_RX_PAUSE |
1541 TG3_FLAG_TX_PAUSE);
1542 }
1543 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1544 if ((remote_adv & LPA_PAUSE_CAP) &&
1545 (remote_adv & LPA_PAUSE_ASYM))
1546 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1547 }
1548
1549 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1550 tp->tg3_flags |= new_tg3_flags;
1551 } else {
1552 new_tg3_flags = tp->tg3_flags;
1553 }
1554
1555 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1556 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1557 else
1558 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1559
1560 if (old_rx_mode != tp->rx_mode) {
1561 tw32_f(MAC_RX_MODE, tp->rx_mode);
1562 }
1563
1564 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1565 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1566 else
1567 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1568
1569 if (old_tx_mode != tp->tx_mode) {
1570 tw32_f(MAC_TX_MODE, tp->tx_mode);
1571 }
1572 }
1573
1574 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1575 {
1576 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1577 case MII_TG3_AUX_STAT_10HALF:
1578 *speed = SPEED_10;
1579 *duplex = DUPLEX_HALF;
1580 break;
1581
1582 case MII_TG3_AUX_STAT_10FULL:
1583 *speed = SPEED_10;
1584 *duplex = DUPLEX_FULL;
1585 break;
1586
1587 case MII_TG3_AUX_STAT_100HALF:
1588 *speed = SPEED_100;
1589 *duplex = DUPLEX_HALF;
1590 break;
1591
1592 case MII_TG3_AUX_STAT_100FULL:
1593 *speed = SPEED_100;
1594 *duplex = DUPLEX_FULL;
1595 break;
1596
1597 case MII_TG3_AUX_STAT_1000HALF:
1598 *speed = SPEED_1000;
1599 *duplex = DUPLEX_HALF;
1600 break;
1601
1602 case MII_TG3_AUX_STAT_1000FULL:
1603 *speed = SPEED_1000;
1604 *duplex = DUPLEX_FULL;
1605 break;
1606
1607 default:
1608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1609 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1610 SPEED_10;
1611 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1612 DUPLEX_HALF;
1613 break;
1614 }
1615 *speed = SPEED_INVALID;
1616 *duplex = DUPLEX_INVALID;
1617 break;
1618 };
1619 }
1620
1621 static void tg3_phy_copper_begin(struct tg3 *tp)
1622 {
1623 u32 new_adv;
1624 int i;
1625
1626 if (tp->link_config.phy_is_low_power) {
1627 /* Entering low power mode. Disable gigabit and
1628 * 100baseT advertisements.
1629 */
1630 tg3_writephy(tp, MII_TG3_CTRL, 0);
1631
1632 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1633 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1634 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1635 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1636
1637 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1638 } else if (tp->link_config.speed == SPEED_INVALID) {
1639 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1640 tp->link_config.advertising &=
1641 ~(ADVERTISED_1000baseT_Half |
1642 ADVERTISED_1000baseT_Full);
1643
1644 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1645 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1646 new_adv |= ADVERTISE_10HALF;
1647 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1648 new_adv |= ADVERTISE_10FULL;
1649 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1650 new_adv |= ADVERTISE_100HALF;
1651 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1652 new_adv |= ADVERTISE_100FULL;
1653 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1654
1655 if (tp->link_config.advertising &
1656 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1657 new_adv = 0;
1658 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1659 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1660 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1661 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1662 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1663 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1664 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1665 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1666 MII_TG3_CTRL_ENABLE_AS_MASTER);
1667 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1668 } else {
1669 tg3_writephy(tp, MII_TG3_CTRL, 0);
1670 }
1671 } else {
1672 /* Asking for a specific link mode. */
1673 if (tp->link_config.speed == SPEED_1000) {
1674 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1675 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1676
1677 if (tp->link_config.duplex == DUPLEX_FULL)
1678 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1679 else
1680 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1681 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1682 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1683 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1684 MII_TG3_CTRL_ENABLE_AS_MASTER);
1685 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1686 } else {
1687 tg3_writephy(tp, MII_TG3_CTRL, 0);
1688
1689 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1690 if (tp->link_config.speed == SPEED_100) {
1691 if (tp->link_config.duplex == DUPLEX_FULL)
1692 new_adv |= ADVERTISE_100FULL;
1693 else
1694 new_adv |= ADVERTISE_100HALF;
1695 } else {
1696 if (tp->link_config.duplex == DUPLEX_FULL)
1697 new_adv |= ADVERTISE_10FULL;
1698 else
1699 new_adv |= ADVERTISE_10HALF;
1700 }
1701 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1702 }
1703 }
1704
1705 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1706 tp->link_config.speed != SPEED_INVALID) {
1707 u32 bmcr, orig_bmcr;
1708
1709 tp->link_config.active_speed = tp->link_config.speed;
1710 tp->link_config.active_duplex = tp->link_config.duplex;
1711
1712 bmcr = 0;
1713 switch (tp->link_config.speed) {
1714 default:
1715 case SPEED_10:
1716 break;
1717
1718 case SPEED_100:
1719 bmcr |= BMCR_SPEED100;
1720 break;
1721
1722 case SPEED_1000:
1723 bmcr |= TG3_BMCR_SPEED1000;
1724 break;
1725 };
1726
1727 if (tp->link_config.duplex == DUPLEX_FULL)
1728 bmcr |= BMCR_FULLDPLX;
1729
1730 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1731 (bmcr != orig_bmcr)) {
1732 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1733 for (i = 0; i < 1500; i++) {
1734 u32 tmp;
1735
1736 udelay(10);
1737 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1738 tg3_readphy(tp, MII_BMSR, &tmp))
1739 continue;
1740 if (!(tmp & BMSR_LSTATUS)) {
1741 udelay(40);
1742 break;
1743 }
1744 }
1745 tg3_writephy(tp, MII_BMCR, bmcr);
1746 udelay(40);
1747 }
1748 } else {
1749 tg3_writephy(tp, MII_BMCR,
1750 BMCR_ANENABLE | BMCR_ANRESTART);
1751 }
1752 }
1753
1754 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1755 {
1756 int err;
1757
1758 /* Turn off tap power management. */
1759 /* Set Extended packet length bit */
1760 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1761
1762 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1763 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1764
1765 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1766 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1767
1768 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1769 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1770
1771 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1772 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1773
1774 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1775 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1776
1777 udelay(40);
1778
1779 return err;
1780 }
1781
1782 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1783 {
1784 u32 adv_reg, all_mask = 0;
1785
1786 if (mask & ADVERTISED_10baseT_Half)
1787 all_mask |= ADVERTISE_10HALF;
1788 if (mask & ADVERTISED_10baseT_Full)
1789 all_mask |= ADVERTISE_10FULL;
1790 if (mask & ADVERTISED_100baseT_Half)
1791 all_mask |= ADVERTISE_100HALF;
1792 if (mask & ADVERTISED_100baseT_Full)
1793 all_mask |= ADVERTISE_100FULL;
1794
1795 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1796 return 0;
1797
1798 if ((adv_reg & all_mask) != all_mask)
1799 return 0;
1800 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1801 u32 tg3_ctrl;
1802
1803 all_mask = 0;
1804 if (mask & ADVERTISED_1000baseT_Half)
1805 all_mask |= ADVERTISE_1000HALF;
1806 if (mask & ADVERTISED_1000baseT_Full)
1807 all_mask |= ADVERTISE_1000FULL;
1808
1809 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1810 return 0;
1811
1812 if ((tg3_ctrl & all_mask) != all_mask)
1813 return 0;
1814 }
1815 return 1;
1816 }
1817
1818 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1819 {
1820 int current_link_up;
1821 u32 bmsr, dummy;
1822 u16 current_speed;
1823 u8 current_duplex;
1824 int i, err;
1825
1826 tw32(MAC_EVENT, 0);
1827
1828 tw32_f(MAC_STATUS,
1829 (MAC_STATUS_SYNC_CHANGED |
1830 MAC_STATUS_CFG_CHANGED |
1831 MAC_STATUS_MI_COMPLETION |
1832 MAC_STATUS_LNKSTATE_CHANGED));
1833 udelay(40);
1834
1835 tp->mi_mode = MAC_MI_MODE_BASE;
1836 tw32_f(MAC_MI_MODE, tp->mi_mode);
1837 udelay(80);
1838
1839 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1840
1841 /* Some third-party PHYs need to be reset on link going
1842 * down.
1843 */
1844 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1847 netif_carrier_ok(tp->dev)) {
1848 tg3_readphy(tp, MII_BMSR, &bmsr);
1849 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850 !(bmsr & BMSR_LSTATUS))
1851 force_reset = 1;
1852 }
1853 if (force_reset)
1854 tg3_phy_reset(tp);
1855
1856 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1857 tg3_readphy(tp, MII_BMSR, &bmsr);
1858 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1859 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1860 bmsr = 0;
1861
1862 if (!(bmsr & BMSR_LSTATUS)) {
1863 err = tg3_init_5401phy_dsp(tp);
1864 if (err)
1865 return err;
1866
1867 tg3_readphy(tp, MII_BMSR, &bmsr);
1868 for (i = 0; i < 1000; i++) {
1869 udelay(10);
1870 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1871 (bmsr & BMSR_LSTATUS)) {
1872 udelay(40);
1873 break;
1874 }
1875 }
1876
1877 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1878 !(bmsr & BMSR_LSTATUS) &&
1879 tp->link_config.active_speed == SPEED_1000) {
1880 err = tg3_phy_reset(tp);
1881 if (!err)
1882 err = tg3_init_5401phy_dsp(tp);
1883 if (err)
1884 return err;
1885 }
1886 }
1887 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1888 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1889 /* 5701 {A0,B0} CRC bug workaround */
1890 tg3_writephy(tp, 0x15, 0x0a75);
1891 tg3_writephy(tp, 0x1c, 0x8c68);
1892 tg3_writephy(tp, 0x1c, 0x8d68);
1893 tg3_writephy(tp, 0x1c, 0x8c68);
1894 }
1895
1896 /* Clear pending interrupts... */
1897 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1898 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1899
1900 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1901 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1902 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1903 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1904
1905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1907 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1908 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1909 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1910 else
1911 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1912 }
1913
1914 current_link_up = 0;
1915 current_speed = SPEED_INVALID;
1916 current_duplex = DUPLEX_INVALID;
1917
1918 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1919 u32 val;
1920
1921 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1922 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1923 if (!(val & (1 << 10))) {
1924 val |= (1 << 10);
1925 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1926 goto relink;
1927 }
1928 }
1929
1930 bmsr = 0;
1931 for (i = 0; i < 100; i++) {
1932 tg3_readphy(tp, MII_BMSR, &bmsr);
1933 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1934 (bmsr & BMSR_LSTATUS))
1935 break;
1936 udelay(40);
1937 }
1938
1939 if (bmsr & BMSR_LSTATUS) {
1940 u32 aux_stat, bmcr;
1941
1942 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1943 for (i = 0; i < 2000; i++) {
1944 udelay(10);
1945 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1946 aux_stat)
1947 break;
1948 }
1949
1950 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1951 &current_speed,
1952 &current_duplex);
1953
1954 bmcr = 0;
1955 for (i = 0; i < 200; i++) {
1956 tg3_readphy(tp, MII_BMCR, &bmcr);
1957 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1958 continue;
1959 if (bmcr && bmcr != 0x7fff)
1960 break;
1961 udelay(10);
1962 }
1963
1964 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1965 if (bmcr & BMCR_ANENABLE) {
1966 current_link_up = 1;
1967
1968 /* Force autoneg restart if we are exiting
1969 * low power mode.
1970 */
1971 if (!tg3_copper_is_advertising_all(tp,
1972 tp->link_config.advertising))
1973 current_link_up = 0;
1974 } else {
1975 current_link_up = 0;
1976 }
1977 } else {
1978 if (!(bmcr & BMCR_ANENABLE) &&
1979 tp->link_config.speed == current_speed &&
1980 tp->link_config.duplex == current_duplex) {
1981 current_link_up = 1;
1982 } else {
1983 current_link_up = 0;
1984 }
1985 }
1986
1987 tp->link_config.active_speed = current_speed;
1988 tp->link_config.active_duplex = current_duplex;
1989 }
1990
1991 if (current_link_up == 1 &&
1992 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1993 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1994 u32 local_adv, remote_adv;
1995
1996 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1997 local_adv = 0;
1998 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1999
2000 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2001 remote_adv = 0;
2002
2003 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2004
2005 /* If we are not advertising full pause capability,
2006 * something is wrong. Bring the link down and reconfigure.
2007 */
2008 if (local_adv != ADVERTISE_PAUSE_CAP) {
2009 current_link_up = 0;
2010 } else {
2011 tg3_setup_flow_control(tp, local_adv, remote_adv);
2012 }
2013 }
2014 relink:
2015 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2016 u32 tmp;
2017
2018 tg3_phy_copper_begin(tp);
2019
2020 tg3_readphy(tp, MII_BMSR, &tmp);
2021 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2022 (tmp & BMSR_LSTATUS))
2023 current_link_up = 1;
2024 }
2025
2026 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2027 if (current_link_up == 1) {
2028 if (tp->link_config.active_speed == SPEED_100 ||
2029 tp->link_config.active_speed == SPEED_10)
2030 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2031 else
2032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2033 } else
2034 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2035
2036 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2037 if (tp->link_config.active_duplex == DUPLEX_HALF)
2038 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2039
2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2041 if (current_link_up == 1 &&
2042 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2043 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2044 else
2045 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2046 }
2047
2048 /* ??? Without this setting Netgear GA302T PHY does not
2049 * ??? send/receive packets...
2050 */
2051 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2052 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2053 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2054 tw32_f(MAC_MI_MODE, tp->mi_mode);
2055 udelay(80);
2056 }
2057
2058 tw32_f(MAC_MODE, tp->mac_mode);
2059 udelay(40);
2060
2061 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2062 /* Polled via timer. */
2063 tw32_f(MAC_EVENT, 0);
2064 } else {
2065 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2066 }
2067 udelay(40);
2068
2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2070 current_link_up == 1 &&
2071 tp->link_config.active_speed == SPEED_1000 &&
2072 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2073 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2074 udelay(120);
2075 tw32_f(MAC_STATUS,
2076 (MAC_STATUS_SYNC_CHANGED |
2077 MAC_STATUS_CFG_CHANGED));
2078 udelay(40);
2079 tg3_write_mem(tp,
2080 NIC_SRAM_FIRMWARE_MBOX,
2081 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2082 }
2083
2084 if (current_link_up != netif_carrier_ok(tp->dev)) {
2085 if (current_link_up)
2086 netif_carrier_on(tp->dev);
2087 else
2088 netif_carrier_off(tp->dev);
2089 tg3_link_report(tp);
2090 }
2091
2092 return 0;
2093 }
2094
2095 struct tg3_fiber_aneginfo {
2096 int state;
2097 #define ANEG_STATE_UNKNOWN 0
2098 #define ANEG_STATE_AN_ENABLE 1
2099 #define ANEG_STATE_RESTART_INIT 2
2100 #define ANEG_STATE_RESTART 3
2101 #define ANEG_STATE_DISABLE_LINK_OK 4
2102 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2103 #define ANEG_STATE_ABILITY_DETECT 6
2104 #define ANEG_STATE_ACK_DETECT_INIT 7
2105 #define ANEG_STATE_ACK_DETECT 8
2106 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2107 #define ANEG_STATE_COMPLETE_ACK 10
2108 #define ANEG_STATE_IDLE_DETECT_INIT 11
2109 #define ANEG_STATE_IDLE_DETECT 12
2110 #define ANEG_STATE_LINK_OK 13
2111 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2112 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2113
2114 u32 flags;
2115 #define MR_AN_ENABLE 0x00000001
2116 #define MR_RESTART_AN 0x00000002
2117 #define MR_AN_COMPLETE 0x00000004
2118 #define MR_PAGE_RX 0x00000008
2119 #define MR_NP_LOADED 0x00000010
2120 #define MR_TOGGLE_TX 0x00000020
2121 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2122 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2123 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2124 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2125 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2126 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2127 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2128 #define MR_TOGGLE_RX 0x00002000
2129 #define MR_NP_RX 0x00004000
2130
2131 #define MR_LINK_OK 0x80000000
2132
2133 unsigned long link_time, cur_time;
2134
2135 u32 ability_match_cfg;
2136 int ability_match_count;
2137
2138 char ability_match, idle_match, ack_match;
2139
2140 u32 txconfig, rxconfig;
2141 #define ANEG_CFG_NP 0x00000080
2142 #define ANEG_CFG_ACK 0x00000040
2143 #define ANEG_CFG_RF2 0x00000020
2144 #define ANEG_CFG_RF1 0x00000010
2145 #define ANEG_CFG_PS2 0x00000001
2146 #define ANEG_CFG_PS1 0x00008000
2147 #define ANEG_CFG_HD 0x00004000
2148 #define ANEG_CFG_FD 0x00002000
2149 #define ANEG_CFG_INVAL 0x00001f06
2150
2151 };
2152 #define ANEG_OK 0
2153 #define ANEG_DONE 1
2154 #define ANEG_TIMER_ENAB 2
2155 #define ANEG_FAILED -1
2156
2157 #define ANEG_STATE_SETTLE_TIME 10000
2158
2159 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2160 struct tg3_fiber_aneginfo *ap)
2161 {
2162 unsigned long delta;
2163 u32 rx_cfg_reg;
2164 int ret;
2165
2166 if (ap->state == ANEG_STATE_UNKNOWN) {
2167 ap->rxconfig = 0;
2168 ap->link_time = 0;
2169 ap->cur_time = 0;
2170 ap->ability_match_cfg = 0;
2171 ap->ability_match_count = 0;
2172 ap->ability_match = 0;
2173 ap->idle_match = 0;
2174 ap->ack_match = 0;
2175 }
2176 ap->cur_time++;
2177
2178 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2179 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2180
2181 if (rx_cfg_reg != ap->ability_match_cfg) {
2182 ap->ability_match_cfg = rx_cfg_reg;
2183 ap->ability_match = 0;
2184 ap->ability_match_count = 0;
2185 } else {
2186 if (++ap->ability_match_count > 1) {
2187 ap->ability_match = 1;
2188 ap->ability_match_cfg = rx_cfg_reg;
2189 }
2190 }
2191 if (rx_cfg_reg & ANEG_CFG_ACK)
2192 ap->ack_match = 1;
2193 else
2194 ap->ack_match = 0;
2195
2196 ap->idle_match = 0;
2197 } else {
2198 ap->idle_match = 1;
2199 ap->ability_match_cfg = 0;
2200 ap->ability_match_count = 0;
2201 ap->ability_match = 0;
2202 ap->ack_match = 0;
2203
2204 rx_cfg_reg = 0;
2205 }
2206
2207 ap->rxconfig = rx_cfg_reg;
2208 ret = ANEG_OK;
2209
2210 switch(ap->state) {
2211 case ANEG_STATE_UNKNOWN:
2212 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2213 ap->state = ANEG_STATE_AN_ENABLE;
2214
2215 /* fallthru */
2216 case ANEG_STATE_AN_ENABLE:
2217 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2218 if (ap->flags & MR_AN_ENABLE) {
2219 ap->link_time = 0;
2220 ap->cur_time = 0;
2221 ap->ability_match_cfg = 0;
2222 ap->ability_match_count = 0;
2223 ap->ability_match = 0;
2224 ap->idle_match = 0;
2225 ap->ack_match = 0;
2226
2227 ap->state = ANEG_STATE_RESTART_INIT;
2228 } else {
2229 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2230 }
2231 break;
2232
2233 case ANEG_STATE_RESTART_INIT:
2234 ap->link_time = ap->cur_time;
2235 ap->flags &= ~(MR_NP_LOADED);
2236 ap->txconfig = 0;
2237 tw32(MAC_TX_AUTO_NEG, 0);
2238 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2239 tw32_f(MAC_MODE, tp->mac_mode);
2240 udelay(40);
2241
2242 ret = ANEG_TIMER_ENAB;
2243 ap->state = ANEG_STATE_RESTART;
2244
2245 /* fallthru */
2246 case ANEG_STATE_RESTART:
2247 delta = ap->cur_time - ap->link_time;
2248 if (delta > ANEG_STATE_SETTLE_TIME) {
2249 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2250 } else {
2251 ret = ANEG_TIMER_ENAB;
2252 }
2253 break;
2254
2255 case ANEG_STATE_DISABLE_LINK_OK:
2256 ret = ANEG_DONE;
2257 break;
2258
2259 case ANEG_STATE_ABILITY_DETECT_INIT:
2260 ap->flags &= ~(MR_TOGGLE_TX);
2261 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2262 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2263 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2264 tw32_f(MAC_MODE, tp->mac_mode);
2265 udelay(40);
2266
2267 ap->state = ANEG_STATE_ABILITY_DETECT;
2268 break;
2269
2270 case ANEG_STATE_ABILITY_DETECT:
2271 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2272 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2273 }
2274 break;
2275
2276 case ANEG_STATE_ACK_DETECT_INIT:
2277 ap->txconfig |= ANEG_CFG_ACK;
2278 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2279 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2280 tw32_f(MAC_MODE, tp->mac_mode);
2281 udelay(40);
2282
2283 ap->state = ANEG_STATE_ACK_DETECT;
2284
2285 /* fallthru */
2286 case ANEG_STATE_ACK_DETECT:
2287 if (ap->ack_match != 0) {
2288 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2289 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2290 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2291 } else {
2292 ap->state = ANEG_STATE_AN_ENABLE;
2293 }
2294 } else if (ap->ability_match != 0 &&
2295 ap->rxconfig == 0) {
2296 ap->state = ANEG_STATE_AN_ENABLE;
2297 }
2298 break;
2299
2300 case ANEG_STATE_COMPLETE_ACK_INIT:
2301 if (ap->rxconfig & ANEG_CFG_INVAL) {
2302 ret = ANEG_FAILED;
2303 break;
2304 }
2305 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2306 MR_LP_ADV_HALF_DUPLEX |
2307 MR_LP_ADV_SYM_PAUSE |
2308 MR_LP_ADV_ASYM_PAUSE |
2309 MR_LP_ADV_REMOTE_FAULT1 |
2310 MR_LP_ADV_REMOTE_FAULT2 |
2311 MR_LP_ADV_NEXT_PAGE |
2312 MR_TOGGLE_RX |
2313 MR_NP_RX);
2314 if (ap->rxconfig & ANEG_CFG_FD)
2315 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2316 if (ap->rxconfig & ANEG_CFG_HD)
2317 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2318 if (ap->rxconfig & ANEG_CFG_PS1)
2319 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2320 if (ap->rxconfig & ANEG_CFG_PS2)
2321 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2322 if (ap->rxconfig & ANEG_CFG_RF1)
2323 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2324 if (ap->rxconfig & ANEG_CFG_RF2)
2325 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2326 if (ap->rxconfig & ANEG_CFG_NP)
2327 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2328
2329 ap->link_time = ap->cur_time;
2330
2331 ap->flags ^= (MR_TOGGLE_TX);
2332 if (ap->rxconfig & 0x0008)
2333 ap->flags |= MR_TOGGLE_RX;
2334 if (ap->rxconfig & ANEG_CFG_NP)
2335 ap->flags |= MR_NP_RX;
2336 ap->flags |= MR_PAGE_RX;
2337
2338 ap->state = ANEG_STATE_COMPLETE_ACK;
2339 ret = ANEG_TIMER_ENAB;
2340 break;
2341
2342 case ANEG_STATE_COMPLETE_ACK:
2343 if (ap->ability_match != 0 &&
2344 ap->rxconfig == 0) {
2345 ap->state = ANEG_STATE_AN_ENABLE;
2346 break;
2347 }
2348 delta = ap->cur_time - ap->link_time;
2349 if (delta > ANEG_STATE_SETTLE_TIME) {
2350 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2352 } else {
2353 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2354 !(ap->flags & MR_NP_RX)) {
2355 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2356 } else {
2357 ret = ANEG_FAILED;
2358 }
2359 }
2360 }
2361 break;
2362
2363 case ANEG_STATE_IDLE_DETECT_INIT:
2364 ap->link_time = ap->cur_time;
2365 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2366 tw32_f(MAC_MODE, tp->mac_mode);
2367 udelay(40);
2368
2369 ap->state = ANEG_STATE_IDLE_DETECT;
2370 ret = ANEG_TIMER_ENAB;
2371 break;
2372
2373 case ANEG_STATE_IDLE_DETECT:
2374 if (ap->ability_match != 0 &&
2375 ap->rxconfig == 0) {
2376 ap->state = ANEG_STATE_AN_ENABLE;
2377 break;
2378 }
2379 delta = ap->cur_time - ap->link_time;
2380 if (delta > ANEG_STATE_SETTLE_TIME) {
2381 /* XXX another gem from the Broadcom driver :( */
2382 ap->state = ANEG_STATE_LINK_OK;
2383 }
2384 break;
2385
2386 case ANEG_STATE_LINK_OK:
2387 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2388 ret = ANEG_DONE;
2389 break;
2390
2391 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2392 /* ??? unimplemented */
2393 break;
2394
2395 case ANEG_STATE_NEXT_PAGE_WAIT:
2396 /* ??? unimplemented */
2397 break;
2398
2399 default:
2400 ret = ANEG_FAILED;
2401 break;
2402 };
2403
2404 return ret;
2405 }
2406
2407 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2408 {
2409 int res = 0;
2410 struct tg3_fiber_aneginfo aninfo;
2411 int status = ANEG_FAILED;
2412 unsigned int tick;
2413 u32 tmp;
2414
2415 tw32_f(MAC_TX_AUTO_NEG, 0);
2416
2417 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2418 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2419 udelay(40);
2420
2421 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2422 udelay(40);
2423
2424 memset(&aninfo, 0, sizeof(aninfo));
2425 aninfo.flags |= MR_AN_ENABLE;
2426 aninfo.state = ANEG_STATE_UNKNOWN;
2427 aninfo.cur_time = 0;
2428 tick = 0;
2429 while (++tick < 195000) {
2430 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2431 if (status == ANEG_DONE || status == ANEG_FAILED)
2432 break;
2433
2434 udelay(1);
2435 }
2436
2437 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2438 tw32_f(MAC_MODE, tp->mac_mode);
2439 udelay(40);
2440
2441 *flags = aninfo.flags;
2442
2443 if (status == ANEG_DONE &&
2444 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2445 MR_LP_ADV_FULL_DUPLEX)))
2446 res = 1;
2447
2448 return res;
2449 }
2450
2451 static void tg3_init_bcm8002(struct tg3 *tp)
2452 {
2453 u32 mac_status = tr32(MAC_STATUS);
2454 int i;
2455
2456 /* Reset when initting first time or we have a link. */
2457 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2458 !(mac_status & MAC_STATUS_PCS_SYNCED))
2459 return;
2460
2461 /* Set PLL lock range. */
2462 tg3_writephy(tp, 0x16, 0x8007);
2463
2464 /* SW reset */
2465 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2466
2467 /* Wait for reset to complete. */
2468 /* XXX schedule_timeout() ... */
2469 for (i = 0; i < 500; i++)
2470 udelay(10);
2471
2472 /* Config mode; select PMA/Ch 1 regs. */
2473 tg3_writephy(tp, 0x10, 0x8411);
2474
2475 /* Enable auto-lock and comdet, select txclk for tx. */
2476 tg3_writephy(tp, 0x11, 0x0a10);
2477
2478 tg3_writephy(tp, 0x18, 0x00a0);
2479 tg3_writephy(tp, 0x16, 0x41ff);
2480
2481 /* Assert and deassert POR. */
2482 tg3_writephy(tp, 0x13, 0x0400);
2483 udelay(40);
2484 tg3_writephy(tp, 0x13, 0x0000);
2485
2486 tg3_writephy(tp, 0x11, 0x0a50);
2487 udelay(40);
2488 tg3_writephy(tp, 0x11, 0x0a10);
2489
2490 /* Wait for signal to stabilize */
2491 /* XXX schedule_timeout() ... */
2492 for (i = 0; i < 15000; i++)
2493 udelay(10);
2494
2495 /* Deselect the channel register so we can read the PHYID
2496 * later.
2497 */
2498 tg3_writephy(tp, 0x10, 0x8011);
2499 }
2500
2501 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2502 {
2503 u32 sg_dig_ctrl, sg_dig_status;
2504 u32 serdes_cfg, expected_sg_dig_ctrl;
2505 int workaround, port_a;
2506 int current_link_up;
2507
2508 serdes_cfg = 0;
2509 expected_sg_dig_ctrl = 0;
2510 workaround = 0;
2511 port_a = 1;
2512 current_link_up = 0;
2513
2514 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2515 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2516 workaround = 1;
2517 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2518 port_a = 0;
2519
2520 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2521 /* preserve bits 20-23 for voltage regulator */
2522 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2523 }
2524
2525 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2526
2527 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2528 if (sg_dig_ctrl & (1 << 31)) {
2529 if (workaround) {
2530 u32 val = serdes_cfg;
2531
2532 if (port_a)
2533 val |= 0xc010000;
2534 else
2535 val |= 0x4010000;
2536 tw32_f(MAC_SERDES_CFG, val);
2537 }
2538 tw32_f(SG_DIG_CTRL, 0x01388400);
2539 }
2540 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2541 tg3_setup_flow_control(tp, 0, 0);
2542 current_link_up = 1;
2543 }
2544 goto out;
2545 }
2546
2547 /* Want auto-negotiation. */
2548 expected_sg_dig_ctrl = 0x81388400;
2549
2550 /* Pause capability */
2551 expected_sg_dig_ctrl |= (1 << 11);
2552
2553 /* Asymettric pause */
2554 expected_sg_dig_ctrl |= (1 << 12);
2555
2556 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2557 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2558 tp->serdes_counter &&
2559 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2560 MAC_STATUS_RCVD_CFG)) ==
2561 MAC_STATUS_PCS_SYNCED)) {
2562 tp->serdes_counter--;
2563 current_link_up = 1;
2564 goto out;
2565 }
2566 restart_autoneg:
2567 if (workaround)
2568 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2569 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2570 udelay(5);
2571 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2572
2573 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2574 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2575 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2576 MAC_STATUS_SIGNAL_DET)) {
2577 sg_dig_status = tr32(SG_DIG_STATUS);
2578 mac_status = tr32(MAC_STATUS);
2579
2580 if ((sg_dig_status & (1 << 1)) &&
2581 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2582 u32 local_adv, remote_adv;
2583
2584 local_adv = ADVERTISE_PAUSE_CAP;
2585 remote_adv = 0;
2586 if (sg_dig_status & (1 << 19))
2587 remote_adv |= LPA_PAUSE_CAP;
2588 if (sg_dig_status & (1 << 20))
2589 remote_adv |= LPA_PAUSE_ASYM;
2590
2591 tg3_setup_flow_control(tp, local_adv, remote_adv);
2592 current_link_up = 1;
2593 tp->serdes_counter = 0;
2594 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2595 } else if (!(sg_dig_status & (1 << 1))) {
2596 if (tp->serdes_counter)
2597 tp->serdes_counter--;
2598 else {
2599 if (workaround) {
2600 u32 val = serdes_cfg;
2601
2602 if (port_a)
2603 val |= 0xc010000;
2604 else
2605 val |= 0x4010000;
2606
2607 tw32_f(MAC_SERDES_CFG, val);
2608 }
2609
2610 tw32_f(SG_DIG_CTRL, 0x01388400);
2611 udelay(40);
2612
2613 /* Link parallel detection - link is up */
2614 /* only if we have PCS_SYNC and not */
2615 /* receiving config code words */
2616 mac_status = tr32(MAC_STATUS);
2617 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2618 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2619 tg3_setup_flow_control(tp, 0, 0);
2620 current_link_up = 1;
2621 tp->tg3_flags2 |=
2622 TG3_FLG2_PARALLEL_DETECT;
2623 tp->serdes_counter =
2624 SERDES_PARALLEL_DET_TIMEOUT;
2625 } else
2626 goto restart_autoneg;
2627 }
2628 }
2629 } else {
2630 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2631 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2632 }
2633
2634 out:
2635 return current_link_up;
2636 }
2637
2638 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2639 {
2640 int current_link_up = 0;
2641
2642 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2643 goto out;
2644
2645 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2646 u32 flags;
2647 int i;
2648
2649 if (fiber_autoneg(tp, &flags)) {
2650 u32 local_adv, remote_adv;
2651
2652 local_adv = ADVERTISE_PAUSE_CAP;
2653 remote_adv = 0;
2654 if (flags & MR_LP_ADV_SYM_PAUSE)
2655 remote_adv |= LPA_PAUSE_CAP;
2656 if (flags & MR_LP_ADV_ASYM_PAUSE)
2657 remote_adv |= LPA_PAUSE_ASYM;
2658
2659 tg3_setup_flow_control(tp, local_adv, remote_adv);
2660
2661 current_link_up = 1;
2662 }
2663 for (i = 0; i < 30; i++) {
2664 udelay(20);
2665 tw32_f(MAC_STATUS,
2666 (MAC_STATUS_SYNC_CHANGED |
2667 MAC_STATUS_CFG_CHANGED));
2668 udelay(40);
2669 if ((tr32(MAC_STATUS) &
2670 (MAC_STATUS_SYNC_CHANGED |
2671 MAC_STATUS_CFG_CHANGED)) == 0)
2672 break;
2673 }
2674
2675 mac_status = tr32(MAC_STATUS);
2676 if (current_link_up == 0 &&
2677 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2678 !(mac_status & MAC_STATUS_RCVD_CFG))
2679 current_link_up = 1;
2680 } else {
2681 /* Forcing 1000FD link up. */
2682 current_link_up = 1;
2683
2684 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2685 udelay(40);
2686
2687 tw32_f(MAC_MODE, tp->mac_mode);
2688 udelay(40);
2689 }
2690
2691 out:
2692 return current_link_up;
2693 }
2694
2695 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2696 {
2697 u32 orig_pause_cfg;
2698 u16 orig_active_speed;
2699 u8 orig_active_duplex;
2700 u32 mac_status;
2701 int current_link_up;
2702 int i;
2703
2704 orig_pause_cfg =
2705 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2706 TG3_FLAG_TX_PAUSE));
2707 orig_active_speed = tp->link_config.active_speed;
2708 orig_active_duplex = tp->link_config.active_duplex;
2709
2710 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2711 netif_carrier_ok(tp->dev) &&
2712 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2713 mac_status = tr32(MAC_STATUS);
2714 mac_status &= (MAC_STATUS_PCS_SYNCED |
2715 MAC_STATUS_SIGNAL_DET |
2716 MAC_STATUS_CFG_CHANGED |
2717 MAC_STATUS_RCVD_CFG);
2718 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2719 MAC_STATUS_SIGNAL_DET)) {
2720 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2721 MAC_STATUS_CFG_CHANGED));
2722 return 0;
2723 }
2724 }
2725
2726 tw32_f(MAC_TX_AUTO_NEG, 0);
2727
2728 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2729 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2730 tw32_f(MAC_MODE, tp->mac_mode);
2731 udelay(40);
2732
2733 if (tp->phy_id == PHY_ID_BCM8002)
2734 tg3_init_bcm8002(tp);
2735
2736 /* Enable link change event even when serdes polling. */
2737 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2738 udelay(40);
2739
2740 current_link_up = 0;
2741 mac_status = tr32(MAC_STATUS);
2742
2743 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2744 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2745 else
2746 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2747
2748 tp->hw_status->status =
2749 (SD_STATUS_UPDATED |
2750 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2751
2752 for (i = 0; i < 100; i++) {
2753 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2754 MAC_STATUS_CFG_CHANGED));
2755 udelay(5);
2756 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2757 MAC_STATUS_CFG_CHANGED |
2758 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2759 break;
2760 }
2761
2762 mac_status = tr32(MAC_STATUS);
2763 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2764 current_link_up = 0;
2765 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2766 tp->serdes_counter == 0) {
2767 tw32_f(MAC_MODE, (tp->mac_mode |
2768 MAC_MODE_SEND_CONFIGS));
2769 udelay(1);
2770 tw32_f(MAC_MODE, tp->mac_mode);
2771 }
2772 }
2773
2774 if (current_link_up == 1) {
2775 tp->link_config.active_speed = SPEED_1000;
2776 tp->link_config.active_duplex = DUPLEX_FULL;
2777 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2778 LED_CTRL_LNKLED_OVERRIDE |
2779 LED_CTRL_1000MBPS_ON));
2780 } else {
2781 tp->link_config.active_speed = SPEED_INVALID;
2782 tp->link_config.active_duplex = DUPLEX_INVALID;
2783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2784 LED_CTRL_LNKLED_OVERRIDE |
2785 LED_CTRL_TRAFFIC_OVERRIDE));
2786 }
2787
2788 if (current_link_up != netif_carrier_ok(tp->dev)) {
2789 if (current_link_up)
2790 netif_carrier_on(tp->dev);
2791 else
2792 netif_carrier_off(tp->dev);
2793 tg3_link_report(tp);
2794 } else {
2795 u32 now_pause_cfg =
2796 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2797 TG3_FLAG_TX_PAUSE);
2798 if (orig_pause_cfg != now_pause_cfg ||
2799 orig_active_speed != tp->link_config.active_speed ||
2800 orig_active_duplex != tp->link_config.active_duplex)
2801 tg3_link_report(tp);
2802 }
2803
2804 return 0;
2805 }
2806
2807 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2808 {
2809 int current_link_up, err = 0;
2810 u32 bmsr, bmcr;
2811 u16 current_speed;
2812 u8 current_duplex;
2813
2814 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2815 tw32_f(MAC_MODE, tp->mac_mode);
2816 udelay(40);
2817
2818 tw32(MAC_EVENT, 0);
2819
2820 tw32_f(MAC_STATUS,
2821 (MAC_STATUS_SYNC_CHANGED |
2822 MAC_STATUS_CFG_CHANGED |
2823 MAC_STATUS_MI_COMPLETION |
2824 MAC_STATUS_LNKSTATE_CHANGED));
2825 udelay(40);
2826
2827 if (force_reset)
2828 tg3_phy_reset(tp);
2829
2830 current_link_up = 0;
2831 current_speed = SPEED_INVALID;
2832 current_duplex = DUPLEX_INVALID;
2833
2834 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2835 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2837 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2838 bmsr |= BMSR_LSTATUS;
2839 else
2840 bmsr &= ~BMSR_LSTATUS;
2841 }
2842
2843 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2844
2845 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2846 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2847 /* do nothing, just check for link up at the end */
2848 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2849 u32 adv, new_adv;
2850
2851 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2852 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2853 ADVERTISE_1000XPAUSE |
2854 ADVERTISE_1000XPSE_ASYM |
2855 ADVERTISE_SLCT);
2856
2857 /* Always advertise symmetric PAUSE just like copper */
2858 new_adv |= ADVERTISE_1000XPAUSE;
2859
2860 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2861 new_adv |= ADVERTISE_1000XHALF;
2862 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2863 new_adv |= ADVERTISE_1000XFULL;
2864
2865 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2868 tg3_writephy(tp, MII_BMCR, bmcr);
2869
2870 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2871 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2872 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2873
2874 return err;
2875 }
2876 } else {
2877 u32 new_bmcr;
2878
2879 bmcr &= ~BMCR_SPEED1000;
2880 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2881
2882 if (tp->link_config.duplex == DUPLEX_FULL)
2883 new_bmcr |= BMCR_FULLDPLX;
2884
2885 if (new_bmcr != bmcr) {
2886 /* BMCR_SPEED1000 is a reserved bit that needs
2887 * to be set on write.
2888 */
2889 new_bmcr |= BMCR_SPEED1000;
2890
2891 /* Force a linkdown */
2892 if (netif_carrier_ok(tp->dev)) {
2893 u32 adv;
2894
2895 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2896 adv &= ~(ADVERTISE_1000XFULL |
2897 ADVERTISE_1000XHALF |
2898 ADVERTISE_SLCT);
2899 tg3_writephy(tp, MII_ADVERTISE, adv);
2900 tg3_writephy(tp, MII_BMCR, bmcr |
2901 BMCR_ANRESTART |
2902 BMCR_ANENABLE);
2903 udelay(10);
2904 netif_carrier_off(tp->dev);
2905 }
2906 tg3_writephy(tp, MII_BMCR, new_bmcr);
2907 bmcr = new_bmcr;
2908 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2909 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2910 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2911 ASIC_REV_5714) {
2912 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2913 bmsr |= BMSR_LSTATUS;
2914 else
2915 bmsr &= ~BMSR_LSTATUS;
2916 }
2917 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2918 }
2919 }
2920
2921 if (bmsr & BMSR_LSTATUS) {
2922 current_speed = SPEED_1000;
2923 current_link_up = 1;
2924 if (bmcr & BMCR_FULLDPLX)
2925 current_duplex = DUPLEX_FULL;
2926 else
2927 current_duplex = DUPLEX_HALF;
2928
2929 if (bmcr & BMCR_ANENABLE) {
2930 u32 local_adv, remote_adv, common;
2931
2932 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2933 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2934 common = local_adv & remote_adv;
2935 if (common & (ADVERTISE_1000XHALF |
2936 ADVERTISE_1000XFULL)) {
2937 if (common & ADVERTISE_1000XFULL)
2938 current_duplex = DUPLEX_FULL;
2939 else
2940 current_duplex = DUPLEX_HALF;
2941
2942 tg3_setup_flow_control(tp, local_adv,
2943 remote_adv);
2944 }
2945 else
2946 current_link_up = 0;
2947 }
2948 }
2949
2950 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2951 if (tp->link_config.active_duplex == DUPLEX_HALF)
2952 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2953
2954 tw32_f(MAC_MODE, tp->mac_mode);
2955 udelay(40);
2956
2957 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2958
2959 tp->link_config.active_speed = current_speed;
2960 tp->link_config.active_duplex = current_duplex;
2961
2962 if (current_link_up != netif_carrier_ok(tp->dev)) {
2963 if (current_link_up)
2964 netif_carrier_on(tp->dev);
2965 else {
2966 netif_carrier_off(tp->dev);
2967 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2968 }
2969 tg3_link_report(tp);
2970 }
2971 return err;
2972 }
2973
2974 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2975 {
2976 if (tp->serdes_counter) {
2977 /* Give autoneg time to complete. */
2978 tp->serdes_counter--;
2979 return;
2980 }
2981 if (!netif_carrier_ok(tp->dev) &&
2982 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2983 u32 bmcr;
2984
2985 tg3_readphy(tp, MII_BMCR, &bmcr);
2986 if (bmcr & BMCR_ANENABLE) {
2987 u32 phy1, phy2;
2988
2989 /* Select shadow register 0x1f */
2990 tg3_writephy(tp, 0x1c, 0x7c00);
2991 tg3_readphy(tp, 0x1c, &phy1);
2992
2993 /* Select expansion interrupt status register */
2994 tg3_writephy(tp, 0x17, 0x0f01);
2995 tg3_readphy(tp, 0x15, &phy2);
2996 tg3_readphy(tp, 0x15, &phy2);
2997
2998 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2999 /* We have signal detect and not receiving
3000 * config code words, link is up by parallel
3001 * detection.
3002 */
3003
3004 bmcr &= ~BMCR_ANENABLE;
3005 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3006 tg3_writephy(tp, MII_BMCR, bmcr);
3007 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3008 }
3009 }
3010 }
3011 else if (netif_carrier_ok(tp->dev) &&
3012 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3013 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3014 u32 phy2;
3015
3016 /* Select expansion interrupt status register */
3017 tg3_writephy(tp, 0x17, 0x0f01);
3018 tg3_readphy(tp, 0x15, &phy2);
3019 if (phy2 & 0x20) {
3020 u32 bmcr;
3021
3022 /* Config code words received, turn on autoneg. */
3023 tg3_readphy(tp, MII_BMCR, &bmcr);
3024 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3025
3026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3027
3028 }
3029 }
3030 }
3031
3032 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3033 {
3034 int err;
3035
3036 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3037 err = tg3_setup_fiber_phy(tp, force_reset);
3038 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3039 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3040 } else {
3041 err = tg3_setup_copper_phy(tp, force_reset);
3042 }
3043
3044 if (tp->link_config.active_speed == SPEED_1000 &&
3045 tp->link_config.active_duplex == DUPLEX_HALF)
3046 tw32(MAC_TX_LENGTHS,
3047 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3048 (6 << TX_LENGTHS_IPG_SHIFT) |
3049 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3050 else
3051 tw32(MAC_TX_LENGTHS,
3052 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3053 (6 << TX_LENGTHS_IPG_SHIFT) |
3054 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3055
3056 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3057 if (netif_carrier_ok(tp->dev)) {
3058 tw32(HOSTCC_STAT_COAL_TICKS,
3059 tp->coal.stats_block_coalesce_usecs);
3060 } else {
3061 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3062 }
3063 }
3064
3065 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3066 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3067 if (!netif_carrier_ok(tp->dev))
3068 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3069 tp->pwrmgmt_thresh;
3070 else
3071 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3072 tw32(PCIE_PWR_MGMT_THRESH, val);
3073 }
3074
3075 return err;
3076 }
3077
3078 /* This is called whenever we suspect that the system chipset is re-
3079 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3080 * is bogus tx completions. We try to recover by setting the
3081 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3082 * in the workqueue.
3083 */
3084 static void tg3_tx_recover(struct tg3 *tp)
3085 {
3086 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3087 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3088
3089 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3090 "mapped I/O cycles to the network device, attempting to "
3091 "recover. Please report the problem to the driver maintainer "
3092 "and include system chipset information.\n", tp->dev->name);
3093
3094 spin_lock(&tp->lock);
3095 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3096 spin_unlock(&tp->lock);
3097 }
3098
3099 static inline u32 tg3_tx_avail(struct tg3 *tp)
3100 {
3101 smp_mb();
3102 return (tp->tx_pending -
3103 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3104 }
3105
3106 /* Tigon3 never reports partial packet sends. So we do not
3107 * need special logic to handle SKBs that have not had all
3108 * of their frags sent yet, like SunGEM does.
3109 */
3110 static void tg3_tx(struct tg3 *tp)
3111 {
3112 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3113 u32 sw_idx = tp->tx_cons;
3114
3115 while (sw_idx != hw_idx) {
3116 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3117 struct sk_buff *skb = ri->skb;
3118 int i, tx_bug = 0;
3119
3120 if (unlikely(skb == NULL)) {
3121 tg3_tx_recover(tp);
3122 return;
3123 }
3124
3125 pci_unmap_single(tp->pdev,
3126 pci_unmap_addr(ri, mapping),
3127 skb_headlen(skb),
3128 PCI_DMA_TODEVICE);
3129
3130 ri->skb = NULL;
3131
3132 sw_idx = NEXT_TX(sw_idx);
3133
3134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3135 ri = &tp->tx_buffers[sw_idx];
3136 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3137 tx_bug = 1;
3138
3139 pci_unmap_page(tp->pdev,
3140 pci_unmap_addr(ri, mapping),
3141 skb_shinfo(skb)->frags[i].size,
3142 PCI_DMA_TODEVICE);
3143
3144 sw_idx = NEXT_TX(sw_idx);
3145 }
3146
3147 dev_kfree_skb(skb);
3148
3149 if (unlikely(tx_bug)) {
3150 tg3_tx_recover(tp);
3151 return;
3152 }
3153 }
3154
3155 tp->tx_cons = sw_idx;
3156
3157 /* Need to make the tx_cons update visible to tg3_start_xmit()
3158 * before checking for netif_queue_stopped(). Without the
3159 * memory barrier, there is a small possibility that tg3_start_xmit()
3160 * will miss it and cause the queue to be stopped forever.
3161 */
3162 smp_mb();
3163
3164 if (unlikely(netif_queue_stopped(tp->dev) &&
3165 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3166 netif_tx_lock(tp->dev);
3167 if (netif_queue_stopped(tp->dev) &&
3168 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3169 netif_wake_queue(tp->dev);
3170 netif_tx_unlock(tp->dev);
3171 }
3172 }
3173
3174 /* Returns size of skb allocated or < 0 on error.
3175 *
3176 * We only need to fill in the address because the other members
3177 * of the RX descriptor are invariant, see tg3_init_rings.
3178 *
3179 * Note the purposeful assymetry of cpu vs. chip accesses. For
3180 * posting buffers we only dirty the first cache line of the RX
3181 * descriptor (containing the address). Whereas for the RX status
3182 * buffers the cpu only reads the last cacheline of the RX descriptor
3183 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3184 */
3185 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3186 int src_idx, u32 dest_idx_unmasked)
3187 {
3188 struct tg3_rx_buffer_desc *desc;
3189 struct ring_info *map, *src_map;
3190 struct sk_buff *skb;
3191 dma_addr_t mapping;
3192 int skb_size, dest_idx;
3193
3194 src_map = NULL;
3195 switch (opaque_key) {
3196 case RXD_OPAQUE_RING_STD:
3197 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3198 desc = &tp->rx_std[dest_idx];
3199 map = &tp->rx_std_buffers[dest_idx];
3200 if (src_idx >= 0)
3201 src_map = &tp->rx_std_buffers[src_idx];
3202 skb_size = tp->rx_pkt_buf_sz;
3203 break;
3204
3205 case RXD_OPAQUE_RING_JUMBO:
3206 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3207 desc = &tp->rx_jumbo[dest_idx];
3208 map = &tp->rx_jumbo_buffers[dest_idx];
3209 if (src_idx >= 0)
3210 src_map = &tp->rx_jumbo_buffers[src_idx];
3211 skb_size = RX_JUMBO_PKT_BUF_SZ;
3212 break;
3213
3214 default:
3215 return -EINVAL;
3216 };
3217
3218 /* Do not overwrite any of the map or rp information
3219 * until we are sure we can commit to a new buffer.
3220 *
3221 * Callers depend upon this behavior and assume that
3222 * we leave everything unchanged if we fail.
3223 */
3224 skb = netdev_alloc_skb(tp->dev, skb_size);
3225 if (skb == NULL)
3226 return -ENOMEM;
3227
3228 skb_reserve(skb, tp->rx_offset);
3229
3230 mapping = pci_map_single(tp->pdev, skb->data,
3231 skb_size - tp->rx_offset,
3232 PCI_DMA_FROMDEVICE);
3233
3234 map->skb = skb;
3235 pci_unmap_addr_set(map, mapping, mapping);
3236
3237 if (src_map != NULL)
3238 src_map->skb = NULL;
3239
3240 desc->addr_hi = ((u64)mapping >> 32);
3241 desc->addr_lo = ((u64)mapping & 0xffffffff);
3242
3243 return skb_size;
3244 }
3245
3246 /* We only need to move over in the address because the other
3247 * members of the RX descriptor are invariant. See notes above
3248 * tg3_alloc_rx_skb for full details.
3249 */
3250 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3251 int src_idx, u32 dest_idx_unmasked)
3252 {
3253 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3254 struct ring_info *src_map, *dest_map;
3255 int dest_idx;
3256
3257 switch (opaque_key) {
3258 case RXD_OPAQUE_RING_STD:
3259 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3260 dest_desc = &tp->rx_std[dest_idx];
3261 dest_map = &tp->rx_std_buffers[dest_idx];
3262 src_desc = &tp->rx_std[src_idx];
3263 src_map = &tp->rx_std_buffers[src_idx];
3264 break;
3265
3266 case RXD_OPAQUE_RING_JUMBO:
3267 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3268 dest_desc = &tp->rx_jumbo[dest_idx];
3269 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3270 src_desc = &tp->rx_jumbo[src_idx];
3271 src_map = &tp->rx_jumbo_buffers[src_idx];
3272 break;
3273
3274 default:
3275 return;
3276 };
3277
3278 dest_map->skb = src_map->skb;
3279 pci_unmap_addr_set(dest_map, mapping,
3280 pci_unmap_addr(src_map, mapping));
3281 dest_desc->addr_hi = src_desc->addr_hi;
3282 dest_desc->addr_lo = src_desc->addr_lo;
3283
3284 src_map->skb = NULL;
3285 }
3286
3287 #if TG3_VLAN_TAG_USED
3288 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3289 {
3290 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3291 }
3292 #endif
3293
3294 /* The RX ring scheme is composed of multiple rings which post fresh
3295 * buffers to the chip, and one special ring the chip uses to report
3296 * status back to the host.
3297 *
3298 * The special ring reports the status of received packets to the
3299 * host. The chip does not write into the original descriptor the
3300 * RX buffer was obtained from. The chip simply takes the original
3301 * descriptor as provided by the host, updates the status and length
3302 * field, then writes this into the next status ring entry.
3303 *
3304 * Each ring the host uses to post buffers to the chip is described
3305 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3306 * it is first placed into the on-chip ram. When the packet's length
3307 * is known, it walks down the TG3_BDINFO entries to select the ring.
3308 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3309 * which is within the range of the new packet's length is chosen.
3310 *
3311 * The "separate ring for rx status" scheme may sound queer, but it makes
3312 * sense from a cache coherency perspective. If only the host writes
3313 * to the buffer post rings, and only the chip writes to the rx status
3314 * rings, then cache lines never move beyond shared-modified state.
3315 * If both the host and chip were to write into the same ring, cache line
3316 * eviction could occur since both entities want it in an exclusive state.
3317 */
3318 static int tg3_rx(struct tg3 *tp, int budget)
3319 {
3320 u32 work_mask, rx_std_posted = 0;
3321 u32 sw_idx = tp->rx_rcb_ptr;
3322 u16 hw_idx;
3323 int received;
3324
3325 hw_idx = tp->hw_status->idx[0].rx_producer;
3326 /*
3327 * We need to order the read of hw_idx and the read of
3328 * the opaque cookie.
3329 */
3330 rmb();
3331 work_mask = 0;
3332 received = 0;
3333 while (sw_idx != hw_idx && budget > 0) {
3334 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3335 unsigned int len;
3336 struct sk_buff *skb;
3337 dma_addr_t dma_addr;
3338 u32 opaque_key, desc_idx, *post_ptr;
3339
3340 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3341 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3342 if (opaque_key == RXD_OPAQUE_RING_STD) {
3343 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3344 mapping);
3345 skb = tp->rx_std_buffers[desc_idx].skb;
3346 post_ptr = &tp->rx_std_ptr;
3347 rx_std_posted++;
3348 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3349 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3350 mapping);
3351 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3352 post_ptr = &tp->rx_jumbo_ptr;
3353 }
3354 else {
3355 goto next_pkt_nopost;
3356 }
3357
3358 work_mask |= opaque_key;
3359
3360 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3361 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3362 drop_it:
3363 tg3_recycle_rx(tp, opaque_key,
3364 desc_idx, *post_ptr);
3365 drop_it_no_recycle:
3366 /* Other statistics kept track of by card. */
3367 tp->net_stats.rx_dropped++;
3368 goto next_pkt;
3369 }
3370
3371 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3372
3373 if (len > RX_COPY_THRESHOLD
3374 && tp->rx_offset == 2
3375 /* rx_offset != 2 iff this is a 5701 card running
3376 * in PCI-X mode [see tg3_get_invariants()] */
3377 ) {
3378 int skb_size;
3379
3380 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3381 desc_idx, *post_ptr);
3382 if (skb_size < 0)
3383 goto drop_it;
3384
3385 pci_unmap_single(tp->pdev, dma_addr,
3386 skb_size - tp->rx_offset,
3387 PCI_DMA_FROMDEVICE);
3388
3389 skb_put(skb, len);
3390 } else {
3391 struct sk_buff *copy_skb;
3392
3393 tg3_recycle_rx(tp, opaque_key,
3394 desc_idx, *post_ptr);
3395
3396 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3397 if (copy_skb == NULL)
3398 goto drop_it_no_recycle;
3399
3400 skb_reserve(copy_skb, 2);
3401 skb_put(copy_skb, len);
3402 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3403 skb_copy_from_linear_data(skb, copy_skb->data, len);
3404 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3405
3406 /* We'll reuse the original ring buffer. */
3407 skb = copy_skb;
3408 }
3409
3410 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3411 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3412 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3413 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3414 skb->ip_summed = CHECKSUM_UNNECESSARY;
3415 else
3416 skb->ip_summed = CHECKSUM_NONE;
3417
3418 skb->protocol = eth_type_trans(skb, tp->dev);
3419 #if TG3_VLAN_TAG_USED
3420 if (tp->vlgrp != NULL &&
3421 desc->type_flags & RXD_FLAG_VLAN) {
3422 tg3_vlan_rx(tp, skb,
3423 desc->err_vlan & RXD_VLAN_MASK);
3424 } else
3425 #endif
3426 netif_receive_skb(skb);
3427
3428 tp->dev->last_rx = jiffies;
3429 received++;
3430 budget--;
3431
3432 next_pkt:
3433 (*post_ptr)++;
3434
3435 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3436 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3437
3438 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3439 TG3_64BIT_REG_LOW, idx);
3440 work_mask &= ~RXD_OPAQUE_RING_STD;
3441 rx_std_posted = 0;
3442 }
3443 next_pkt_nopost:
3444 sw_idx++;
3445 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3446
3447 /* Refresh hw_idx to see if there is new work */
3448 if (sw_idx == hw_idx) {
3449 hw_idx = tp->hw_status->idx[0].rx_producer;
3450 rmb();
3451 }
3452 }
3453
3454 /* ACK the status ring. */
3455 tp->rx_rcb_ptr = sw_idx;
3456 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3457
3458 /* Refill RX ring(s). */
3459 if (work_mask & RXD_OPAQUE_RING_STD) {
3460 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3461 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3462 sw_idx);
3463 }
3464 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3465 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3466 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3467 sw_idx);
3468 }
3469 mmiowb();
3470
3471 return received;
3472 }
3473
3474 static int tg3_poll(struct net_device *netdev, int *budget)
3475 {
3476 struct tg3 *tp = netdev_priv(netdev);
3477 struct tg3_hw_status *sblk = tp->hw_status;
3478 int done;
3479
3480 /* handle link change and other phy events */
3481 if (!(tp->tg3_flags &
3482 (TG3_FLAG_USE_LINKCHG_REG |
3483 TG3_FLAG_POLL_SERDES))) {
3484 if (sblk->status & SD_STATUS_LINK_CHG) {
3485 sblk->status = SD_STATUS_UPDATED |
3486 (sblk->status & ~SD_STATUS_LINK_CHG);
3487 spin_lock(&tp->lock);
3488 tg3_setup_phy(tp, 0);
3489 spin_unlock(&tp->lock);
3490 }
3491 }
3492
3493 /* run TX completion thread */
3494 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3495 tg3_tx(tp);
3496 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3497 netif_rx_complete(netdev);
3498 schedule_work(&tp->reset_task);
3499 return 0;
3500 }
3501 }
3502
3503 /* run RX thread, within the bounds set by NAPI.
3504 * All RX "locking" is done by ensuring outside
3505 * code synchronizes with dev->poll()
3506 */
3507 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3508 int orig_budget = *budget;
3509 int work_done;
3510
3511 if (orig_budget > netdev->quota)
3512 orig_budget = netdev->quota;
3513
3514 work_done = tg3_rx(tp, orig_budget);
3515
3516 *budget -= work_done;
3517 netdev->quota -= work_done;
3518 }
3519
3520 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3521 tp->last_tag = sblk->status_tag;
3522 rmb();
3523 } else
3524 sblk->status &= ~SD_STATUS_UPDATED;
3525
3526 /* if no more work, tell net stack and NIC we're done */
3527 done = !tg3_has_work(tp);
3528 if (done) {
3529 netif_rx_complete(netdev);
3530 tg3_restart_ints(tp);
3531 }
3532
3533 return (done ? 0 : 1);
3534 }
3535
3536 static void tg3_irq_quiesce(struct tg3 *tp)
3537 {
3538 BUG_ON(tp->irq_sync);
3539
3540 tp->irq_sync = 1;
3541 smp_mb();
3542
3543 synchronize_irq(tp->pdev->irq);
3544 }
3545
3546 static inline int tg3_irq_sync(struct tg3 *tp)
3547 {
3548 return tp->irq_sync;
3549 }
3550
3551 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3552 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3553 * with as well. Most of the time, this is not necessary except when
3554 * shutting down the device.
3555 */
3556 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3557 {
3558 spin_lock_bh(&tp->lock);
3559 if (irq_sync)
3560 tg3_irq_quiesce(tp);
3561 }
3562
3563 static inline void tg3_full_unlock(struct tg3 *tp)
3564 {
3565 spin_unlock_bh(&tp->lock);
3566 }
3567
3568 /* One-shot MSI handler - Chip automatically disables interrupt
3569 * after sending MSI so driver doesn't have to do it.
3570 */
3571 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3572 {
3573 struct net_device *dev = dev_id;
3574 struct tg3 *tp = netdev_priv(dev);
3575
3576 prefetch(tp->hw_status);
3577 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3578
3579 if (likely(!tg3_irq_sync(tp)))
3580 netif_rx_schedule(dev); /* schedule NAPI poll */
3581
3582 return IRQ_HANDLED;
3583 }
3584
3585 /* MSI ISR - No need to check for interrupt sharing and no need to
3586 * flush status block and interrupt mailbox. PCI ordering rules
3587 * guarantee that MSI will arrive after the status block.
3588 */
3589 static irqreturn_t tg3_msi(int irq, void *dev_id)
3590 {
3591 struct net_device *dev = dev_id;
3592 struct tg3 *tp = netdev_priv(dev);
3593
3594 prefetch(tp->hw_status);
3595 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3596 /*
3597 * Writing any value to intr-mbox-0 clears PCI INTA# and
3598 * chip-internal interrupt pending events.
3599 * Writing non-zero to intr-mbox-0 additional tells the
3600 * NIC to stop sending us irqs, engaging "in-intr-handler"
3601 * event coalescing.
3602 */
3603 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3604 if (likely(!tg3_irq_sync(tp)))
3605 netif_rx_schedule(dev); /* schedule NAPI poll */
3606
3607 return IRQ_RETVAL(1);
3608 }
3609
3610 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3611 {
3612 struct net_device *dev = dev_id;
3613 struct tg3 *tp = netdev_priv(dev);
3614 struct tg3_hw_status *sblk = tp->hw_status;
3615 unsigned int handled = 1;
3616
3617 /* In INTx mode, it is possible for the interrupt to arrive at
3618 * the CPU before the status block posted prior to the interrupt.
3619 * Reading the PCI State register will confirm whether the
3620 * interrupt is ours and will flush the status block.
3621 */
3622 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3623 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3624 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3625 handled = 0;
3626 goto out;
3627 }
3628 }
3629
3630 /*
3631 * Writing any value to intr-mbox-0 clears PCI INTA# and
3632 * chip-internal interrupt pending events.
3633 * Writing non-zero to intr-mbox-0 additional tells the
3634 * NIC to stop sending us irqs, engaging "in-intr-handler"
3635 * event coalescing.
3636 *
3637 * Flush the mailbox to de-assert the IRQ immediately to prevent
3638 * spurious interrupts. The flush impacts performance but
3639 * excessive spurious interrupts can be worse in some cases.
3640 */
3641 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3642 if (tg3_irq_sync(tp))
3643 goto out;
3644 sblk->status &= ~SD_STATUS_UPDATED;
3645 if (likely(tg3_has_work(tp))) {
3646 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3647 netif_rx_schedule(dev); /* schedule NAPI poll */
3648 } else {
3649 /* No work, shared interrupt perhaps? re-enable
3650 * interrupts, and flush that PCI write
3651 */
3652 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3653 0x00000000);
3654 }
3655 out:
3656 return IRQ_RETVAL(handled);
3657 }
3658
3659 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3660 {
3661 struct net_device *dev = dev_id;
3662 struct tg3 *tp = netdev_priv(dev);
3663 struct tg3_hw_status *sblk = tp->hw_status;
3664 unsigned int handled = 1;
3665
3666 /* In INTx mode, it is possible for the interrupt to arrive at
3667 * the CPU before the status block posted prior to the interrupt.
3668 * Reading the PCI State register will confirm whether the
3669 * interrupt is ours and will flush the status block.
3670 */
3671 if (unlikely(sblk->status_tag == tp->last_tag)) {
3672 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3673 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3674 handled = 0;
3675 goto out;
3676 }
3677 }
3678
3679 /*
3680 * writing any value to intr-mbox-0 clears PCI INTA# and
3681 * chip-internal interrupt pending events.
3682 * writing non-zero to intr-mbox-0 additional tells the
3683 * NIC to stop sending us irqs, engaging "in-intr-handler"
3684 * event coalescing.
3685 *
3686 * Flush the mailbox to de-assert the IRQ immediately to prevent
3687 * spurious interrupts. The flush impacts performance but
3688 * excessive spurious interrupts can be worse in some cases.
3689 */
3690 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3691 if (tg3_irq_sync(tp))
3692 goto out;
3693 if (netif_rx_schedule_prep(dev)) {
3694 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3695 /* Update last_tag to mark that this status has been
3696 * seen. Because interrupt may be shared, we may be
3697 * racing with tg3_poll(), so only update last_tag
3698 * if tg3_poll() is not scheduled.
3699 */
3700 tp->last_tag = sblk->status_tag;
3701 __netif_rx_schedule(dev);
3702 }
3703 out:
3704 return IRQ_RETVAL(handled);
3705 }
3706
3707 /* ISR for interrupt test */
3708 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3709 {
3710 struct net_device *dev = dev_id;
3711 struct tg3 *tp = netdev_priv(dev);
3712 struct tg3_hw_status *sblk = tp->hw_status;
3713
3714 if ((sblk->status & SD_STATUS_UPDATED) ||
3715 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3716 tg3_disable_ints(tp);
3717 return IRQ_RETVAL(1);
3718 }
3719 return IRQ_RETVAL(0);
3720 }
3721
3722 static int tg3_init_hw(struct tg3 *, int);
3723 static int tg3_halt(struct tg3 *, int, int);
3724
3725 /* Restart hardware after configuration changes, self-test, etc.
3726 * Invoked with tp->lock held.
3727 */
3728 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3729 {
3730 int err;
3731
3732 err = tg3_init_hw(tp, reset_phy);
3733 if (err) {
3734 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3735 "aborting.\n", tp->dev->name);
3736 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3737 tg3_full_unlock(tp);
3738 del_timer_sync(&tp->timer);
3739 tp->irq_sync = 0;
3740 netif_poll_enable(tp->dev);
3741 dev_close(tp->dev);
3742 tg3_full_lock(tp, 0);
3743 }
3744 return err;
3745 }
3746
3747 #ifdef CONFIG_NET_POLL_CONTROLLER
3748 static void tg3_poll_controller(struct net_device *dev)
3749 {
3750 struct tg3 *tp = netdev_priv(dev);
3751
3752 tg3_interrupt(tp->pdev->irq, dev);
3753 }
3754 #endif
3755
3756 static void tg3_reset_task(struct work_struct *work)
3757 {
3758 struct tg3 *tp = container_of(work, struct tg3, reset_task);
3759 unsigned int restart_timer;
3760
3761 tg3_full_lock(tp, 0);
3762
3763 if (!netif_running(tp->dev)) {
3764 tg3_full_unlock(tp);
3765 return;
3766 }
3767
3768 tg3_full_unlock(tp);
3769
3770 tg3_netif_stop(tp);
3771
3772 tg3_full_lock(tp, 1);
3773
3774 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3775 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3776
3777 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3778 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3779 tp->write32_rx_mbox = tg3_write_flush_reg32;
3780 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3781 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3782 }
3783
3784 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3785 if (tg3_init_hw(tp, 1))
3786 goto out;
3787
3788 tg3_netif_start(tp);
3789
3790 if (restart_timer)
3791 mod_timer(&tp->timer, jiffies + 1);
3792
3793 out:
3794 tg3_full_unlock(tp);
3795 }
3796
3797 static void tg3_dump_short_state(struct tg3 *tp)
3798 {
3799 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3800 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3801 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3802 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3803 }
3804
3805 static void tg3_tx_timeout(struct net_device *dev)
3806 {
3807 struct tg3 *tp = netdev_priv(dev);
3808
3809 if (netif_msg_tx_err(tp)) {
3810 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3811 dev->name);
3812 tg3_dump_short_state(tp);
3813 }
3814
3815 schedule_work(&tp->reset_task);
3816 }
3817
3818 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3819 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3820 {
3821 u32 base = (u32) mapping & 0xffffffff;
3822
3823 return ((base > 0xffffdcc0) &&
3824 (base + len + 8 < base));
3825 }
3826
3827 /* Test for DMA addresses > 40-bit */
3828 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3829 int len)
3830 {
3831 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3832 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3833 return (((u64) mapping + len) > DMA_40BIT_MASK);
3834 return 0;
3835 #else
3836 return 0;
3837 #endif
3838 }
3839
3840 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3841
3842 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3843 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3844 u32 last_plus_one, u32 *start,
3845 u32 base_flags, u32 mss)
3846 {
3847 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3848 dma_addr_t new_addr = 0;
3849 u32 entry = *start;
3850 int i, ret = 0;
3851
3852 if (!new_skb) {
3853 ret = -1;
3854 } else {
3855 /* New SKB is guaranteed to be linear. */
3856 entry = *start;
3857 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3858 PCI_DMA_TODEVICE);
3859 /* Make sure new skb does not cross any 4G boundaries.
3860 * Drop the packet if it does.
3861 */
3862 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3863 ret = -1;
3864 dev_kfree_skb(new_skb);
3865 new_skb = NULL;
3866 } else {
3867 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3868 base_flags, 1 | (mss << 1));
3869 *start = NEXT_TX(entry);
3870 }
3871 }
3872
3873 /* Now clean up the sw ring entries. */
3874 i = 0;
3875 while (entry != last_plus_one) {
3876 int len;
3877
3878 if (i == 0)
3879 len = skb_headlen(skb);
3880 else
3881 len = skb_shinfo(skb)->frags[i-1].size;
3882 pci_unmap_single(tp->pdev,
3883 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3884 len, PCI_DMA_TODEVICE);
3885 if (i == 0) {
3886 tp->tx_buffers[entry].skb = new_skb;
3887 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3888 } else {
3889 tp->tx_buffers[entry].skb = NULL;
3890 }
3891 entry = NEXT_TX(entry);
3892 i++;
3893 }
3894
3895 dev_kfree_skb(skb);
3896
3897 return ret;
3898 }
3899
3900 static void tg3_set_txd(struct tg3 *tp, int entry,
3901 dma_addr_t mapping, int len, u32 flags,
3902 u32 mss_and_is_end)
3903 {
3904 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3905 int is_end = (mss_and_is_end & 0x1);
3906 u32 mss = (mss_and_is_end >> 1);
3907 u32 vlan_tag = 0;
3908
3909 if (is_end)
3910 flags |= TXD_FLAG_END;
3911 if (flags & TXD_FLAG_VLAN) {
3912 vlan_tag = flags >> 16;
3913 flags &= 0xffff;
3914 }
3915 vlan_tag |= (mss << TXD_MSS_SHIFT);
3916
3917 txd->addr_hi = ((u64) mapping >> 32);
3918 txd->addr_lo = ((u64) mapping & 0xffffffff);
3919 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3920 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3921 }
3922
3923 /* hard_start_xmit for devices that don't have any bugs and
3924 * support TG3_FLG2_HW_TSO_2 only.
3925 */
3926 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3927 {
3928 struct tg3 *tp = netdev_priv(dev);
3929 dma_addr_t mapping;
3930 u32 len, entry, base_flags, mss;
3931
3932 len = skb_headlen(skb);
3933
3934 /* We are running in BH disabled context with netif_tx_lock
3935 * and TX reclaim runs via tp->poll inside of a software
3936 * interrupt. Furthermore, IRQ processing runs lockless so we have
3937 * no IRQ context deadlocks to worry about either. Rejoice!
3938 */
3939 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3940 if (!netif_queue_stopped(dev)) {
3941 netif_stop_queue(dev);
3942
3943 /* This is a hard error, log it. */
3944 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3945 "queue awake!\n", dev->name);
3946 }
3947 return NETDEV_TX_BUSY;
3948 }
3949
3950 entry = tp->tx_prod;
3951 base_flags = 0;
3952 mss = 0;
3953 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3954 int tcp_opt_len, ip_tcp_len;
3955
3956 if (skb_header_cloned(skb) &&
3957 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3958 dev_kfree_skb(skb);
3959 goto out_unlock;
3960 }
3961
3962 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3963 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3964 else {
3965 struct iphdr *iph = ip_hdr(skb);
3966
3967 tcp_opt_len = tcp_optlen(skb);
3968 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3969
3970 iph->check = 0;
3971 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3972 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3973 }
3974
3975 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3976 TXD_FLAG_CPU_POST_DMA);
3977
3978 tcp_hdr(skb)->check = 0;
3979
3980 }
3981 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3982 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3983 #if TG3_VLAN_TAG_USED
3984 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3985 base_flags |= (TXD_FLAG_VLAN |
3986 (vlan_tx_tag_get(skb) << 16));
3987 #endif
3988
3989 /* Queue skb data, a.k.a. the main skb fragment. */
3990 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3991
3992 tp->tx_buffers[entry].skb = skb;
3993 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3994
3995 tg3_set_txd(tp, entry, mapping, len, base_flags,
3996 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3997
3998 entry = NEXT_TX(entry);
3999
4000 /* Now loop through additional data fragments, and queue them. */
4001 if (skb_shinfo(skb)->nr_frags > 0) {
4002 unsigned int i, last;
4003
4004 last = skb_shinfo(skb)->nr_frags - 1;
4005 for (i = 0; i <= last; i++) {
4006 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4007
4008 len = frag->size;
4009 mapping = pci_map_page(tp->pdev,
4010 frag->page,
4011 frag->page_offset,
4012 len, PCI_DMA_TODEVICE);
4013
4014 tp->tx_buffers[entry].skb = NULL;
4015 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4016
4017 tg3_set_txd(tp, entry, mapping, len,
4018 base_flags, (i == last) | (mss << 1));
4019
4020 entry = NEXT_TX(entry);
4021 }
4022 }
4023
4024 /* Packets are ready, update Tx producer idx local and on card. */
4025 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4026
4027 tp->tx_prod = entry;
4028 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4029 netif_stop_queue(dev);
4030 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4031 netif_wake_queue(tp->dev);
4032 }
4033
4034 out_unlock:
4035 mmiowb();
4036
4037 dev->trans_start = jiffies;
4038
4039 return NETDEV_TX_OK;
4040 }
4041
4042 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4043
4044 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4045 * TSO header is greater than 80 bytes.
4046 */
4047 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4048 {
4049 struct sk_buff *segs, *nskb;
4050
4051 /* Estimate the number of fragments in the worst case */
4052 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4053 netif_stop_queue(tp->dev);
4054 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4055 return NETDEV_TX_BUSY;
4056
4057 netif_wake_queue(tp->dev);
4058 }
4059
4060 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4061 if (unlikely(IS_ERR(segs)))
4062 goto tg3_tso_bug_end;
4063
4064 do {
4065 nskb = segs;
4066 segs = segs->next;
4067 nskb->next = NULL;
4068 tg3_start_xmit_dma_bug(nskb, tp->dev);
4069 } while (segs);
4070
4071 tg3_tso_bug_end:
4072 dev_kfree_skb(skb);
4073
4074 return NETDEV_TX_OK;
4075 }
4076
4077 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4078 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4079 */
4080 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4081 {
4082 struct tg3 *tp = netdev_priv(dev);
4083 dma_addr_t mapping;
4084 u32 len, entry, base_flags, mss;
4085 int would_hit_hwbug;
4086
4087 len = skb_headlen(skb);
4088
4089 /* We are running in BH disabled context with netif_tx_lock
4090 * and TX reclaim runs via tp->poll inside of a software
4091 * interrupt. Furthermore, IRQ processing runs lockless so we have
4092 * no IRQ context deadlocks to worry about either. Rejoice!
4093 */
4094 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4095 if (!netif_queue_stopped(dev)) {
4096 netif_stop_queue(dev);
4097
4098 /* This is a hard error, log it. */
4099 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4100 "queue awake!\n", dev->name);
4101 }
4102 return NETDEV_TX_BUSY;
4103 }
4104
4105 entry = tp->tx_prod;
4106 base_flags = 0;
4107 if (skb->ip_summed == CHECKSUM_PARTIAL)
4108 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4109 mss = 0;
4110 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4111 struct iphdr *iph;
4112 int tcp_opt_len, ip_tcp_len, hdr_len;
4113
4114 if (skb_header_cloned(skb) &&
4115 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4116 dev_kfree_skb(skb);
4117 goto out_unlock;
4118 }
4119
4120 tcp_opt_len = tcp_optlen(skb);
4121 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4122
4123 hdr_len = ip_tcp_len + tcp_opt_len;
4124 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4125 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4126 return (tg3_tso_bug(tp, skb));
4127
4128 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4129 TXD_FLAG_CPU_POST_DMA);
4130
4131 iph = ip_hdr(skb);
4132 iph->check = 0;
4133 iph->tot_len = htons(mss + hdr_len);
4134 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4135 tcp_hdr(skb)->check = 0;
4136 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4137 } else
4138 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4139 iph->daddr, 0,
4140 IPPROTO_TCP,
4141 0);
4142
4143 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4144 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4145 if (tcp_opt_len || iph->ihl > 5) {
4146 int tsflags;
4147
4148 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4149 mss |= (tsflags << 11);
4150 }
4151 } else {
4152 if (tcp_opt_len || iph->ihl > 5) {
4153 int tsflags;
4154
4155 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4156 base_flags |= tsflags << 12;
4157 }
4158 }
4159 }
4160 #if TG3_VLAN_TAG_USED
4161 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4162 base_flags |= (TXD_FLAG_VLAN |
4163 (vlan_tx_tag_get(skb) << 16));
4164 #endif
4165
4166 /* Queue skb data, a.k.a. the main skb fragment. */
4167 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4168
4169 tp->tx_buffers[entry].skb = skb;
4170 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4171
4172 would_hit_hwbug = 0;
4173
4174 if (tg3_4g_overflow_test(mapping, len))
4175 would_hit_hwbug = 1;
4176
4177 tg3_set_txd(tp, entry, mapping, len, base_flags,
4178 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4179
4180 entry = NEXT_TX(entry);
4181
4182 /* Now loop through additional data fragments, and queue them. */
4183 if (skb_shinfo(skb)->nr_frags > 0) {
4184 unsigned int i, last;
4185
4186 last = skb_shinfo(skb)->nr_frags - 1;
4187 for (i = 0; i <= last; i++) {
4188 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4189
4190 len = frag->size;
4191 mapping = pci_map_page(tp->pdev,
4192 frag->page,
4193 frag->page_offset,
4194 len, PCI_DMA_TODEVICE);
4195
4196 tp->tx_buffers[entry].skb = NULL;
4197 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4198
4199 if (tg3_4g_overflow_test(mapping, len))
4200 would_hit_hwbug = 1;
4201
4202 if (tg3_40bit_overflow_test(tp, mapping, len))
4203 would_hit_hwbug = 1;
4204
4205 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4206 tg3_set_txd(tp, entry, mapping, len,
4207 base_flags, (i == last)|(mss << 1));
4208 else
4209 tg3_set_txd(tp, entry, mapping, len,
4210 base_flags, (i == last));
4211
4212 entry = NEXT_TX(entry);
4213 }
4214 }
4215
4216 if (would_hit_hwbug) {
4217 u32 last_plus_one = entry;
4218 u32 start;
4219
4220 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4221 start &= (TG3_TX_RING_SIZE - 1);
4222
4223 /* If the workaround fails due to memory/mapping
4224 * failure, silently drop this packet.
4225 */
4226 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4227 &start, base_flags, mss))
4228 goto out_unlock;
4229
4230 entry = start;
4231 }
4232
4233 /* Packets are ready, update Tx producer idx local and on card. */
4234 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4235
4236 tp->tx_prod = entry;
4237 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4238 netif_stop_queue(dev);
4239 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4240 netif_wake_queue(tp->dev);
4241 }
4242
4243 out_unlock:
4244 mmiowb();
4245
4246 dev->trans_start = jiffies;
4247
4248 return NETDEV_TX_OK;
4249 }
4250
4251 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4252 int new_mtu)
4253 {
4254 dev->mtu = new_mtu;
4255
4256 if (new_mtu > ETH_DATA_LEN) {
4257 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4258 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4259 ethtool_op_set_tso(dev, 0);
4260 }
4261 else
4262 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4263 } else {
4264 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4265 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4266 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4267 }
4268 }
4269
4270 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4271 {
4272 struct tg3 *tp = netdev_priv(dev);
4273 int err;
4274
4275 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4276 return -EINVAL;
4277
4278 if (!netif_running(dev)) {
4279 /* We'll just catch it later when the
4280 * device is up'd.
4281 */
4282 tg3_set_mtu(dev, tp, new_mtu);
4283 return 0;
4284 }
4285
4286 tg3_netif_stop(tp);
4287
4288 tg3_full_lock(tp, 1);
4289
4290 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4291
4292 tg3_set_mtu(dev, tp, new_mtu);
4293
4294 err = tg3_restart_hw(tp, 0);
4295
4296 if (!err)
4297 tg3_netif_start(tp);
4298
4299 tg3_full_unlock(tp);
4300
4301 return err;
4302 }
4303
4304 /* Free up pending packets in all rx/tx rings.
4305 *
4306 * The chip has been shut down and the driver detached from
4307 * the networking, so no interrupts or new tx packets will
4308 * end up in the driver. tp->{tx,}lock is not held and we are not
4309 * in an interrupt context and thus may sleep.
4310 */
4311 static void tg3_free_rings(struct tg3 *tp)
4312 {
4313 struct ring_info *rxp;
4314 int i;
4315
4316 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4317 rxp = &tp->rx_std_buffers[i];
4318
4319 if (rxp->skb == NULL)
4320 continue;
4321 pci_unmap_single(tp->pdev,
4322 pci_unmap_addr(rxp, mapping),
4323 tp->rx_pkt_buf_sz - tp->rx_offset,
4324 PCI_DMA_FROMDEVICE);
4325 dev_kfree_skb_any(rxp->skb);
4326 rxp->skb = NULL;
4327 }
4328
4329 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4330 rxp = &tp->rx_jumbo_buffers[i];
4331
4332 if (rxp->skb == NULL)
4333 continue;
4334 pci_unmap_single(tp->pdev,
4335 pci_unmap_addr(rxp, mapping),
4336 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4337 PCI_DMA_FROMDEVICE);
4338 dev_kfree_skb_any(rxp->skb);
4339 rxp->skb = NULL;
4340 }
4341
4342 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4343 struct tx_ring_info *txp;
4344 struct sk_buff *skb;
4345 int j;
4346
4347 txp = &tp->tx_buffers[i];
4348 skb = txp->skb;
4349
4350 if (skb == NULL) {
4351 i++;
4352 continue;
4353 }
4354
4355 pci_unmap_single(tp->pdev,
4356 pci_unmap_addr(txp, mapping),
4357 skb_headlen(skb),
4358 PCI_DMA_TODEVICE);
4359 txp->skb = NULL;
4360
4361 i++;
4362
4363 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4364 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4365 pci_unmap_page(tp->pdev,
4366 pci_unmap_addr(txp, mapping),
4367 skb_shinfo(skb)->frags[j].size,
4368 PCI_DMA_TODEVICE);
4369 i++;
4370 }
4371
4372 dev_kfree_skb_any(skb);
4373 }
4374 }
4375
4376 /* Initialize tx/rx rings for packet processing.
4377 *
4378 * The chip has been shut down and the driver detached from
4379 * the networking, so no interrupts or new tx packets will
4380 * end up in the driver. tp->{tx,}lock are held and thus
4381 * we may not sleep.
4382 */
4383 static int tg3_init_rings(struct tg3 *tp)
4384 {
4385 u32 i;
4386
4387 /* Free up all the SKBs. */
4388 tg3_free_rings(tp);
4389
4390 /* Zero out all descriptors. */
4391 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4392 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4393 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4394 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4395
4396 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4397 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4398 (tp->dev->mtu > ETH_DATA_LEN))
4399 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4400
4401 /* Initialize invariants of the rings, we only set this
4402 * stuff once. This works because the card does not
4403 * write into the rx buffer posting rings.
4404 */
4405 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4406 struct tg3_rx_buffer_desc *rxd;
4407
4408 rxd = &tp->rx_std[i];
4409 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4410 << RXD_LEN_SHIFT;
4411 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4412 rxd->opaque = (RXD_OPAQUE_RING_STD |
4413 (i << RXD_OPAQUE_INDEX_SHIFT));
4414 }
4415
4416 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4417 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4418 struct tg3_rx_buffer_desc *rxd;
4419
4420 rxd = &tp->rx_jumbo[i];
4421 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4422 << RXD_LEN_SHIFT;
4423 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4424 RXD_FLAG_JUMBO;
4425 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4426 (i << RXD_OPAQUE_INDEX_SHIFT));
4427 }
4428 }
4429
4430 /* Now allocate fresh SKBs for each rx ring. */
4431 for (i = 0; i < tp->rx_pending; i++) {
4432 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4433 printk(KERN_WARNING PFX
4434 "%s: Using a smaller RX standard ring, "
4435 "only %d out of %d buffers were allocated "
4436 "successfully.\n",
4437 tp->dev->name, i, tp->rx_pending);
4438 if (i == 0)
4439 return -ENOMEM;
4440 tp->rx_pending = i;
4441 break;
4442 }
4443 }
4444
4445 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4446 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4447 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4448 -1, i) < 0) {
4449 printk(KERN_WARNING PFX
4450 "%s: Using a smaller RX jumbo ring, "
4451 "only %d out of %d buffers were "
4452 "allocated successfully.\n",
4453 tp->dev->name, i, tp->rx_jumbo_pending);
4454 if (i == 0) {
4455 tg3_free_rings(tp);
4456 return -ENOMEM;
4457 }
4458 tp->rx_jumbo_pending = i;
4459 break;
4460 }
4461 }
4462 }
4463 return 0;
4464 }
4465
4466 /*
4467 * Must not be invoked with interrupt sources disabled and
4468 * the hardware shutdown down.
4469 */
4470 static void tg3_free_consistent(struct tg3 *tp)
4471 {
4472 kfree(tp->rx_std_buffers);
4473 tp->rx_std_buffers = NULL;
4474 if (tp->rx_std) {
4475 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4476 tp->rx_std, tp->rx_std_mapping);
4477 tp->rx_std = NULL;
4478 }
4479 if (tp->rx_jumbo) {
4480 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4481 tp->rx_jumbo, tp->rx_jumbo_mapping);
4482 tp->rx_jumbo = NULL;
4483 }
4484 if (tp->rx_rcb) {
4485 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4486 tp->rx_rcb, tp->rx_rcb_mapping);
4487 tp->rx_rcb = NULL;
4488 }
4489 if (tp->tx_ring) {
4490 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4491 tp->tx_ring, tp->tx_desc_mapping);
4492 tp->tx_ring = NULL;
4493 }
4494 if (tp->hw_status) {
4495 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4496 tp->hw_status, tp->status_mapping);
4497 tp->hw_status = NULL;
4498 }
4499 if (tp->hw_stats) {
4500 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4501 tp->hw_stats, tp->stats_mapping);
4502 tp->hw_stats = NULL;
4503 }
4504 }
4505
4506 /*
4507 * Must not be invoked with interrupt sources disabled and
4508 * the hardware shutdown down. Can sleep.
4509 */
4510 static int tg3_alloc_consistent(struct tg3 *tp)
4511 {
4512 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4513 (TG3_RX_RING_SIZE +
4514 TG3_RX_JUMBO_RING_SIZE)) +
4515 (sizeof(struct tx_ring_info) *
4516 TG3_TX_RING_SIZE),
4517 GFP_KERNEL);
4518 if (!tp->rx_std_buffers)
4519 return -ENOMEM;
4520
4521 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4522 tp->tx_buffers = (struct tx_ring_info *)
4523 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4524
4525 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4526 &tp->rx_std_mapping);
4527 if (!tp->rx_std)
4528 goto err_out;
4529
4530 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4531 &tp->rx_jumbo_mapping);
4532
4533 if (!tp->rx_jumbo)
4534 goto err_out;
4535
4536 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4537 &tp->rx_rcb_mapping);
4538 if (!tp->rx_rcb)
4539 goto err_out;
4540
4541 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4542 &tp->tx_desc_mapping);
4543 if (!tp->tx_ring)
4544 goto err_out;
4545
4546 tp->hw_status = pci_alloc_consistent(tp->pdev,
4547 TG3_HW_STATUS_SIZE,
4548 &tp->status_mapping);
4549 if (!tp->hw_status)
4550 goto err_out;
4551
4552 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4553 sizeof(struct tg3_hw_stats),
4554 &tp->stats_mapping);
4555 if (!tp->hw_stats)
4556 goto err_out;
4557
4558 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4559 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4560
4561 return 0;
4562
4563 err_out:
4564 tg3_free_consistent(tp);
4565 return -ENOMEM;
4566 }
4567
4568 #define MAX_WAIT_CNT 1000
4569
4570 /* To stop a block, clear the enable bit and poll till it
4571 * clears. tp->lock is held.
4572 */
4573 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4574 {
4575 unsigned int i;
4576 u32 val;
4577
4578 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4579 switch (ofs) {
4580 case RCVLSC_MODE:
4581 case DMAC_MODE:
4582 case MBFREE_MODE:
4583 case BUFMGR_MODE:
4584 case MEMARB_MODE:
4585 /* We can't enable/disable these bits of the
4586 * 5705/5750, just say success.
4587 */
4588 return 0;
4589
4590 default:
4591 break;
4592 };
4593 }
4594
4595 val = tr32(ofs);
4596 val &= ~enable_bit;
4597 tw32_f(ofs, val);
4598
4599 for (i = 0; i < MAX_WAIT_CNT; i++) {
4600 udelay(100);
4601 val = tr32(ofs);
4602 if ((val & enable_bit) == 0)
4603 break;
4604 }
4605
4606 if (i == MAX_WAIT_CNT && !silent) {
4607 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4608 "ofs=%lx enable_bit=%x\n",
4609 ofs, enable_bit);
4610 return -ENODEV;
4611 }
4612
4613 return 0;
4614 }
4615
4616 /* tp->lock is held. */
4617 static int tg3_abort_hw(struct tg3 *tp, int silent)
4618 {
4619 int i, err;
4620
4621 tg3_disable_ints(tp);
4622
4623 tp->rx_mode &= ~RX_MODE_ENABLE;
4624 tw32_f(MAC_RX_MODE, tp->rx_mode);
4625 udelay(10);
4626
4627 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4628 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4629 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4630 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4631 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4632 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4633
4634 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4635 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4636 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4637 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4638 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4639 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4640 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4641
4642 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4643 tw32_f(MAC_MODE, tp->mac_mode);
4644 udelay(40);
4645
4646 tp->tx_mode &= ~TX_MODE_ENABLE;
4647 tw32_f(MAC_TX_MODE, tp->tx_mode);
4648
4649 for (i = 0; i < MAX_WAIT_CNT; i++) {
4650 udelay(100);
4651 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4652 break;
4653 }
4654 if (i >= MAX_WAIT_CNT) {
4655 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4656 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4657 tp->dev->name, tr32(MAC_TX_MODE));
4658 err |= -ENODEV;
4659 }
4660
4661 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4662 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4663 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4664
4665 tw32(FTQ_RESET, 0xffffffff);
4666 tw32(FTQ_RESET, 0x00000000);
4667
4668 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4669 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4670
4671 if (tp->hw_status)
4672 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4673 if (tp->hw_stats)
4674 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4675
4676 return err;
4677 }
4678
4679 /* tp->lock is held. */
4680 static int tg3_nvram_lock(struct tg3 *tp)
4681 {
4682 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4683 int i;
4684
4685 if (tp->nvram_lock_cnt == 0) {
4686 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4687 for (i = 0; i < 8000; i++) {
4688 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4689 break;
4690 udelay(20);
4691 }
4692 if (i == 8000) {
4693 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4694 return -ENODEV;
4695 }
4696 }
4697 tp->nvram_lock_cnt++;
4698 }
4699 return 0;
4700 }
4701
4702 /* tp->lock is held. */
4703 static void tg3_nvram_unlock(struct tg3 *tp)
4704 {
4705 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4706 if (tp->nvram_lock_cnt > 0)
4707 tp->nvram_lock_cnt--;
4708 if (tp->nvram_lock_cnt == 0)
4709 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4710 }
4711 }
4712
4713 /* tp->lock is held. */
4714 static void tg3_enable_nvram_access(struct tg3 *tp)
4715 {
4716 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4717 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4718 u32 nvaccess = tr32(NVRAM_ACCESS);
4719
4720 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4721 }
4722 }
4723
4724 /* tp->lock is held. */
4725 static void tg3_disable_nvram_access(struct tg3 *tp)
4726 {
4727 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4728 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4729 u32 nvaccess = tr32(NVRAM_ACCESS);
4730
4731 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4732 }
4733 }
4734
4735 /* tp->lock is held. */
4736 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4737 {
4738 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4739 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4740
4741 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4742 switch (kind) {
4743 case RESET_KIND_INIT:
4744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4745 DRV_STATE_START);
4746 break;
4747
4748 case RESET_KIND_SHUTDOWN:
4749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4750 DRV_STATE_UNLOAD);
4751 break;
4752
4753 case RESET_KIND_SUSPEND:
4754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4755 DRV_STATE_SUSPEND);
4756 break;
4757
4758 default:
4759 break;
4760 };
4761 }
4762 }
4763
4764 /* tp->lock is held. */
4765 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4766 {
4767 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4768 switch (kind) {
4769 case RESET_KIND_INIT:
4770 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4771 DRV_STATE_START_DONE);
4772 break;
4773
4774 case RESET_KIND_SHUTDOWN:
4775 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4776 DRV_STATE_UNLOAD_DONE);
4777 break;
4778
4779 default:
4780 break;
4781 };
4782 }
4783 }
4784
4785 /* tp->lock is held. */
4786 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4787 {
4788 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4789 switch (kind) {
4790 case RESET_KIND_INIT:
4791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4792 DRV_STATE_START);
4793 break;
4794
4795 case RESET_KIND_SHUTDOWN:
4796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4797 DRV_STATE_UNLOAD);
4798 break;
4799
4800 case RESET_KIND_SUSPEND:
4801 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4802 DRV_STATE_SUSPEND);
4803 break;
4804
4805 default:
4806 break;
4807 };
4808 }
4809 }
4810
4811 static int tg3_poll_fw(struct tg3 *tp)
4812 {
4813 int i;
4814 u32 val;
4815
4816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4817 /* Wait up to 20ms for init done. */
4818 for (i = 0; i < 200; i++) {
4819 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4820 return 0;
4821 udelay(100);
4822 }
4823 return -ENODEV;
4824 }
4825
4826 /* Wait for firmware initialization to complete. */
4827 for (i = 0; i < 100000; i++) {
4828 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4829 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4830 break;
4831 udelay(10);
4832 }
4833
4834 /* Chip might not be fitted with firmware. Some Sun onboard
4835 * parts are configured like that. So don't signal the timeout
4836 * of the above loop as an error, but do report the lack of
4837 * running firmware once.
4838 */
4839 if (i >= 100000 &&
4840 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4841 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4842
4843 printk(KERN_INFO PFX "%s: No firmware running.\n",
4844 tp->dev->name);
4845 }
4846
4847 return 0;
4848 }
4849
4850 static void tg3_stop_fw(struct tg3 *);
4851
4852 /* tp->lock is held. */
4853 static int tg3_chip_reset(struct tg3 *tp)
4854 {
4855 u32 val;
4856 void (*write_op)(struct tg3 *, u32, u32);
4857 int err;
4858
4859 tg3_nvram_lock(tp);
4860
4861 /* No matching tg3_nvram_unlock() after this because
4862 * chip reset below will undo the nvram lock.
4863 */
4864 tp->nvram_lock_cnt = 0;
4865
4866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4868 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4869 tw32(GRC_FASTBOOT_PC, 0);
4870
4871 /*
4872 * We must avoid the readl() that normally takes place.
4873 * It locks machines, causes machine checks, and other
4874 * fun things. So, temporarily disable the 5701
4875 * hardware workaround, while we do the reset.
4876 */
4877 write_op = tp->write32;
4878 if (write_op == tg3_write_flush_reg32)
4879 tp->write32 = tg3_write32;
4880
4881 /* Prevent the irq handler from reading or writing PCI registers
4882 * during chip reset when the memory enable bit in the PCI command
4883 * register may be cleared. The chip does not generate interrupt
4884 * at this time, but the irq handler may still be called due to irq
4885 * sharing or irqpoll.
4886 */
4887 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4888 if (tp->hw_status) {
4889 tp->hw_status->status = 0;
4890 tp->hw_status->status_tag = 0;
4891 }
4892 tp->last_tag = 0;
4893 smp_mb();
4894 synchronize_irq(tp->pdev->irq);
4895
4896 /* do the reset */
4897 val = GRC_MISC_CFG_CORECLK_RESET;
4898
4899 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4900 if (tr32(0x7e2c) == 0x60) {
4901 tw32(0x7e2c, 0x20);
4902 }
4903 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4904 tw32(GRC_MISC_CFG, (1 << 29));
4905 val |= (1 << 29);
4906 }
4907 }
4908
4909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4910 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4911 tw32(GRC_VCPU_EXT_CTRL,
4912 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4913 }
4914
4915 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4916 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4917 tw32(GRC_MISC_CFG, val);
4918
4919 /* restore 5701 hardware bug workaround write method */
4920 tp->write32 = write_op;
4921
4922 /* Unfortunately, we have to delay before the PCI read back.
4923 * Some 575X chips even will not respond to a PCI cfg access
4924 * when the reset command is given to the chip.
4925 *
4926 * How do these hardware designers expect things to work
4927 * properly if the PCI write is posted for a long period
4928 * of time? It is always necessary to have some method by
4929 * which a register read back can occur to push the write
4930 * out which does the reset.
4931 *
4932 * For most tg3 variants the trick below was working.
4933 * Ho hum...
4934 */
4935 udelay(120);
4936
4937 /* Flush PCI posted writes. The normal MMIO registers
4938 * are inaccessible at this time so this is the only
4939 * way to make this reliably (actually, this is no longer
4940 * the case, see above). I tried to use indirect
4941 * register read/write but this upset some 5701 variants.
4942 */
4943 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4944
4945 udelay(120);
4946
4947 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4948 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4949 int i;
4950 u32 cfg_val;
4951
4952 /* Wait for link training to complete. */
4953 for (i = 0; i < 5000; i++)
4954 udelay(100);
4955
4956 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4957 pci_write_config_dword(tp->pdev, 0xc4,
4958 cfg_val | (1 << 15));
4959 }
4960 /* Set PCIE max payload size and clear error status. */
4961 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4962 }
4963
4964 /* Re-enable indirect register accesses. */
4965 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4966 tp->misc_host_ctrl);
4967
4968 /* Set MAX PCI retry to zero. */
4969 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4970 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4971 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4972 val |= PCISTATE_RETRY_SAME_DMA;
4973 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4974
4975 pci_restore_state(tp->pdev);
4976
4977 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4978
4979 /* Make sure PCI-X relaxed ordering bit is clear. */
4980 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4981 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4982 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4983
4984 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4985 u32 val;
4986
4987 /* Chip reset on 5780 will reset MSI enable bit,
4988 * so need to restore it.
4989 */
4990 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4991 u16 ctrl;
4992
4993 pci_read_config_word(tp->pdev,
4994 tp->msi_cap + PCI_MSI_FLAGS,
4995 &ctrl);
4996 pci_write_config_word(tp->pdev,
4997 tp->msi_cap + PCI_MSI_FLAGS,
4998 ctrl | PCI_MSI_FLAGS_ENABLE);
4999 val = tr32(MSGINT_MODE);
5000 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5001 }
5002
5003 val = tr32(MEMARB_MODE);
5004 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5005
5006 } else
5007 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
5008
5009 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5010 tg3_stop_fw(tp);
5011 tw32(0x5000, 0x400);
5012 }
5013
5014 tw32(GRC_MODE, tp->grc_mode);
5015
5016 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5017 u32 val = tr32(0xc4);
5018
5019 tw32(0xc4, val | (1 << 15));
5020 }
5021
5022 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5024 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5025 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5026 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5027 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5028 }
5029
5030 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5031 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5032 tw32_f(MAC_MODE, tp->mac_mode);
5033 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5034 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5035 tw32_f(MAC_MODE, tp->mac_mode);
5036 } else
5037 tw32_f(MAC_MODE, 0);
5038 udelay(40);
5039
5040 err = tg3_poll_fw(tp);
5041 if (err)
5042 return err;
5043
5044 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5045 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5046 u32 val = tr32(0x7c00);
5047
5048 tw32(0x7c00, val | (1 << 25));
5049 }
5050
5051 /* Reprobe ASF enable state. */
5052 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5053 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5054 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5055 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5056 u32 nic_cfg;
5057
5058 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5059 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5060 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5061 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5062 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5063 }
5064 }
5065
5066 return 0;
5067 }
5068
5069 /* tp->lock is held. */
5070 static void tg3_stop_fw(struct tg3 *tp)
5071 {
5072 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5073 u32 val;
5074 int i;
5075
5076 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5077 val = tr32(GRC_RX_CPU_EVENT);
5078 val |= (1 << 14);
5079 tw32(GRC_RX_CPU_EVENT, val);
5080
5081 /* Wait for RX cpu to ACK the event. */
5082 for (i = 0; i < 100; i++) {
5083 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5084 break;
5085 udelay(1);
5086 }
5087 }
5088 }
5089
5090 /* tp->lock is held. */
5091 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5092 {
5093 int err;
5094
5095 tg3_stop_fw(tp);
5096
5097 tg3_write_sig_pre_reset(tp, kind);
5098
5099 tg3_abort_hw(tp, silent);
5100 err = tg3_chip_reset(tp);
5101
5102 tg3_write_sig_legacy(tp, kind);
5103 tg3_write_sig_post_reset(tp, kind);
5104
5105 if (err)
5106 return err;
5107
5108 return 0;
5109 }
5110
5111 #define TG3_FW_RELEASE_MAJOR 0x0
5112 #define TG3_FW_RELASE_MINOR 0x0
5113 #define TG3_FW_RELEASE_FIX 0x0
5114 #define TG3_FW_START_ADDR 0x08000000
5115 #define TG3_FW_TEXT_ADDR 0x08000000
5116 #define TG3_FW_TEXT_LEN 0x9c0
5117 #define TG3_FW_RODATA_ADDR 0x080009c0
5118 #define TG3_FW_RODATA_LEN 0x60
5119 #define TG3_FW_DATA_ADDR 0x08000a40
5120 #define TG3_FW_DATA_LEN 0x20
5121 #define TG3_FW_SBSS_ADDR 0x08000a60
5122 #define TG3_FW_SBSS_LEN 0xc
5123 #define TG3_FW_BSS_ADDR 0x08000a70
5124 #define TG3_FW_BSS_LEN 0x10
5125
5126 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5127 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5128 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5129 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5130 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5131 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5132 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5133 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5134 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5135 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5136 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5137 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5138 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5139 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5140 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5141 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5142 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5143 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5144 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5145 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5146 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5147 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5148 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5149 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5150 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5151 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5152 0, 0, 0, 0, 0, 0,
5153 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5154 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5155 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5156 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5157 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5158 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5159 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5160 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5161 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5162 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5163 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5164 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5165 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5166 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5167 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5168 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5169 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5170 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5171 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5172 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5173 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5174 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5175 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5176 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5177 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5178 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5179 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5180 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5181 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5182 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5183 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5184 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5185 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5186 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5187 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5188 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5189 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5190 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5191 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5192 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5193 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5194 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5195 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5196 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5197 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5198 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5199 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5200 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5201 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5202 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5203 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5204 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5205 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5206 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5207 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5208 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5209 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5210 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5211 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5212 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5213 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5214 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5215 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5216 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5217 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5218 };
5219
5220 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5221 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5222 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5223 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5224 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5225 0x00000000
5226 };
5227
5228 #if 0 /* All zeros, don't eat up space with it. */
5229 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5230 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5231 0x00000000, 0x00000000, 0x00000000, 0x00000000
5232 };
5233 #endif
5234
5235 #define RX_CPU_SCRATCH_BASE 0x30000
5236 #define RX_CPU_SCRATCH_SIZE 0x04000
5237 #define TX_CPU_SCRATCH_BASE 0x34000
5238 #define TX_CPU_SCRATCH_SIZE 0x04000
5239
5240 /* tp->lock is held. */
5241 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5242 {
5243 int i;
5244
5245 BUG_ON(offset == TX_CPU_BASE &&
5246 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5247
5248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5249 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5250
5251 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5252 return 0;
5253 }
5254 if (offset == RX_CPU_BASE) {
5255 for (i = 0; i < 10000; i++) {
5256 tw32(offset + CPU_STATE, 0xffffffff);
5257 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5258 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5259 break;
5260 }
5261
5262 tw32(offset + CPU_STATE, 0xffffffff);
5263 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5264 udelay(10);
5265 } else {
5266 for (i = 0; i < 10000; i++) {
5267 tw32(offset + CPU_STATE, 0xffffffff);
5268 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5269 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5270 break;
5271 }
5272 }
5273
5274 if (i >= 10000) {
5275 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5276 "and %s CPU\n",
5277 tp->dev->name,
5278 (offset == RX_CPU_BASE ? "RX" : "TX"));
5279 return -ENODEV;
5280 }
5281
5282 /* Clear firmware's nvram arbitration. */
5283 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5284 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5285 return 0;
5286 }
5287
5288 struct fw_info {
5289 unsigned int text_base;
5290 unsigned int text_len;
5291 const u32 *text_data;
5292 unsigned int rodata_base;
5293 unsigned int rodata_len;
5294 const u32 *rodata_data;
5295 unsigned int data_base;
5296 unsigned int data_len;
5297 const u32 *data_data;
5298 };
5299
5300 /* tp->lock is held. */
5301 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5302 int cpu_scratch_size, struct fw_info *info)
5303 {
5304 int err, lock_err, i;
5305 void (*write_op)(struct tg3 *, u32, u32);
5306
5307 if (cpu_base == TX_CPU_BASE &&
5308 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5309 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5310 "TX cpu firmware on %s which is 5705.\n",
5311 tp->dev->name);
5312 return -EINVAL;
5313 }
5314
5315 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5316 write_op = tg3_write_mem;
5317 else
5318 write_op = tg3_write_indirect_reg32;
5319
5320 /* It is possible that bootcode is still loading at this point.
5321 * Get the nvram lock first before halting the cpu.
5322 */
5323 lock_err = tg3_nvram_lock(tp);
5324 err = tg3_halt_cpu(tp, cpu_base);
5325 if (!lock_err)
5326 tg3_nvram_unlock(tp);
5327 if (err)
5328 goto out;
5329
5330 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5331 write_op(tp, cpu_scratch_base + i, 0);
5332 tw32(cpu_base + CPU_STATE, 0xffffffff);
5333 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5334 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5335 write_op(tp, (cpu_scratch_base +
5336 (info->text_base & 0xffff) +
5337 (i * sizeof(u32))),
5338 (info->text_data ?
5339 info->text_data[i] : 0));
5340 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5341 write_op(tp, (cpu_scratch_base +
5342 (info->rodata_base & 0xffff) +
5343 (i * sizeof(u32))),
5344 (info->rodata_data ?
5345 info->rodata_data[i] : 0));
5346 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5347 write_op(tp, (cpu_scratch_base +
5348 (info->data_base & 0xffff) +
5349 (i * sizeof(u32))),
5350 (info->data_data ?
5351 info->data_data[i] : 0));
5352
5353 err = 0;
5354
5355 out:
5356 return err;
5357 }
5358
5359 /* tp->lock is held. */
5360 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5361 {
5362 struct fw_info info;
5363 int err, i;
5364
5365 info.text_base = TG3_FW_TEXT_ADDR;
5366 info.text_len = TG3_FW_TEXT_LEN;
5367 info.text_data = &tg3FwText[0];
5368 info.rodata_base = TG3_FW_RODATA_ADDR;
5369 info.rodata_len = TG3_FW_RODATA_LEN;
5370 info.rodata_data = &tg3FwRodata[0];
5371 info.data_base = TG3_FW_DATA_ADDR;
5372 info.data_len = TG3_FW_DATA_LEN;
5373 info.data_data = NULL;
5374
5375 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5376 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5377 &info);
5378 if (err)
5379 return err;
5380
5381 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5382 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5383 &info);
5384 if (err)
5385 return err;
5386
5387 /* Now startup only the RX cpu. */
5388 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5389 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5390
5391 for (i = 0; i < 5; i++) {
5392 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5393 break;
5394 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5395 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5396 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5397 udelay(1000);
5398 }
5399 if (i >= 5) {
5400 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5401 "to set RX CPU PC, is %08x should be %08x\n",
5402 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5403 TG3_FW_TEXT_ADDR);
5404 return -ENODEV;
5405 }
5406 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5407 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5408
5409 return 0;
5410 }
5411
5412
5413 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5414 #define TG3_TSO_FW_RELASE_MINOR 0x6
5415 #define TG3_TSO_FW_RELEASE_FIX 0x0
5416 #define TG3_TSO_FW_START_ADDR 0x08000000
5417 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5418 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5419 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5420 #define TG3_TSO_FW_RODATA_LEN 0x60
5421 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5422 #define TG3_TSO_FW_DATA_LEN 0x30
5423 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5424 #define TG3_TSO_FW_SBSS_LEN 0x2c
5425 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5426 #define TG3_TSO_FW_BSS_LEN 0x894
5427
5428 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5429 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5430 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5431 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5432 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5433 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5434 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5435 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5436 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5437 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5438 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5439 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5440 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5441 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5442 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5443 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5444 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5445 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5446 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5447 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5448 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5449 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5450 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5451 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5452 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5453 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5454 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5455 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5456 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5457 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5458 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5459 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5460 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5461 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5462 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5463 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5464 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5465 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5466 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5467 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5468 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5469 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5470 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5471 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5472 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5473 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5474 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5475 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5476 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5477 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5478 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5479 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5480 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5481 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5482 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5483 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5484 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5485 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5486 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5487 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5488 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5489 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5490 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5491 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5492 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5493 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5494 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5495 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5496 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5497 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5498 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5499 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5500 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5501 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5502 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5503 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5504 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5505 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5506 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5507 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5508 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5509 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5510 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5511 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5512 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5513 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5514 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5515 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5516 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5517 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5518 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5519 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5520 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5521 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5522 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5523 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5524 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5525 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5526 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5527 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5528 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5529 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5530 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5531 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5532 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5533 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5534 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5535 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5536 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5537 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5538 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5539 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5540 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5541 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5542 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5543 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5544 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5545 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5546 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5547 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5548 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5549 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5550 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5551 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5552 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5553 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5554 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5555 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5556 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5557 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5558 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5559 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5560 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5561 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5562 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5563 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5564 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5565 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5566 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5567 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5568 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5569 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5570 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5571 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5572 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5573 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5574 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5575 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5576 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5577 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5578 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5579 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5580 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5581 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5582 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5583 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5584 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5585 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5586 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5587 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5588 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5589 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5590 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5591 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5592 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5593 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5594 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5595 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5596 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5597 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5598 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5599 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5600 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5601 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5602 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5603 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5604 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5605 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5606 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5607 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5608 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5609 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5610 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5611 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5612 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5613 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5614 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5615 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5616 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5617 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5618 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5619 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5620 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5621 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5622 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5623 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5624 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5625 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5626 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5627 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5628 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5629 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5630 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5631 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5632 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5633 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5634 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5635 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5636 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5637 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5638 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5639 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5640 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5641 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5642 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5643 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5644 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5645 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5646 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5647 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5648 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5649 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5650 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5651 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5652 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5653 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5654 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5655 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5656 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5657 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5658 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5659 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5660 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5661 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5662 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5663 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5664 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5665 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5666 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5667 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5668 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5669 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5670 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5671 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5672 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5673 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5674 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5675 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5676 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5677 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5678 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5679 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5680 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5681 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5682 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5683 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5684 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5685 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5686 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5687 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5688 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5689 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5690 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5691 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5692 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5693 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5694 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5695 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5696 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5697 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5698 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5699 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5700 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5701 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5702 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5703 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5704 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5705 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5706 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5707 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5708 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5709 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5710 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5711 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5712 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5713 };
5714
5715 static const u32 tg3TsoFwRodata[] = {
5716 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5717 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5718 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5719 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5720 0x00000000,
5721 };
5722
5723 static const u32 tg3TsoFwData[] = {
5724 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5725 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5726 0x00000000,
5727 };
5728
5729 /* 5705 needs a special version of the TSO firmware. */
5730 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5731 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5732 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5733 #define TG3_TSO5_FW_START_ADDR 0x00010000
5734 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5735 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5736 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5737 #define TG3_TSO5_FW_RODATA_LEN 0x50
5738 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5739 #define TG3_TSO5_FW_DATA_LEN 0x20
5740 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5741 #define TG3_TSO5_FW_SBSS_LEN 0x28
5742 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5743 #define TG3_TSO5_FW_BSS_LEN 0x88
5744
5745 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5746 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5747 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5748 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5749 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5750 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5751 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5752 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5753 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5754 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5755 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5756 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5757 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5758 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5759 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5760 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5761 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5762 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5763 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5764 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5765 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5766 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5767 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5768 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5769 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5770 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5771 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5772 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5773 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5774 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5775 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5776 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5777 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5778 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5779 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5780 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5781 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5782 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5783 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5784 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5785 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5786 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5787 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5788 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5789 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5790 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5791 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5792 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5793 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5794 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5795 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5796 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5797 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5798 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5799 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5800 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5801 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5802 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5803 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5804 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5805 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5806 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5807 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5808 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5809 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5810 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5811 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5812 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5813 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5814 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5815 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5816 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5817 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5818 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5819 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5820 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5821 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5822 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5823 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5824 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5825 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5826 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5827 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5828 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5829 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5830 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5831 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5832 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5833 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5834 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5835 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5836 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5837 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5838 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5839 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5840 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5841 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5842 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5843 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5844 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5845 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5846 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5847 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5848 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5849 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5850 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5851 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5852 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5853 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5854 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5855 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5856 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5857 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5858 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5859 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5860 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5861 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5862 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5863 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5864 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5865 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5866 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5867 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5868 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5869 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5870 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5871 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5872 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5873 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5874 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5875 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5876 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5877 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5878 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5879 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5880 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5881 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5882 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5883 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5884 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5885 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5886 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5887 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5888 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5889 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5890 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5891 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5892 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5893 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5894 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5895 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5896 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5897 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5898 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5899 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5900 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5901 0x00000000, 0x00000000, 0x00000000,
5902 };
5903
5904 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5905 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5906 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5907 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5908 0x00000000, 0x00000000, 0x00000000,
5909 };
5910
5911 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5912 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5913 0x00000000, 0x00000000, 0x00000000,
5914 };
5915
5916 /* tp->lock is held. */
5917 static int tg3_load_tso_firmware(struct tg3 *tp)
5918 {
5919 struct fw_info info;
5920 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5921 int err, i;
5922
5923 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5924 return 0;
5925
5926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5927 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5928 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5929 info.text_data = &tg3Tso5FwText[0];
5930 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5931 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5932 info.rodata_data = &tg3Tso5FwRodata[0];
5933 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5934 info.data_len = TG3_TSO5_FW_DATA_LEN;
5935 info.data_data = &tg3Tso5FwData[0];
5936 cpu_base = RX_CPU_BASE;
5937 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5938 cpu_scratch_size = (info.text_len +
5939 info.rodata_len +
5940 info.data_len +
5941 TG3_TSO5_FW_SBSS_LEN +
5942 TG3_TSO5_FW_BSS_LEN);
5943 } else {
5944 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5945 info.text_len = TG3_TSO_FW_TEXT_LEN;
5946 info.text_data = &tg3TsoFwText[0];
5947 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5948 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5949 info.rodata_data = &tg3TsoFwRodata[0];
5950 info.data_base = TG3_TSO_FW_DATA_ADDR;
5951 info.data_len = TG3_TSO_FW_DATA_LEN;
5952 info.data_data = &tg3TsoFwData[0];
5953 cpu_base = TX_CPU_BASE;
5954 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5955 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5956 }
5957
5958 err = tg3_load_firmware_cpu(tp, cpu_base,
5959 cpu_scratch_base, cpu_scratch_size,
5960 &info);
5961 if (err)
5962 return err;
5963
5964 /* Now startup the cpu. */
5965 tw32(cpu_base + CPU_STATE, 0xffffffff);
5966 tw32_f(cpu_base + CPU_PC, info.text_base);
5967
5968 for (i = 0; i < 5; i++) {
5969 if (tr32(cpu_base + CPU_PC) == info.text_base)
5970 break;
5971 tw32(cpu_base + CPU_STATE, 0xffffffff);
5972 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5973 tw32_f(cpu_base + CPU_PC, info.text_base);
5974 udelay(1000);
5975 }
5976 if (i >= 5) {
5977 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5978 "to set CPU PC, is %08x should be %08x\n",
5979 tp->dev->name, tr32(cpu_base + CPU_PC),
5980 info.text_base);
5981 return -ENODEV;
5982 }
5983 tw32(cpu_base + CPU_STATE, 0xffffffff);
5984 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5985 return 0;
5986 }
5987
5988
5989 /* tp->lock is held. */
5990 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
5991 {
5992 u32 addr_high, addr_low;
5993 int i;
5994
5995 addr_high = ((tp->dev->dev_addr[0] << 8) |
5996 tp->dev->dev_addr[1]);
5997 addr_low = ((tp->dev->dev_addr[2] << 24) |
5998 (tp->dev->dev_addr[3] << 16) |
5999 (tp->dev->dev_addr[4] << 8) |
6000 (tp->dev->dev_addr[5] << 0));
6001 for (i = 0; i < 4; i++) {
6002 if (i == 1 && skip_mac_1)
6003 continue;
6004 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6005 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6006 }
6007
6008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6010 for (i = 0; i < 12; i++) {
6011 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6012 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6013 }
6014 }
6015
6016 addr_high = (tp->dev->dev_addr[0] +
6017 tp->dev->dev_addr[1] +
6018 tp->dev->dev_addr[2] +
6019 tp->dev->dev_addr[3] +
6020 tp->dev->dev_addr[4] +
6021 tp->dev->dev_addr[5]) &
6022 TX_BACKOFF_SEED_MASK;
6023 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6024 }
6025
6026 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6027 {
6028 struct tg3 *tp = netdev_priv(dev);
6029 struct sockaddr *addr = p;
6030 int err = 0, skip_mac_1 = 0;
6031
6032 if (!is_valid_ether_addr(addr->sa_data))
6033 return -EINVAL;
6034
6035 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6036
6037 if (!netif_running(dev))
6038 return 0;
6039
6040 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6041 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6042
6043 addr0_high = tr32(MAC_ADDR_0_HIGH);
6044 addr0_low = tr32(MAC_ADDR_0_LOW);
6045 addr1_high = tr32(MAC_ADDR_1_HIGH);
6046 addr1_low = tr32(MAC_ADDR_1_LOW);
6047
6048 /* Skip MAC addr 1 if ASF is using it. */
6049 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6050 !(addr1_high == 0 && addr1_low == 0))
6051 skip_mac_1 = 1;
6052 }
6053 spin_lock_bh(&tp->lock);
6054 __tg3_set_mac_addr(tp, skip_mac_1);
6055 spin_unlock_bh(&tp->lock);
6056
6057 return err;
6058 }
6059
6060 /* tp->lock is held. */
6061 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6062 dma_addr_t mapping, u32 maxlen_flags,
6063 u32 nic_addr)
6064 {
6065 tg3_write_mem(tp,
6066 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6067 ((u64) mapping >> 32));
6068 tg3_write_mem(tp,
6069 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6070 ((u64) mapping & 0xffffffff));
6071 tg3_write_mem(tp,
6072 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6073 maxlen_flags);
6074
6075 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6076 tg3_write_mem(tp,
6077 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6078 nic_addr);
6079 }
6080
6081 static void __tg3_set_rx_mode(struct net_device *);
6082 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6083 {
6084 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6085 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6086 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6087 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6088 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6089 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6090 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6091 }
6092 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6093 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6094 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6095 u32 val = ec->stats_block_coalesce_usecs;
6096
6097 if (!netif_carrier_ok(tp->dev))
6098 val = 0;
6099
6100 tw32(HOSTCC_STAT_COAL_TICKS, val);
6101 }
6102 }
6103
6104 /* tp->lock is held. */
6105 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6106 {
6107 u32 val, rdmac_mode;
6108 int i, err, limit;
6109
6110 tg3_disable_ints(tp);
6111
6112 tg3_stop_fw(tp);
6113
6114 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6115
6116 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6117 tg3_abort_hw(tp, 1);
6118 }
6119
6120 if (reset_phy)
6121 tg3_phy_reset(tp);
6122
6123 err = tg3_chip_reset(tp);
6124 if (err)
6125 return err;
6126
6127 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6128
6129 /* This works around an issue with Athlon chipsets on
6130 * B3 tigon3 silicon. This bit has no effect on any
6131 * other revision. But do not set this on PCI Express
6132 * chips.
6133 */
6134 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6135 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6136 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6137
6138 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6139 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6140 val = tr32(TG3PCI_PCISTATE);
6141 val |= PCISTATE_RETRY_SAME_DMA;
6142 tw32(TG3PCI_PCISTATE, val);
6143 }
6144
6145 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6146 /* Enable some hw fixes. */
6147 val = tr32(TG3PCI_MSI_DATA);
6148 val |= (1 << 26) | (1 << 28) | (1 << 29);
6149 tw32(TG3PCI_MSI_DATA, val);
6150 }
6151
6152 /* Descriptor ring init may make accesses to the
6153 * NIC SRAM area to setup the TX descriptors, so we
6154 * can only do this after the hardware has been
6155 * successfully reset.
6156 */
6157 err = tg3_init_rings(tp);
6158 if (err)
6159 return err;
6160
6161 /* This value is determined during the probe time DMA
6162 * engine test, tg3_test_dma.
6163 */
6164 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6165
6166 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6167 GRC_MODE_4X_NIC_SEND_RINGS |
6168 GRC_MODE_NO_TX_PHDR_CSUM |
6169 GRC_MODE_NO_RX_PHDR_CSUM);
6170 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6171
6172 /* Pseudo-header checksum is done by hardware logic and not
6173 * the offload processers, so make the chip do the pseudo-
6174 * header checksums on receive. For transmit it is more
6175 * convenient to do the pseudo-header checksum in software
6176 * as Linux does that on transmit for us in all cases.
6177 */
6178 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6179
6180 tw32(GRC_MODE,
6181 tp->grc_mode |
6182 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6183
6184 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6185 val = tr32(GRC_MISC_CFG);
6186 val &= ~0xff;
6187 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6188 tw32(GRC_MISC_CFG, val);
6189
6190 /* Initialize MBUF/DESC pool. */
6191 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6192 /* Do nothing. */
6193 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6194 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6196 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6197 else
6198 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6199 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6200 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6201 }
6202 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6203 int fw_len;
6204
6205 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6206 TG3_TSO5_FW_RODATA_LEN +
6207 TG3_TSO5_FW_DATA_LEN +
6208 TG3_TSO5_FW_SBSS_LEN +
6209 TG3_TSO5_FW_BSS_LEN);
6210 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6211 tw32(BUFMGR_MB_POOL_ADDR,
6212 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6213 tw32(BUFMGR_MB_POOL_SIZE,
6214 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6215 }
6216
6217 if (tp->dev->mtu <= ETH_DATA_LEN) {
6218 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6219 tp->bufmgr_config.mbuf_read_dma_low_water);
6220 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6221 tp->bufmgr_config.mbuf_mac_rx_low_water);
6222 tw32(BUFMGR_MB_HIGH_WATER,
6223 tp->bufmgr_config.mbuf_high_water);
6224 } else {
6225 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6226 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6227 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6228 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6229 tw32(BUFMGR_MB_HIGH_WATER,
6230 tp->bufmgr_config.mbuf_high_water_jumbo);
6231 }
6232 tw32(BUFMGR_DMA_LOW_WATER,
6233 tp->bufmgr_config.dma_low_water);
6234 tw32(BUFMGR_DMA_HIGH_WATER,
6235 tp->bufmgr_config.dma_high_water);
6236
6237 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6238 for (i = 0; i < 2000; i++) {
6239 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6240 break;
6241 udelay(10);
6242 }
6243 if (i >= 2000) {
6244 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6245 tp->dev->name);
6246 return -ENODEV;
6247 }
6248
6249 /* Setup replenish threshold. */
6250 val = tp->rx_pending / 8;
6251 if (val == 0)
6252 val = 1;
6253 else if (val > tp->rx_std_max_post)
6254 val = tp->rx_std_max_post;
6255 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6256 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6257 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6258
6259 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6260 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6261 }
6262
6263 tw32(RCVBDI_STD_THRESH, val);
6264
6265 /* Initialize TG3_BDINFO's at:
6266 * RCVDBDI_STD_BD: standard eth size rx ring
6267 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6268 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6269 *
6270 * like so:
6271 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6272 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6273 * ring attribute flags
6274 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6275 *
6276 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6277 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6278 *
6279 * The size of each ring is fixed in the firmware, but the location is
6280 * configurable.
6281 */
6282 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6283 ((u64) tp->rx_std_mapping >> 32));
6284 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6285 ((u64) tp->rx_std_mapping & 0xffffffff));
6286 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6287 NIC_SRAM_RX_BUFFER_DESC);
6288
6289 /* Don't even try to program the JUMBO/MINI buffer descriptor
6290 * configs on 5705.
6291 */
6292 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6293 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6294 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6295 } else {
6296 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6297 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6298
6299 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6300 BDINFO_FLAGS_DISABLED);
6301
6302 /* Setup replenish threshold. */
6303 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6304
6305 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6306 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6307 ((u64) tp->rx_jumbo_mapping >> 32));
6308 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6309 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6310 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6311 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6312 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6313 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6314 } else {
6315 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6316 BDINFO_FLAGS_DISABLED);
6317 }
6318
6319 }
6320
6321 /* There is only one send ring on 5705/5750, no need to explicitly
6322 * disable the others.
6323 */
6324 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6325 /* Clear out send RCB ring in SRAM. */
6326 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6327 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6328 BDINFO_FLAGS_DISABLED);
6329 }
6330
6331 tp->tx_prod = 0;
6332 tp->tx_cons = 0;
6333 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6334 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6335
6336 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6337 tp->tx_desc_mapping,
6338 (TG3_TX_RING_SIZE <<
6339 BDINFO_FLAGS_MAXLEN_SHIFT),
6340 NIC_SRAM_TX_BUFFER_DESC);
6341
6342 /* There is only one receive return ring on 5705/5750, no need
6343 * to explicitly disable the others.
6344 */
6345 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6346 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6347 i += TG3_BDINFO_SIZE) {
6348 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6349 BDINFO_FLAGS_DISABLED);
6350 }
6351 }
6352
6353 tp->rx_rcb_ptr = 0;
6354 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6355
6356 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6357 tp->rx_rcb_mapping,
6358 (TG3_RX_RCB_RING_SIZE(tp) <<
6359 BDINFO_FLAGS_MAXLEN_SHIFT),
6360 0);
6361
6362 tp->rx_std_ptr = tp->rx_pending;
6363 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6364 tp->rx_std_ptr);
6365
6366 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6367 tp->rx_jumbo_pending : 0;
6368 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6369 tp->rx_jumbo_ptr);
6370
6371 /* Initialize MAC address and backoff seed. */
6372 __tg3_set_mac_addr(tp, 0);
6373
6374 /* MTU + ethernet header + FCS + optional VLAN tag */
6375 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6376
6377 /* The slot time is changed by tg3_setup_phy if we
6378 * run at gigabit with half duplex.
6379 */
6380 tw32(MAC_TX_LENGTHS,
6381 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6382 (6 << TX_LENGTHS_IPG_SHIFT) |
6383 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6384
6385 /* Receive rules. */
6386 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6387 tw32(RCVLPC_CONFIG, 0x0181);
6388
6389 /* Calculate RDMAC_MODE setting early, we need it to determine
6390 * the RCVLPC_STATE_ENABLE mask.
6391 */
6392 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6393 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6394 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6395 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6396 RDMAC_MODE_LNGREAD_ENAB);
6397
6398 /* If statement applies to 5705 and 5750 PCI devices only */
6399 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6400 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6401 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6402 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6403 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6404 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6405 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6406 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6407 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6408 }
6409 }
6410
6411 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6412 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6413
6414 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6415 rdmac_mode |= (1 << 27);
6416
6417 /* Receive/send statistics. */
6418 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6419 val = tr32(RCVLPC_STATS_ENABLE);
6420 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6421 tw32(RCVLPC_STATS_ENABLE, val);
6422 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6423 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6424 val = tr32(RCVLPC_STATS_ENABLE);
6425 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6426 tw32(RCVLPC_STATS_ENABLE, val);
6427 } else {
6428 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6429 }
6430 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6431 tw32(SNDDATAI_STATSENAB, 0xffffff);
6432 tw32(SNDDATAI_STATSCTRL,
6433 (SNDDATAI_SCTRL_ENABLE |
6434 SNDDATAI_SCTRL_FASTUPD));
6435
6436 /* Setup host coalescing engine. */
6437 tw32(HOSTCC_MODE, 0);
6438 for (i = 0; i < 2000; i++) {
6439 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6440 break;
6441 udelay(10);
6442 }
6443
6444 __tg3_set_coalesce(tp, &tp->coal);
6445
6446 /* set status block DMA address */
6447 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6448 ((u64) tp->status_mapping >> 32));
6449 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6450 ((u64) tp->status_mapping & 0xffffffff));
6451
6452 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6453 /* Status/statistics block address. See tg3_timer,
6454 * the tg3_periodic_fetch_stats call there, and
6455 * tg3_get_stats to see how this works for 5705/5750 chips.
6456 */
6457 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6458 ((u64) tp->stats_mapping >> 32));
6459 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6460 ((u64) tp->stats_mapping & 0xffffffff));
6461 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6462 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6463 }
6464
6465 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6466
6467 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6468 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6469 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6470 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6471
6472 /* Clear statistics/status block in chip, and status block in ram. */
6473 for (i = NIC_SRAM_STATS_BLK;
6474 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6475 i += sizeof(u32)) {
6476 tg3_write_mem(tp, i, 0);
6477 udelay(40);
6478 }
6479 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6480
6481 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6482 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6483 /* reset to prevent losing 1st rx packet intermittently */
6484 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6485 udelay(10);
6486 }
6487
6488 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6489 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6490 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6491 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6492 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6493 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6494 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6495 udelay(40);
6496
6497 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6498 * If TG3_FLG2_IS_NIC is zero, we should read the
6499 * register to preserve the GPIO settings for LOMs. The GPIOs,
6500 * whether used as inputs or outputs, are set by boot code after
6501 * reset.
6502 */
6503 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6504 u32 gpio_mask;
6505
6506 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6507 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6508 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6509
6510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6511 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6512 GRC_LCLCTRL_GPIO_OUTPUT3;
6513
6514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6515 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6516
6517 tp->grc_local_ctrl &= ~gpio_mask;
6518 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6519
6520 /* GPIO1 must be driven high for eeprom write protect */
6521 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6522 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6523 GRC_LCLCTRL_GPIO_OUTPUT1);
6524 }
6525 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6526 udelay(100);
6527
6528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6529 tp->last_tag = 0;
6530
6531 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6532 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6533 udelay(40);
6534 }
6535
6536 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6537 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6538 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6539 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6540 WDMAC_MODE_LNGREAD_ENAB);
6541
6542 /* If statement applies to 5705 and 5750 PCI devices only */
6543 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6544 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6546 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6547 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6548 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6549 /* nothing */
6550 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6551 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6552 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6553 val |= WDMAC_MODE_RX_ACCEL;
6554 }
6555 }
6556
6557 /* Enable host coalescing bug fix */
6558 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6559 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6560 val |= (1 << 29);
6561
6562 tw32_f(WDMAC_MODE, val);
6563 udelay(40);
6564
6565 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6566 val = tr32(TG3PCI_X_CAPS);
6567 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6568 val &= ~PCIX_CAPS_BURST_MASK;
6569 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6570 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6571 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6572 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6573 }
6574 tw32(TG3PCI_X_CAPS, val);
6575 }
6576
6577 tw32_f(RDMAC_MODE, rdmac_mode);
6578 udelay(40);
6579
6580 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6581 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6582 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6583 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6584 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6585 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6586 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6587 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6588 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6589 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6590 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6591 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6592
6593 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6594 err = tg3_load_5701_a0_firmware_fix(tp);
6595 if (err)
6596 return err;
6597 }
6598
6599 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6600 err = tg3_load_tso_firmware(tp);
6601 if (err)
6602 return err;
6603 }
6604
6605 tp->tx_mode = TX_MODE_ENABLE;
6606 tw32_f(MAC_TX_MODE, tp->tx_mode);
6607 udelay(100);
6608
6609 tp->rx_mode = RX_MODE_ENABLE;
6610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6611 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6612
6613 tw32_f(MAC_RX_MODE, tp->rx_mode);
6614 udelay(10);
6615
6616 if (tp->link_config.phy_is_low_power) {
6617 tp->link_config.phy_is_low_power = 0;
6618 tp->link_config.speed = tp->link_config.orig_speed;
6619 tp->link_config.duplex = tp->link_config.orig_duplex;
6620 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6621 }
6622
6623 tp->mi_mode = MAC_MI_MODE_BASE;
6624 tw32_f(MAC_MI_MODE, tp->mi_mode);
6625 udelay(80);
6626
6627 tw32(MAC_LED_CTRL, tp->led_ctrl);
6628
6629 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6630 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6631 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6632 udelay(10);
6633 }
6634 tw32_f(MAC_RX_MODE, tp->rx_mode);
6635 udelay(10);
6636
6637 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6638 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6639 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6640 /* Set drive transmission level to 1.2V */
6641 /* only if the signal pre-emphasis bit is not set */
6642 val = tr32(MAC_SERDES_CFG);
6643 val &= 0xfffff000;
6644 val |= 0x880;
6645 tw32(MAC_SERDES_CFG, val);
6646 }
6647 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6648 tw32(MAC_SERDES_CFG, 0x616000);
6649 }
6650
6651 /* Prevent chip from dropping frames when flow control
6652 * is enabled.
6653 */
6654 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6655
6656 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6657 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6658 /* Use hardware link auto-negotiation */
6659 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6660 }
6661
6662 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6663 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6664 u32 tmp;
6665
6666 tmp = tr32(SERDES_RX_CTRL);
6667 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6668 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6669 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6670 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6671 }
6672
6673 err = tg3_setup_phy(tp, 0);
6674 if (err)
6675 return err;
6676
6677 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6678 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6679 u32 tmp;
6680
6681 /* Clear CRC stats. */
6682 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6683 tg3_writephy(tp, MII_TG3_TEST1,
6684 tmp | MII_TG3_TEST1_CRC_EN);
6685 tg3_readphy(tp, 0x14, &tmp);
6686 }
6687 }
6688
6689 __tg3_set_rx_mode(tp->dev);
6690
6691 /* Initialize receive rules. */
6692 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6693 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6694 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6695 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6696
6697 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6698 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6699 limit = 8;
6700 else
6701 limit = 16;
6702 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6703 limit -= 4;
6704 switch (limit) {
6705 case 16:
6706 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6707 case 15:
6708 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6709 case 14:
6710 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6711 case 13:
6712 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6713 case 12:
6714 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6715 case 11:
6716 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6717 case 10:
6718 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6719 case 9:
6720 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6721 case 8:
6722 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6723 case 7:
6724 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6725 case 6:
6726 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6727 case 5:
6728 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6729 case 4:
6730 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6731 case 3:
6732 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6733 case 2:
6734 case 1:
6735
6736 default:
6737 break;
6738 };
6739
6740 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6741
6742 return 0;
6743 }
6744
6745 /* Called at device open time to get the chip ready for
6746 * packet processing. Invoked with tp->lock held.
6747 */
6748 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6749 {
6750 int err;
6751
6752 /* Force the chip into D0. */
6753 err = tg3_set_power_state(tp, PCI_D0);
6754 if (err)
6755 goto out;
6756
6757 tg3_switch_clocks(tp);
6758
6759 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6760
6761 err = tg3_reset_hw(tp, reset_phy);
6762
6763 out:
6764 return err;
6765 }
6766
6767 #define TG3_STAT_ADD32(PSTAT, REG) \
6768 do { u32 __val = tr32(REG); \
6769 (PSTAT)->low += __val; \
6770 if ((PSTAT)->low < __val) \
6771 (PSTAT)->high += 1; \
6772 } while (0)
6773
6774 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6775 {
6776 struct tg3_hw_stats *sp = tp->hw_stats;
6777
6778 if (!netif_carrier_ok(tp->dev))
6779 return;
6780
6781 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6782 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6783 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6784 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6785 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6786 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6787 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6788 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6789 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6790 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6791 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6792 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6793 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6794
6795 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6796 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6797 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6798 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6799 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6800 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6801 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6802 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6803 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6804 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6805 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6806 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6807 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6808 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6809
6810 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6811 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6812 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6813 }
6814
6815 static void tg3_timer(unsigned long __opaque)
6816 {
6817 struct tg3 *tp = (struct tg3 *) __opaque;
6818
6819 if (tp->irq_sync)
6820 goto restart_timer;
6821
6822 spin_lock(&tp->lock);
6823
6824 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6825 /* All of this garbage is because when using non-tagged
6826 * IRQ status the mailbox/status_block protocol the chip
6827 * uses with the cpu is race prone.
6828 */
6829 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6830 tw32(GRC_LOCAL_CTRL,
6831 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6832 } else {
6833 tw32(HOSTCC_MODE, tp->coalesce_mode |
6834 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6835 }
6836
6837 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6838 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6839 spin_unlock(&tp->lock);
6840 schedule_work(&tp->reset_task);
6841 return;
6842 }
6843 }
6844
6845 /* This part only runs once per second. */
6846 if (!--tp->timer_counter) {
6847 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6848 tg3_periodic_fetch_stats(tp);
6849
6850 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6851 u32 mac_stat;
6852 int phy_event;
6853
6854 mac_stat = tr32(MAC_STATUS);
6855
6856 phy_event = 0;
6857 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6858 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6859 phy_event = 1;
6860 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6861 phy_event = 1;
6862
6863 if (phy_event)
6864 tg3_setup_phy(tp, 0);
6865 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6866 u32 mac_stat = tr32(MAC_STATUS);
6867 int need_setup = 0;
6868
6869 if (netif_carrier_ok(tp->dev) &&
6870 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6871 need_setup = 1;
6872 }
6873 if (! netif_carrier_ok(tp->dev) &&
6874 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6875 MAC_STATUS_SIGNAL_DET))) {
6876 need_setup = 1;
6877 }
6878 if (need_setup) {
6879 if (!tp->serdes_counter) {
6880 tw32_f(MAC_MODE,
6881 (tp->mac_mode &
6882 ~MAC_MODE_PORT_MODE_MASK));
6883 udelay(40);
6884 tw32_f(MAC_MODE, tp->mac_mode);
6885 udelay(40);
6886 }
6887 tg3_setup_phy(tp, 0);
6888 }
6889 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6890 tg3_serdes_parallel_detect(tp);
6891
6892 tp->timer_counter = tp->timer_multiplier;
6893 }
6894
6895 /* Heartbeat is only sent once every 2 seconds.
6896 *
6897 * The heartbeat is to tell the ASF firmware that the host
6898 * driver is still alive. In the event that the OS crashes,
6899 * ASF needs to reset the hardware to free up the FIFO space
6900 * that may be filled with rx packets destined for the host.
6901 * If the FIFO is full, ASF will no longer function properly.
6902 *
6903 * Unintended resets have been reported on real time kernels
6904 * where the timer doesn't run on time. Netpoll will also have
6905 * same problem.
6906 *
6907 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6908 * to check the ring condition when the heartbeat is expiring
6909 * before doing the reset. This will prevent most unintended
6910 * resets.
6911 */
6912 if (!--tp->asf_counter) {
6913 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6914 u32 val;
6915
6916 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6917 FWCMD_NICDRV_ALIVE3);
6918 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6919 /* 5 seconds timeout */
6920 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6921 val = tr32(GRC_RX_CPU_EVENT);
6922 val |= (1 << 14);
6923 tw32(GRC_RX_CPU_EVENT, val);
6924 }
6925 tp->asf_counter = tp->asf_multiplier;
6926 }
6927
6928 spin_unlock(&tp->lock);
6929
6930 restart_timer:
6931 tp->timer.expires = jiffies + tp->timer_offset;
6932 add_timer(&tp->timer);
6933 }
6934
6935 static int tg3_request_irq(struct tg3 *tp)
6936 {
6937 irq_handler_t fn;
6938 unsigned long flags;
6939 struct net_device *dev = tp->dev;
6940
6941 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6942 fn = tg3_msi;
6943 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6944 fn = tg3_msi_1shot;
6945 flags = IRQF_SAMPLE_RANDOM;
6946 } else {
6947 fn = tg3_interrupt;
6948 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6949 fn = tg3_interrupt_tagged;
6950 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6951 }
6952 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6953 }
6954
6955 static int tg3_test_interrupt(struct tg3 *tp)
6956 {
6957 struct net_device *dev = tp->dev;
6958 int err, i, intr_ok = 0;
6959
6960 if (!netif_running(dev))
6961 return -ENODEV;
6962
6963 tg3_disable_ints(tp);
6964
6965 free_irq(tp->pdev->irq, dev);
6966
6967 err = request_irq(tp->pdev->irq, tg3_test_isr,
6968 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6969 if (err)
6970 return err;
6971
6972 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6973 tg3_enable_ints(tp);
6974
6975 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6976 HOSTCC_MODE_NOW);
6977
6978 for (i = 0; i < 5; i++) {
6979 u32 int_mbox, misc_host_ctrl;
6980
6981 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6982 TG3_64BIT_REG_LOW);
6983 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6984
6985 if ((int_mbox != 0) ||
6986 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6987 intr_ok = 1;
6988 break;
6989 }
6990
6991 msleep(10);
6992 }
6993
6994 tg3_disable_ints(tp);
6995
6996 free_irq(tp->pdev->irq, dev);
6997
6998 err = tg3_request_irq(tp);
6999
7000 if (err)
7001 return err;
7002
7003 if (intr_ok)
7004 return 0;
7005
7006 return -EIO;
7007 }
7008
7009 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7010 * successfully restored
7011 */
7012 static int tg3_test_msi(struct tg3 *tp)
7013 {
7014 struct net_device *dev = tp->dev;
7015 int err;
7016 u16 pci_cmd;
7017
7018 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7019 return 0;
7020
7021 /* Turn off SERR reporting in case MSI terminates with Master
7022 * Abort.
7023 */
7024 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7025 pci_write_config_word(tp->pdev, PCI_COMMAND,
7026 pci_cmd & ~PCI_COMMAND_SERR);
7027
7028 err = tg3_test_interrupt(tp);
7029
7030 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7031
7032 if (!err)
7033 return 0;
7034
7035 /* other failures */
7036 if (err != -EIO)
7037 return err;
7038
7039 /* MSI test failed, go back to INTx mode */
7040 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7041 "switching to INTx mode. Please report this failure to "
7042 "the PCI maintainer and include system chipset information.\n",
7043 tp->dev->name);
7044
7045 free_irq(tp->pdev->irq, dev);
7046 pci_disable_msi(tp->pdev);
7047
7048 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7049
7050 err = tg3_request_irq(tp);
7051 if (err)
7052 return err;
7053
7054 /* Need to reset the chip because the MSI cycle may have terminated
7055 * with Master Abort.
7056 */
7057 tg3_full_lock(tp, 1);
7058
7059 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7060 err = tg3_init_hw(tp, 1);
7061
7062 tg3_full_unlock(tp);
7063
7064 if (err)
7065 free_irq(tp->pdev->irq, dev);
7066
7067 return err;
7068 }
7069
7070 static int tg3_open(struct net_device *dev)
7071 {
7072 struct tg3 *tp = netdev_priv(dev);
7073 int err;
7074
7075 netif_carrier_off(tp->dev);
7076
7077 tg3_full_lock(tp, 0);
7078
7079 err = tg3_set_power_state(tp, PCI_D0);
7080 if (err) {
7081 tg3_full_unlock(tp);
7082 return err;
7083 }
7084
7085 tg3_disable_ints(tp);
7086 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7087
7088 tg3_full_unlock(tp);
7089
7090 /* The placement of this call is tied
7091 * to the setup and use of Host TX descriptors.
7092 */
7093 err = tg3_alloc_consistent(tp);
7094 if (err)
7095 return err;
7096
7097 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7098 /* All MSI supporting chips should support tagged
7099 * status. Assert that this is the case.
7100 */
7101 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7102 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7103 "Not using MSI.\n", tp->dev->name);
7104 } else if (pci_enable_msi(tp->pdev) == 0) {
7105 u32 msi_mode;
7106
7107 msi_mode = tr32(MSGINT_MODE);
7108 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7109 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7110 }
7111 }
7112 err = tg3_request_irq(tp);
7113
7114 if (err) {
7115 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7116 pci_disable_msi(tp->pdev);
7117 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7118 }
7119 tg3_free_consistent(tp);
7120 return err;
7121 }
7122
7123 tg3_full_lock(tp, 0);
7124
7125 err = tg3_init_hw(tp, 1);
7126 if (err) {
7127 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7128 tg3_free_rings(tp);
7129 } else {
7130 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7131 tp->timer_offset = HZ;
7132 else
7133 tp->timer_offset = HZ / 10;
7134
7135 BUG_ON(tp->timer_offset > HZ);
7136 tp->timer_counter = tp->timer_multiplier =
7137 (HZ / tp->timer_offset);
7138 tp->asf_counter = tp->asf_multiplier =
7139 ((HZ / tp->timer_offset) * 2);
7140
7141 init_timer(&tp->timer);
7142 tp->timer.expires = jiffies + tp->timer_offset;
7143 tp->timer.data = (unsigned long) tp;
7144 tp->timer.function = tg3_timer;
7145 }
7146
7147 tg3_full_unlock(tp);
7148
7149 if (err) {
7150 free_irq(tp->pdev->irq, dev);
7151 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7152 pci_disable_msi(tp->pdev);
7153 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7154 }
7155 tg3_free_consistent(tp);
7156 return err;
7157 }
7158
7159 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7160 err = tg3_test_msi(tp);
7161
7162 if (err) {
7163 tg3_full_lock(tp, 0);
7164
7165 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7166 pci_disable_msi(tp->pdev);
7167 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7168 }
7169 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7170 tg3_free_rings(tp);
7171 tg3_free_consistent(tp);
7172
7173 tg3_full_unlock(tp);
7174
7175 return err;
7176 }
7177
7178 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7179 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7180 u32 val = tr32(PCIE_TRANSACTION_CFG);
7181
7182 tw32(PCIE_TRANSACTION_CFG,
7183 val | PCIE_TRANS_CFG_1SHOT_MSI);
7184 }
7185 }
7186 }
7187
7188 tg3_full_lock(tp, 0);
7189
7190 add_timer(&tp->timer);
7191 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7192 tg3_enable_ints(tp);
7193
7194 tg3_full_unlock(tp);
7195
7196 netif_start_queue(dev);
7197
7198 return 0;
7199 }
7200
7201 #if 0
7202 /*static*/ void tg3_dump_state(struct tg3 *tp)
7203 {
7204 u32 val32, val32_2, val32_3, val32_4, val32_5;
7205 u16 val16;
7206 int i;
7207
7208 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7209 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7210 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7211 val16, val32);
7212
7213 /* MAC block */
7214 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7215 tr32(MAC_MODE), tr32(MAC_STATUS));
7216 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7217 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7218 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7219 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7220 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7221 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7222
7223 /* Send data initiator control block */
7224 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7225 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7226 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7227 tr32(SNDDATAI_STATSCTRL));
7228
7229 /* Send data completion control block */
7230 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7231
7232 /* Send BD ring selector block */
7233 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7234 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7235
7236 /* Send BD initiator control block */
7237 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7238 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7239
7240 /* Send BD completion control block */
7241 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7242
7243 /* Receive list placement control block */
7244 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7245 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7246 printk(" RCVLPC_STATSCTRL[%08x]\n",
7247 tr32(RCVLPC_STATSCTRL));
7248
7249 /* Receive data and receive BD initiator control block */
7250 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7251 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7252
7253 /* Receive data completion control block */
7254 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7255 tr32(RCVDCC_MODE));
7256
7257 /* Receive BD initiator control block */
7258 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7259 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7260
7261 /* Receive BD completion control block */
7262 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7263 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7264
7265 /* Receive list selector control block */
7266 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7267 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7268
7269 /* Mbuf cluster free block */
7270 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7271 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7272
7273 /* Host coalescing control block */
7274 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7275 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7276 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7277 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7278 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7279 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7280 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7281 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7282 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7283 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7284 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7285 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7286
7287 /* Memory arbiter control block */
7288 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7289 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7290
7291 /* Buffer manager control block */
7292 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7293 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7294 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7295 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7296 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7297 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7298 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7299 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7300
7301 /* Read DMA control block */
7302 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7303 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7304
7305 /* Write DMA control block */
7306 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7307 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7308
7309 /* DMA completion block */
7310 printk("DEBUG: DMAC_MODE[%08x]\n",
7311 tr32(DMAC_MODE));
7312
7313 /* GRC block */
7314 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7315 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7316 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7317 tr32(GRC_LOCAL_CTRL));
7318
7319 /* TG3_BDINFOs */
7320 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7321 tr32(RCVDBDI_JUMBO_BD + 0x0),
7322 tr32(RCVDBDI_JUMBO_BD + 0x4),
7323 tr32(RCVDBDI_JUMBO_BD + 0x8),
7324 tr32(RCVDBDI_JUMBO_BD + 0xc));
7325 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7326 tr32(RCVDBDI_STD_BD + 0x0),
7327 tr32(RCVDBDI_STD_BD + 0x4),
7328 tr32(RCVDBDI_STD_BD + 0x8),
7329 tr32(RCVDBDI_STD_BD + 0xc));
7330 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7331 tr32(RCVDBDI_MINI_BD + 0x0),
7332 tr32(RCVDBDI_MINI_BD + 0x4),
7333 tr32(RCVDBDI_MINI_BD + 0x8),
7334 tr32(RCVDBDI_MINI_BD + 0xc));
7335
7336 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7337 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7338 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7339 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7340 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7341 val32, val32_2, val32_3, val32_4);
7342
7343 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7344 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7345 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7346 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7347 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7348 val32, val32_2, val32_3, val32_4);
7349
7350 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7351 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7352 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7353 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7354 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7355 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7356 val32, val32_2, val32_3, val32_4, val32_5);
7357
7358 /* SW status block */
7359 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7360 tp->hw_status->status,
7361 tp->hw_status->status_tag,
7362 tp->hw_status->rx_jumbo_consumer,
7363 tp->hw_status->rx_consumer,
7364 tp->hw_status->rx_mini_consumer,
7365 tp->hw_status->idx[0].rx_producer,
7366 tp->hw_status->idx[0].tx_consumer);
7367
7368 /* SW statistics block */
7369 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7370 ((u32 *)tp->hw_stats)[0],
7371 ((u32 *)tp->hw_stats)[1],
7372 ((u32 *)tp->hw_stats)[2],
7373 ((u32 *)tp->hw_stats)[3]);
7374
7375 /* Mailboxes */
7376 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7377 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7378 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7379 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7380 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7381
7382 /* NIC side send descriptors. */
7383 for (i = 0; i < 6; i++) {
7384 unsigned long txd;
7385
7386 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7387 + (i * sizeof(struct tg3_tx_buffer_desc));
7388 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7389 i,
7390 readl(txd + 0x0), readl(txd + 0x4),
7391 readl(txd + 0x8), readl(txd + 0xc));
7392 }
7393
7394 /* NIC side RX descriptors. */
7395 for (i = 0; i < 6; i++) {
7396 unsigned long rxd;
7397
7398 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7399 + (i * sizeof(struct tg3_rx_buffer_desc));
7400 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7401 i,
7402 readl(rxd + 0x0), readl(rxd + 0x4),
7403 readl(rxd + 0x8), readl(rxd + 0xc));
7404 rxd += (4 * sizeof(u32));
7405 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7406 i,
7407 readl(rxd + 0x0), readl(rxd + 0x4),
7408 readl(rxd + 0x8), readl(rxd + 0xc));
7409 }
7410
7411 for (i = 0; i < 6; i++) {
7412 unsigned long rxd;
7413
7414 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7415 + (i * sizeof(struct tg3_rx_buffer_desc));
7416 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7417 i,
7418 readl(rxd + 0x0), readl(rxd + 0x4),
7419 readl(rxd + 0x8), readl(rxd + 0xc));
7420 rxd += (4 * sizeof(u32));
7421 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7422 i,
7423 readl(rxd + 0x0), readl(rxd + 0x4),
7424 readl(rxd + 0x8), readl(rxd + 0xc));
7425 }
7426 }
7427 #endif
7428
7429 static struct net_device_stats *tg3_get_stats(struct net_device *);
7430 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7431
7432 static int tg3_close(struct net_device *dev)
7433 {
7434 struct tg3 *tp = netdev_priv(dev);
7435
7436 cancel_work_sync(&tp->reset_task);
7437
7438 netif_stop_queue(dev);
7439
7440 del_timer_sync(&tp->timer);
7441
7442 tg3_full_lock(tp, 1);
7443 #if 0
7444 tg3_dump_state(tp);
7445 #endif
7446
7447 tg3_disable_ints(tp);
7448
7449 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7450 tg3_free_rings(tp);
7451 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7452
7453 tg3_full_unlock(tp);
7454
7455 free_irq(tp->pdev->irq, dev);
7456 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7457 pci_disable_msi(tp->pdev);
7458 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7459 }
7460
7461 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7462 sizeof(tp->net_stats_prev));
7463 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7464 sizeof(tp->estats_prev));
7465
7466 tg3_free_consistent(tp);
7467
7468 tg3_set_power_state(tp, PCI_D3hot);
7469
7470 netif_carrier_off(tp->dev);
7471
7472 return 0;
7473 }
7474
7475 static inline unsigned long get_stat64(tg3_stat64_t *val)
7476 {
7477 unsigned long ret;
7478
7479 #if (BITS_PER_LONG == 32)
7480 ret = val->low;
7481 #else
7482 ret = ((u64)val->high << 32) | ((u64)val->low);
7483 #endif
7484 return ret;
7485 }
7486
7487 static unsigned long calc_crc_errors(struct tg3 *tp)
7488 {
7489 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7490
7491 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7492 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7493 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7494 u32 val;
7495
7496 spin_lock_bh(&tp->lock);
7497 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7498 tg3_writephy(tp, MII_TG3_TEST1,
7499 val | MII_TG3_TEST1_CRC_EN);
7500 tg3_readphy(tp, 0x14, &val);
7501 } else
7502 val = 0;
7503 spin_unlock_bh(&tp->lock);
7504
7505 tp->phy_crc_errors += val;
7506
7507 return tp->phy_crc_errors;
7508 }
7509
7510 return get_stat64(&hw_stats->rx_fcs_errors);
7511 }
7512
7513 #define ESTAT_ADD(member) \
7514 estats->member = old_estats->member + \
7515 get_stat64(&hw_stats->member)
7516
7517 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7518 {
7519 struct tg3_ethtool_stats *estats = &tp->estats;
7520 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7521 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7522
7523 if (!hw_stats)
7524 return old_estats;
7525
7526 ESTAT_ADD(rx_octets);
7527 ESTAT_ADD(rx_fragments);
7528 ESTAT_ADD(rx_ucast_packets);
7529 ESTAT_ADD(rx_mcast_packets);
7530 ESTAT_ADD(rx_bcast_packets);
7531 ESTAT_ADD(rx_fcs_errors);
7532 ESTAT_ADD(rx_align_errors);
7533 ESTAT_ADD(rx_xon_pause_rcvd);
7534 ESTAT_ADD(rx_xoff_pause_rcvd);
7535 ESTAT_ADD(rx_mac_ctrl_rcvd);
7536 ESTAT_ADD(rx_xoff_entered);
7537 ESTAT_ADD(rx_frame_too_long_errors);
7538 ESTAT_ADD(rx_jabbers);
7539 ESTAT_ADD(rx_undersize_packets);
7540 ESTAT_ADD(rx_in_length_errors);
7541 ESTAT_ADD(rx_out_length_errors);
7542 ESTAT_ADD(rx_64_or_less_octet_packets);
7543 ESTAT_ADD(rx_65_to_127_octet_packets);
7544 ESTAT_ADD(rx_128_to_255_octet_packets);
7545 ESTAT_ADD(rx_256_to_511_octet_packets);
7546 ESTAT_ADD(rx_512_to_1023_octet_packets);
7547 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7548 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7549 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7550 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7551 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7552
7553 ESTAT_ADD(tx_octets);
7554 ESTAT_ADD(tx_collisions);
7555 ESTAT_ADD(tx_xon_sent);
7556 ESTAT_ADD(tx_xoff_sent);
7557 ESTAT_ADD(tx_flow_control);
7558 ESTAT_ADD(tx_mac_errors);
7559 ESTAT_ADD(tx_single_collisions);
7560 ESTAT_ADD(tx_mult_collisions);
7561 ESTAT_ADD(tx_deferred);
7562 ESTAT_ADD(tx_excessive_collisions);
7563 ESTAT_ADD(tx_late_collisions);
7564 ESTAT_ADD(tx_collide_2times);
7565 ESTAT_ADD(tx_collide_3times);
7566 ESTAT_ADD(tx_collide_4times);
7567 ESTAT_ADD(tx_collide_5times);
7568 ESTAT_ADD(tx_collide_6times);
7569 ESTAT_ADD(tx_collide_7times);
7570 ESTAT_ADD(tx_collide_8times);
7571 ESTAT_ADD(tx_collide_9times);
7572 ESTAT_ADD(tx_collide_10times);
7573 ESTAT_ADD(tx_collide_11times);
7574 ESTAT_ADD(tx_collide_12times);
7575 ESTAT_ADD(tx_collide_13times);
7576 ESTAT_ADD(tx_collide_14times);
7577 ESTAT_ADD(tx_collide_15times);
7578 ESTAT_ADD(tx_ucast_packets);
7579 ESTAT_ADD(tx_mcast_packets);
7580 ESTAT_ADD(tx_bcast_packets);
7581 ESTAT_ADD(tx_carrier_sense_errors);
7582 ESTAT_ADD(tx_discards);
7583 ESTAT_ADD(tx_errors);
7584
7585 ESTAT_ADD(dma_writeq_full);
7586 ESTAT_ADD(dma_write_prioq_full);
7587 ESTAT_ADD(rxbds_empty);
7588 ESTAT_ADD(rx_discards);
7589 ESTAT_ADD(rx_errors);
7590 ESTAT_ADD(rx_threshold_hit);
7591
7592 ESTAT_ADD(dma_readq_full);
7593 ESTAT_ADD(dma_read_prioq_full);
7594 ESTAT_ADD(tx_comp_queue_full);
7595
7596 ESTAT_ADD(ring_set_send_prod_index);
7597 ESTAT_ADD(ring_status_update);
7598 ESTAT_ADD(nic_irqs);
7599 ESTAT_ADD(nic_avoided_irqs);
7600 ESTAT_ADD(nic_tx_threshold_hit);
7601
7602 return estats;
7603 }
7604
7605 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7606 {
7607 struct tg3 *tp = netdev_priv(dev);
7608 struct net_device_stats *stats = &tp->net_stats;
7609 struct net_device_stats *old_stats = &tp->net_stats_prev;
7610 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7611
7612 if (!hw_stats)
7613 return old_stats;
7614
7615 stats->rx_packets = old_stats->rx_packets +
7616 get_stat64(&hw_stats->rx_ucast_packets) +
7617 get_stat64(&hw_stats->rx_mcast_packets) +
7618 get_stat64(&hw_stats->rx_bcast_packets);
7619
7620 stats->tx_packets = old_stats->tx_packets +
7621 get_stat64(&hw_stats->tx_ucast_packets) +
7622 get_stat64(&hw_stats->tx_mcast_packets) +
7623 get_stat64(&hw_stats->tx_bcast_packets);
7624
7625 stats->rx_bytes = old_stats->rx_bytes +
7626 get_stat64(&hw_stats->rx_octets);
7627 stats->tx_bytes = old_stats->tx_bytes +
7628 get_stat64(&hw_stats->tx_octets);
7629
7630 stats->rx_errors = old_stats->rx_errors +
7631 get_stat64(&hw_stats->rx_errors);
7632 stats->tx_errors = old_stats->tx_errors +
7633 get_stat64(&hw_stats->tx_errors) +
7634 get_stat64(&hw_stats->tx_mac_errors) +
7635 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7636 get_stat64(&hw_stats->tx_discards);
7637
7638 stats->multicast = old_stats->multicast +
7639 get_stat64(&hw_stats->rx_mcast_packets);
7640 stats->collisions = old_stats->collisions +
7641 get_stat64(&hw_stats->tx_collisions);
7642
7643 stats->rx_length_errors = old_stats->rx_length_errors +
7644 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7645 get_stat64(&hw_stats->rx_undersize_packets);
7646
7647 stats->rx_over_errors = old_stats->rx_over_errors +
7648 get_stat64(&hw_stats->rxbds_empty);
7649 stats->rx_frame_errors = old_stats->rx_frame_errors +
7650 get_stat64(&hw_stats->rx_align_errors);
7651 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7652 get_stat64(&hw_stats->tx_discards);
7653 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7654 get_stat64(&hw_stats->tx_carrier_sense_errors);
7655
7656 stats->rx_crc_errors = old_stats->rx_crc_errors +
7657 calc_crc_errors(tp);
7658
7659 stats->rx_missed_errors = old_stats->rx_missed_errors +
7660 get_stat64(&hw_stats->rx_discards);
7661
7662 return stats;
7663 }
7664
7665 static inline u32 calc_crc(unsigned char *buf, int len)
7666 {
7667 u32 reg;
7668 u32 tmp;
7669 int j, k;
7670
7671 reg = 0xffffffff;
7672
7673 for (j = 0; j < len; j++) {
7674 reg ^= buf[j];
7675
7676 for (k = 0; k < 8; k++) {
7677 tmp = reg & 0x01;
7678
7679 reg >>= 1;
7680
7681 if (tmp) {
7682 reg ^= 0xedb88320;
7683 }
7684 }
7685 }
7686
7687 return ~reg;
7688 }
7689
7690 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7691 {
7692 /* accept or reject all multicast frames */
7693 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7694 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7695 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7696 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7697 }
7698
7699 static void __tg3_set_rx_mode(struct net_device *dev)
7700 {
7701 struct tg3 *tp = netdev_priv(dev);
7702 u32 rx_mode;
7703
7704 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7705 RX_MODE_KEEP_VLAN_TAG);
7706
7707 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7708 * flag clear.
7709 */
7710 #if TG3_VLAN_TAG_USED
7711 if (!tp->vlgrp &&
7712 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7713 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7714 #else
7715 /* By definition, VLAN is disabled always in this
7716 * case.
7717 */
7718 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7719 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7720 #endif
7721
7722 if (dev->flags & IFF_PROMISC) {
7723 /* Promiscuous mode. */
7724 rx_mode |= RX_MODE_PROMISC;
7725 } else if (dev->flags & IFF_ALLMULTI) {
7726 /* Accept all multicast. */
7727 tg3_set_multi (tp, 1);
7728 } else if (dev->mc_count < 1) {
7729 /* Reject all multicast. */
7730 tg3_set_multi (tp, 0);
7731 } else {
7732 /* Accept one or more multicast(s). */
7733 struct dev_mc_list *mclist;
7734 unsigned int i;
7735 u32 mc_filter[4] = { 0, };
7736 u32 regidx;
7737 u32 bit;
7738 u32 crc;
7739
7740 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7741 i++, mclist = mclist->next) {
7742
7743 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7744 bit = ~crc & 0x7f;
7745 regidx = (bit & 0x60) >> 5;
7746 bit &= 0x1f;
7747 mc_filter[regidx] |= (1 << bit);
7748 }
7749
7750 tw32(MAC_HASH_REG_0, mc_filter[0]);
7751 tw32(MAC_HASH_REG_1, mc_filter[1]);
7752 tw32(MAC_HASH_REG_2, mc_filter[2]);
7753 tw32(MAC_HASH_REG_3, mc_filter[3]);
7754 }
7755
7756 if (rx_mode != tp->rx_mode) {
7757 tp->rx_mode = rx_mode;
7758 tw32_f(MAC_RX_MODE, rx_mode);
7759 udelay(10);
7760 }
7761 }
7762
7763 static void tg3_set_rx_mode(struct net_device *dev)
7764 {
7765 struct tg3 *tp = netdev_priv(dev);
7766
7767 if (!netif_running(dev))
7768 return;
7769
7770 tg3_full_lock(tp, 0);
7771 __tg3_set_rx_mode(dev);
7772 tg3_full_unlock(tp);
7773 }
7774
7775 #define TG3_REGDUMP_LEN (32 * 1024)
7776
7777 static int tg3_get_regs_len(struct net_device *dev)
7778 {
7779 return TG3_REGDUMP_LEN;
7780 }
7781
7782 static void tg3_get_regs(struct net_device *dev,
7783 struct ethtool_regs *regs, void *_p)
7784 {
7785 u32 *p = _p;
7786 struct tg3 *tp = netdev_priv(dev);
7787 u8 *orig_p = _p;
7788 int i;
7789
7790 regs->version = 0;
7791
7792 memset(p, 0, TG3_REGDUMP_LEN);
7793
7794 if (tp->link_config.phy_is_low_power)
7795 return;
7796
7797 tg3_full_lock(tp, 0);
7798
7799 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7800 #define GET_REG32_LOOP(base,len) \
7801 do { p = (u32 *)(orig_p + (base)); \
7802 for (i = 0; i < len; i += 4) \
7803 __GET_REG32((base) + i); \
7804 } while (0)
7805 #define GET_REG32_1(reg) \
7806 do { p = (u32 *)(orig_p + (reg)); \
7807 __GET_REG32((reg)); \
7808 } while (0)
7809
7810 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7811 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7812 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7813 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7814 GET_REG32_1(SNDDATAC_MODE);
7815 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7816 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7817 GET_REG32_1(SNDBDC_MODE);
7818 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7819 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7820 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7821 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7822 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7823 GET_REG32_1(RCVDCC_MODE);
7824 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7825 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7826 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7827 GET_REG32_1(MBFREE_MODE);
7828 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7829 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7830 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7831 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7832 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7833 GET_REG32_1(RX_CPU_MODE);
7834 GET_REG32_1(RX_CPU_STATE);
7835 GET_REG32_1(RX_CPU_PGMCTR);
7836 GET_REG32_1(RX_CPU_HWBKPT);
7837 GET_REG32_1(TX_CPU_MODE);
7838 GET_REG32_1(TX_CPU_STATE);
7839 GET_REG32_1(TX_CPU_PGMCTR);
7840 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7841 GET_REG32_LOOP(FTQ_RESET, 0x120);
7842 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7843 GET_REG32_1(DMAC_MODE);
7844 GET_REG32_LOOP(GRC_MODE, 0x4c);
7845 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7846 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7847
7848 #undef __GET_REG32
7849 #undef GET_REG32_LOOP
7850 #undef GET_REG32_1
7851
7852 tg3_full_unlock(tp);
7853 }
7854
7855 static int tg3_get_eeprom_len(struct net_device *dev)
7856 {
7857 struct tg3 *tp = netdev_priv(dev);
7858
7859 return tp->nvram_size;
7860 }
7861
7862 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7863 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7864
7865 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7866 {
7867 struct tg3 *tp = netdev_priv(dev);
7868 int ret;
7869 u8 *pd;
7870 u32 i, offset, len, val, b_offset, b_count;
7871
7872 if (tp->link_config.phy_is_low_power)
7873 return -EAGAIN;
7874
7875 offset = eeprom->offset;
7876 len = eeprom->len;
7877 eeprom->len = 0;
7878
7879 eeprom->magic = TG3_EEPROM_MAGIC;
7880
7881 if (offset & 3) {
7882 /* adjustments to start on required 4 byte boundary */
7883 b_offset = offset & 3;
7884 b_count = 4 - b_offset;
7885 if (b_count > len) {
7886 /* i.e. offset=1 len=2 */
7887 b_count = len;
7888 }
7889 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7890 if (ret)
7891 return ret;
7892 val = cpu_to_le32(val);
7893 memcpy(data, ((char*)&val) + b_offset, b_count);
7894 len -= b_count;
7895 offset += b_count;
7896 eeprom->len += b_count;
7897 }
7898
7899 /* read bytes upto the last 4 byte boundary */
7900 pd = &data[eeprom->len];
7901 for (i = 0; i < (len - (len & 3)); i += 4) {
7902 ret = tg3_nvram_read(tp, offset + i, &val);
7903 if (ret) {
7904 eeprom->len += i;
7905 return ret;
7906 }
7907 val = cpu_to_le32(val);
7908 memcpy(pd + i, &val, 4);
7909 }
7910 eeprom->len += i;
7911
7912 if (len & 3) {
7913 /* read last bytes not ending on 4 byte boundary */
7914 pd = &data[eeprom->len];
7915 b_count = len & 3;
7916 b_offset = offset + len - b_count;
7917 ret = tg3_nvram_read(tp, b_offset, &val);
7918 if (ret)
7919 return ret;
7920 val = cpu_to_le32(val);
7921 memcpy(pd, ((char*)&val), b_count);
7922 eeprom->len += b_count;
7923 }
7924 return 0;
7925 }
7926
7927 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7928
7929 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7930 {
7931 struct tg3 *tp = netdev_priv(dev);
7932 int ret;
7933 u32 offset, len, b_offset, odd_len, start, end;
7934 u8 *buf;
7935
7936 if (tp->link_config.phy_is_low_power)
7937 return -EAGAIN;
7938
7939 if (eeprom->magic != TG3_EEPROM_MAGIC)
7940 return -EINVAL;
7941
7942 offset = eeprom->offset;
7943 len = eeprom->len;
7944
7945 if ((b_offset = (offset & 3))) {
7946 /* adjustments to start on required 4 byte boundary */
7947 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7948 if (ret)
7949 return ret;
7950 start = cpu_to_le32(start);
7951 len += b_offset;
7952 offset &= ~3;
7953 if (len < 4)
7954 len = 4;
7955 }
7956
7957 odd_len = 0;
7958 if (len & 3) {
7959 /* adjustments to end on required 4 byte boundary */
7960 odd_len = 1;
7961 len = (len + 3) & ~3;
7962 ret = tg3_nvram_read(tp, offset+len-4, &end);
7963 if (ret)
7964 return ret;
7965 end = cpu_to_le32(end);
7966 }
7967
7968 buf = data;
7969 if (b_offset || odd_len) {
7970 buf = kmalloc(len, GFP_KERNEL);
7971 if (buf == 0)
7972 return -ENOMEM;
7973 if (b_offset)
7974 memcpy(buf, &start, 4);
7975 if (odd_len)
7976 memcpy(buf+len-4, &end, 4);
7977 memcpy(buf + b_offset, data, eeprom->len);
7978 }
7979
7980 ret = tg3_nvram_write_block(tp, offset, len, buf);
7981
7982 if (buf != data)
7983 kfree(buf);
7984
7985 return ret;
7986 }
7987
7988 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7989 {
7990 struct tg3 *tp = netdev_priv(dev);
7991
7992 cmd->supported = (SUPPORTED_Autoneg);
7993
7994 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7995 cmd->supported |= (SUPPORTED_1000baseT_Half |
7996 SUPPORTED_1000baseT_Full);
7997
7998 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7999 cmd->supported |= (SUPPORTED_100baseT_Half |
8000 SUPPORTED_100baseT_Full |
8001 SUPPORTED_10baseT_Half |
8002 SUPPORTED_10baseT_Full |
8003 SUPPORTED_MII);
8004 cmd->port = PORT_TP;
8005 } else {
8006 cmd->supported |= SUPPORTED_FIBRE;
8007 cmd->port = PORT_FIBRE;
8008 }
8009
8010 cmd->advertising = tp->link_config.advertising;
8011 if (netif_running(dev)) {
8012 cmd->speed = tp->link_config.active_speed;
8013 cmd->duplex = tp->link_config.active_duplex;
8014 }
8015 cmd->phy_address = PHY_ADDR;
8016 cmd->transceiver = 0;
8017 cmd->autoneg = tp->link_config.autoneg;
8018 cmd->maxtxpkt = 0;
8019 cmd->maxrxpkt = 0;
8020 return 0;
8021 }
8022
8023 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8024 {
8025 struct tg3 *tp = netdev_priv(dev);
8026
8027 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8028 /* These are the only valid advertisement bits allowed. */
8029 if (cmd->autoneg == AUTONEG_ENABLE &&
8030 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8031 ADVERTISED_1000baseT_Full |
8032 ADVERTISED_Autoneg |
8033 ADVERTISED_FIBRE)))
8034 return -EINVAL;
8035 /* Fiber can only do SPEED_1000. */
8036 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8037 (cmd->speed != SPEED_1000))
8038 return -EINVAL;
8039 /* Copper cannot force SPEED_1000. */
8040 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8041 (cmd->speed == SPEED_1000))
8042 return -EINVAL;
8043 else if ((cmd->speed == SPEED_1000) &&
8044 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8045 return -EINVAL;
8046
8047 tg3_full_lock(tp, 0);
8048
8049 tp->link_config.autoneg = cmd->autoneg;
8050 if (cmd->autoneg == AUTONEG_ENABLE) {
8051 tp->link_config.advertising = cmd->advertising;
8052 tp->link_config.speed = SPEED_INVALID;
8053 tp->link_config.duplex = DUPLEX_INVALID;
8054 } else {
8055 tp->link_config.advertising = 0;
8056 tp->link_config.speed = cmd->speed;
8057 tp->link_config.duplex = cmd->duplex;
8058 }
8059
8060 tp->link_config.orig_speed = tp->link_config.speed;
8061 tp->link_config.orig_duplex = tp->link_config.duplex;
8062 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8063
8064 if (netif_running(dev))
8065 tg3_setup_phy(tp, 1);
8066
8067 tg3_full_unlock(tp);
8068
8069 return 0;
8070 }
8071
8072 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8073 {
8074 struct tg3 *tp = netdev_priv(dev);
8075
8076 strcpy(info->driver, DRV_MODULE_NAME);
8077 strcpy(info->version, DRV_MODULE_VERSION);
8078 strcpy(info->fw_version, tp->fw_ver);
8079 strcpy(info->bus_info, pci_name(tp->pdev));
8080 }
8081
8082 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8083 {
8084 struct tg3 *tp = netdev_priv(dev);
8085
8086 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8087 wol->supported = WAKE_MAGIC;
8088 else
8089 wol->supported = 0;
8090 wol->wolopts = 0;
8091 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8092 wol->wolopts = WAKE_MAGIC;
8093 memset(&wol->sopass, 0, sizeof(wol->sopass));
8094 }
8095
8096 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8097 {
8098 struct tg3 *tp = netdev_priv(dev);
8099
8100 if (wol->wolopts & ~WAKE_MAGIC)
8101 return -EINVAL;
8102 if ((wol->wolopts & WAKE_MAGIC) &&
8103 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8104 return -EINVAL;
8105
8106 spin_lock_bh(&tp->lock);
8107 if (wol->wolopts & WAKE_MAGIC)
8108 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8109 else
8110 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8111 spin_unlock_bh(&tp->lock);
8112
8113 return 0;
8114 }
8115
8116 static u32 tg3_get_msglevel(struct net_device *dev)
8117 {
8118 struct tg3 *tp = netdev_priv(dev);
8119 return tp->msg_enable;
8120 }
8121
8122 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8123 {
8124 struct tg3 *tp = netdev_priv(dev);
8125 tp->msg_enable = value;
8126 }
8127
8128 static int tg3_set_tso(struct net_device *dev, u32 value)
8129 {
8130 struct tg3 *tp = netdev_priv(dev);
8131
8132 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8133 if (value)
8134 return -EINVAL;
8135 return 0;
8136 }
8137 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8138 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8139 if (value)
8140 dev->features |= NETIF_F_TSO6;
8141 else
8142 dev->features &= ~NETIF_F_TSO6;
8143 }
8144 return ethtool_op_set_tso(dev, value);
8145 }
8146
8147 static int tg3_nway_reset(struct net_device *dev)
8148 {
8149 struct tg3 *tp = netdev_priv(dev);
8150 u32 bmcr;
8151 int r;
8152
8153 if (!netif_running(dev))
8154 return -EAGAIN;
8155
8156 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8157 return -EINVAL;
8158
8159 spin_lock_bh(&tp->lock);
8160 r = -EINVAL;
8161 tg3_readphy(tp, MII_BMCR, &bmcr);
8162 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8163 ((bmcr & BMCR_ANENABLE) ||
8164 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8165 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8166 BMCR_ANENABLE);
8167 r = 0;
8168 }
8169 spin_unlock_bh(&tp->lock);
8170
8171 return r;
8172 }
8173
8174 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8175 {
8176 struct tg3 *tp = netdev_priv(dev);
8177
8178 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8179 ering->rx_mini_max_pending = 0;
8180 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8181 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8182 else
8183 ering->rx_jumbo_max_pending = 0;
8184
8185 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8186
8187 ering->rx_pending = tp->rx_pending;
8188 ering->rx_mini_pending = 0;
8189 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8190 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8191 else
8192 ering->rx_jumbo_pending = 0;
8193
8194 ering->tx_pending = tp->tx_pending;
8195 }
8196
8197 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8198 {
8199 struct tg3 *tp = netdev_priv(dev);
8200 int irq_sync = 0, err = 0;
8201
8202 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8203 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8204 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8205 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8206 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8207 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8208 return -EINVAL;
8209
8210 if (netif_running(dev)) {
8211 tg3_netif_stop(tp);
8212 irq_sync = 1;
8213 }
8214
8215 tg3_full_lock(tp, irq_sync);
8216
8217 tp->rx_pending = ering->rx_pending;
8218
8219 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8220 tp->rx_pending > 63)
8221 tp->rx_pending = 63;
8222 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8223 tp->tx_pending = ering->tx_pending;
8224
8225 if (netif_running(dev)) {
8226 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8227 err = tg3_restart_hw(tp, 1);
8228 if (!err)
8229 tg3_netif_start(tp);
8230 }
8231
8232 tg3_full_unlock(tp);
8233
8234 return err;
8235 }
8236
8237 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8238 {
8239 struct tg3 *tp = netdev_priv(dev);
8240
8241 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8242 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8243 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8244 }
8245
8246 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8247 {
8248 struct tg3 *tp = netdev_priv(dev);
8249 int irq_sync = 0, err = 0;
8250
8251 if (netif_running(dev)) {
8252 tg3_netif_stop(tp);
8253 irq_sync = 1;
8254 }
8255
8256 tg3_full_lock(tp, irq_sync);
8257
8258 if (epause->autoneg)
8259 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8260 else
8261 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8262 if (epause->rx_pause)
8263 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8264 else
8265 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8266 if (epause->tx_pause)
8267 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8268 else
8269 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8270
8271 if (netif_running(dev)) {
8272 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8273 err = tg3_restart_hw(tp, 1);
8274 if (!err)
8275 tg3_netif_start(tp);
8276 }
8277
8278 tg3_full_unlock(tp);
8279
8280 return err;
8281 }
8282
8283 static u32 tg3_get_rx_csum(struct net_device *dev)
8284 {
8285 struct tg3 *tp = netdev_priv(dev);
8286 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8287 }
8288
8289 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8290 {
8291 struct tg3 *tp = netdev_priv(dev);
8292
8293 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8294 if (data != 0)
8295 return -EINVAL;
8296 return 0;
8297 }
8298
8299 spin_lock_bh(&tp->lock);
8300 if (data)
8301 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8302 else
8303 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8304 spin_unlock_bh(&tp->lock);
8305
8306 return 0;
8307 }
8308
8309 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8310 {
8311 struct tg3 *tp = netdev_priv(dev);
8312
8313 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8314 if (data != 0)
8315 return -EINVAL;
8316 return 0;
8317 }
8318
8319 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8320 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8321 ethtool_op_set_tx_hw_csum(dev, data);
8322 else
8323 ethtool_op_set_tx_csum(dev, data);
8324
8325 return 0;
8326 }
8327
8328 static int tg3_get_stats_count (struct net_device *dev)
8329 {
8330 return TG3_NUM_STATS;
8331 }
8332
8333 static int tg3_get_test_count (struct net_device *dev)
8334 {
8335 return TG3_NUM_TEST;
8336 }
8337
8338 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8339 {
8340 switch (stringset) {
8341 case ETH_SS_STATS:
8342 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8343 break;
8344 case ETH_SS_TEST:
8345 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8346 break;
8347 default:
8348 WARN_ON(1); /* we need a WARN() */
8349 break;
8350 }
8351 }
8352
8353 static int tg3_phys_id(struct net_device *dev, u32 data)
8354 {
8355 struct tg3 *tp = netdev_priv(dev);
8356 int i;
8357
8358 if (!netif_running(tp->dev))
8359 return -EAGAIN;
8360
8361 if (data == 0)
8362 data = 2;
8363
8364 for (i = 0; i < (data * 2); i++) {
8365 if ((i % 2) == 0)
8366 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8367 LED_CTRL_1000MBPS_ON |
8368 LED_CTRL_100MBPS_ON |
8369 LED_CTRL_10MBPS_ON |
8370 LED_CTRL_TRAFFIC_OVERRIDE |
8371 LED_CTRL_TRAFFIC_BLINK |
8372 LED_CTRL_TRAFFIC_LED);
8373
8374 else
8375 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8376 LED_CTRL_TRAFFIC_OVERRIDE);
8377
8378 if (msleep_interruptible(500))
8379 break;
8380 }
8381 tw32(MAC_LED_CTRL, tp->led_ctrl);
8382 return 0;
8383 }
8384
8385 static void tg3_get_ethtool_stats (struct net_device *dev,
8386 struct ethtool_stats *estats, u64 *tmp_stats)
8387 {
8388 struct tg3 *tp = netdev_priv(dev);
8389 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8390 }
8391
8392 #define NVRAM_TEST_SIZE 0x100
8393 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8394 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8395 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8396
8397 static int tg3_test_nvram(struct tg3 *tp)
8398 {
8399 u32 *buf, csum, magic;
8400 int i, j, err = 0, size;
8401
8402 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8403 return -EIO;
8404
8405 if (magic == TG3_EEPROM_MAGIC)
8406 size = NVRAM_TEST_SIZE;
8407 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8408 if ((magic & 0xe00000) == 0x200000)
8409 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8410 else
8411 return 0;
8412 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8413 size = NVRAM_SELFBOOT_HW_SIZE;
8414 else
8415 return -EIO;
8416
8417 buf = kmalloc(size, GFP_KERNEL);
8418 if (buf == NULL)
8419 return -ENOMEM;
8420
8421 err = -EIO;
8422 for (i = 0, j = 0; i < size; i += 4, j++) {
8423 u32 val;
8424
8425 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8426 break;
8427 buf[j] = cpu_to_le32(val);
8428 }
8429 if (i < size)
8430 goto out;
8431
8432 /* Selfboot format */
8433 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8434 TG3_EEPROM_MAGIC_FW) {
8435 u8 *buf8 = (u8 *) buf, csum8 = 0;
8436
8437 for (i = 0; i < size; i++)
8438 csum8 += buf8[i];
8439
8440 if (csum8 == 0) {
8441 err = 0;
8442 goto out;
8443 }
8444
8445 err = -EIO;
8446 goto out;
8447 }
8448
8449 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8450 TG3_EEPROM_MAGIC_HW) {
8451 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8452 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8453 u8 *buf8 = (u8 *) buf;
8454 int j, k;
8455
8456 /* Separate the parity bits and the data bytes. */
8457 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8458 if ((i == 0) || (i == 8)) {
8459 int l;
8460 u8 msk;
8461
8462 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8463 parity[k++] = buf8[i] & msk;
8464 i++;
8465 }
8466 else if (i == 16) {
8467 int l;
8468 u8 msk;
8469
8470 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8471 parity[k++] = buf8[i] & msk;
8472 i++;
8473
8474 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8475 parity[k++] = buf8[i] & msk;
8476 i++;
8477 }
8478 data[j++] = buf8[i];
8479 }
8480
8481 err = -EIO;
8482 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8483 u8 hw8 = hweight8(data[i]);
8484
8485 if ((hw8 & 0x1) && parity[i])
8486 goto out;
8487 else if (!(hw8 & 0x1) && !parity[i])
8488 goto out;
8489 }
8490 err = 0;
8491 goto out;
8492 }
8493
8494 /* Bootstrap checksum at offset 0x10 */
8495 csum = calc_crc((unsigned char *) buf, 0x10);
8496 if(csum != cpu_to_le32(buf[0x10/4]))
8497 goto out;
8498
8499 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8500 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8501 if (csum != cpu_to_le32(buf[0xfc/4]))
8502 goto out;
8503
8504 err = 0;
8505
8506 out:
8507 kfree(buf);
8508 return err;
8509 }
8510
8511 #define TG3_SERDES_TIMEOUT_SEC 2
8512 #define TG3_COPPER_TIMEOUT_SEC 6
8513
8514 static int tg3_test_link(struct tg3 *tp)
8515 {
8516 int i, max;
8517
8518 if (!netif_running(tp->dev))
8519 return -ENODEV;
8520
8521 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8522 max = TG3_SERDES_TIMEOUT_SEC;
8523 else
8524 max = TG3_COPPER_TIMEOUT_SEC;
8525
8526 for (i = 0; i < max; i++) {
8527 if (netif_carrier_ok(tp->dev))
8528 return 0;
8529
8530 if (msleep_interruptible(1000))
8531 break;
8532 }
8533
8534 return -EIO;
8535 }
8536
8537 /* Only test the commonly used registers */
8538 static int tg3_test_registers(struct tg3 *tp)
8539 {
8540 int i, is_5705, is_5750;
8541 u32 offset, read_mask, write_mask, val, save_val, read_val;
8542 static struct {
8543 u16 offset;
8544 u16 flags;
8545 #define TG3_FL_5705 0x1
8546 #define TG3_FL_NOT_5705 0x2
8547 #define TG3_FL_NOT_5788 0x4
8548 #define TG3_FL_NOT_5750 0x8
8549 u32 read_mask;
8550 u32 write_mask;
8551 } reg_tbl[] = {
8552 /* MAC Control Registers */
8553 { MAC_MODE, TG3_FL_NOT_5705,
8554 0x00000000, 0x00ef6f8c },
8555 { MAC_MODE, TG3_FL_5705,
8556 0x00000000, 0x01ef6b8c },
8557 { MAC_STATUS, TG3_FL_NOT_5705,
8558 0x03800107, 0x00000000 },
8559 { MAC_STATUS, TG3_FL_5705,
8560 0x03800100, 0x00000000 },
8561 { MAC_ADDR_0_HIGH, 0x0000,
8562 0x00000000, 0x0000ffff },
8563 { MAC_ADDR_0_LOW, 0x0000,
8564 0x00000000, 0xffffffff },
8565 { MAC_RX_MTU_SIZE, 0x0000,
8566 0x00000000, 0x0000ffff },
8567 { MAC_TX_MODE, 0x0000,
8568 0x00000000, 0x00000070 },
8569 { MAC_TX_LENGTHS, 0x0000,
8570 0x00000000, 0x00003fff },
8571 { MAC_RX_MODE, TG3_FL_NOT_5705,
8572 0x00000000, 0x000007fc },
8573 { MAC_RX_MODE, TG3_FL_5705,
8574 0x00000000, 0x000007dc },
8575 { MAC_HASH_REG_0, 0x0000,
8576 0x00000000, 0xffffffff },
8577 { MAC_HASH_REG_1, 0x0000,
8578 0x00000000, 0xffffffff },
8579 { MAC_HASH_REG_2, 0x0000,
8580 0x00000000, 0xffffffff },
8581 { MAC_HASH_REG_3, 0x0000,
8582 0x00000000, 0xffffffff },
8583
8584 /* Receive Data and Receive BD Initiator Control Registers. */
8585 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8586 0x00000000, 0xffffffff },
8587 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8588 0x00000000, 0xffffffff },
8589 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8590 0x00000000, 0x00000003 },
8591 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8592 0x00000000, 0xffffffff },
8593 { RCVDBDI_STD_BD+0, 0x0000,
8594 0x00000000, 0xffffffff },
8595 { RCVDBDI_STD_BD+4, 0x0000,
8596 0x00000000, 0xffffffff },
8597 { RCVDBDI_STD_BD+8, 0x0000,
8598 0x00000000, 0xffff0002 },
8599 { RCVDBDI_STD_BD+0xc, 0x0000,
8600 0x00000000, 0xffffffff },
8601
8602 /* Receive BD Initiator Control Registers. */
8603 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8604 0x00000000, 0xffffffff },
8605 { RCVBDI_STD_THRESH, TG3_FL_5705,
8606 0x00000000, 0x000003ff },
8607 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8608 0x00000000, 0xffffffff },
8609
8610 /* Host Coalescing Control Registers. */
8611 { HOSTCC_MODE, TG3_FL_NOT_5705,
8612 0x00000000, 0x00000004 },
8613 { HOSTCC_MODE, TG3_FL_5705,
8614 0x00000000, 0x000000f6 },
8615 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8616 0x00000000, 0xffffffff },
8617 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8618 0x00000000, 0x000003ff },
8619 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8620 0x00000000, 0xffffffff },
8621 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8622 0x00000000, 0x000003ff },
8623 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8624 0x00000000, 0xffffffff },
8625 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8626 0x00000000, 0x000000ff },
8627 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8628 0x00000000, 0xffffffff },
8629 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8630 0x00000000, 0x000000ff },
8631 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8632 0x00000000, 0xffffffff },
8633 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8634 0x00000000, 0xffffffff },
8635 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8636 0x00000000, 0xffffffff },
8637 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8638 0x00000000, 0x000000ff },
8639 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8640 0x00000000, 0xffffffff },
8641 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8642 0x00000000, 0x000000ff },
8643 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8644 0x00000000, 0xffffffff },
8645 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8646 0x00000000, 0xffffffff },
8647 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8648 0x00000000, 0xffffffff },
8649 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8650 0x00000000, 0xffffffff },
8651 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8652 0x00000000, 0xffffffff },
8653 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8654 0xffffffff, 0x00000000 },
8655 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8656 0xffffffff, 0x00000000 },
8657
8658 /* Buffer Manager Control Registers. */
8659 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8660 0x00000000, 0x007fff80 },
8661 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8662 0x00000000, 0x007fffff },
8663 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8664 0x00000000, 0x0000003f },
8665 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8666 0x00000000, 0x000001ff },
8667 { BUFMGR_MB_HIGH_WATER, 0x0000,
8668 0x00000000, 0x000001ff },
8669 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8670 0xffffffff, 0x00000000 },
8671 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8672 0xffffffff, 0x00000000 },
8673
8674 /* Mailbox Registers */
8675 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8676 0x00000000, 0x000001ff },
8677 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8678 0x00000000, 0x000001ff },
8679 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8680 0x00000000, 0x000007ff },
8681 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8682 0x00000000, 0x000001ff },
8683
8684 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8685 };
8686
8687 is_5705 = is_5750 = 0;
8688 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8689 is_5705 = 1;
8690 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8691 is_5750 = 1;
8692 }
8693
8694 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8695 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8696 continue;
8697
8698 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8699 continue;
8700
8701 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8702 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8703 continue;
8704
8705 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8706 continue;
8707
8708 offset = (u32) reg_tbl[i].offset;
8709 read_mask = reg_tbl[i].read_mask;
8710 write_mask = reg_tbl[i].write_mask;
8711
8712 /* Save the original register content */
8713 save_val = tr32(offset);
8714
8715 /* Determine the read-only value. */
8716 read_val = save_val & read_mask;
8717
8718 /* Write zero to the register, then make sure the read-only bits
8719 * are not changed and the read/write bits are all zeros.
8720 */
8721 tw32(offset, 0);
8722
8723 val = tr32(offset);
8724
8725 /* Test the read-only and read/write bits. */
8726 if (((val & read_mask) != read_val) || (val & write_mask))
8727 goto out;
8728
8729 /* Write ones to all the bits defined by RdMask and WrMask, then
8730 * make sure the read-only bits are not changed and the
8731 * read/write bits are all ones.
8732 */
8733 tw32(offset, read_mask | write_mask);
8734
8735 val = tr32(offset);
8736
8737 /* Test the read-only bits. */
8738 if ((val & read_mask) != read_val)
8739 goto out;
8740
8741 /* Test the read/write bits. */
8742 if ((val & write_mask) != write_mask)
8743 goto out;
8744
8745 tw32(offset, save_val);
8746 }
8747
8748 return 0;
8749
8750 out:
8751 if (netif_msg_hw(tp))
8752 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8753 offset);
8754 tw32(offset, save_val);
8755 return -EIO;
8756 }
8757
8758 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8759 {
8760 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8761 int i;
8762 u32 j;
8763
8764 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8765 for (j = 0; j < len; j += 4) {
8766 u32 val;
8767
8768 tg3_write_mem(tp, offset + j, test_pattern[i]);
8769 tg3_read_mem(tp, offset + j, &val);
8770 if (val != test_pattern[i])
8771 return -EIO;
8772 }
8773 }
8774 return 0;
8775 }
8776
8777 static int tg3_test_memory(struct tg3 *tp)
8778 {
8779 static struct mem_entry {
8780 u32 offset;
8781 u32 len;
8782 } mem_tbl_570x[] = {
8783 { 0x00000000, 0x00b50},
8784 { 0x00002000, 0x1c000},
8785 { 0xffffffff, 0x00000}
8786 }, mem_tbl_5705[] = {
8787 { 0x00000100, 0x0000c},
8788 { 0x00000200, 0x00008},
8789 { 0x00004000, 0x00800},
8790 { 0x00006000, 0x01000},
8791 { 0x00008000, 0x02000},
8792 { 0x00010000, 0x0e000},
8793 { 0xffffffff, 0x00000}
8794 }, mem_tbl_5755[] = {
8795 { 0x00000200, 0x00008},
8796 { 0x00004000, 0x00800},
8797 { 0x00006000, 0x00800},
8798 { 0x00008000, 0x02000},
8799 { 0x00010000, 0x0c000},
8800 { 0xffffffff, 0x00000}
8801 }, mem_tbl_5906[] = {
8802 { 0x00000200, 0x00008},
8803 { 0x00004000, 0x00400},
8804 { 0x00006000, 0x00400},
8805 { 0x00008000, 0x01000},
8806 { 0x00010000, 0x01000},
8807 { 0xffffffff, 0x00000}
8808 };
8809 struct mem_entry *mem_tbl;
8810 int err = 0;
8811 int i;
8812
8813 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8815 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8816 mem_tbl = mem_tbl_5755;
8817 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8818 mem_tbl = mem_tbl_5906;
8819 else
8820 mem_tbl = mem_tbl_5705;
8821 } else
8822 mem_tbl = mem_tbl_570x;
8823
8824 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8825 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8826 mem_tbl[i].len)) != 0)
8827 break;
8828 }
8829
8830 return err;
8831 }
8832
8833 #define TG3_MAC_LOOPBACK 0
8834 #define TG3_PHY_LOOPBACK 1
8835
8836 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8837 {
8838 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8839 u32 desc_idx;
8840 struct sk_buff *skb, *rx_skb;
8841 u8 *tx_data;
8842 dma_addr_t map;
8843 int num_pkts, tx_len, rx_len, i, err;
8844 struct tg3_rx_buffer_desc *desc;
8845
8846 if (loopback_mode == TG3_MAC_LOOPBACK) {
8847 /* HW errata - mac loopback fails in some cases on 5780.
8848 * Normal traffic and PHY loopback are not affected by
8849 * errata.
8850 */
8851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8852 return 0;
8853
8854 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8855 MAC_MODE_PORT_INT_LPBACK;
8856 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8857 mac_mode |= MAC_MODE_LINK_POLARITY;
8858 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8859 mac_mode |= MAC_MODE_PORT_MODE_MII;
8860 else
8861 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8862 tw32(MAC_MODE, mac_mode);
8863 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8864 u32 val;
8865
8866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8867 u32 phytest;
8868
8869 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8870 u32 phy;
8871
8872 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8873 phytest | MII_TG3_EPHY_SHADOW_EN);
8874 if (!tg3_readphy(tp, 0x1b, &phy))
8875 tg3_writephy(tp, 0x1b, phy & ~0x20);
8876 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8877 }
8878 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8879 } else
8880 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8881
8882 tg3_phy_toggle_automdix(tp, 0);
8883
8884 tg3_writephy(tp, MII_BMCR, val);
8885 udelay(40);
8886
8887 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
8888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8889 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8890 mac_mode |= MAC_MODE_PORT_MODE_MII;
8891 } else
8892 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8893
8894 /* reset to prevent losing 1st rx packet intermittently */
8895 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8896 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8897 udelay(10);
8898 tw32_f(MAC_RX_MODE, tp->rx_mode);
8899 }
8900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
8901 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8902 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8903 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
8904 mac_mode |= MAC_MODE_LINK_POLARITY;
8905 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8906 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8907 }
8908 tw32(MAC_MODE, mac_mode);
8909 }
8910 else
8911 return -EINVAL;
8912
8913 err = -EIO;
8914
8915 tx_len = 1514;
8916 skb = netdev_alloc_skb(tp->dev, tx_len);
8917 if (!skb)
8918 return -ENOMEM;
8919
8920 tx_data = skb_put(skb, tx_len);
8921 memcpy(tx_data, tp->dev->dev_addr, 6);
8922 memset(tx_data + 6, 0x0, 8);
8923
8924 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8925
8926 for (i = 14; i < tx_len; i++)
8927 tx_data[i] = (u8) (i & 0xff);
8928
8929 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8930
8931 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8932 HOSTCC_MODE_NOW);
8933
8934 udelay(10);
8935
8936 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8937
8938 num_pkts = 0;
8939
8940 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8941
8942 tp->tx_prod++;
8943 num_pkts++;
8944
8945 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8946 tp->tx_prod);
8947 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8948
8949 udelay(10);
8950
8951 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8952 for (i = 0; i < 25; i++) {
8953 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8954 HOSTCC_MODE_NOW);
8955
8956 udelay(10);
8957
8958 tx_idx = tp->hw_status->idx[0].tx_consumer;
8959 rx_idx = tp->hw_status->idx[0].rx_producer;
8960 if ((tx_idx == tp->tx_prod) &&
8961 (rx_idx == (rx_start_idx + num_pkts)))
8962 break;
8963 }
8964
8965 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8966 dev_kfree_skb(skb);
8967
8968 if (tx_idx != tp->tx_prod)
8969 goto out;
8970
8971 if (rx_idx != rx_start_idx + num_pkts)
8972 goto out;
8973
8974 desc = &tp->rx_rcb[rx_start_idx];
8975 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8976 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8977 if (opaque_key != RXD_OPAQUE_RING_STD)
8978 goto out;
8979
8980 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8981 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8982 goto out;
8983
8984 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8985 if (rx_len != tx_len)
8986 goto out;
8987
8988 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8989
8990 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8991 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8992
8993 for (i = 14; i < tx_len; i++) {
8994 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8995 goto out;
8996 }
8997 err = 0;
8998
8999 /* tg3_free_rings will unmap and free the rx_skb */
9000 out:
9001 return err;
9002 }
9003
9004 #define TG3_MAC_LOOPBACK_FAILED 1
9005 #define TG3_PHY_LOOPBACK_FAILED 2
9006 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9007 TG3_PHY_LOOPBACK_FAILED)
9008
9009 static int tg3_test_loopback(struct tg3 *tp)
9010 {
9011 int err = 0;
9012
9013 if (!netif_running(tp->dev))
9014 return TG3_LOOPBACK_FAILED;
9015
9016 err = tg3_reset_hw(tp, 1);
9017 if (err)
9018 return TG3_LOOPBACK_FAILED;
9019
9020 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9021 err |= TG3_MAC_LOOPBACK_FAILED;
9022 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9023 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9024 err |= TG3_PHY_LOOPBACK_FAILED;
9025 }
9026
9027 return err;
9028 }
9029
9030 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9031 u64 *data)
9032 {
9033 struct tg3 *tp = netdev_priv(dev);
9034
9035 if (tp->link_config.phy_is_low_power)
9036 tg3_set_power_state(tp, PCI_D0);
9037
9038 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9039
9040 if (tg3_test_nvram(tp) != 0) {
9041 etest->flags |= ETH_TEST_FL_FAILED;
9042 data[0] = 1;
9043 }
9044 if (tg3_test_link(tp) != 0) {
9045 etest->flags |= ETH_TEST_FL_FAILED;
9046 data[1] = 1;
9047 }
9048 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9049 int err, irq_sync = 0;
9050
9051 if (netif_running(dev)) {
9052 tg3_netif_stop(tp);
9053 irq_sync = 1;
9054 }
9055
9056 tg3_full_lock(tp, irq_sync);
9057
9058 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9059 err = tg3_nvram_lock(tp);
9060 tg3_halt_cpu(tp, RX_CPU_BASE);
9061 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9062 tg3_halt_cpu(tp, TX_CPU_BASE);
9063 if (!err)
9064 tg3_nvram_unlock(tp);
9065
9066 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9067 tg3_phy_reset(tp);
9068
9069 if (tg3_test_registers(tp) != 0) {
9070 etest->flags |= ETH_TEST_FL_FAILED;
9071 data[2] = 1;
9072 }
9073 if (tg3_test_memory(tp) != 0) {
9074 etest->flags |= ETH_TEST_FL_FAILED;
9075 data[3] = 1;
9076 }
9077 if ((data[4] = tg3_test_loopback(tp)) != 0)
9078 etest->flags |= ETH_TEST_FL_FAILED;
9079
9080 tg3_full_unlock(tp);
9081
9082 if (tg3_test_interrupt(tp) != 0) {
9083 etest->flags |= ETH_TEST_FL_FAILED;
9084 data[5] = 1;
9085 }
9086
9087 tg3_full_lock(tp, 0);
9088
9089 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9090 if (netif_running(dev)) {
9091 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9092 if (!tg3_restart_hw(tp, 1))
9093 tg3_netif_start(tp);
9094 }
9095
9096 tg3_full_unlock(tp);
9097 }
9098 if (tp->link_config.phy_is_low_power)
9099 tg3_set_power_state(tp, PCI_D3hot);
9100
9101 }
9102
9103 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9104 {
9105 struct mii_ioctl_data *data = if_mii(ifr);
9106 struct tg3 *tp = netdev_priv(dev);
9107 int err;
9108
9109 switch(cmd) {
9110 case SIOCGMIIPHY:
9111 data->phy_id = PHY_ADDR;
9112
9113 /* fallthru */
9114 case SIOCGMIIREG: {
9115 u32 mii_regval;
9116
9117 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9118 break; /* We have no PHY */
9119
9120 if (tp->link_config.phy_is_low_power)
9121 return -EAGAIN;
9122
9123 spin_lock_bh(&tp->lock);
9124 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9125 spin_unlock_bh(&tp->lock);
9126
9127 data->val_out = mii_regval;
9128
9129 return err;
9130 }
9131
9132 case SIOCSMIIREG:
9133 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9134 break; /* We have no PHY */
9135
9136 if (!capable(CAP_NET_ADMIN))
9137 return -EPERM;
9138
9139 if (tp->link_config.phy_is_low_power)
9140 return -EAGAIN;
9141
9142 spin_lock_bh(&tp->lock);
9143 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9144 spin_unlock_bh(&tp->lock);
9145
9146 return err;
9147
9148 default:
9149 /* do nothing */
9150 break;
9151 }
9152 return -EOPNOTSUPP;
9153 }
9154
9155 #if TG3_VLAN_TAG_USED
9156 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9157 {
9158 struct tg3 *tp = netdev_priv(dev);
9159
9160 if (netif_running(dev))
9161 tg3_netif_stop(tp);
9162
9163 tg3_full_lock(tp, 0);
9164
9165 tp->vlgrp = grp;
9166
9167 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9168 __tg3_set_rx_mode(dev);
9169
9170 if (netif_running(dev))
9171 tg3_netif_start(tp);
9172
9173 tg3_full_unlock(tp);
9174 }
9175 #endif
9176
9177 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9178 {
9179 struct tg3 *tp = netdev_priv(dev);
9180
9181 memcpy(ec, &tp->coal, sizeof(*ec));
9182 return 0;
9183 }
9184
9185 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9186 {
9187 struct tg3 *tp = netdev_priv(dev);
9188 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9189 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9190
9191 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9192 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9193 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9194 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9195 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9196 }
9197
9198 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9199 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9200 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9201 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9202 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9203 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9204 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9205 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9206 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9207 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9208 return -EINVAL;
9209
9210 /* No rx interrupts will be generated if both are zero */
9211 if ((ec->rx_coalesce_usecs == 0) &&
9212 (ec->rx_max_coalesced_frames == 0))
9213 return -EINVAL;
9214
9215 /* No tx interrupts will be generated if both are zero */
9216 if ((ec->tx_coalesce_usecs == 0) &&
9217 (ec->tx_max_coalesced_frames == 0))
9218 return -EINVAL;
9219
9220 /* Only copy relevant parameters, ignore all others. */
9221 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9222 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9223 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9224 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9225 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9226 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9227 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9228 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9229 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9230
9231 if (netif_running(dev)) {
9232 tg3_full_lock(tp, 0);
9233 __tg3_set_coalesce(tp, &tp->coal);
9234 tg3_full_unlock(tp);
9235 }
9236 return 0;
9237 }
9238
9239 static const struct ethtool_ops tg3_ethtool_ops = {
9240 .get_settings = tg3_get_settings,
9241 .set_settings = tg3_set_settings,
9242 .get_drvinfo = tg3_get_drvinfo,
9243 .get_regs_len = tg3_get_regs_len,
9244 .get_regs = tg3_get_regs,
9245 .get_wol = tg3_get_wol,
9246 .set_wol = tg3_set_wol,
9247 .get_msglevel = tg3_get_msglevel,
9248 .set_msglevel = tg3_set_msglevel,
9249 .nway_reset = tg3_nway_reset,
9250 .get_link = ethtool_op_get_link,
9251 .get_eeprom_len = tg3_get_eeprom_len,
9252 .get_eeprom = tg3_get_eeprom,
9253 .set_eeprom = tg3_set_eeprom,
9254 .get_ringparam = tg3_get_ringparam,
9255 .set_ringparam = tg3_set_ringparam,
9256 .get_pauseparam = tg3_get_pauseparam,
9257 .set_pauseparam = tg3_set_pauseparam,
9258 .get_rx_csum = tg3_get_rx_csum,
9259 .set_rx_csum = tg3_set_rx_csum,
9260 .get_tx_csum = ethtool_op_get_tx_csum,
9261 .set_tx_csum = tg3_set_tx_csum,
9262 .get_sg = ethtool_op_get_sg,
9263 .set_sg = ethtool_op_set_sg,
9264 .get_tso = ethtool_op_get_tso,
9265 .set_tso = tg3_set_tso,
9266 .self_test_count = tg3_get_test_count,
9267 .self_test = tg3_self_test,
9268 .get_strings = tg3_get_strings,
9269 .phys_id = tg3_phys_id,
9270 .get_stats_count = tg3_get_stats_count,
9271 .get_ethtool_stats = tg3_get_ethtool_stats,
9272 .get_coalesce = tg3_get_coalesce,
9273 .set_coalesce = tg3_set_coalesce,
9274 .get_perm_addr = ethtool_op_get_perm_addr,
9275 };
9276
9277 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9278 {
9279 u32 cursize, val, magic;
9280
9281 tp->nvram_size = EEPROM_CHIP_SIZE;
9282
9283 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9284 return;
9285
9286 if ((magic != TG3_EEPROM_MAGIC) &&
9287 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9288 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9289 return;
9290
9291 /*
9292 * Size the chip by reading offsets at increasing powers of two.
9293 * When we encounter our validation signature, we know the addressing
9294 * has wrapped around, and thus have our chip size.
9295 */
9296 cursize = 0x10;
9297
9298 while (cursize < tp->nvram_size) {
9299 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9300 return;
9301
9302 if (val == magic)
9303 break;
9304
9305 cursize <<= 1;
9306 }
9307
9308 tp->nvram_size = cursize;
9309 }
9310
9311 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9312 {
9313 u32 val;
9314
9315 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9316 return;
9317
9318 /* Selfboot format */
9319 if (val != TG3_EEPROM_MAGIC) {
9320 tg3_get_eeprom_size(tp);
9321 return;
9322 }
9323
9324 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9325 if (val != 0) {
9326 tp->nvram_size = (val >> 16) * 1024;
9327 return;
9328 }
9329 }
9330 tp->nvram_size = 0x80000;
9331 }
9332
9333 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9334 {
9335 u32 nvcfg1;
9336
9337 nvcfg1 = tr32(NVRAM_CFG1);
9338 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9339 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9340 }
9341 else {
9342 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9343 tw32(NVRAM_CFG1, nvcfg1);
9344 }
9345
9346 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9347 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9348 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9349 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9350 tp->nvram_jedecnum = JEDEC_ATMEL;
9351 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9352 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9353 break;
9354 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9355 tp->nvram_jedecnum = JEDEC_ATMEL;
9356 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9357 break;
9358 case FLASH_VENDOR_ATMEL_EEPROM:
9359 tp->nvram_jedecnum = JEDEC_ATMEL;
9360 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9361 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9362 break;
9363 case FLASH_VENDOR_ST:
9364 tp->nvram_jedecnum = JEDEC_ST;
9365 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9367 break;
9368 case FLASH_VENDOR_SAIFUN:
9369 tp->nvram_jedecnum = JEDEC_SAIFUN;
9370 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9371 break;
9372 case FLASH_VENDOR_SST_SMALL:
9373 case FLASH_VENDOR_SST_LARGE:
9374 tp->nvram_jedecnum = JEDEC_SST;
9375 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9376 break;
9377 }
9378 }
9379 else {
9380 tp->nvram_jedecnum = JEDEC_ATMEL;
9381 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9382 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9383 }
9384 }
9385
9386 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9387 {
9388 u32 nvcfg1;
9389
9390 nvcfg1 = tr32(NVRAM_CFG1);
9391
9392 /* NVRAM protection for TPM */
9393 if (nvcfg1 & (1 << 27))
9394 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9395
9396 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9397 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9398 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9399 tp->nvram_jedecnum = JEDEC_ATMEL;
9400 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9401 break;
9402 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9403 tp->nvram_jedecnum = JEDEC_ATMEL;
9404 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9405 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9406 break;
9407 case FLASH_5752VENDOR_ST_M45PE10:
9408 case FLASH_5752VENDOR_ST_M45PE20:
9409 case FLASH_5752VENDOR_ST_M45PE40:
9410 tp->nvram_jedecnum = JEDEC_ST;
9411 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9412 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9413 break;
9414 }
9415
9416 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9417 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9418 case FLASH_5752PAGE_SIZE_256:
9419 tp->nvram_pagesize = 256;
9420 break;
9421 case FLASH_5752PAGE_SIZE_512:
9422 tp->nvram_pagesize = 512;
9423 break;
9424 case FLASH_5752PAGE_SIZE_1K:
9425 tp->nvram_pagesize = 1024;
9426 break;
9427 case FLASH_5752PAGE_SIZE_2K:
9428 tp->nvram_pagesize = 2048;
9429 break;
9430 case FLASH_5752PAGE_SIZE_4K:
9431 tp->nvram_pagesize = 4096;
9432 break;
9433 case FLASH_5752PAGE_SIZE_264:
9434 tp->nvram_pagesize = 264;
9435 break;
9436 }
9437 }
9438 else {
9439 /* For eeprom, set pagesize to maximum eeprom size */
9440 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9441
9442 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9443 tw32(NVRAM_CFG1, nvcfg1);
9444 }
9445 }
9446
9447 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9448 {
9449 u32 nvcfg1, protect = 0;
9450
9451 nvcfg1 = tr32(NVRAM_CFG1);
9452
9453 /* NVRAM protection for TPM */
9454 if (nvcfg1 & (1 << 27)) {
9455 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9456 protect = 1;
9457 }
9458
9459 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9460 switch (nvcfg1) {
9461 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9462 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9463 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9464 case FLASH_5755VENDOR_ATMEL_FLASH_5:
9465 tp->nvram_jedecnum = JEDEC_ATMEL;
9466 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9467 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9468 tp->nvram_pagesize = 264;
9469 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
9470 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
9471 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9472 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9473 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9474 else
9475 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9476 break;
9477 case FLASH_5752VENDOR_ST_M45PE10:
9478 case FLASH_5752VENDOR_ST_M45PE20:
9479 case FLASH_5752VENDOR_ST_M45PE40:
9480 tp->nvram_jedecnum = JEDEC_ST;
9481 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9482 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9483 tp->nvram_pagesize = 256;
9484 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9485 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9486 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9487 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9488 else
9489 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9490 break;
9491 }
9492 }
9493
9494 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9495 {
9496 u32 nvcfg1;
9497
9498 nvcfg1 = tr32(NVRAM_CFG1);
9499
9500 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9501 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9502 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9503 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9504 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9505 tp->nvram_jedecnum = JEDEC_ATMEL;
9506 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9507 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9508
9509 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9510 tw32(NVRAM_CFG1, nvcfg1);
9511 break;
9512 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9513 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9514 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9515 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9516 tp->nvram_jedecnum = JEDEC_ATMEL;
9517 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9518 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9519 tp->nvram_pagesize = 264;
9520 break;
9521 case FLASH_5752VENDOR_ST_M45PE10:
9522 case FLASH_5752VENDOR_ST_M45PE20:
9523 case FLASH_5752VENDOR_ST_M45PE40:
9524 tp->nvram_jedecnum = JEDEC_ST;
9525 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9526 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9527 tp->nvram_pagesize = 256;
9528 break;
9529 }
9530 }
9531
9532 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9533 {
9534 tp->nvram_jedecnum = JEDEC_ATMEL;
9535 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9536 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9537 }
9538
9539 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9540 static void __devinit tg3_nvram_init(struct tg3 *tp)
9541 {
9542 tw32_f(GRC_EEPROM_ADDR,
9543 (EEPROM_ADDR_FSM_RESET |
9544 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9545 EEPROM_ADDR_CLKPERD_SHIFT)));
9546
9547 msleep(1);
9548
9549 /* Enable seeprom accesses. */
9550 tw32_f(GRC_LOCAL_CTRL,
9551 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9552 udelay(100);
9553
9554 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9555 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9556 tp->tg3_flags |= TG3_FLAG_NVRAM;
9557
9558 if (tg3_nvram_lock(tp)) {
9559 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9560 "tg3_nvram_init failed.\n", tp->dev->name);
9561 return;
9562 }
9563 tg3_enable_nvram_access(tp);
9564
9565 tp->nvram_size = 0;
9566
9567 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9568 tg3_get_5752_nvram_info(tp);
9569 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9570 tg3_get_5755_nvram_info(tp);
9571 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9572 tg3_get_5787_nvram_info(tp);
9573 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9574 tg3_get_5906_nvram_info(tp);
9575 else
9576 tg3_get_nvram_info(tp);
9577
9578 if (tp->nvram_size == 0)
9579 tg3_get_nvram_size(tp);
9580
9581 tg3_disable_nvram_access(tp);
9582 tg3_nvram_unlock(tp);
9583
9584 } else {
9585 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9586
9587 tg3_get_eeprom_size(tp);
9588 }
9589 }
9590
9591 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9592 u32 offset, u32 *val)
9593 {
9594 u32 tmp;
9595 int i;
9596
9597 if (offset > EEPROM_ADDR_ADDR_MASK ||
9598 (offset % 4) != 0)
9599 return -EINVAL;
9600
9601 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9602 EEPROM_ADDR_DEVID_MASK |
9603 EEPROM_ADDR_READ);
9604 tw32(GRC_EEPROM_ADDR,
9605 tmp |
9606 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9607 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9608 EEPROM_ADDR_ADDR_MASK) |
9609 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9610
9611 for (i = 0; i < 1000; i++) {
9612 tmp = tr32(GRC_EEPROM_ADDR);
9613
9614 if (tmp & EEPROM_ADDR_COMPLETE)
9615 break;
9616 msleep(1);
9617 }
9618 if (!(tmp & EEPROM_ADDR_COMPLETE))
9619 return -EBUSY;
9620
9621 *val = tr32(GRC_EEPROM_DATA);
9622 return 0;
9623 }
9624
9625 #define NVRAM_CMD_TIMEOUT 10000
9626
9627 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9628 {
9629 int i;
9630
9631 tw32(NVRAM_CMD, nvram_cmd);
9632 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9633 udelay(10);
9634 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9635 udelay(10);
9636 break;
9637 }
9638 }
9639 if (i == NVRAM_CMD_TIMEOUT) {
9640 return -EBUSY;
9641 }
9642 return 0;
9643 }
9644
9645 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9646 {
9647 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9648 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9649 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9650 (tp->nvram_jedecnum == JEDEC_ATMEL))
9651
9652 addr = ((addr / tp->nvram_pagesize) <<
9653 ATMEL_AT45DB0X1B_PAGE_POS) +
9654 (addr % tp->nvram_pagesize);
9655
9656 return addr;
9657 }
9658
9659 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9660 {
9661 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9662 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9663 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9664 (tp->nvram_jedecnum == JEDEC_ATMEL))
9665
9666 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9667 tp->nvram_pagesize) +
9668 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9669
9670 return addr;
9671 }
9672
9673 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9674 {
9675 int ret;
9676
9677 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9678 return tg3_nvram_read_using_eeprom(tp, offset, val);
9679
9680 offset = tg3_nvram_phys_addr(tp, offset);
9681
9682 if (offset > NVRAM_ADDR_MSK)
9683 return -EINVAL;
9684
9685 ret = tg3_nvram_lock(tp);
9686 if (ret)
9687 return ret;
9688
9689 tg3_enable_nvram_access(tp);
9690
9691 tw32(NVRAM_ADDR, offset);
9692 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9693 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9694
9695 if (ret == 0)
9696 *val = swab32(tr32(NVRAM_RDDATA));
9697
9698 tg3_disable_nvram_access(tp);
9699
9700 tg3_nvram_unlock(tp);
9701
9702 return ret;
9703 }
9704
9705 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9706 {
9707 int err;
9708 u32 tmp;
9709
9710 err = tg3_nvram_read(tp, offset, &tmp);
9711 *val = swab32(tmp);
9712 return err;
9713 }
9714
9715 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9716 u32 offset, u32 len, u8 *buf)
9717 {
9718 int i, j, rc = 0;
9719 u32 val;
9720
9721 for (i = 0; i < len; i += 4) {
9722 u32 addr, data;
9723
9724 addr = offset + i;
9725
9726 memcpy(&data, buf + i, 4);
9727
9728 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9729
9730 val = tr32(GRC_EEPROM_ADDR);
9731 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9732
9733 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9734 EEPROM_ADDR_READ);
9735 tw32(GRC_EEPROM_ADDR, val |
9736 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9737 (addr & EEPROM_ADDR_ADDR_MASK) |
9738 EEPROM_ADDR_START |
9739 EEPROM_ADDR_WRITE);
9740
9741 for (j = 0; j < 1000; j++) {
9742 val = tr32(GRC_EEPROM_ADDR);
9743
9744 if (val & EEPROM_ADDR_COMPLETE)
9745 break;
9746 msleep(1);
9747 }
9748 if (!(val & EEPROM_ADDR_COMPLETE)) {
9749 rc = -EBUSY;
9750 break;
9751 }
9752 }
9753
9754 return rc;
9755 }
9756
9757 /* offset and length are dword aligned */
9758 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9759 u8 *buf)
9760 {
9761 int ret = 0;
9762 u32 pagesize = tp->nvram_pagesize;
9763 u32 pagemask = pagesize - 1;
9764 u32 nvram_cmd;
9765 u8 *tmp;
9766
9767 tmp = kmalloc(pagesize, GFP_KERNEL);
9768 if (tmp == NULL)
9769 return -ENOMEM;
9770
9771 while (len) {
9772 int j;
9773 u32 phy_addr, page_off, size;
9774
9775 phy_addr = offset & ~pagemask;
9776
9777 for (j = 0; j < pagesize; j += 4) {
9778 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9779 (u32 *) (tmp + j))))
9780 break;
9781 }
9782 if (ret)
9783 break;
9784
9785 page_off = offset & pagemask;
9786 size = pagesize;
9787 if (len < size)
9788 size = len;
9789
9790 len -= size;
9791
9792 memcpy(tmp + page_off, buf, size);
9793
9794 offset = offset + (pagesize - page_off);
9795
9796 tg3_enable_nvram_access(tp);
9797
9798 /*
9799 * Before we can erase the flash page, we need
9800 * to issue a special "write enable" command.
9801 */
9802 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9803
9804 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9805 break;
9806
9807 /* Erase the target page */
9808 tw32(NVRAM_ADDR, phy_addr);
9809
9810 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9811 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9812
9813 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9814 break;
9815
9816 /* Issue another write enable to start the write. */
9817 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9818
9819 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9820 break;
9821
9822 for (j = 0; j < pagesize; j += 4) {
9823 u32 data;
9824
9825 data = *((u32 *) (tmp + j));
9826 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9827
9828 tw32(NVRAM_ADDR, phy_addr + j);
9829
9830 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9831 NVRAM_CMD_WR;
9832
9833 if (j == 0)
9834 nvram_cmd |= NVRAM_CMD_FIRST;
9835 else if (j == (pagesize - 4))
9836 nvram_cmd |= NVRAM_CMD_LAST;
9837
9838 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9839 break;
9840 }
9841 if (ret)
9842 break;
9843 }
9844
9845 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9846 tg3_nvram_exec_cmd(tp, nvram_cmd);
9847
9848 kfree(tmp);
9849
9850 return ret;
9851 }
9852
9853 /* offset and length are dword aligned */
9854 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9855 u8 *buf)
9856 {
9857 int i, ret = 0;
9858
9859 for (i = 0; i < len; i += 4, offset += 4) {
9860 u32 data, page_off, phy_addr, nvram_cmd;
9861
9862 memcpy(&data, buf + i, 4);
9863 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9864
9865 page_off = offset % tp->nvram_pagesize;
9866
9867 phy_addr = tg3_nvram_phys_addr(tp, offset);
9868
9869 tw32(NVRAM_ADDR, phy_addr);
9870
9871 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9872
9873 if ((page_off == 0) || (i == 0))
9874 nvram_cmd |= NVRAM_CMD_FIRST;
9875 if (page_off == (tp->nvram_pagesize - 4))
9876 nvram_cmd |= NVRAM_CMD_LAST;
9877
9878 if (i == (len - 4))
9879 nvram_cmd |= NVRAM_CMD_LAST;
9880
9881 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9882 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9883 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9884 (tp->nvram_jedecnum == JEDEC_ST) &&
9885 (nvram_cmd & NVRAM_CMD_FIRST)) {
9886
9887 if ((ret = tg3_nvram_exec_cmd(tp,
9888 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9889 NVRAM_CMD_DONE)))
9890
9891 break;
9892 }
9893 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9894 /* We always do complete word writes to eeprom. */
9895 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9896 }
9897
9898 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9899 break;
9900 }
9901 return ret;
9902 }
9903
9904 /* offset and length are dword aligned */
9905 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9906 {
9907 int ret;
9908
9909 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9910 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9911 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9912 udelay(40);
9913 }
9914
9915 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9916 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9917 }
9918 else {
9919 u32 grc_mode;
9920
9921 ret = tg3_nvram_lock(tp);
9922 if (ret)
9923 return ret;
9924
9925 tg3_enable_nvram_access(tp);
9926 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9927 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9928 tw32(NVRAM_WRITE1, 0x406);
9929
9930 grc_mode = tr32(GRC_MODE);
9931 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9932
9933 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9934 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9935
9936 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9937 buf);
9938 }
9939 else {
9940 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9941 buf);
9942 }
9943
9944 grc_mode = tr32(GRC_MODE);
9945 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9946
9947 tg3_disable_nvram_access(tp);
9948 tg3_nvram_unlock(tp);
9949 }
9950
9951 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9952 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9953 udelay(40);
9954 }
9955
9956 return ret;
9957 }
9958
9959 struct subsys_tbl_ent {
9960 u16 subsys_vendor, subsys_devid;
9961 u32 phy_id;
9962 };
9963
9964 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9965 /* Broadcom boards. */
9966 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9967 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9968 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9969 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9970 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9971 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9972 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9973 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9974 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9975 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9976 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9977
9978 /* 3com boards. */
9979 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9980 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9981 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9982 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9983 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9984
9985 /* DELL boards. */
9986 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9987 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9988 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9989 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9990
9991 /* Compaq boards. */
9992 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9993 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9994 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9995 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9996 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9997
9998 /* IBM boards. */
9999 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10000 };
10001
10002 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10003 {
10004 int i;
10005
10006 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10007 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10008 tp->pdev->subsystem_vendor) &&
10009 (subsys_id_to_phy_id[i].subsys_devid ==
10010 tp->pdev->subsystem_device))
10011 return &subsys_id_to_phy_id[i];
10012 }
10013 return NULL;
10014 }
10015
10016 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10017 {
10018 u32 val;
10019 u16 pmcsr;
10020
10021 /* On some early chips the SRAM cannot be accessed in D3hot state,
10022 * so need make sure we're in D0.
10023 */
10024 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10025 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10026 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10027 msleep(1);
10028
10029 /* Make sure register accesses (indirect or otherwise)
10030 * will function correctly.
10031 */
10032 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10033 tp->misc_host_ctrl);
10034
10035 /* The memory arbiter has to be enabled in order for SRAM accesses
10036 * to succeed. Normally on powerup the tg3 chip firmware will make
10037 * sure it is enabled, but other entities such as system netboot
10038 * code might disable it.
10039 */
10040 val = tr32(MEMARB_MODE);
10041 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10042
10043 tp->phy_id = PHY_ID_INVALID;
10044 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10045
10046 /* Assume an onboard device and WOL capable by default. */
10047 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10048
10049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10050 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10051 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10052 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10053 }
10054 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10055 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10056 return;
10057 }
10058
10059 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10060 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10061 u32 nic_cfg, led_cfg;
10062 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10063 int eeprom_phy_serdes = 0;
10064
10065 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10066 tp->nic_sram_data_cfg = nic_cfg;
10067
10068 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10069 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10070 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10071 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10072 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10073 (ver > 0) && (ver < 0x100))
10074 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10075
10076 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10077 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10078 eeprom_phy_serdes = 1;
10079
10080 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10081 if (nic_phy_id != 0) {
10082 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10083 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10084
10085 eeprom_phy_id = (id1 >> 16) << 10;
10086 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10087 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10088 } else
10089 eeprom_phy_id = 0;
10090
10091 tp->phy_id = eeprom_phy_id;
10092 if (eeprom_phy_serdes) {
10093 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10094 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10095 else
10096 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10097 }
10098
10099 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10100 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10101 SHASTA_EXT_LED_MODE_MASK);
10102 else
10103 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10104
10105 switch (led_cfg) {
10106 default:
10107 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10108 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10109 break;
10110
10111 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10112 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10113 break;
10114
10115 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10116 tp->led_ctrl = LED_CTRL_MODE_MAC;
10117
10118 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10119 * read on some older 5700/5701 bootcode.
10120 */
10121 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10122 ASIC_REV_5700 ||
10123 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10124 ASIC_REV_5701)
10125 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10126
10127 break;
10128
10129 case SHASTA_EXT_LED_SHARED:
10130 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10131 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10132 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10133 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10134 LED_CTRL_MODE_PHY_2);
10135 break;
10136
10137 case SHASTA_EXT_LED_MAC:
10138 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10139 break;
10140
10141 case SHASTA_EXT_LED_COMBO:
10142 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10143 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10144 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10145 LED_CTRL_MODE_PHY_2);
10146 break;
10147
10148 };
10149
10150 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10152 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10153 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10154
10155 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10156 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10157 if ((tp->pdev->subsystem_vendor ==
10158 PCI_VENDOR_ID_ARIMA) &&
10159 (tp->pdev->subsystem_device == 0x205a ||
10160 tp->pdev->subsystem_device == 0x2063))
10161 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10162 } else {
10163 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10164 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10165 }
10166
10167 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10168 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10169 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10170 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10171 }
10172 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10173 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10174 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10175
10176 if (cfg2 & (1 << 17))
10177 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10178
10179 /* serdes signal pre-emphasis in register 0x590 set by */
10180 /* bootcode if bit 18 is set */
10181 if (cfg2 & (1 << 18))
10182 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10183
10184 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10185 u32 cfg3;
10186
10187 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10188 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10189 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10190 }
10191 }
10192 }
10193
10194 static int __devinit tg3_phy_probe(struct tg3 *tp)
10195 {
10196 u32 hw_phy_id_1, hw_phy_id_2;
10197 u32 hw_phy_id, hw_phy_id_masked;
10198 int err;
10199
10200 /* Reading the PHY ID register can conflict with ASF
10201 * firwmare access to the PHY hardware.
10202 */
10203 err = 0;
10204 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10205 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10206 } else {
10207 /* Now read the physical PHY_ID from the chip and verify
10208 * that it is sane. If it doesn't look good, we fall back
10209 * to either the hard-coded table based PHY_ID and failing
10210 * that the value found in the eeprom area.
10211 */
10212 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10213 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10214
10215 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10216 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10217 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10218
10219 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10220 }
10221
10222 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10223 tp->phy_id = hw_phy_id;
10224 if (hw_phy_id_masked == PHY_ID_BCM8002)
10225 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10226 else
10227 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10228 } else {
10229 if (tp->phy_id != PHY_ID_INVALID) {
10230 /* Do nothing, phy ID already set up in
10231 * tg3_get_eeprom_hw_cfg().
10232 */
10233 } else {
10234 struct subsys_tbl_ent *p;
10235
10236 /* No eeprom signature? Try the hardcoded
10237 * subsys device table.
10238 */
10239 p = lookup_by_subsys(tp);
10240 if (!p)
10241 return -ENODEV;
10242
10243 tp->phy_id = p->phy_id;
10244 if (!tp->phy_id ||
10245 tp->phy_id == PHY_ID_BCM8002)
10246 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10247 }
10248 }
10249
10250 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10251 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10252 u32 bmsr, adv_reg, tg3_ctrl, mask;
10253
10254 tg3_readphy(tp, MII_BMSR, &bmsr);
10255 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10256 (bmsr & BMSR_LSTATUS))
10257 goto skip_phy_reset;
10258
10259 err = tg3_phy_reset(tp);
10260 if (err)
10261 return err;
10262
10263 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10264 ADVERTISE_100HALF | ADVERTISE_100FULL |
10265 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10266 tg3_ctrl = 0;
10267 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10268 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10269 MII_TG3_CTRL_ADV_1000_FULL);
10270 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10271 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10272 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10273 MII_TG3_CTRL_ENABLE_AS_MASTER);
10274 }
10275
10276 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10277 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10278 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10279 if (!tg3_copper_is_advertising_all(tp, mask)) {
10280 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10281
10282 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10283 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10284
10285 tg3_writephy(tp, MII_BMCR,
10286 BMCR_ANENABLE | BMCR_ANRESTART);
10287 }
10288 tg3_phy_set_wirespeed(tp);
10289
10290 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10291 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10292 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10293 }
10294
10295 skip_phy_reset:
10296 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10297 err = tg3_init_5401phy_dsp(tp);
10298 if (err)
10299 return err;
10300 }
10301
10302 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10303 err = tg3_init_5401phy_dsp(tp);
10304 }
10305
10306 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10307 tp->link_config.advertising =
10308 (ADVERTISED_1000baseT_Half |
10309 ADVERTISED_1000baseT_Full |
10310 ADVERTISED_Autoneg |
10311 ADVERTISED_FIBRE);
10312 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10313 tp->link_config.advertising &=
10314 ~(ADVERTISED_1000baseT_Half |
10315 ADVERTISED_1000baseT_Full);
10316
10317 return err;
10318 }
10319
10320 static void __devinit tg3_read_partno(struct tg3 *tp)
10321 {
10322 unsigned char vpd_data[256];
10323 unsigned int i;
10324 u32 magic;
10325
10326 if (tg3_nvram_read_swab(tp, 0x0, &magic))
10327 goto out_not_found;
10328
10329 if (magic == TG3_EEPROM_MAGIC) {
10330 for (i = 0; i < 256; i += 4) {
10331 u32 tmp;
10332
10333 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10334 goto out_not_found;
10335
10336 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10337 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10338 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10339 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10340 }
10341 } else {
10342 int vpd_cap;
10343
10344 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10345 for (i = 0; i < 256; i += 4) {
10346 u32 tmp, j = 0;
10347 u16 tmp16;
10348
10349 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10350 i);
10351 while (j++ < 100) {
10352 pci_read_config_word(tp->pdev, vpd_cap +
10353 PCI_VPD_ADDR, &tmp16);
10354 if (tmp16 & 0x8000)
10355 break;
10356 msleep(1);
10357 }
10358 if (!(tmp16 & 0x8000))
10359 goto out_not_found;
10360
10361 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10362 &tmp);
10363 tmp = cpu_to_le32(tmp);
10364 memcpy(&vpd_data[i], &tmp, 4);
10365 }
10366 }
10367
10368 /* Now parse and find the part number. */
10369 for (i = 0; i < 254; ) {
10370 unsigned char val = vpd_data[i];
10371 unsigned int block_end;
10372
10373 if (val == 0x82 || val == 0x91) {
10374 i = (i + 3 +
10375 (vpd_data[i + 1] +
10376 (vpd_data[i + 2] << 8)));
10377 continue;
10378 }
10379
10380 if (val != 0x90)
10381 goto out_not_found;
10382
10383 block_end = (i + 3 +
10384 (vpd_data[i + 1] +
10385 (vpd_data[i + 2] << 8)));
10386 i += 3;
10387
10388 if (block_end > 256)
10389 goto out_not_found;
10390
10391 while (i < (block_end - 2)) {
10392 if (vpd_data[i + 0] == 'P' &&
10393 vpd_data[i + 1] == 'N') {
10394 int partno_len = vpd_data[i + 2];
10395
10396 i += 3;
10397 if (partno_len > 24 || (partno_len + i) > 256)
10398 goto out_not_found;
10399
10400 memcpy(tp->board_part_number,
10401 &vpd_data[i], partno_len);
10402
10403 /* Success. */
10404 return;
10405 }
10406 i += 3 + vpd_data[i + 2];
10407 }
10408
10409 /* Part number not found. */
10410 goto out_not_found;
10411 }
10412
10413 out_not_found:
10414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10415 strcpy(tp->board_part_number, "BCM95906");
10416 else
10417 strcpy(tp->board_part_number, "none");
10418 }
10419
10420 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10421 {
10422 u32 val, offset, start;
10423
10424 if (tg3_nvram_read_swab(tp, 0, &val))
10425 return;
10426
10427 if (val != TG3_EEPROM_MAGIC)
10428 return;
10429
10430 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10431 tg3_nvram_read_swab(tp, 0x4, &start))
10432 return;
10433
10434 offset = tg3_nvram_logical_addr(tp, offset);
10435 if (tg3_nvram_read_swab(tp, offset, &val))
10436 return;
10437
10438 if ((val & 0xfc000000) == 0x0c000000) {
10439 u32 ver_offset, addr;
10440 int i;
10441
10442 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10443 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10444 return;
10445
10446 if (val != 0)
10447 return;
10448
10449 addr = offset + ver_offset - start;
10450 for (i = 0; i < 16; i += 4) {
10451 if (tg3_nvram_read(tp, addr + i, &val))
10452 return;
10453
10454 val = cpu_to_le32(val);
10455 memcpy(tp->fw_ver + i, &val, 4);
10456 }
10457 }
10458 }
10459
10460 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10461
10462 static int __devinit tg3_get_invariants(struct tg3 *tp)
10463 {
10464 static struct pci_device_id write_reorder_chipsets[] = {
10465 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10466 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10467 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10468 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10469 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10470 PCI_DEVICE_ID_VIA_8385_0) },
10471 { },
10472 };
10473 u32 misc_ctrl_reg;
10474 u32 cacheline_sz_reg;
10475 u32 pci_state_reg, grc_misc_cfg;
10476 u32 val;
10477 u16 pci_cmd;
10478 int err, pcie_cap;
10479
10480 /* Force memory write invalidate off. If we leave it on,
10481 * then on 5700_BX chips we have to enable a workaround.
10482 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10483 * to match the cacheline size. The Broadcom driver have this
10484 * workaround but turns MWI off all the times so never uses
10485 * it. This seems to suggest that the workaround is insufficient.
10486 */
10487 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10488 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10489 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10490
10491 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10492 * has the register indirect write enable bit set before
10493 * we try to access any of the MMIO registers. It is also
10494 * critical that the PCI-X hw workaround situation is decided
10495 * before that as well.
10496 */
10497 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10498 &misc_ctrl_reg);
10499
10500 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10501 MISC_HOST_CTRL_CHIPREV_SHIFT);
10502
10503 /* Wrong chip ID in 5752 A0. This code can be removed later
10504 * as A0 is not in production.
10505 */
10506 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10507 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10508
10509 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10510 * we need to disable memory and use config. cycles
10511 * only to access all registers. The 5702/03 chips
10512 * can mistakenly decode the special cycles from the
10513 * ICH chipsets as memory write cycles, causing corruption
10514 * of register and memory space. Only certain ICH bridges
10515 * will drive special cycles with non-zero data during the
10516 * address phase which can fall within the 5703's address
10517 * range. This is not an ICH bug as the PCI spec allows
10518 * non-zero address during special cycles. However, only
10519 * these ICH bridges are known to drive non-zero addresses
10520 * during special cycles.
10521 *
10522 * Since special cycles do not cross PCI bridges, we only
10523 * enable this workaround if the 5703 is on the secondary
10524 * bus of these ICH bridges.
10525 */
10526 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10527 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10528 static struct tg3_dev_id {
10529 u32 vendor;
10530 u32 device;
10531 u32 rev;
10532 } ich_chipsets[] = {
10533 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10534 PCI_ANY_ID },
10535 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10536 PCI_ANY_ID },
10537 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10538 0xa },
10539 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10540 PCI_ANY_ID },
10541 { },
10542 };
10543 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10544 struct pci_dev *bridge = NULL;
10545
10546 while (pci_id->vendor != 0) {
10547 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10548 bridge);
10549 if (!bridge) {
10550 pci_id++;
10551 continue;
10552 }
10553 if (pci_id->rev != PCI_ANY_ID) {
10554 if (bridge->revision > pci_id->rev)
10555 continue;
10556 }
10557 if (bridge->subordinate &&
10558 (bridge->subordinate->number ==
10559 tp->pdev->bus->number)) {
10560
10561 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10562 pci_dev_put(bridge);
10563 break;
10564 }
10565 }
10566 }
10567
10568 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10569 * DMA addresses > 40-bit. This bridge may have other additional
10570 * 57xx devices behind it in some 4-port NIC designs for example.
10571 * Any tg3 device found behind the bridge will also need the 40-bit
10572 * DMA workaround.
10573 */
10574 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10575 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10576 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10577 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10578 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10579 }
10580 else {
10581 struct pci_dev *bridge = NULL;
10582
10583 do {
10584 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10585 PCI_DEVICE_ID_SERVERWORKS_EPB,
10586 bridge);
10587 if (bridge && bridge->subordinate &&
10588 (bridge->subordinate->number <=
10589 tp->pdev->bus->number) &&
10590 (bridge->subordinate->subordinate >=
10591 tp->pdev->bus->number)) {
10592 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10593 pci_dev_put(bridge);
10594 break;
10595 }
10596 } while (bridge);
10597 }
10598
10599 /* Initialize misc host control in PCI block. */
10600 tp->misc_host_ctrl |= (misc_ctrl_reg &
10601 MISC_HOST_CTRL_CHIPREV);
10602 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10603 tp->misc_host_ctrl);
10604
10605 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10606 &cacheline_sz_reg);
10607
10608 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10609 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10610 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10611 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10612
10613 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10614 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10615 tp->pdev_peer = tg3_find_peer(tp);
10616
10617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10618 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10621 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10622 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10623 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10624
10625 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10626 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10627 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10628
10629 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10630 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10631 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10632 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10633 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10634 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10635 tp->pdev_peer == tp->pdev))
10636 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10637
10638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10639 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10641 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10642 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10643 } else {
10644 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10645 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10646 ASIC_REV_5750 &&
10647 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10648 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10649 }
10650 }
10651
10652 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10653 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10654 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10655 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10656 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10657 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10658 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10659
10660 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10661 if (pcie_cap != 0) {
10662 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10664 u16 lnkctl;
10665
10666 pci_read_config_word(tp->pdev,
10667 pcie_cap + PCI_EXP_LNKCTL,
10668 &lnkctl);
10669 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10670 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10671 }
10672 }
10673
10674 /* If we have an AMD 762 or VIA K8T800 chipset, write
10675 * reordering to the mailbox registers done by the host
10676 * controller can cause major troubles. We read back from
10677 * every mailbox register write to force the writes to be
10678 * posted to the chip in order.
10679 */
10680 if (pci_dev_present(write_reorder_chipsets) &&
10681 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10682 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10683
10684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10685 tp->pci_lat_timer < 64) {
10686 tp->pci_lat_timer = 64;
10687
10688 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10689 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10690 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10691 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10692
10693 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10694 cacheline_sz_reg);
10695 }
10696
10697 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10698 &pci_state_reg);
10699
10700 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10701 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10702
10703 /* If this is a 5700 BX chipset, and we are in PCI-X
10704 * mode, enable register write workaround.
10705 *
10706 * The workaround is to use indirect register accesses
10707 * for all chip writes not to mailbox registers.
10708 */
10709 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10710 u32 pm_reg;
10711 u16 pci_cmd;
10712
10713 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10714
10715 /* The chip can have it's power management PCI config
10716 * space registers clobbered due to this bug.
10717 * So explicitly force the chip into D0 here.
10718 */
10719 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10720 &pm_reg);
10721 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10722 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10723 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10724 pm_reg);
10725
10726 /* Also, force SERR#/PERR# in PCI command. */
10727 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10728 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10729 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10730 }
10731 }
10732
10733 /* 5700 BX chips need to have their TX producer index mailboxes
10734 * written twice to workaround a bug.
10735 */
10736 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10737 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10738
10739 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10740 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10741 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10742 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10743
10744 /* Chip-specific fixup from Broadcom driver */
10745 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10746 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10747 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10748 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10749 }
10750
10751 /* Default fast path register access methods */
10752 tp->read32 = tg3_read32;
10753 tp->write32 = tg3_write32;
10754 tp->read32_mbox = tg3_read32;
10755 tp->write32_mbox = tg3_write32;
10756 tp->write32_tx_mbox = tg3_write32;
10757 tp->write32_rx_mbox = tg3_write32;
10758
10759 /* Various workaround register access methods */
10760 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10761 tp->write32 = tg3_write_indirect_reg32;
10762 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10763 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10764 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10765 /*
10766 * Back to back register writes can cause problems on these
10767 * chips, the workaround is to read back all reg writes
10768 * except those to mailbox regs.
10769 *
10770 * See tg3_write_indirect_reg32().
10771 */
10772 tp->write32 = tg3_write_flush_reg32;
10773 }
10774
10775
10776 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10777 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10778 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10779 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10780 tp->write32_rx_mbox = tg3_write_flush_reg32;
10781 }
10782
10783 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10784 tp->read32 = tg3_read_indirect_reg32;
10785 tp->write32 = tg3_write_indirect_reg32;
10786 tp->read32_mbox = tg3_read_indirect_mbox;
10787 tp->write32_mbox = tg3_write_indirect_mbox;
10788 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10789 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10790
10791 iounmap(tp->regs);
10792 tp->regs = NULL;
10793
10794 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10795 pci_cmd &= ~PCI_COMMAND_MEMORY;
10796 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10797 }
10798 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10799 tp->read32_mbox = tg3_read32_mbox_5906;
10800 tp->write32_mbox = tg3_write32_mbox_5906;
10801 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10802 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10803 }
10804
10805 if (tp->write32 == tg3_write_indirect_reg32 ||
10806 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10807 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10808 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10809 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10810
10811 /* Get eeprom hw config before calling tg3_set_power_state().
10812 * In particular, the TG3_FLG2_IS_NIC flag must be
10813 * determined before calling tg3_set_power_state() so that
10814 * we know whether or not to switch out of Vaux power.
10815 * When the flag is set, it means that GPIO1 is used for eeprom
10816 * write protect and also implies that it is a LOM where GPIOs
10817 * are not used to switch power.
10818 */
10819 tg3_get_eeprom_hw_cfg(tp);
10820
10821 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10822 * GPIO1 driven high will bring 5700's external PHY out of reset.
10823 * It is also used as eeprom write protect on LOMs.
10824 */
10825 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10826 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10827 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10828 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10829 GRC_LCLCTRL_GPIO_OUTPUT1);
10830 /* Unused GPIO3 must be driven as output on 5752 because there
10831 * are no pull-up resistors on unused GPIO pins.
10832 */
10833 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10834 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10835
10836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10837 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10838
10839 /* Force the chip into D0. */
10840 err = tg3_set_power_state(tp, PCI_D0);
10841 if (err) {
10842 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10843 pci_name(tp->pdev));
10844 return err;
10845 }
10846
10847 /* 5700 B0 chips do not support checksumming correctly due
10848 * to hardware bugs.
10849 */
10850 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10851 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10852
10853 /* Derive initial jumbo mode from MTU assigned in
10854 * ether_setup() via the alloc_etherdev() call
10855 */
10856 if (tp->dev->mtu > ETH_DATA_LEN &&
10857 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10858 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10859
10860 /* Determine WakeOnLan speed to use. */
10861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10862 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10863 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10864 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10865 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10866 } else {
10867 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10868 }
10869
10870 /* A few boards don't want Ethernet@WireSpeed phy feature */
10871 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10872 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10873 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10874 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10875 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10876 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10877 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10878
10879 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10880 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10881 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10882 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10883 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10884
10885 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10888 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10889 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10890 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10891 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10892 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10893 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10894 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10895 }
10896
10897 tp->coalesce_mode = 0;
10898 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10899 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10900 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10901
10902 /* Initialize MAC MI mode, polling disabled. */
10903 tw32_f(MAC_MI_MODE, tp->mi_mode);
10904 udelay(80);
10905
10906 /* Initialize data/descriptor byte/word swapping. */
10907 val = tr32(GRC_MODE);
10908 val &= GRC_MODE_HOST_STACKUP;
10909 tw32(GRC_MODE, val | tp->grc_mode);
10910
10911 tg3_switch_clocks(tp);
10912
10913 /* Clear this out for sanity. */
10914 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10915
10916 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10917 &pci_state_reg);
10918 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10919 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10920 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10921
10922 if (chiprevid == CHIPREV_ID_5701_A0 ||
10923 chiprevid == CHIPREV_ID_5701_B0 ||
10924 chiprevid == CHIPREV_ID_5701_B2 ||
10925 chiprevid == CHIPREV_ID_5701_B5) {
10926 void __iomem *sram_base;
10927
10928 /* Write some dummy words into the SRAM status block
10929 * area, see if it reads back correctly. If the return
10930 * value is bad, force enable the PCIX workaround.
10931 */
10932 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10933
10934 writel(0x00000000, sram_base);
10935 writel(0x00000000, sram_base + 4);
10936 writel(0xffffffff, sram_base + 4);
10937 if (readl(sram_base) != 0x00000000)
10938 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10939 }
10940 }
10941
10942 udelay(50);
10943 tg3_nvram_init(tp);
10944
10945 grc_misc_cfg = tr32(GRC_MISC_CFG);
10946 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10947
10948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10949 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10950 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10951 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10952
10953 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10954 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10955 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10956 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10957 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10958 HOSTCC_MODE_CLRTICK_TXBD);
10959
10960 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10961 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10962 tp->misc_host_ctrl);
10963 }
10964
10965 /* these are limited to 10/100 only */
10966 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10967 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10968 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10969 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10970 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10971 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10972 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10973 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10974 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10975 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10976 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10978 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10979
10980 err = tg3_phy_probe(tp);
10981 if (err) {
10982 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10983 pci_name(tp->pdev), err);
10984 /* ... but do not return immediately ... */
10985 }
10986
10987 tg3_read_partno(tp);
10988 tg3_read_fw_ver(tp);
10989
10990 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10991 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10992 } else {
10993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10994 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10995 else
10996 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10997 }
10998
10999 /* 5700 {AX,BX} chips have a broken status block link
11000 * change bit implementation, so we must use the
11001 * status register in those cases.
11002 */
11003 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11004 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11005 else
11006 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11007
11008 /* The led_ctrl is set during tg3_phy_probe, here we might
11009 * have to force the link status polling mechanism based
11010 * upon subsystem IDs.
11011 */
11012 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11014 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11015 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11016 TG3_FLAG_USE_LINKCHG_REG);
11017 }
11018
11019 /* For all SERDES we poll the MAC status register. */
11020 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11021 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11022 else
11023 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11024
11025 /* All chips before 5787 can get confused if TX buffers
11026 * straddle the 4GB address boundary in some cases.
11027 */
11028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11031 tp->dev->hard_start_xmit = tg3_start_xmit;
11032 else
11033 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11034
11035 tp->rx_offset = 2;
11036 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11037 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11038 tp->rx_offset = 0;
11039
11040 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11041
11042 /* Increment the rx prod index on the rx std ring by at most
11043 * 8 for these chips to workaround hw errata.
11044 */
11045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11048 tp->rx_std_max_post = 8;
11049
11050 /* By default, disable wake-on-lan. User can change this
11051 * using ETHTOOL_SWOL.
11052 */
11053 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11054
11055 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11056 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11057 PCIE_PWR_MGMT_L1_THRESH_MSK;
11058
11059 return err;
11060 }
11061
11062 #ifdef CONFIG_SPARC
11063 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11064 {
11065 struct net_device *dev = tp->dev;
11066 struct pci_dev *pdev = tp->pdev;
11067 struct device_node *dp = pci_device_to_OF_node(pdev);
11068 const unsigned char *addr;
11069 int len;
11070
11071 addr = of_get_property(dp, "local-mac-address", &len);
11072 if (addr && len == 6) {
11073 memcpy(dev->dev_addr, addr, 6);
11074 memcpy(dev->perm_addr, dev->dev_addr, 6);
11075 return 0;
11076 }
11077 return -ENODEV;
11078 }
11079
11080 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11081 {
11082 struct net_device *dev = tp->dev;
11083
11084 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11085 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11086 return 0;
11087 }
11088 #endif
11089
11090 static int __devinit tg3_get_device_address(struct tg3 *tp)
11091 {
11092 struct net_device *dev = tp->dev;
11093 u32 hi, lo, mac_offset;
11094 int addr_ok = 0;
11095
11096 #ifdef CONFIG_SPARC
11097 if (!tg3_get_macaddr_sparc(tp))
11098 return 0;
11099 #endif
11100
11101 mac_offset = 0x7c;
11102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11103 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11104 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11105 mac_offset = 0xcc;
11106 if (tg3_nvram_lock(tp))
11107 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11108 else
11109 tg3_nvram_unlock(tp);
11110 }
11111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11112 mac_offset = 0x10;
11113
11114 /* First try to get it from MAC address mailbox. */
11115 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11116 if ((hi >> 16) == 0x484b) {
11117 dev->dev_addr[0] = (hi >> 8) & 0xff;
11118 dev->dev_addr[1] = (hi >> 0) & 0xff;
11119
11120 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11121 dev->dev_addr[2] = (lo >> 24) & 0xff;
11122 dev->dev_addr[3] = (lo >> 16) & 0xff;
11123 dev->dev_addr[4] = (lo >> 8) & 0xff;
11124 dev->dev_addr[5] = (lo >> 0) & 0xff;
11125
11126 /* Some old bootcode may report a 0 MAC address in SRAM */
11127 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11128 }
11129 if (!addr_ok) {
11130 /* Next, try NVRAM. */
11131 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11132 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11133 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11134 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11135 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11136 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11137 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11138 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11139 }
11140 /* Finally just fetch it out of the MAC control regs. */
11141 else {
11142 hi = tr32(MAC_ADDR_0_HIGH);
11143 lo = tr32(MAC_ADDR_0_LOW);
11144
11145 dev->dev_addr[5] = lo & 0xff;
11146 dev->dev_addr[4] = (lo >> 8) & 0xff;
11147 dev->dev_addr[3] = (lo >> 16) & 0xff;
11148 dev->dev_addr[2] = (lo >> 24) & 0xff;
11149 dev->dev_addr[1] = hi & 0xff;
11150 dev->dev_addr[0] = (hi >> 8) & 0xff;
11151 }
11152 }
11153
11154 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11155 #ifdef CONFIG_SPARC64
11156 if (!tg3_get_default_macaddr_sparc(tp))
11157 return 0;
11158 #endif
11159 return -EINVAL;
11160 }
11161 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11162 return 0;
11163 }
11164
11165 #define BOUNDARY_SINGLE_CACHELINE 1
11166 #define BOUNDARY_MULTI_CACHELINE 2
11167
11168 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11169 {
11170 int cacheline_size;
11171 u8 byte;
11172 int goal;
11173
11174 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11175 if (byte == 0)
11176 cacheline_size = 1024;
11177 else
11178 cacheline_size = (int) byte * 4;
11179
11180 /* On 5703 and later chips, the boundary bits have no
11181 * effect.
11182 */
11183 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11184 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11185 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11186 goto out;
11187
11188 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11189 goal = BOUNDARY_MULTI_CACHELINE;
11190 #else
11191 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11192 goal = BOUNDARY_SINGLE_CACHELINE;
11193 #else
11194 goal = 0;
11195 #endif
11196 #endif
11197
11198 if (!goal)
11199 goto out;
11200
11201 /* PCI controllers on most RISC systems tend to disconnect
11202 * when a device tries to burst across a cache-line boundary.
11203 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11204 *
11205 * Unfortunately, for PCI-E there are only limited
11206 * write-side controls for this, and thus for reads
11207 * we will still get the disconnects. We'll also waste
11208 * these PCI cycles for both read and write for chips
11209 * other than 5700 and 5701 which do not implement the
11210 * boundary bits.
11211 */
11212 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11213 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11214 switch (cacheline_size) {
11215 case 16:
11216 case 32:
11217 case 64:
11218 case 128:
11219 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11220 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11221 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11222 } else {
11223 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11224 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11225 }
11226 break;
11227
11228 case 256:
11229 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11230 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11231 break;
11232
11233 default:
11234 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11235 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11236 break;
11237 };
11238 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11239 switch (cacheline_size) {
11240 case 16:
11241 case 32:
11242 case 64:
11243 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11244 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11245 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11246 break;
11247 }
11248 /* fallthrough */
11249 case 128:
11250 default:
11251 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11252 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11253 break;
11254 };
11255 } else {
11256 switch (cacheline_size) {
11257 case 16:
11258 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11259 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11260 DMA_RWCTRL_WRITE_BNDRY_16);
11261 break;
11262 }
11263 /* fallthrough */
11264 case 32:
11265 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11266 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11267 DMA_RWCTRL_WRITE_BNDRY_32);
11268 break;
11269 }
11270 /* fallthrough */
11271 case 64:
11272 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11273 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11274 DMA_RWCTRL_WRITE_BNDRY_64);
11275 break;
11276 }
11277 /* fallthrough */
11278 case 128:
11279 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11280 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11281 DMA_RWCTRL_WRITE_BNDRY_128);
11282 break;
11283 }
11284 /* fallthrough */
11285 case 256:
11286 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11287 DMA_RWCTRL_WRITE_BNDRY_256);
11288 break;
11289 case 512:
11290 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11291 DMA_RWCTRL_WRITE_BNDRY_512);
11292 break;
11293 case 1024:
11294 default:
11295 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11296 DMA_RWCTRL_WRITE_BNDRY_1024);
11297 break;
11298 };
11299 }
11300
11301 out:
11302 return val;
11303 }
11304
11305 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11306 {
11307 struct tg3_internal_buffer_desc test_desc;
11308 u32 sram_dma_descs;
11309 int i, ret;
11310
11311 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11312
11313 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11314 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11315 tw32(RDMAC_STATUS, 0);
11316 tw32(WDMAC_STATUS, 0);
11317
11318 tw32(BUFMGR_MODE, 0);
11319 tw32(FTQ_RESET, 0);
11320
11321 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11322 test_desc.addr_lo = buf_dma & 0xffffffff;
11323 test_desc.nic_mbuf = 0x00002100;
11324 test_desc.len = size;
11325
11326 /*
11327 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11328 * the *second* time the tg3 driver was getting loaded after an
11329 * initial scan.
11330 *
11331 * Broadcom tells me:
11332 * ...the DMA engine is connected to the GRC block and a DMA
11333 * reset may affect the GRC block in some unpredictable way...
11334 * The behavior of resets to individual blocks has not been tested.
11335 *
11336 * Broadcom noted the GRC reset will also reset all sub-components.
11337 */
11338 if (to_device) {
11339 test_desc.cqid_sqid = (13 << 8) | 2;
11340
11341 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11342 udelay(40);
11343 } else {
11344 test_desc.cqid_sqid = (16 << 8) | 7;
11345
11346 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11347 udelay(40);
11348 }
11349 test_desc.flags = 0x00000005;
11350
11351 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11352 u32 val;
11353
11354 val = *(((u32 *)&test_desc) + i);
11355 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11356 sram_dma_descs + (i * sizeof(u32)));
11357 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11358 }
11359 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11360
11361 if (to_device) {
11362 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11363 } else {
11364 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11365 }
11366
11367 ret = -ENODEV;
11368 for (i = 0; i < 40; i++) {
11369 u32 val;
11370
11371 if (to_device)
11372 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11373 else
11374 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11375 if ((val & 0xffff) == sram_dma_descs) {
11376 ret = 0;
11377 break;
11378 }
11379
11380 udelay(100);
11381 }
11382
11383 return ret;
11384 }
11385
11386 #define TEST_BUFFER_SIZE 0x2000
11387
11388 static int __devinit tg3_test_dma(struct tg3 *tp)
11389 {
11390 dma_addr_t buf_dma;
11391 u32 *buf, saved_dma_rwctrl;
11392 int ret;
11393
11394 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11395 if (!buf) {
11396 ret = -ENOMEM;
11397 goto out_nofree;
11398 }
11399
11400 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11401 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11402
11403 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11404
11405 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11406 /* DMA read watermark not used on PCIE */
11407 tp->dma_rwctrl |= 0x00180000;
11408 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11411 tp->dma_rwctrl |= 0x003f0000;
11412 else
11413 tp->dma_rwctrl |= 0x003f000f;
11414 } else {
11415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11416 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11417 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11418 u32 read_water = 0x7;
11419
11420 /* If the 5704 is behind the EPB bridge, we can
11421 * do the less restrictive ONE_DMA workaround for
11422 * better performance.
11423 */
11424 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11426 tp->dma_rwctrl |= 0x8000;
11427 else if (ccval == 0x6 || ccval == 0x7)
11428 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11429
11430 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11431 read_water = 4;
11432 /* Set bit 23 to enable PCIX hw bug fix */
11433 tp->dma_rwctrl |=
11434 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11435 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11436 (1 << 23);
11437 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11438 /* 5780 always in PCIX mode */
11439 tp->dma_rwctrl |= 0x00144000;
11440 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11441 /* 5714 always in PCIX mode */
11442 tp->dma_rwctrl |= 0x00148000;
11443 } else {
11444 tp->dma_rwctrl |= 0x001b000f;
11445 }
11446 }
11447
11448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11449 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11450 tp->dma_rwctrl &= 0xfffffff0;
11451
11452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11453 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11454 /* Remove this if it causes problems for some boards. */
11455 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11456
11457 /* On 5700/5701 chips, we need to set this bit.
11458 * Otherwise the chip will issue cacheline transactions
11459 * to streamable DMA memory with not all the byte
11460 * enables turned on. This is an error on several
11461 * RISC PCI controllers, in particular sparc64.
11462 *
11463 * On 5703/5704 chips, this bit has been reassigned
11464 * a different meaning. In particular, it is used
11465 * on those chips to enable a PCI-X workaround.
11466 */
11467 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11468 }
11469
11470 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11471
11472 #if 0
11473 /* Unneeded, already done by tg3_get_invariants. */
11474 tg3_switch_clocks(tp);
11475 #endif
11476
11477 ret = 0;
11478 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11479 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11480 goto out;
11481
11482 /* It is best to perform DMA test with maximum write burst size
11483 * to expose the 5700/5701 write DMA bug.
11484 */
11485 saved_dma_rwctrl = tp->dma_rwctrl;
11486 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11487 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11488
11489 while (1) {
11490 u32 *p = buf, i;
11491
11492 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11493 p[i] = i;
11494
11495 /* Send the buffer to the chip. */
11496 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11497 if (ret) {
11498 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11499 break;
11500 }
11501
11502 #if 0
11503 /* validate data reached card RAM correctly. */
11504 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11505 u32 val;
11506 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11507 if (le32_to_cpu(val) != p[i]) {
11508 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11509 /* ret = -ENODEV here? */
11510 }
11511 p[i] = 0;
11512 }
11513 #endif
11514 /* Now read it back. */
11515 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11516 if (ret) {
11517 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11518
11519 break;
11520 }
11521
11522 /* Verify it. */
11523 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11524 if (p[i] == i)
11525 continue;
11526
11527 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11528 DMA_RWCTRL_WRITE_BNDRY_16) {
11529 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11530 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11531 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11532 break;
11533 } else {
11534 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11535 ret = -ENODEV;
11536 goto out;
11537 }
11538 }
11539
11540 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11541 /* Success. */
11542 ret = 0;
11543 break;
11544 }
11545 }
11546 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11547 DMA_RWCTRL_WRITE_BNDRY_16) {
11548 static struct pci_device_id dma_wait_state_chipsets[] = {
11549 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11550 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11551 { },
11552 };
11553
11554 /* DMA test passed without adjusting DMA boundary,
11555 * now look for chipsets that are known to expose the
11556 * DMA bug without failing the test.
11557 */
11558 if (pci_dev_present(dma_wait_state_chipsets)) {
11559 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11560 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11561 }
11562 else
11563 /* Safe to use the calculated DMA boundary. */
11564 tp->dma_rwctrl = saved_dma_rwctrl;
11565
11566 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11567 }
11568
11569 out:
11570 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11571 out_nofree:
11572 return ret;
11573 }
11574
11575 static void __devinit tg3_init_link_config(struct tg3 *tp)
11576 {
11577 tp->link_config.advertising =
11578 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11579 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11580 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11581 ADVERTISED_Autoneg | ADVERTISED_MII);
11582 tp->link_config.speed = SPEED_INVALID;
11583 tp->link_config.duplex = DUPLEX_INVALID;
11584 tp->link_config.autoneg = AUTONEG_ENABLE;
11585 tp->link_config.active_speed = SPEED_INVALID;
11586 tp->link_config.active_duplex = DUPLEX_INVALID;
11587 tp->link_config.phy_is_low_power = 0;
11588 tp->link_config.orig_speed = SPEED_INVALID;
11589 tp->link_config.orig_duplex = DUPLEX_INVALID;
11590 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11591 }
11592
11593 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11594 {
11595 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11596 tp->bufmgr_config.mbuf_read_dma_low_water =
11597 DEFAULT_MB_RDMA_LOW_WATER_5705;
11598 tp->bufmgr_config.mbuf_mac_rx_low_water =
11599 DEFAULT_MB_MACRX_LOW_WATER_5705;
11600 tp->bufmgr_config.mbuf_high_water =
11601 DEFAULT_MB_HIGH_WATER_5705;
11602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11603 tp->bufmgr_config.mbuf_mac_rx_low_water =
11604 DEFAULT_MB_MACRX_LOW_WATER_5906;
11605 tp->bufmgr_config.mbuf_high_water =
11606 DEFAULT_MB_HIGH_WATER_5906;
11607 }
11608
11609 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11610 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11611 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11612 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11613 tp->bufmgr_config.mbuf_high_water_jumbo =
11614 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11615 } else {
11616 tp->bufmgr_config.mbuf_read_dma_low_water =
11617 DEFAULT_MB_RDMA_LOW_WATER;
11618 tp->bufmgr_config.mbuf_mac_rx_low_water =
11619 DEFAULT_MB_MACRX_LOW_WATER;
11620 tp->bufmgr_config.mbuf_high_water =
11621 DEFAULT_MB_HIGH_WATER;
11622
11623 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11624 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11625 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11626 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11627 tp->bufmgr_config.mbuf_high_water_jumbo =
11628 DEFAULT_MB_HIGH_WATER_JUMBO;
11629 }
11630
11631 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11632 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11633 }
11634
11635 static char * __devinit tg3_phy_string(struct tg3 *tp)
11636 {
11637 switch (tp->phy_id & PHY_ID_MASK) {
11638 case PHY_ID_BCM5400: return "5400";
11639 case PHY_ID_BCM5401: return "5401";
11640 case PHY_ID_BCM5411: return "5411";
11641 case PHY_ID_BCM5701: return "5701";
11642 case PHY_ID_BCM5703: return "5703";
11643 case PHY_ID_BCM5704: return "5704";
11644 case PHY_ID_BCM5705: return "5705";
11645 case PHY_ID_BCM5750: return "5750";
11646 case PHY_ID_BCM5752: return "5752";
11647 case PHY_ID_BCM5714: return "5714";
11648 case PHY_ID_BCM5780: return "5780";
11649 case PHY_ID_BCM5755: return "5755";
11650 case PHY_ID_BCM5787: return "5787";
11651 case PHY_ID_BCM5756: return "5722/5756";
11652 case PHY_ID_BCM5906: return "5906";
11653 case PHY_ID_BCM8002: return "8002/serdes";
11654 case 0: return "serdes";
11655 default: return "unknown";
11656 };
11657 }
11658
11659 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11660 {
11661 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11662 strcpy(str, "PCI Express");
11663 return str;
11664 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11665 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11666
11667 strcpy(str, "PCIX:");
11668
11669 if ((clock_ctrl == 7) ||
11670 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11671 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11672 strcat(str, "133MHz");
11673 else if (clock_ctrl == 0)
11674 strcat(str, "33MHz");
11675 else if (clock_ctrl == 2)
11676 strcat(str, "50MHz");
11677 else if (clock_ctrl == 4)
11678 strcat(str, "66MHz");
11679 else if (clock_ctrl == 6)
11680 strcat(str, "100MHz");
11681 } else {
11682 strcpy(str, "PCI:");
11683 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11684 strcat(str, "66MHz");
11685 else
11686 strcat(str, "33MHz");
11687 }
11688 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11689 strcat(str, ":32-bit");
11690 else
11691 strcat(str, ":64-bit");
11692 return str;
11693 }
11694
11695 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11696 {
11697 struct pci_dev *peer;
11698 unsigned int func, devnr = tp->pdev->devfn & ~7;
11699
11700 for (func = 0; func < 8; func++) {
11701 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11702 if (peer && peer != tp->pdev)
11703 break;
11704 pci_dev_put(peer);
11705 }
11706 /* 5704 can be configured in single-port mode, set peer to
11707 * tp->pdev in that case.
11708 */
11709 if (!peer) {
11710 peer = tp->pdev;
11711 return peer;
11712 }
11713
11714 /*
11715 * We don't need to keep the refcount elevated; there's no way
11716 * to remove one half of this device without removing the other
11717 */
11718 pci_dev_put(peer);
11719
11720 return peer;
11721 }
11722
11723 static void __devinit tg3_init_coal(struct tg3 *tp)
11724 {
11725 struct ethtool_coalesce *ec = &tp->coal;
11726
11727 memset(ec, 0, sizeof(*ec));
11728 ec->cmd = ETHTOOL_GCOALESCE;
11729 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11730 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11731 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11732 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11733 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11734 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11735 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11736 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11737 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11738
11739 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11740 HOSTCC_MODE_CLRTICK_TXBD)) {
11741 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11742 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11743 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11744 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11745 }
11746
11747 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11748 ec->rx_coalesce_usecs_irq = 0;
11749 ec->tx_coalesce_usecs_irq = 0;
11750 ec->stats_block_coalesce_usecs = 0;
11751 }
11752 }
11753
11754 static int __devinit tg3_init_one(struct pci_dev *pdev,
11755 const struct pci_device_id *ent)
11756 {
11757 static int tg3_version_printed = 0;
11758 unsigned long tg3reg_base, tg3reg_len;
11759 struct net_device *dev;
11760 struct tg3 *tp;
11761 int i, err, pm_cap;
11762 char str[40];
11763 u64 dma_mask, persist_dma_mask;
11764
11765 if (tg3_version_printed++ == 0)
11766 printk(KERN_INFO "%s", version);
11767
11768 err = pci_enable_device(pdev);
11769 if (err) {
11770 printk(KERN_ERR PFX "Cannot enable PCI device, "
11771 "aborting.\n");
11772 return err;
11773 }
11774
11775 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11776 printk(KERN_ERR PFX "Cannot find proper PCI device "
11777 "base address, aborting.\n");
11778 err = -ENODEV;
11779 goto err_out_disable_pdev;
11780 }
11781
11782 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11783 if (err) {
11784 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11785 "aborting.\n");
11786 goto err_out_disable_pdev;
11787 }
11788
11789 pci_set_master(pdev);
11790
11791 /* Find power-management capability. */
11792 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11793 if (pm_cap == 0) {
11794 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11795 "aborting.\n");
11796 err = -EIO;
11797 goto err_out_free_res;
11798 }
11799
11800 tg3reg_base = pci_resource_start(pdev, 0);
11801 tg3reg_len = pci_resource_len(pdev, 0);
11802
11803 dev = alloc_etherdev(sizeof(*tp));
11804 if (!dev) {
11805 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11806 err = -ENOMEM;
11807 goto err_out_free_res;
11808 }
11809
11810 SET_MODULE_OWNER(dev);
11811 SET_NETDEV_DEV(dev, &pdev->dev);
11812
11813 #if TG3_VLAN_TAG_USED
11814 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11815 dev->vlan_rx_register = tg3_vlan_rx_register;
11816 #endif
11817
11818 tp = netdev_priv(dev);
11819 tp->pdev = pdev;
11820 tp->dev = dev;
11821 tp->pm_cap = pm_cap;
11822 tp->mac_mode = TG3_DEF_MAC_MODE;
11823 tp->rx_mode = TG3_DEF_RX_MODE;
11824 tp->tx_mode = TG3_DEF_TX_MODE;
11825 tp->mi_mode = MAC_MI_MODE_BASE;
11826 if (tg3_debug > 0)
11827 tp->msg_enable = tg3_debug;
11828 else
11829 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11830
11831 /* The word/byte swap controls here control register access byte
11832 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11833 * setting below.
11834 */
11835 tp->misc_host_ctrl =
11836 MISC_HOST_CTRL_MASK_PCI_INT |
11837 MISC_HOST_CTRL_WORD_SWAP |
11838 MISC_HOST_CTRL_INDIR_ACCESS |
11839 MISC_HOST_CTRL_PCISTATE_RW;
11840
11841 /* The NONFRM (non-frame) byte/word swap controls take effect
11842 * on descriptor entries, anything which isn't packet data.
11843 *
11844 * The StrongARM chips on the board (one for tx, one for rx)
11845 * are running in big-endian mode.
11846 */
11847 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11848 GRC_MODE_WSWAP_NONFRM_DATA);
11849 #ifdef __BIG_ENDIAN
11850 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11851 #endif
11852 spin_lock_init(&tp->lock);
11853 spin_lock_init(&tp->indirect_lock);
11854 INIT_WORK(&tp->reset_task, tg3_reset_task);
11855
11856 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11857 if (tp->regs == 0UL) {
11858 printk(KERN_ERR PFX "Cannot map device registers, "
11859 "aborting.\n");
11860 err = -ENOMEM;
11861 goto err_out_free_dev;
11862 }
11863
11864 tg3_init_link_config(tp);
11865
11866 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11867 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11868 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11869
11870 dev->open = tg3_open;
11871 dev->stop = tg3_close;
11872 dev->get_stats = tg3_get_stats;
11873 dev->set_multicast_list = tg3_set_rx_mode;
11874 dev->set_mac_address = tg3_set_mac_addr;
11875 dev->do_ioctl = tg3_ioctl;
11876 dev->tx_timeout = tg3_tx_timeout;
11877 dev->poll = tg3_poll;
11878 dev->ethtool_ops = &tg3_ethtool_ops;
11879 dev->weight = 64;
11880 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11881 dev->change_mtu = tg3_change_mtu;
11882 dev->irq = pdev->irq;
11883 #ifdef CONFIG_NET_POLL_CONTROLLER
11884 dev->poll_controller = tg3_poll_controller;
11885 #endif
11886
11887 err = tg3_get_invariants(tp);
11888 if (err) {
11889 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11890 "aborting.\n");
11891 goto err_out_iounmap;
11892 }
11893
11894 /* The EPB bridge inside 5714, 5715, and 5780 and any
11895 * device behind the EPB cannot support DMA addresses > 40-bit.
11896 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11897 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11898 * do DMA address check in tg3_start_xmit().
11899 */
11900 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11901 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11902 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11903 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11904 #ifdef CONFIG_HIGHMEM
11905 dma_mask = DMA_64BIT_MASK;
11906 #endif
11907 } else
11908 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11909
11910 /* Configure DMA attributes. */
11911 if (dma_mask > DMA_32BIT_MASK) {
11912 err = pci_set_dma_mask(pdev, dma_mask);
11913 if (!err) {
11914 dev->features |= NETIF_F_HIGHDMA;
11915 err = pci_set_consistent_dma_mask(pdev,
11916 persist_dma_mask);
11917 if (err < 0) {
11918 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11919 "DMA for consistent allocations\n");
11920 goto err_out_iounmap;
11921 }
11922 }
11923 }
11924 if (err || dma_mask == DMA_32BIT_MASK) {
11925 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11926 if (err) {
11927 printk(KERN_ERR PFX "No usable DMA configuration, "
11928 "aborting.\n");
11929 goto err_out_iounmap;
11930 }
11931 }
11932
11933 tg3_init_bufmgr_config(tp);
11934
11935 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11936 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11937 }
11938 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11940 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11942 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11943 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11944 } else {
11945 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11946 }
11947
11948 /* TSO is on by default on chips that support hardware TSO.
11949 * Firmware TSO on older chips gives lower performance, so it
11950 * is off by default, but can be enabled using ethtool.
11951 */
11952 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11953 dev->features |= NETIF_F_TSO;
11954 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11955 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11956 dev->features |= NETIF_F_TSO6;
11957 }
11958
11959
11960 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11961 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11962 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11963 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11964 tp->rx_pending = 63;
11965 }
11966
11967 err = tg3_get_device_address(tp);
11968 if (err) {
11969 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11970 "aborting.\n");
11971 goto err_out_iounmap;
11972 }
11973
11974 /*
11975 * Reset chip in case UNDI or EFI driver did not shutdown
11976 * DMA self test will enable WDMAC and we'll see (spurious)
11977 * pending DMA on the PCI bus at that point.
11978 */
11979 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11980 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11981 pci_save_state(tp->pdev);
11982 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11983 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11984 }
11985
11986 err = tg3_test_dma(tp);
11987 if (err) {
11988 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11989 goto err_out_iounmap;
11990 }
11991
11992 /* Tigon3 can do ipv4 only... and some chips have buggy
11993 * checksumming.
11994 */
11995 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11996 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11999 dev->features |= NETIF_F_IPV6_CSUM;
12000
12001 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12002 } else
12003 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12004
12005 /* flow control autonegotiation is default behavior */
12006 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12007
12008 tg3_init_coal(tp);
12009
12010 /* Now that we have fully setup the chip, save away a snapshot
12011 * of the PCI config space. We need to restore this after
12012 * GRC_MISC_CFG core clock resets and some resume events.
12013 */
12014 pci_save_state(tp->pdev);
12015
12016 pci_set_drvdata(pdev, dev);
12017
12018 err = register_netdev(dev);
12019 if (err) {
12020 printk(KERN_ERR PFX "Cannot register net device, "
12021 "aborting.\n");
12022 goto err_out_iounmap;
12023 }
12024
12025 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
12026 dev->name,
12027 tp->board_part_number,
12028 tp->pci_chip_rev_id,
12029 tg3_phy_string(tp),
12030 tg3_bus_string(tp, str),
12031 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12032 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12033 "10/100/1000Base-T")));
12034
12035 for (i = 0; i < 6; i++)
12036 printk("%2.2x%c", dev->dev_addr[i],
12037 i == 5 ? '\n' : ':');
12038
12039 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
12040 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
12041 dev->name,
12042 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12043 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12044 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12045 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
12046 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12047 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12048 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12049 dev->name, tp->dma_rwctrl,
12050 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12051 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12052
12053 return 0;
12054
12055 err_out_iounmap:
12056 if (tp->regs) {
12057 iounmap(tp->regs);
12058 tp->regs = NULL;
12059 }
12060
12061 err_out_free_dev:
12062 free_netdev(dev);
12063
12064 err_out_free_res:
12065 pci_release_regions(pdev);
12066
12067 err_out_disable_pdev:
12068 pci_disable_device(pdev);
12069 pci_set_drvdata(pdev, NULL);
12070 return err;
12071 }
12072
12073 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12074 {
12075 struct net_device *dev = pci_get_drvdata(pdev);
12076
12077 if (dev) {
12078 struct tg3 *tp = netdev_priv(dev);
12079
12080 flush_scheduled_work();
12081 unregister_netdev(dev);
12082 if (tp->regs) {
12083 iounmap(tp->regs);
12084 tp->regs = NULL;
12085 }
12086 free_netdev(dev);
12087 pci_release_regions(pdev);
12088 pci_disable_device(pdev);
12089 pci_set_drvdata(pdev, NULL);
12090 }
12091 }
12092
12093 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12094 {
12095 struct net_device *dev = pci_get_drvdata(pdev);
12096 struct tg3 *tp = netdev_priv(dev);
12097 int err;
12098
12099 if (!netif_running(dev))
12100 return 0;
12101
12102 flush_scheduled_work();
12103 tg3_netif_stop(tp);
12104
12105 del_timer_sync(&tp->timer);
12106
12107 tg3_full_lock(tp, 1);
12108 tg3_disable_ints(tp);
12109 tg3_full_unlock(tp);
12110
12111 netif_device_detach(dev);
12112
12113 tg3_full_lock(tp, 0);
12114 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12115 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12116 tg3_full_unlock(tp);
12117
12118 /* Save MSI address and data for resume. */
12119 pci_save_state(pdev);
12120
12121 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12122 if (err) {
12123 tg3_full_lock(tp, 0);
12124
12125 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12126 if (tg3_restart_hw(tp, 1))
12127 goto out;
12128
12129 tp->timer.expires = jiffies + tp->timer_offset;
12130 add_timer(&tp->timer);
12131
12132 netif_device_attach(dev);
12133 tg3_netif_start(tp);
12134
12135 out:
12136 tg3_full_unlock(tp);
12137 }
12138
12139 return err;
12140 }
12141
12142 static int tg3_resume(struct pci_dev *pdev)
12143 {
12144 struct net_device *dev = pci_get_drvdata(pdev);
12145 struct tg3 *tp = netdev_priv(dev);
12146 int err;
12147
12148 if (!netif_running(dev))
12149 return 0;
12150
12151 pci_restore_state(tp->pdev);
12152
12153 err = tg3_set_power_state(tp, PCI_D0);
12154 if (err)
12155 return err;
12156
12157 netif_device_attach(dev);
12158
12159 tg3_full_lock(tp, 0);
12160
12161 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12162 err = tg3_restart_hw(tp, 1);
12163 if (err)
12164 goto out;
12165
12166 tp->timer.expires = jiffies + tp->timer_offset;
12167 add_timer(&tp->timer);
12168
12169 tg3_netif_start(tp);
12170
12171 out:
12172 tg3_full_unlock(tp);
12173
12174 return err;
12175 }
12176
12177 static struct pci_driver tg3_driver = {
12178 .name = DRV_MODULE_NAME,
12179 .id_table = tg3_pci_tbl,
12180 .probe = tg3_init_one,
12181 .remove = __devexit_p(tg3_remove_one),
12182 .suspend = tg3_suspend,
12183 .resume = tg3_resume
12184 };
12185
12186 static int __init tg3_init(void)
12187 {
12188 return pci_register_driver(&tg3_driver);
12189 }
12190
12191 static void __exit tg3_cleanup(void)
12192 {
12193 pci_unregister_driver(&tg3_driver);
12194 }
12195
12196 module_init(tg3_init);
12197 module_exit(tg3_cleanup);
Software Suspend 2 for Linus's 2.6 head (mirror)