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Force reset on decompression error
[linux-2.6/tcp-comp.git] / drivers / net / skge.c
blobb3d4728725170a3db0457deb6e0e79b132178e5f
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/in.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ip.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.11"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
59 #define BLINK_MS 250
60 #define LINK_HZ HZ
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
87 { 0 }
88 };
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct net_device *dev);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
102
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
110
111 static int skge_get_regs_len(struct net_device *dev)
112 {
113 return 0x4000;
114 }
115
116 /*
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
119 * cause bus hangs!
120 */
121 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123 {
124 const struct skge_port *skge = netdev_priv(dev);
125 const void __iomem *io = skge->hw->regs;
126
127 regs->version = 1;
128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
130
131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
133 }
134
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static u32 wol_supported(const struct skge_hw *hw)
137 {
138 if (hw->chip_id == CHIP_ID_GENESIS)
139 return 0;
140
141 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
142 return 0;
143
144 return WAKE_MAGIC | WAKE_PHY;
145 }
146
147 static u32 pci_wake_enabled(struct pci_dev *dev)
148 {
149 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
150 u16 value;
151
152 /* If device doesn't support PM Capabilities, but request is to disable
153 * wake events, it's a nop; otherwise fail */
154 if (!pm)
155 return 0;
156
157 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
158
159 value &= PCI_PM_CAP_PME_MASK;
160 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
161
162 return value != 0;
163 }
164
165 static void skge_wol_init(struct skge_port *skge)
166 {
167 struct skge_hw *hw = skge->hw;
168 int port = skge->port;
169 u16 ctrl;
170
171 skge_write16(hw, B0_CTST, CS_RST_CLR);
172 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
173
174 /* Turn on Vaux */
175 skge_write8(hw, B0_POWER_CTRL,
176 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
177
178 /* WA code for COMA mode -- clear PHY reset */
179 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
180 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
181 u32 reg = skge_read32(hw, B2_GP_IO);
182 reg |= GP_DIR_9;
183 reg &= ~GP_IO_9;
184 skge_write32(hw, B2_GP_IO, reg);
185 }
186
187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 GPC_DIS_SLEEP |
189 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
190 GPC_ANEG_1 | GPC_RST_SET);
191
192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_CLR);
196
197 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
198
199 /* Force to 10/100 skge_reset will re-enable on resume */
200 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
201 PHY_AN_100FULL | PHY_AN_100HALF |
202 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
203 /* no 1000 HD/FD */
204 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
205 gm_phy_write(hw, port, PHY_MARV_CTRL,
206 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
207 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
208
209
210 /* Set GMAC to no flow control and auto update for speed/duplex */
211 gma_write16(hw, port, GM_GP_CTRL,
212 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
213 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
214
215 /* Set WOL address */
216 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
217 skge->netdev->dev_addr, ETH_ALEN);
218
219 /* Turn on appropriate WOL control bits */
220 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
221 ctrl = 0;
222 if (skge->wol & WAKE_PHY)
223 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
224 else
225 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
226
227 if (skge->wol & WAKE_MAGIC)
228 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
231
232 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
233 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
234
235 /* block receiver */
236 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
237 }
238
239 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
240 {
241 struct skge_port *skge = netdev_priv(dev);
242
243 wol->supported = wol_supported(skge->hw);
244 wol->wolopts = skge->wol;
245 }
246
247 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
248 {
249 struct skge_port *skge = netdev_priv(dev);
250 struct skge_hw *hw = skge->hw;
251
252 if (wol->wolopts & ~wol_supported(hw))
253 return -EOPNOTSUPP;
254
255 skge->wol = wol->wolopts;
256 return 0;
257 }
258
259 /* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
261 */
262 static u32 skge_supported_modes(const struct skge_hw *hw)
263 {
264 u32 supported;
265
266 if (hw->copper) {
267 supported = SUPPORTED_10baseT_Half
268 | SUPPORTED_10baseT_Full
269 | SUPPORTED_100baseT_Half
270 | SUPPORTED_100baseT_Full
271 | SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full
273 | SUPPORTED_Autoneg| SUPPORTED_TP;
274
275 if (hw->chip_id == CHIP_ID_GENESIS)
276 supported &= ~(SUPPORTED_10baseT_Half
277 | SUPPORTED_10baseT_Full
278 | SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full);
280
281 else if (hw->chip_id == CHIP_ID_YUKON)
282 supported &= ~SUPPORTED_1000baseT_Half;
283 } else
284 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
285 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
286
287 return supported;
288 }
289
290 static int skge_get_settings(struct net_device *dev,
291 struct ethtool_cmd *ecmd)
292 {
293 struct skge_port *skge = netdev_priv(dev);
294 struct skge_hw *hw = skge->hw;
295
296 ecmd->transceiver = XCVR_INTERNAL;
297 ecmd->supported = skge_supported_modes(hw);
298
299 if (hw->copper) {
300 ecmd->port = PORT_TP;
301 ecmd->phy_address = hw->phy_addr;
302 } else
303 ecmd->port = PORT_FIBRE;
304
305 ecmd->advertising = skge->advertising;
306 ecmd->autoneg = skge->autoneg;
307 ecmd->speed = skge->speed;
308 ecmd->duplex = skge->duplex;
309 return 0;
310 }
311
312 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
313 {
314 struct skge_port *skge = netdev_priv(dev);
315 const struct skge_hw *hw = skge->hw;
316 u32 supported = skge_supported_modes(hw);
317
318 if (ecmd->autoneg == AUTONEG_ENABLE) {
319 ecmd->advertising = supported;
320 skge->duplex = -1;
321 skge->speed = -1;
322 } else {
323 u32 setting;
324
325 switch (ecmd->speed) {
326 case SPEED_1000:
327 if (ecmd->duplex == DUPLEX_FULL)
328 setting = SUPPORTED_1000baseT_Full;
329 else if (ecmd->duplex == DUPLEX_HALF)
330 setting = SUPPORTED_1000baseT_Half;
331 else
332 return -EINVAL;
333 break;
334 case SPEED_100:
335 if (ecmd->duplex == DUPLEX_FULL)
336 setting = SUPPORTED_100baseT_Full;
337 else if (ecmd->duplex == DUPLEX_HALF)
338 setting = SUPPORTED_100baseT_Half;
339 else
340 return -EINVAL;
341 break;
342
343 case SPEED_10:
344 if (ecmd->duplex == DUPLEX_FULL)
345 setting = SUPPORTED_10baseT_Full;
346 else if (ecmd->duplex == DUPLEX_HALF)
347 setting = SUPPORTED_10baseT_Half;
348 else
349 return -EINVAL;
350 break;
351 default:
352 return -EINVAL;
353 }
354
355 if ((setting & supported) == 0)
356 return -EINVAL;
357
358 skge->speed = ecmd->speed;
359 skge->duplex = ecmd->duplex;
360 }
361
362 skge->autoneg = ecmd->autoneg;
363 skge->advertising = ecmd->advertising;
364
365 if (netif_running(dev))
366 skge_phy_reset(skge);
367
368 return (0);
369 }
370
371 static void skge_get_drvinfo(struct net_device *dev,
372 struct ethtool_drvinfo *info)
373 {
374 struct skge_port *skge = netdev_priv(dev);
375
376 strcpy(info->driver, DRV_NAME);
377 strcpy(info->version, DRV_VERSION);
378 strcpy(info->fw_version, "N/A");
379 strcpy(info->bus_info, pci_name(skge->hw->pdev));
380 }
381
382 static const struct skge_stat {
383 char name[ETH_GSTRING_LEN];
384 u16 xmac_offset;
385 u16 gma_offset;
386 } skge_stats[] = {
387 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
388 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
389
390 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
391 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
392 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
393 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
394 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
395 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
396 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
397 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
398
399 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
400 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
401 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
402 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
403 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
404 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
405
406 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
407 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
408 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
409 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
411 };
412
413 static int skge_get_stats_count(struct net_device *dev)
414 {
415 return ARRAY_SIZE(skge_stats);
416 }
417
418 static void skge_get_ethtool_stats(struct net_device *dev,
419 struct ethtool_stats *stats, u64 *data)
420 {
421 struct skge_port *skge = netdev_priv(dev);
422
423 if (skge->hw->chip_id == CHIP_ID_GENESIS)
424 genesis_get_stats(skge, data);
425 else
426 yukon_get_stats(skge, data);
427 }
428
429 /* Use hardware MIB variables for critical path statistics and
430 * transmit feedback not reported at interrupt.
431 * Other errors are accounted for in interrupt handler.
432 */
433 static struct net_device_stats *skge_get_stats(struct net_device *dev)
434 {
435 struct skge_port *skge = netdev_priv(dev);
436 u64 data[ARRAY_SIZE(skge_stats)];
437
438 if (skge->hw->chip_id == CHIP_ID_GENESIS)
439 genesis_get_stats(skge, data);
440 else
441 yukon_get_stats(skge, data);
442
443 skge->net_stats.tx_bytes = data[0];
444 skge->net_stats.rx_bytes = data[1];
445 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
446 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
447 skge->net_stats.multicast = data[3] + data[5];
448 skge->net_stats.collisions = data[10];
449 skge->net_stats.tx_aborted_errors = data[12];
450
451 return &skge->net_stats;
452 }
453
454 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
455 {
456 int i;
457
458 switch (stringset) {
459 case ETH_SS_STATS:
460 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
461 memcpy(data + i * ETH_GSTRING_LEN,
462 skge_stats[i].name, ETH_GSTRING_LEN);
463 break;
464 }
465 }
466
467 static void skge_get_ring_param(struct net_device *dev,
468 struct ethtool_ringparam *p)
469 {
470 struct skge_port *skge = netdev_priv(dev);
471
472 p->rx_max_pending = MAX_RX_RING_SIZE;
473 p->tx_max_pending = MAX_TX_RING_SIZE;
474 p->rx_mini_max_pending = 0;
475 p->rx_jumbo_max_pending = 0;
476
477 p->rx_pending = skge->rx_ring.count;
478 p->tx_pending = skge->tx_ring.count;
479 p->rx_mini_pending = 0;
480 p->rx_jumbo_pending = 0;
481 }
482
483 static int skge_set_ring_param(struct net_device *dev,
484 struct ethtool_ringparam *p)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487 int err;
488
489 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
490 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
491 return -EINVAL;
492
493 skge->rx_ring.count = p->rx_pending;
494 skge->tx_ring.count = p->tx_pending;
495
496 if (netif_running(dev)) {
497 skge_down(dev);
498 err = skge_up(dev);
499 if (err)
500 dev_close(dev);
501 }
502
503 return 0;
504 }
505
506 static u32 skge_get_msglevel(struct net_device *netdev)
507 {
508 struct skge_port *skge = netdev_priv(netdev);
509 return skge->msg_enable;
510 }
511
512 static void skge_set_msglevel(struct net_device *netdev, u32 value)
513 {
514 struct skge_port *skge = netdev_priv(netdev);
515 skge->msg_enable = value;
516 }
517
518 static int skge_nway_reset(struct net_device *dev)
519 {
520 struct skge_port *skge = netdev_priv(dev);
521
522 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
523 return -EINVAL;
524
525 skge_phy_reset(skge);
526 return 0;
527 }
528
529 static int skge_set_sg(struct net_device *dev, u32 data)
530 {
531 struct skge_port *skge = netdev_priv(dev);
532 struct skge_hw *hw = skge->hw;
533
534 if (hw->chip_id == CHIP_ID_GENESIS && data)
535 return -EOPNOTSUPP;
536 return ethtool_op_set_sg(dev, data);
537 }
538
539 static int skge_set_tx_csum(struct net_device *dev, u32 data)
540 {
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543
544 if (hw->chip_id == CHIP_ID_GENESIS && data)
545 return -EOPNOTSUPP;
546
547 return ethtool_op_set_tx_csum(dev, data);
548 }
549
550 static u32 skge_get_rx_csum(struct net_device *dev)
551 {
552 struct skge_port *skge = netdev_priv(dev);
553
554 return skge->rx_csum;
555 }
556
557 /* Only Yukon supports checksum offload. */
558 static int skge_set_rx_csum(struct net_device *dev, u32 data)
559 {
560 struct skge_port *skge = netdev_priv(dev);
561
562 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
563 return -EOPNOTSUPP;
564
565 skge->rx_csum = data;
566 return 0;
567 }
568
569 static void skge_get_pauseparam(struct net_device *dev,
570 struct ethtool_pauseparam *ecmd)
571 {
572 struct skge_port *skge = netdev_priv(dev);
573
574 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
575 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
576 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
577
578 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
579 }
580
581 static int skge_set_pauseparam(struct net_device *dev,
582 struct ethtool_pauseparam *ecmd)
583 {
584 struct skge_port *skge = netdev_priv(dev);
585 struct ethtool_pauseparam old;
586
587 skge_get_pauseparam(dev, &old);
588
589 if (ecmd->autoneg != old.autoneg)
590 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
591 else {
592 if (ecmd->rx_pause && ecmd->tx_pause)
593 skge->flow_control = FLOW_MODE_SYMMETRIC;
594 else if (ecmd->rx_pause && !ecmd->tx_pause)
595 skge->flow_control = FLOW_MODE_SYM_OR_REM;
596 else if (!ecmd->rx_pause && ecmd->tx_pause)
597 skge->flow_control = FLOW_MODE_LOC_SEND;
598 else
599 skge->flow_control = FLOW_MODE_NONE;
600 }
601
602 if (netif_running(dev))
603 skge_phy_reset(skge);
604
605 return 0;
606 }
607
608 /* Chip internal frequency for clock calculations */
609 static inline u32 hwkhz(const struct skge_hw *hw)
610 {
611 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
612 }
613
614 /* Chip HZ to microseconds */
615 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
616 {
617 return (ticks * 1000) / hwkhz(hw);
618 }
619
620 /* Microseconds to chip HZ */
621 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
622 {
623 return hwkhz(hw) * usec / 1000;
624 }
625
626 static int skge_get_coalesce(struct net_device *dev,
627 struct ethtool_coalesce *ecmd)
628 {
629 struct skge_port *skge = netdev_priv(dev);
630 struct skge_hw *hw = skge->hw;
631 int port = skge->port;
632
633 ecmd->rx_coalesce_usecs = 0;
634 ecmd->tx_coalesce_usecs = 0;
635
636 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
637 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
638 u32 msk = skge_read32(hw, B2_IRQM_MSK);
639
640 if (msk & rxirqmask[port])
641 ecmd->rx_coalesce_usecs = delay;
642 if (msk & txirqmask[port])
643 ecmd->tx_coalesce_usecs = delay;
644 }
645
646 return 0;
647 }
648
649 /* Note: interrupt timer is per board, but can turn on/off per port */
650 static int skge_set_coalesce(struct net_device *dev,
651 struct ethtool_coalesce *ecmd)
652 {
653 struct skge_port *skge = netdev_priv(dev);
654 struct skge_hw *hw = skge->hw;
655 int port = skge->port;
656 u32 msk = skge_read32(hw, B2_IRQM_MSK);
657 u32 delay = 25;
658
659 if (ecmd->rx_coalesce_usecs == 0)
660 msk &= ~rxirqmask[port];
661 else if (ecmd->rx_coalesce_usecs < 25 ||
662 ecmd->rx_coalesce_usecs > 33333)
663 return -EINVAL;
664 else {
665 msk |= rxirqmask[port];
666 delay = ecmd->rx_coalesce_usecs;
667 }
668
669 if (ecmd->tx_coalesce_usecs == 0)
670 msk &= ~txirqmask[port];
671 else if (ecmd->tx_coalesce_usecs < 25 ||
672 ecmd->tx_coalesce_usecs > 33333)
673 return -EINVAL;
674 else {
675 msk |= txirqmask[port];
676 delay = min(delay, ecmd->rx_coalesce_usecs);
677 }
678
679 skge_write32(hw, B2_IRQM_MSK, msk);
680 if (msk == 0)
681 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
682 else {
683 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
684 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
685 }
686 return 0;
687 }
688
689 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
690 static void skge_led(struct skge_port *skge, enum led_mode mode)
691 {
692 struct skge_hw *hw = skge->hw;
693 int port = skge->port;
694
695 spin_lock_bh(&hw->phy_lock);
696 if (hw->chip_id == CHIP_ID_GENESIS) {
697 switch (mode) {
698 case LED_MODE_OFF:
699 if (hw->phy_type == SK_PHY_BCOM)
700 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
701 else {
702 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
703 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
704 }
705 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
706 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
707 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
708 break;
709
710 case LED_MODE_ON:
711 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
712 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
713
714 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
715 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
716
717 break;
718
719 case LED_MODE_TST:
720 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
721 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
722 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
723
724 if (hw->phy_type == SK_PHY_BCOM)
725 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
726 else {
727 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
728 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
729 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
730 }
731
732 }
733 } else {
734 switch (mode) {
735 case LED_MODE_OFF:
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
737 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
738 PHY_M_LED_MO_DUP(MO_LED_OFF) |
739 PHY_M_LED_MO_10(MO_LED_OFF) |
740 PHY_M_LED_MO_100(MO_LED_OFF) |
741 PHY_M_LED_MO_1000(MO_LED_OFF) |
742 PHY_M_LED_MO_RX(MO_LED_OFF));
743 break;
744 case LED_MODE_ON:
745 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
746 PHY_M_LED_PULS_DUR(PULS_170MS) |
747 PHY_M_LED_BLINK_RT(BLINK_84MS) |
748 PHY_M_LEDC_TX_CTRL |
749 PHY_M_LEDC_DP_CTRL);
750
751 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
752 PHY_M_LED_MO_RX(MO_LED_OFF) |
753 (skge->speed == SPEED_100 ?
754 PHY_M_LED_MO_100(MO_LED_ON) : 0));
755 break;
756 case LED_MODE_TST:
757 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
758 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
759 PHY_M_LED_MO_DUP(MO_LED_ON) |
760 PHY_M_LED_MO_10(MO_LED_ON) |
761 PHY_M_LED_MO_100(MO_LED_ON) |
762 PHY_M_LED_MO_1000(MO_LED_ON) |
763 PHY_M_LED_MO_RX(MO_LED_ON));
764 }
765 }
766 spin_unlock_bh(&hw->phy_lock);
767 }
768
769 /* blink LED's for finding board */
770 static int skge_phys_id(struct net_device *dev, u32 data)
771 {
772 struct skge_port *skge = netdev_priv(dev);
773 unsigned long ms;
774 enum led_mode mode = LED_MODE_TST;
775
776 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
777 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
778 else
779 ms = data * 1000;
780
781 while (ms > 0) {
782 skge_led(skge, mode);
783 mode ^= LED_MODE_TST;
784
785 if (msleep_interruptible(BLINK_MS))
786 break;
787 ms -= BLINK_MS;
788 }
789
790 /* back to regular LED state */
791 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
792
793 return 0;
794 }
795
796 static const struct ethtool_ops skge_ethtool_ops = {
797 .get_settings = skge_get_settings,
798 .set_settings = skge_set_settings,
799 .get_drvinfo = skge_get_drvinfo,
800 .get_regs_len = skge_get_regs_len,
801 .get_regs = skge_get_regs,
802 .get_wol = skge_get_wol,
803 .set_wol = skge_set_wol,
804 .get_msglevel = skge_get_msglevel,
805 .set_msglevel = skge_set_msglevel,
806 .nway_reset = skge_nway_reset,
807 .get_link = ethtool_op_get_link,
808 .get_ringparam = skge_get_ring_param,
809 .set_ringparam = skge_set_ring_param,
810 .get_pauseparam = skge_get_pauseparam,
811 .set_pauseparam = skge_set_pauseparam,
812 .get_coalesce = skge_get_coalesce,
813 .set_coalesce = skge_set_coalesce,
814 .get_sg = ethtool_op_get_sg,
815 .set_sg = skge_set_sg,
816 .get_tx_csum = ethtool_op_get_tx_csum,
817 .set_tx_csum = skge_set_tx_csum,
818 .get_rx_csum = skge_get_rx_csum,
819 .set_rx_csum = skge_set_rx_csum,
820 .get_strings = skge_get_strings,
821 .phys_id = skge_phys_id,
822 .get_stats_count = skge_get_stats_count,
823 .get_ethtool_stats = skge_get_ethtool_stats,
824 };
825
826 /*
827 * Allocate ring elements and chain them together
828 * One-to-one association of board descriptors with ring elements
829 */
830 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
831 {
832 struct skge_tx_desc *d;
833 struct skge_element *e;
834 int i;
835
836 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
837 if (!ring->start)
838 return -ENOMEM;
839
840 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
841 e->desc = d;
842 if (i == ring->count - 1) {
843 e->next = ring->start;
844 d->next_offset = base;
845 } else {
846 e->next = e + 1;
847 d->next_offset = base + (i+1) * sizeof(*d);
848 }
849 }
850 ring->to_use = ring->to_clean = ring->start;
851
852 return 0;
853 }
854
855 /* Allocate and setup a new buffer for receiving */
856 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
857 struct sk_buff *skb, unsigned int bufsize)
858 {
859 struct skge_rx_desc *rd = e->desc;
860 u64 map;
861
862 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
863 PCI_DMA_FROMDEVICE);
864
865 rd->dma_lo = map;
866 rd->dma_hi = map >> 32;
867 e->skb = skb;
868 rd->csum1_start = ETH_HLEN;
869 rd->csum2_start = ETH_HLEN;
870 rd->csum1 = 0;
871 rd->csum2 = 0;
872
873 wmb();
874
875 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
876 pci_unmap_addr_set(e, mapaddr, map);
877 pci_unmap_len_set(e, maplen, bufsize);
878 }
879
880 /* Resume receiving using existing skb,
881 * Note: DMA address is not changed by chip.
882 * MTU not changed while receiver active.
883 */
884 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
885 {
886 struct skge_rx_desc *rd = e->desc;
887
888 rd->csum2 = 0;
889 rd->csum2_start = ETH_HLEN;
890
891 wmb();
892
893 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
894 }
895
896
897 /* Free all buffers in receive ring, assumes receiver stopped */
898 static void skge_rx_clean(struct skge_port *skge)
899 {
900 struct skge_hw *hw = skge->hw;
901 struct skge_ring *ring = &skge->rx_ring;
902 struct skge_element *e;
903
904 e = ring->start;
905 do {
906 struct skge_rx_desc *rd = e->desc;
907 rd->control = 0;
908 if (e->skb) {
909 pci_unmap_single(hw->pdev,
910 pci_unmap_addr(e, mapaddr),
911 pci_unmap_len(e, maplen),
912 PCI_DMA_FROMDEVICE);
913 dev_kfree_skb(e->skb);
914 e->skb = NULL;
915 }
916 } while ((e = e->next) != ring->start);
917 }
918
919
920 /* Allocate buffers for receive ring
921 * For receive: to_clean is next received frame.
922 */
923 static int skge_rx_fill(struct net_device *dev)
924 {
925 struct skge_port *skge = netdev_priv(dev);
926 struct skge_ring *ring = &skge->rx_ring;
927 struct skge_element *e;
928
929 e = ring->start;
930 do {
931 struct sk_buff *skb;
932
933 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
934 GFP_KERNEL);
935 if (!skb)
936 return -ENOMEM;
937
938 skb_reserve(skb, NET_IP_ALIGN);
939 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
940 } while ( (e = e->next) != ring->start);
941
942 ring->to_clean = ring->start;
943 return 0;
944 }
945
946 static const char *skge_pause(enum pause_status status)
947 {
948 switch(status) {
949 case FLOW_STAT_NONE:
950 return "none";
951 case FLOW_STAT_REM_SEND:
952 return "rx only";
953 case FLOW_STAT_LOC_SEND:
954 return "tx_only";
955 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
956 return "both";
957 default:
958 return "indeterminated";
959 }
960 }
961
962
963 static void skge_link_up(struct skge_port *skge)
964 {
965 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
966 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
967
968 netif_carrier_on(skge->netdev);
969 netif_wake_queue(skge->netdev);
970
971 if (netif_msg_link(skge)) {
972 printk(KERN_INFO PFX
973 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
974 skge->netdev->name, skge->speed,
975 skge->duplex == DUPLEX_FULL ? "full" : "half",
976 skge_pause(skge->flow_status));
977 }
978 }
979
980 static void skge_link_down(struct skge_port *skge)
981 {
982 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
983 netif_carrier_off(skge->netdev);
984 netif_stop_queue(skge->netdev);
985
986 if (netif_msg_link(skge))
987 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
988 }
989
990
991 static void xm_link_down(struct skge_hw *hw, int port)
992 {
993 struct net_device *dev = hw->dev[port];
994 struct skge_port *skge = netdev_priv(dev);
995 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
996
997 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
998
999 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1000 xm_write16(hw, port, XM_MMU_CMD, cmd);
1001
1002 /* dummy read to ensure writing */
1003 xm_read16(hw, port, XM_MMU_CMD);
1004
1005 if (netif_carrier_ok(dev))
1006 skge_link_down(skge);
1007 }
1008
1009 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1010 {
1011 int i;
1012
1013 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1014 *val = xm_read16(hw, port, XM_PHY_DATA);
1015
1016 if (hw->phy_type == SK_PHY_XMAC)
1017 goto ready;
1018
1019 for (i = 0; i < PHY_RETRIES; i++) {
1020 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1021 goto ready;
1022 udelay(1);
1023 }
1024
1025 return -ETIMEDOUT;
1026 ready:
1027 *val = xm_read16(hw, port, XM_PHY_DATA);
1028
1029 return 0;
1030 }
1031
1032 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1033 {
1034 u16 v = 0;
1035 if (__xm_phy_read(hw, port, reg, &v))
1036 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1037 hw->dev[port]->name);
1038 return v;
1039 }
1040
1041 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1042 {
1043 int i;
1044
1045 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1046 for (i = 0; i < PHY_RETRIES; i++) {
1047 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1048 goto ready;
1049 udelay(1);
1050 }
1051 return -EIO;
1052
1053 ready:
1054 xm_write16(hw, port, XM_PHY_DATA, val);
1055 for (i = 0; i < PHY_RETRIES; i++) {
1056 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1057 return 0;
1058 udelay(1);
1059 }
1060 return -ETIMEDOUT;
1061 }
1062
1063 static void genesis_init(struct skge_hw *hw)
1064 {
1065 /* set blink source counter */
1066 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1067 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1068
1069 /* configure mac arbiter */
1070 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1071
1072 /* configure mac arbiter timeout values */
1073 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1074 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1075 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1076 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1077
1078 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1079 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1080 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1081 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1082
1083 /* configure packet arbiter timeout */
1084 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1085 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1086 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1087 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1088 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1089 }
1090
1091 static void genesis_reset(struct skge_hw *hw, int port)
1092 {
1093 const u8 zero[8] = { 0 };
1094
1095 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1096
1097 /* reset the statistics module */
1098 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1099 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1100 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1101 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1102 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1103
1104 /* disable Broadcom PHY IRQ */
1105 if (hw->phy_type == SK_PHY_BCOM)
1106 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1107
1108 xm_outhash(hw, port, XM_HSM, zero);
1109 }
1110
1111
1112 /* Convert mode to MII values */
1113 static const u16 phy_pause_map[] = {
1114 [FLOW_MODE_NONE] = 0,
1115 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1116 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1117 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1118 };
1119
1120 /* special defines for FIBER (88E1011S only) */
1121 static const u16 fiber_pause_map[] = {
1122 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1123 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1124 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1125 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1126 };
1127
1128
1129 /* Check status of Broadcom phy link */
1130 static void bcom_check_link(struct skge_hw *hw, int port)
1131 {
1132 struct net_device *dev = hw->dev[port];
1133 struct skge_port *skge = netdev_priv(dev);
1134 u16 status;
1135
1136 /* read twice because of latch */
1137 xm_phy_read(hw, port, PHY_BCOM_STAT);
1138 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1139
1140 if ((status & PHY_ST_LSYNC) == 0) {
1141 xm_link_down(hw, port);
1142 return;
1143 }
1144
1145 if (skge->autoneg == AUTONEG_ENABLE) {
1146 u16 lpa, aux;
1147
1148 if (!(status & PHY_ST_AN_OVER))
1149 return;
1150
1151 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1152 if (lpa & PHY_B_AN_RF) {
1153 printk(KERN_NOTICE PFX "%s: remote fault\n",
1154 dev->name);
1155 return;
1156 }
1157
1158 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1159
1160 /* Check Duplex mismatch */
1161 switch (aux & PHY_B_AS_AN_RES_MSK) {
1162 case PHY_B_RES_1000FD:
1163 skge->duplex = DUPLEX_FULL;
1164 break;
1165 case PHY_B_RES_1000HD:
1166 skge->duplex = DUPLEX_HALF;
1167 break;
1168 default:
1169 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1170 dev->name);
1171 return;
1172 }
1173
1174 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1175 switch (aux & PHY_B_AS_PAUSE_MSK) {
1176 case PHY_B_AS_PAUSE_MSK:
1177 skge->flow_status = FLOW_STAT_SYMMETRIC;
1178 break;
1179 case PHY_B_AS_PRR:
1180 skge->flow_status = FLOW_STAT_REM_SEND;
1181 break;
1182 case PHY_B_AS_PRT:
1183 skge->flow_status = FLOW_STAT_LOC_SEND;
1184 break;
1185 default:
1186 skge->flow_status = FLOW_STAT_NONE;
1187 }
1188 skge->speed = SPEED_1000;
1189 }
1190
1191 if (!netif_carrier_ok(dev))
1192 genesis_link_up(skge);
1193 }
1194
1195 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1196 * Phy on for 100 or 10Mbit operation
1197 */
1198 static void bcom_phy_init(struct skge_port *skge)
1199 {
1200 struct skge_hw *hw = skge->hw;
1201 int port = skge->port;
1202 int i;
1203 u16 id1, r, ext, ctl;
1204
1205 /* magic workaround patterns for Broadcom */
1206 static const struct {
1207 u16 reg;
1208 u16 val;
1209 } A1hack[] = {
1210 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1211 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1212 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1213 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1214 }, C0hack[] = {
1215 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1216 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1217 };
1218
1219 /* read Id from external PHY (all have the same address) */
1220 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1221
1222 /* Optimize MDIO transfer by suppressing preamble. */
1223 r = xm_read16(hw, port, XM_MMU_CMD);
1224 r |= XM_MMU_NO_PRE;
1225 xm_write16(hw, port, XM_MMU_CMD,r);
1226
1227 switch (id1) {
1228 case PHY_BCOM_ID1_C0:
1229 /*
1230 * Workaround BCOM Errata for the C0 type.
1231 * Write magic patterns to reserved registers.
1232 */
1233 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1234 xm_phy_write(hw, port,
1235 C0hack[i].reg, C0hack[i].val);
1236
1237 break;
1238 case PHY_BCOM_ID1_A1:
1239 /*
1240 * Workaround BCOM Errata for the A1 type.
1241 * Write magic patterns to reserved registers.
1242 */
1243 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1244 xm_phy_write(hw, port,
1245 A1hack[i].reg, A1hack[i].val);
1246 break;
1247 }
1248
1249 /*
1250 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1251 * Disable Power Management after reset.
1252 */
1253 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1254 r |= PHY_B_AC_DIS_PM;
1255 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1256
1257 /* Dummy read */
1258 xm_read16(hw, port, XM_ISRC);
1259
1260 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1261 ctl = PHY_CT_SP1000; /* always 1000mbit */
1262
1263 if (skge->autoneg == AUTONEG_ENABLE) {
1264 /*
1265 * Workaround BCOM Errata #1 for the C5 type.
1266 * 1000Base-T Link Acquisition Failure in Slave Mode
1267 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1268 */
1269 u16 adv = PHY_B_1000C_RD;
1270 if (skge->advertising & ADVERTISED_1000baseT_Half)
1271 adv |= PHY_B_1000C_AHD;
1272 if (skge->advertising & ADVERTISED_1000baseT_Full)
1273 adv |= PHY_B_1000C_AFD;
1274 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1275
1276 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1277 } else {
1278 if (skge->duplex == DUPLEX_FULL)
1279 ctl |= PHY_CT_DUP_MD;
1280 /* Force to slave */
1281 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1282 }
1283
1284 /* Set autonegotiation pause parameters */
1285 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1286 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1287
1288 /* Handle Jumbo frames */
1289 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1290 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1291 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1292
1293 ext |= PHY_B_PEC_HIGH_LA;
1294
1295 }
1296
1297 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1298 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1299
1300 /* Use link status change interrupt */
1301 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1302 }
1303
1304 static void xm_phy_init(struct skge_port *skge)
1305 {
1306 struct skge_hw *hw = skge->hw;
1307 int port = skge->port;
1308 u16 ctrl = 0;
1309
1310 if (skge->autoneg == AUTONEG_ENABLE) {
1311 if (skge->advertising & ADVERTISED_1000baseT_Half)
1312 ctrl |= PHY_X_AN_HD;
1313 if (skge->advertising & ADVERTISED_1000baseT_Full)
1314 ctrl |= PHY_X_AN_FD;
1315
1316 ctrl |= fiber_pause_map[skge->flow_control];
1317
1318 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1319
1320 /* Restart Auto-negotiation */
1321 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1322 } else {
1323 /* Set DuplexMode in Config register */
1324 if (skge->duplex == DUPLEX_FULL)
1325 ctrl |= PHY_CT_DUP_MD;
1326 /*
1327 * Do NOT enable Auto-negotiation here. This would hold
1328 * the link down because no IDLEs are transmitted
1329 */
1330 }
1331
1332 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1333
1334 /* Poll PHY for status changes */
1335 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1336 }
1337
1338 static int xm_check_link(struct net_device *dev)
1339 {
1340 struct skge_port *skge = netdev_priv(dev);
1341 struct skge_hw *hw = skge->hw;
1342 int port = skge->port;
1343 u16 status;
1344
1345 /* read twice because of latch */
1346 xm_phy_read(hw, port, PHY_XMAC_STAT);
1347 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1348
1349 if ((status & PHY_ST_LSYNC) == 0) {
1350 xm_link_down(hw, port);
1351 return 0;
1352 }
1353
1354 if (skge->autoneg == AUTONEG_ENABLE) {
1355 u16 lpa, res;
1356
1357 if (!(status & PHY_ST_AN_OVER))
1358 return 0;
1359
1360 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1361 if (lpa & PHY_B_AN_RF) {
1362 printk(KERN_NOTICE PFX "%s: remote fault\n",
1363 dev->name);
1364 return 0;
1365 }
1366
1367 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1368
1369 /* Check Duplex mismatch */
1370 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1371 case PHY_X_RS_FD:
1372 skge->duplex = DUPLEX_FULL;
1373 break;
1374 case PHY_X_RS_HD:
1375 skge->duplex = DUPLEX_HALF;
1376 break;
1377 default:
1378 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1379 dev->name);
1380 return 0;
1381 }
1382
1383 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1384 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1385 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1386 (lpa & PHY_X_P_SYM_MD))
1387 skge->flow_status = FLOW_STAT_SYMMETRIC;
1388 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1389 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1390 /* Enable PAUSE receive, disable PAUSE transmit */
1391 skge->flow_status = FLOW_STAT_REM_SEND;
1392 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1393 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1394 /* Disable PAUSE receive, enable PAUSE transmit */
1395 skge->flow_status = FLOW_STAT_LOC_SEND;
1396 else
1397 skge->flow_status = FLOW_STAT_NONE;
1398
1399 skge->speed = SPEED_1000;
1400 }
1401
1402 if (!netif_carrier_ok(dev))
1403 genesis_link_up(skge);
1404 return 1;
1405 }
1406
1407 /* Poll to check for link coming up.
1408 *
1409 * Since internal PHY is wired to a level triggered pin, can't
1410 * get an interrupt when carrier is detected, need to poll for
1411 * link coming up.
1412 */
1413 static void xm_link_timer(unsigned long arg)
1414 {
1415 struct skge_port *skge = (struct skge_port *) arg;
1416 struct net_device *dev = skge->netdev;
1417 struct skge_hw *hw = skge->hw;
1418 int port = skge->port;
1419 int i;
1420 unsigned long flags;
1421
1422 if (!netif_running(dev))
1423 return;
1424
1425 spin_lock_irqsave(&hw->phy_lock, flags);
1426
1427 /*
1428 * Verify that the link by checking GPIO register three times.
1429 * This pin has the signal from the link_sync pin connected to it.
1430 */
1431 for (i = 0; i < 3; i++) {
1432 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1433 goto link_down;
1434 }
1435
1436 /* Re-enable interrupt to detect link down */
1437 if (xm_check_link(dev)) {
1438 u16 msk = xm_read16(hw, port, XM_IMSK);
1439 msk &= ~XM_IS_INP_ASS;
1440 xm_write16(hw, port, XM_IMSK, msk);
1441 xm_read16(hw, port, XM_ISRC);
1442 } else {
1443 link_down:
1444 mod_timer(&skge->link_timer,
1445 round_jiffies(jiffies + LINK_HZ));
1446 }
1447 spin_unlock_irqrestore(&hw->phy_lock, flags);
1448 }
1449
1450 static void genesis_mac_init(struct skge_hw *hw, int port)
1451 {
1452 struct net_device *dev = hw->dev[port];
1453 struct skge_port *skge = netdev_priv(dev);
1454 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1455 int i;
1456 u32 r;
1457 const u8 zero[6] = { 0 };
1458
1459 for (i = 0; i < 10; i++) {
1460 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1461 MFF_SET_MAC_RST);
1462 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1463 goto reset_ok;
1464 udelay(1);
1465 }
1466
1467 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1468
1469 reset_ok:
1470 /* Unreset the XMAC. */
1471 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1472
1473 /*
1474 * Perform additional initialization for external PHYs,
1475 * namely for the 1000baseTX cards that use the XMAC's
1476 * GMII mode.
1477 */
1478 if (hw->phy_type != SK_PHY_XMAC) {
1479 /* Take external Phy out of reset */
1480 r = skge_read32(hw, B2_GP_IO);
1481 if (port == 0)
1482 r |= GP_DIR_0|GP_IO_0;
1483 else
1484 r |= GP_DIR_2|GP_IO_2;
1485
1486 skge_write32(hw, B2_GP_IO, r);
1487
1488 /* Enable GMII interface */
1489 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1490 }
1491
1492
1493 switch(hw->phy_type) {
1494 case SK_PHY_XMAC:
1495 xm_phy_init(skge);
1496 break;
1497 case SK_PHY_BCOM:
1498 bcom_phy_init(skge);
1499 bcom_check_link(hw, port);
1500 }
1501
1502 /* Set Station Address */
1503 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1504
1505 /* We don't use match addresses so clear */
1506 for (i = 1; i < 16; i++)
1507 xm_outaddr(hw, port, XM_EXM(i), zero);
1508
1509 /* Clear MIB counters */
1510 xm_write16(hw, port, XM_STAT_CMD,
1511 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1512 /* Clear two times according to Errata #3 */
1513 xm_write16(hw, port, XM_STAT_CMD,
1514 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1515
1516 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1517 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1518
1519 /* We don't need the FCS appended to the packet. */
1520 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1521 if (jumbo)
1522 r |= XM_RX_BIG_PK_OK;
1523
1524 if (skge->duplex == DUPLEX_HALF) {
1525 /*
1526 * If in manual half duplex mode the other side might be in
1527 * full duplex mode, so ignore if a carrier extension is not seen
1528 * on frames received
1529 */
1530 r |= XM_RX_DIS_CEXT;
1531 }
1532 xm_write16(hw, port, XM_RX_CMD, r);
1533
1534
1535 /* We want short frames padded to 60 bytes. */
1536 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1537
1538 /*
1539 * Bump up the transmit threshold. This helps hold off transmit
1540 * underruns when we're blasting traffic from both ports at once.
1541 */
1542 xm_write16(hw, port, XM_TX_THR, 512);
1543
1544 /*
1545 * Enable the reception of all error frames. This is is
1546 * a necessary evil due to the design of the XMAC. The
1547 * XMAC's receive FIFO is only 8K in size, however jumbo
1548 * frames can be up to 9000 bytes in length. When bad
1549 * frame filtering is enabled, the XMAC's RX FIFO operates
1550 * in 'store and forward' mode. For this to work, the
1551 * entire frame has to fit into the FIFO, but that means
1552 * that jumbo frames larger than 8192 bytes will be
1553 * truncated. Disabling all bad frame filtering causes
1554 * the RX FIFO to operate in streaming mode, in which
1555 * case the XMAC will start transferring frames out of the
1556 * RX FIFO as soon as the FIFO threshold is reached.
1557 */
1558 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1559
1560
1561 /*
1562 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1563 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1564 * and 'Octets Rx OK Hi Cnt Ov'.
1565 */
1566 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1567
1568 /*
1569 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1570 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1571 * and 'Octets Tx OK Hi Cnt Ov'.
1572 */
1573 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1574
1575 /* Configure MAC arbiter */
1576 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1577
1578 /* configure timeout values */
1579 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1580 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1581 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1582 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1583
1584 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1585 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1586 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1587 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1588
1589 /* Configure Rx MAC FIFO */
1590 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1591 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1592 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1593
1594 /* Configure Tx MAC FIFO */
1595 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1596 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1597 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1598
1599 if (jumbo) {
1600 /* Enable frame flushing if jumbo frames used */
1601 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1602 } else {
1603 /* enable timeout timers if normal frames */
1604 skge_write16(hw, B3_PA_CTRL,
1605 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1606 }
1607 }
1608
1609 static void genesis_stop(struct skge_port *skge)
1610 {
1611 struct skge_hw *hw = skge->hw;
1612 int port = skge->port;
1613 u32 reg;
1614
1615 genesis_reset(hw, port);
1616
1617 /* Clear Tx packet arbiter timeout IRQ */
1618 skge_write16(hw, B3_PA_CTRL,
1619 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1620
1621 /*
1622 * If the transfer sticks at the MAC the STOP command will not
1623 * terminate if we don't flush the XMAC's transmit FIFO !
1624 */
1625 xm_write32(hw, port, XM_MODE,
1626 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1627
1628
1629 /* Reset the MAC */
1630 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1631
1632 /* For external PHYs there must be special handling */
1633 if (hw->phy_type != SK_PHY_XMAC) {
1634 reg = skge_read32(hw, B2_GP_IO);
1635 if (port == 0) {
1636 reg |= GP_DIR_0;
1637 reg &= ~GP_IO_0;
1638 } else {
1639 reg |= GP_DIR_2;
1640 reg &= ~GP_IO_2;
1641 }
1642 skge_write32(hw, B2_GP_IO, reg);
1643 skge_read32(hw, B2_GP_IO);
1644 }
1645
1646 xm_write16(hw, port, XM_MMU_CMD,
1647 xm_read16(hw, port, XM_MMU_CMD)
1648 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1649
1650 xm_read16(hw, port, XM_MMU_CMD);
1651 }
1652
1653
1654 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1655 {
1656 struct skge_hw *hw = skge->hw;
1657 int port = skge->port;
1658 int i;
1659 unsigned long timeout = jiffies + HZ;
1660
1661 xm_write16(hw, port,
1662 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1663
1664 /* wait for update to complete */
1665 while (xm_read16(hw, port, XM_STAT_CMD)
1666 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1667 if (time_after(jiffies, timeout))
1668 break;
1669 udelay(10);
1670 }
1671
1672 /* special case for 64 bit octet counter */
1673 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1674 | xm_read32(hw, port, XM_TXO_OK_LO);
1675 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1676 | xm_read32(hw, port, XM_RXO_OK_LO);
1677
1678 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1679 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1680 }
1681
1682 static void genesis_mac_intr(struct skge_hw *hw, int port)
1683 {
1684 struct skge_port *skge = netdev_priv(hw->dev[port]);
1685 u16 status = xm_read16(hw, port, XM_ISRC);
1686
1687 if (netif_msg_intr(skge))
1688 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1689 skge->netdev->name, status);
1690
1691 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1692 xm_link_down(hw, port);
1693 mod_timer(&skge->link_timer, jiffies + 1);
1694 }
1695
1696 if (status & XM_IS_TXF_UR) {
1697 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1698 ++skge->net_stats.tx_fifo_errors;
1699 }
1700
1701 if (status & XM_IS_RXF_OV) {
1702 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1703 ++skge->net_stats.rx_fifo_errors;
1704 }
1705 }
1706
1707 static void genesis_link_up(struct skge_port *skge)
1708 {
1709 struct skge_hw *hw = skge->hw;
1710 int port = skge->port;
1711 u16 cmd, msk;
1712 u32 mode;
1713
1714 cmd = xm_read16(hw, port, XM_MMU_CMD);
1715
1716 /*
1717 * enabling pause frame reception is required for 1000BT
1718 * because the XMAC is not reset if the link is going down
1719 */
1720 if (skge->flow_status == FLOW_STAT_NONE ||
1721 skge->flow_status == FLOW_STAT_LOC_SEND)
1722 /* Disable Pause Frame Reception */
1723 cmd |= XM_MMU_IGN_PF;
1724 else
1725 /* Enable Pause Frame Reception */
1726 cmd &= ~XM_MMU_IGN_PF;
1727
1728 xm_write16(hw, port, XM_MMU_CMD, cmd);
1729
1730 mode = xm_read32(hw, port, XM_MODE);
1731 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1732 skge->flow_status == FLOW_STAT_LOC_SEND) {
1733 /*
1734 * Configure Pause Frame Generation
1735 * Use internal and external Pause Frame Generation.
1736 * Sending pause frames is edge triggered.
1737 * Send a Pause frame with the maximum pause time if
1738 * internal oder external FIFO full condition occurs.
1739 * Send a zero pause time frame to re-start transmission.
1740 */
1741 /* XM_PAUSE_DA = '010000C28001' (default) */
1742 /* XM_MAC_PTIME = 0xffff (maximum) */
1743 /* remember this value is defined in big endian (!) */
1744 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1745
1746 mode |= XM_PAUSE_MODE;
1747 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1748 } else {
1749 /*
1750 * disable pause frame generation is required for 1000BT
1751 * because the XMAC is not reset if the link is going down
1752 */
1753 /* Disable Pause Mode in Mode Register */
1754 mode &= ~XM_PAUSE_MODE;
1755
1756 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1757 }
1758
1759 xm_write32(hw, port, XM_MODE, mode);
1760
1761 /* Turn on detection of Tx underrun, Rx overrun */
1762 msk = xm_read16(hw, port, XM_IMSK);
1763 msk &= ~(XM_IS_RXF_OV | XM_IS_TXF_UR);
1764 xm_write16(hw, port, XM_IMSK, msk);
1765
1766 xm_read16(hw, port, XM_ISRC);
1767
1768 /* get MMU Command Reg. */
1769 cmd = xm_read16(hw, port, XM_MMU_CMD);
1770 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1771 cmd |= XM_MMU_GMII_FD;
1772
1773 /*
1774 * Workaround BCOM Errata (#10523) for all BCom Phys
1775 * Enable Power Management after link up
1776 */
1777 if (hw->phy_type == SK_PHY_BCOM) {
1778 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1779 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1780 & ~PHY_B_AC_DIS_PM);
1781 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1782 }
1783
1784 /* enable Rx/Tx */
1785 xm_write16(hw, port, XM_MMU_CMD,
1786 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1787 skge_link_up(skge);
1788 }
1789
1790
1791 static inline void bcom_phy_intr(struct skge_port *skge)
1792 {
1793 struct skge_hw *hw = skge->hw;
1794 int port = skge->port;
1795 u16 isrc;
1796
1797 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1798 if (netif_msg_intr(skge))
1799 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1800 skge->netdev->name, isrc);
1801
1802 if (isrc & PHY_B_IS_PSE)
1803 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1804 hw->dev[port]->name);
1805
1806 /* Workaround BCom Errata:
1807 * enable and disable loopback mode if "NO HCD" occurs.
1808 */
1809 if (isrc & PHY_B_IS_NO_HDCL) {
1810 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1811 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1812 ctrl | PHY_CT_LOOP);
1813 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1814 ctrl & ~PHY_CT_LOOP);
1815 }
1816
1817 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1818 bcom_check_link(hw, port);
1819
1820 }
1821
1822 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1823 {
1824 int i;
1825
1826 gma_write16(hw, port, GM_SMI_DATA, val);
1827 gma_write16(hw, port, GM_SMI_CTRL,
1828 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1829 for (i = 0; i < PHY_RETRIES; i++) {
1830 udelay(1);
1831
1832 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1833 return 0;
1834 }
1835
1836 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1837 hw->dev[port]->name);
1838 return -EIO;
1839 }
1840
1841 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1842 {
1843 int i;
1844
1845 gma_write16(hw, port, GM_SMI_CTRL,
1846 GM_SMI_CT_PHY_AD(hw->phy_addr)
1847 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1848
1849 for (i = 0; i < PHY_RETRIES; i++) {
1850 udelay(1);
1851 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1852 goto ready;
1853 }
1854
1855 return -ETIMEDOUT;
1856 ready:
1857 *val = gma_read16(hw, port, GM_SMI_DATA);
1858 return 0;
1859 }
1860
1861 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1862 {
1863 u16 v = 0;
1864 if (__gm_phy_read(hw, port, reg, &v))
1865 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1866 hw->dev[port]->name);
1867 return v;
1868 }
1869
1870 /* Marvell Phy Initialization */
1871 static void yukon_init(struct skge_hw *hw, int port)
1872 {
1873 struct skge_port *skge = netdev_priv(hw->dev[port]);
1874 u16 ctrl, ct1000, adv;
1875
1876 if (skge->autoneg == AUTONEG_ENABLE) {
1877 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1878
1879 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1880 PHY_M_EC_MAC_S_MSK);
1881 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1882
1883 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1884
1885 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1886 }
1887
1888 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1889 if (skge->autoneg == AUTONEG_DISABLE)
1890 ctrl &= ~PHY_CT_ANE;
1891
1892 ctrl |= PHY_CT_RESET;
1893 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1894
1895 ctrl = 0;
1896 ct1000 = 0;
1897 adv = PHY_AN_CSMA;
1898
1899 if (skge->autoneg == AUTONEG_ENABLE) {
1900 if (hw->copper) {
1901 if (skge->advertising & ADVERTISED_1000baseT_Full)
1902 ct1000 |= PHY_M_1000C_AFD;
1903 if (skge->advertising & ADVERTISED_1000baseT_Half)
1904 ct1000 |= PHY_M_1000C_AHD;
1905 if (skge->advertising & ADVERTISED_100baseT_Full)
1906 adv |= PHY_M_AN_100_FD;
1907 if (skge->advertising & ADVERTISED_100baseT_Half)
1908 adv |= PHY_M_AN_100_HD;
1909 if (skge->advertising & ADVERTISED_10baseT_Full)
1910 adv |= PHY_M_AN_10_FD;
1911 if (skge->advertising & ADVERTISED_10baseT_Half)
1912 adv |= PHY_M_AN_10_HD;
1913
1914 /* Set Flow-control capabilities */
1915 adv |= phy_pause_map[skge->flow_control];
1916 } else {
1917 if (skge->advertising & ADVERTISED_1000baseT_Full)
1918 adv |= PHY_M_AN_1000X_AFD;
1919 if (skge->advertising & ADVERTISED_1000baseT_Half)
1920 adv |= PHY_M_AN_1000X_AHD;
1921
1922 adv |= fiber_pause_map[skge->flow_control];
1923 }
1924
1925 /* Restart Auto-negotiation */
1926 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1927 } else {
1928 /* forced speed/duplex settings */
1929 ct1000 = PHY_M_1000C_MSE;
1930
1931 if (skge->duplex == DUPLEX_FULL)
1932 ctrl |= PHY_CT_DUP_MD;
1933
1934 switch (skge->speed) {
1935 case SPEED_1000:
1936 ctrl |= PHY_CT_SP1000;
1937 break;
1938 case SPEED_100:
1939 ctrl |= PHY_CT_SP100;
1940 break;
1941 }
1942
1943 ctrl |= PHY_CT_RESET;
1944 }
1945
1946 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1947
1948 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1949 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1950
1951 /* Enable phy interrupt on autonegotiation complete (or link up) */
1952 if (skge->autoneg == AUTONEG_ENABLE)
1953 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1954 else
1955 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1956 }
1957
1958 static void yukon_reset(struct skge_hw *hw, int port)
1959 {
1960 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1961 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1962 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1963 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1964 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1965
1966 gma_write16(hw, port, GM_RX_CTRL,
1967 gma_read16(hw, port, GM_RX_CTRL)
1968 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1969 }
1970
1971 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1972 static int is_yukon_lite_a0(struct skge_hw *hw)
1973 {
1974 u32 reg;
1975 int ret;
1976
1977 if (hw->chip_id != CHIP_ID_YUKON)
1978 return 0;
1979
1980 reg = skge_read32(hw, B2_FAR);
1981 skge_write8(hw, B2_FAR + 3, 0xff);
1982 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1983 skge_write32(hw, B2_FAR, reg);
1984 return ret;
1985 }
1986
1987 static void yukon_mac_init(struct skge_hw *hw, int port)
1988 {
1989 struct skge_port *skge = netdev_priv(hw->dev[port]);
1990 int i;
1991 u32 reg;
1992 const u8 *addr = hw->dev[port]->dev_addr;
1993
1994 /* WA code for COMA mode -- set PHY reset */
1995 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1996 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1997 reg = skge_read32(hw, B2_GP_IO);
1998 reg |= GP_DIR_9 | GP_IO_9;
1999 skge_write32(hw, B2_GP_IO, reg);
2000 }
2001
2002 /* hard reset */
2003 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2004 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2005
2006 /* WA code for COMA mode -- clear PHY reset */
2007 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2008 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2009 reg = skge_read32(hw, B2_GP_IO);
2010 reg |= GP_DIR_9;
2011 reg &= ~GP_IO_9;
2012 skge_write32(hw, B2_GP_IO, reg);
2013 }
2014
2015 /* Set hardware config mode */
2016 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2017 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2018 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2019
2020 /* Clear GMC reset */
2021 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2022 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2023 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2024
2025 if (skge->autoneg == AUTONEG_DISABLE) {
2026 reg = GM_GPCR_AU_ALL_DIS;
2027 gma_write16(hw, port, GM_GP_CTRL,
2028 gma_read16(hw, port, GM_GP_CTRL) | reg);
2029
2030 switch (skge->speed) {
2031 case SPEED_1000:
2032 reg &= ~GM_GPCR_SPEED_100;
2033 reg |= GM_GPCR_SPEED_1000;
2034 break;
2035 case SPEED_100:
2036 reg &= ~GM_GPCR_SPEED_1000;
2037 reg |= GM_GPCR_SPEED_100;
2038 break;
2039 case SPEED_10:
2040 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2041 break;
2042 }
2043
2044 if (skge->duplex == DUPLEX_FULL)
2045 reg |= GM_GPCR_DUP_FULL;
2046 } else
2047 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2048
2049 switch (skge->flow_control) {
2050 case FLOW_MODE_NONE:
2051 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2052 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2053 break;
2054 case FLOW_MODE_LOC_SEND:
2055 /* disable Rx flow-control */
2056 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2057 break;
2058 case FLOW_MODE_SYMMETRIC:
2059 case FLOW_MODE_SYM_OR_REM:
2060 /* enable Tx & Rx flow-control */
2061 break;
2062 }
2063
2064 gma_write16(hw, port, GM_GP_CTRL, reg);
2065 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2066
2067 yukon_init(hw, port);
2068
2069 /* MIB clear */
2070 reg = gma_read16(hw, port, GM_PHY_ADDR);
2071 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2072
2073 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2074 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2075 gma_write16(hw, port, GM_PHY_ADDR, reg);
2076
2077 /* transmit control */
2078 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2079
2080 /* receive control reg: unicast + multicast + no FCS */
2081 gma_write16(hw, port, GM_RX_CTRL,
2082 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2083
2084 /* transmit flow control */
2085 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2086
2087 /* transmit parameter */
2088 gma_write16(hw, port, GM_TX_PARAM,
2089 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2090 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2091 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2092
2093 /* serial mode register */
2094 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2095 if (hw->dev[port]->mtu > 1500)
2096 reg |= GM_SMOD_JUMBO_ENA;
2097
2098 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2099
2100 /* physical address: used for pause frames */
2101 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2102 /* virtual address for data */
2103 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2104
2105 /* enable interrupt mask for counter overflows */
2106 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2107 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2108 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2109
2110 /* Initialize Mac Fifo */
2111
2112 /* Configure Rx MAC FIFO */
2113 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2114 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2115
2116 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2117 if (is_yukon_lite_a0(hw))
2118 reg &= ~GMF_RX_F_FL_ON;
2119
2120 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2121 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2122 /*
2123 * because Pause Packet Truncation in GMAC is not working
2124 * we have to increase the Flush Threshold to 64 bytes
2125 * in order to flush pause packets in Rx FIFO on Yukon-1
2126 */
2127 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2128
2129 /* Configure Tx MAC FIFO */
2130 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2131 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2132 }
2133
2134 /* Go into power down mode */
2135 static void yukon_suspend(struct skge_hw *hw, int port)
2136 {
2137 u16 ctrl;
2138
2139 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2140 ctrl |= PHY_M_PC_POL_R_DIS;
2141 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2142
2143 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2144 ctrl |= PHY_CT_RESET;
2145 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2146
2147 /* switch IEEE compatible power down mode on */
2148 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2149 ctrl |= PHY_CT_PDOWN;
2150 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2151 }
2152
2153 static void yukon_stop(struct skge_port *skge)
2154 {
2155 struct skge_hw *hw = skge->hw;
2156 int port = skge->port;
2157
2158 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2159 yukon_reset(hw, port);
2160
2161 gma_write16(hw, port, GM_GP_CTRL,
2162 gma_read16(hw, port, GM_GP_CTRL)
2163 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2164 gma_read16(hw, port, GM_GP_CTRL);
2165
2166 yukon_suspend(hw, port);
2167
2168 /* set GPHY Control reset */
2169 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2170 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2171 }
2172
2173 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2174 {
2175 struct skge_hw *hw = skge->hw;
2176 int port = skge->port;
2177 int i;
2178
2179 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2180 | gma_read32(hw, port, GM_TXO_OK_LO);
2181 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2182 | gma_read32(hw, port, GM_RXO_OK_LO);
2183
2184 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2185 data[i] = gma_read32(hw, port,
2186 skge_stats[i].gma_offset);
2187 }
2188
2189 static void yukon_mac_intr(struct skge_hw *hw, int port)
2190 {
2191 struct net_device *dev = hw->dev[port];
2192 struct skge_port *skge = netdev_priv(dev);
2193 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2194
2195 if (netif_msg_intr(skge))
2196 printk(KERN_DEBUG PFX "%s: yukon mac interrupt status 0x%x\n",
2197 dev->name, status);
2198
2199 if (status & GM_IS_RX_FF_OR) {
2200 ++skge->net_stats.rx_fifo_errors;
2201 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2202 }
2203
2204 if (status & GM_IS_TX_FF_UR) {
2205 ++skge->net_stats.tx_fifo_errors;
2206 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2207 }
2208
2209 }
2210
2211 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2212 {
2213 switch (aux & PHY_M_PS_SPEED_MSK) {
2214 case PHY_M_PS_SPEED_1000:
2215 return SPEED_1000;
2216 case PHY_M_PS_SPEED_100:
2217 return SPEED_100;
2218 default:
2219 return SPEED_10;
2220 }
2221 }
2222
2223 static void yukon_link_up(struct skge_port *skge)
2224 {
2225 struct skge_hw *hw = skge->hw;
2226 int port = skge->port;
2227 u16 reg;
2228
2229 /* Enable Transmit FIFO Underrun */
2230 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2231
2232 reg = gma_read16(hw, port, GM_GP_CTRL);
2233 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2234 reg |= GM_GPCR_DUP_FULL;
2235
2236 /* enable Rx/Tx */
2237 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2238 gma_write16(hw, port, GM_GP_CTRL, reg);
2239
2240 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2241 skge_link_up(skge);
2242 }
2243
2244 static void yukon_link_down(struct skge_port *skge)
2245 {
2246 struct skge_hw *hw = skge->hw;
2247 int port = skge->port;
2248 u16 ctrl;
2249
2250 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2251 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2252 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2253
2254 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2255 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2256 ctrl |= PHY_M_AN_ASP;
2257 /* restore Asymmetric Pause bit */
2258 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2259 }
2260
2261 skge_link_down(skge);
2262
2263 yukon_init(hw, port);
2264 }
2265
2266 static void yukon_phy_intr(struct skge_port *skge)
2267 {
2268 struct skge_hw *hw = skge->hw;
2269 int port = skge->port;
2270 const char *reason = NULL;
2271 u16 istatus, phystat;
2272
2273 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2274 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2275
2276 if (netif_msg_intr(skge))
2277 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2278 skge->netdev->name, istatus, phystat);
2279
2280 if (istatus & PHY_M_IS_AN_COMPL) {
2281 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2282 & PHY_M_AN_RF) {
2283 reason = "remote fault";
2284 goto failed;
2285 }
2286
2287 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2288 reason = "master/slave fault";
2289 goto failed;
2290 }
2291
2292 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2293 reason = "speed/duplex";
2294 goto failed;
2295 }
2296
2297 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2298 ? DUPLEX_FULL : DUPLEX_HALF;
2299 skge->speed = yukon_speed(hw, phystat);
2300
2301 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2302 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2303 case PHY_M_PS_PAUSE_MSK:
2304 skge->flow_status = FLOW_STAT_SYMMETRIC;
2305 break;
2306 case PHY_M_PS_RX_P_EN:
2307 skge->flow_status = FLOW_STAT_REM_SEND;
2308 break;
2309 case PHY_M_PS_TX_P_EN:
2310 skge->flow_status = FLOW_STAT_LOC_SEND;
2311 break;
2312 default:
2313 skge->flow_status = FLOW_STAT_NONE;
2314 }
2315
2316 if (skge->flow_status == FLOW_STAT_NONE ||
2317 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2318 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2319 else
2320 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2321 yukon_link_up(skge);
2322 return;
2323 }
2324
2325 if (istatus & PHY_M_IS_LSP_CHANGE)
2326 skge->speed = yukon_speed(hw, phystat);
2327
2328 if (istatus & PHY_M_IS_DUP_CHANGE)
2329 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2330 if (istatus & PHY_M_IS_LST_CHANGE) {
2331 if (phystat & PHY_M_PS_LINK_UP)
2332 yukon_link_up(skge);
2333 else
2334 yukon_link_down(skge);
2335 }
2336 return;
2337 failed:
2338 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2339 skge->netdev->name, reason);
2340
2341 /* XXX restart autonegotiation? */
2342 }
2343
2344 static void skge_phy_reset(struct skge_port *skge)
2345 {
2346 struct skge_hw *hw = skge->hw;
2347 int port = skge->port;
2348 struct net_device *dev = hw->dev[port];
2349
2350 netif_stop_queue(skge->netdev);
2351 netif_carrier_off(skge->netdev);
2352
2353 spin_lock_bh(&hw->phy_lock);
2354 if (hw->chip_id == CHIP_ID_GENESIS) {
2355 genesis_reset(hw, port);
2356 genesis_mac_init(hw, port);
2357 } else {
2358 yukon_reset(hw, port);
2359 yukon_init(hw, port);
2360 }
2361 spin_unlock_bh(&hw->phy_lock);
2362
2363 dev->set_multicast_list(dev);
2364 }
2365
2366 /* Basic MII support */
2367 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2368 {
2369 struct mii_ioctl_data *data = if_mii(ifr);
2370 struct skge_port *skge = netdev_priv(dev);
2371 struct skge_hw *hw = skge->hw;
2372 int err = -EOPNOTSUPP;
2373
2374 if (!netif_running(dev))
2375 return -ENODEV; /* Phy still in reset */
2376
2377 switch(cmd) {
2378 case SIOCGMIIPHY:
2379 data->phy_id = hw->phy_addr;
2380
2381 /* fallthru */
2382 case SIOCGMIIREG: {
2383 u16 val = 0;
2384 spin_lock_bh(&hw->phy_lock);
2385 if (hw->chip_id == CHIP_ID_GENESIS)
2386 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2387 else
2388 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2389 spin_unlock_bh(&hw->phy_lock);
2390 data->val_out = val;
2391 break;
2392 }
2393
2394 case SIOCSMIIREG:
2395 if (!capable(CAP_NET_ADMIN))
2396 return -EPERM;
2397
2398 spin_lock_bh(&hw->phy_lock);
2399 if (hw->chip_id == CHIP_ID_GENESIS)
2400 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2401 data->val_in);
2402 else
2403 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2404 data->val_in);
2405 spin_unlock_bh(&hw->phy_lock);
2406 break;
2407 }
2408 return err;
2409 }
2410
2411 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2412 {
2413 u32 end;
2414
2415 start /= 8;
2416 len /= 8;
2417 end = start + len - 1;
2418
2419 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2420 skge_write32(hw, RB_ADDR(q, RB_START), start);
2421 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2422 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2423 skge_write32(hw, RB_ADDR(q, RB_END), end);
2424
2425 if (q == Q_R1 || q == Q_R2) {
2426 /* Set thresholds on receive queue's */
2427 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2428 start + (2*len)/3);
2429 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2430 start + (len/3));
2431 } else {
2432 /* Enable store & forward on Tx queue's because
2433 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2434 */
2435 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2436 }
2437
2438 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2439 }
2440
2441 /* Setup Bus Memory Interface */
2442 static void skge_qset(struct skge_port *skge, u16 q,
2443 const struct skge_element *e)
2444 {
2445 struct skge_hw *hw = skge->hw;
2446 u32 watermark = 0x600;
2447 u64 base = skge->dma + (e->desc - skge->mem);
2448
2449 /* optimization to reduce window on 32bit/33mhz */
2450 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2451 watermark /= 2;
2452
2453 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2454 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2455 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2456 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2457 }
2458
2459 static int skge_up(struct net_device *dev)
2460 {
2461 struct skge_port *skge = netdev_priv(dev);
2462 struct skge_hw *hw = skge->hw;
2463 int port = skge->port;
2464 u32 chunk, ram_addr;
2465 size_t rx_size, tx_size;
2466 int err;
2467
2468 if (!is_valid_ether_addr(dev->dev_addr))
2469 return -EINVAL;
2470
2471 if (netif_msg_ifup(skge))
2472 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2473
2474 if (dev->mtu > RX_BUF_SIZE)
2475 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2476 else
2477 skge->rx_buf_size = RX_BUF_SIZE;
2478
2479
2480 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2481 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2482 skge->mem_size = tx_size + rx_size;
2483 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2484 if (!skge->mem)
2485 return -ENOMEM;
2486
2487 BUG_ON(skge->dma & 7);
2488
2489 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2490 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2491 err = -EINVAL;
2492 goto free_pci_mem;
2493 }
2494
2495 memset(skge->mem, 0, skge->mem_size);
2496
2497 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2498 if (err)
2499 goto free_pci_mem;
2500
2501 err = skge_rx_fill(dev);
2502 if (err)
2503 goto free_rx_ring;
2504
2505 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2506 skge->dma + rx_size);
2507 if (err)
2508 goto free_rx_ring;
2509
2510 /* Initialize MAC */
2511 spin_lock_bh(&hw->phy_lock);
2512 if (hw->chip_id == CHIP_ID_GENESIS)
2513 genesis_mac_init(hw, port);
2514 else
2515 yukon_mac_init(hw, port);
2516 spin_unlock_bh(&hw->phy_lock);
2517
2518 /* Configure RAMbuffers */
2519 chunk = hw->ram_size / ((hw->ports + 1)*2);
2520 ram_addr = hw->ram_offset + 2 * chunk * port;
2521
2522 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2523 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2524
2525 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2526 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2527 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2528
2529 /* Start receiver BMU */
2530 wmb();
2531 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2532 skge_led(skge, LED_MODE_ON);
2533
2534 spin_lock_irq(&hw->hw_lock);
2535 hw->intr_mask |= portmask[port];
2536 skge_write32(hw, B0_IMSK, hw->intr_mask);
2537 spin_unlock_irq(&hw->hw_lock);
2538
2539 netif_poll_enable(dev);
2540 return 0;
2541
2542 free_rx_ring:
2543 skge_rx_clean(skge);
2544 kfree(skge->rx_ring.start);
2545 free_pci_mem:
2546 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2547 skge->mem = NULL;
2548
2549 return err;
2550 }
2551
2552 static int skge_down(struct net_device *dev)
2553 {
2554 struct skge_port *skge = netdev_priv(dev);
2555 struct skge_hw *hw = skge->hw;
2556 int port = skge->port;
2557
2558 if (skge->mem == NULL)
2559 return 0;
2560
2561 if (netif_msg_ifdown(skge))
2562 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2563
2564 netif_stop_queue(dev);
2565
2566 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2567 del_timer_sync(&skge->link_timer);
2568
2569 netif_poll_disable(dev);
2570 netif_carrier_off(dev);
2571
2572 spin_lock_irq(&hw->hw_lock);
2573 hw->intr_mask &= ~portmask[port];
2574 skge_write32(hw, B0_IMSK, hw->intr_mask);
2575 spin_unlock_irq(&hw->hw_lock);
2576
2577 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2578 if (hw->chip_id == CHIP_ID_GENESIS)
2579 genesis_stop(skge);
2580 else
2581 yukon_stop(skge);
2582
2583 /* Stop transmitter */
2584 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2585 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2586 RB_RST_SET|RB_DIS_OP_MD);
2587
2588
2589 /* Disable Force Sync bit and Enable Alloc bit */
2590 skge_write8(hw, SK_REG(port, TXA_CTRL),
2591 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2592
2593 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2594 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2595 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2596
2597 /* Reset PCI FIFO */
2598 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2599 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2600
2601 /* Reset the RAM Buffer async Tx queue */
2602 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2603 /* stop receiver */
2604 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2605 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2606 RB_RST_SET|RB_DIS_OP_MD);
2607 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2608
2609 if (hw->chip_id == CHIP_ID_GENESIS) {
2610 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2611 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2612 } else {
2613 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2614 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2615 }
2616
2617 skge_led(skge, LED_MODE_OFF);
2618
2619 netif_tx_lock_bh(dev);
2620 skge_tx_clean(dev);
2621 netif_tx_unlock_bh(dev);
2622
2623 skge_rx_clean(skge);
2624
2625 kfree(skge->rx_ring.start);
2626 kfree(skge->tx_ring.start);
2627 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2628 skge->mem = NULL;
2629 return 0;
2630 }
2631
2632 static inline int skge_avail(const struct skge_ring *ring)
2633 {
2634 smp_mb();
2635 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2636 + (ring->to_clean - ring->to_use) - 1;
2637 }
2638
2639 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2640 {
2641 struct skge_port *skge = netdev_priv(dev);
2642 struct skge_hw *hw = skge->hw;
2643 struct skge_element *e;
2644 struct skge_tx_desc *td;
2645 int i;
2646 u32 control, len;
2647 u64 map;
2648
2649 if (skb_padto(skb, ETH_ZLEN))
2650 return NETDEV_TX_OK;
2651
2652 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2653 return NETDEV_TX_BUSY;
2654
2655 e = skge->tx_ring.to_use;
2656 td = e->desc;
2657 BUG_ON(td->control & BMU_OWN);
2658 e->skb = skb;
2659 len = skb_headlen(skb);
2660 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2661 pci_unmap_addr_set(e, mapaddr, map);
2662 pci_unmap_len_set(e, maplen, len);
2663
2664 td->dma_lo = map;
2665 td->dma_hi = map >> 32;
2666
2667 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2668 const int offset = skb_transport_offset(skb);
2669
2670 /* This seems backwards, but it is what the sk98lin
2671 * does. Looks like hardware is wrong?
2672 */
2673 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2674 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2675 control = BMU_TCP_CHECK;
2676 else
2677 control = BMU_UDP_CHECK;
2678
2679 td->csum_offs = 0;
2680 td->csum_start = offset;
2681 td->csum_write = offset + skb->csum_offset;
2682 } else
2683 control = BMU_CHECK;
2684
2685 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2686 control |= BMU_EOF| BMU_IRQ_EOF;
2687 else {
2688 struct skge_tx_desc *tf = td;
2689
2690 control |= BMU_STFWD;
2691 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2692 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2693
2694 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2695 frag->size, PCI_DMA_TODEVICE);
2696
2697 e = e->next;
2698 e->skb = skb;
2699 tf = e->desc;
2700 BUG_ON(tf->control & BMU_OWN);
2701
2702 tf->dma_lo = map;
2703 tf->dma_hi = (u64) map >> 32;
2704 pci_unmap_addr_set(e, mapaddr, map);
2705 pci_unmap_len_set(e, maplen, frag->size);
2706
2707 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2708 }
2709 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2710 }
2711 /* Make sure all the descriptors written */
2712 wmb();
2713 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2714 wmb();
2715
2716 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2717
2718 if (unlikely(netif_msg_tx_queued(skge)))
2719 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2720 dev->name, e - skge->tx_ring.start, skb->len);
2721
2722 skge->tx_ring.to_use = e->next;
2723 smp_wmb();
2724
2725 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2726 pr_debug("%s: transmit queue full\n", dev->name);
2727 netif_stop_queue(dev);
2728 }
2729
2730 dev->trans_start = jiffies;
2731
2732 return NETDEV_TX_OK;
2733 }
2734
2735
2736 /* Free resources associated with this reing element */
2737 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2738 u32 control)
2739 {
2740 struct pci_dev *pdev = skge->hw->pdev;
2741
2742 /* skb header vs. fragment */
2743 if (control & BMU_STF)
2744 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2745 pci_unmap_len(e, maplen),
2746 PCI_DMA_TODEVICE);
2747 else
2748 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2749 pci_unmap_len(e, maplen),
2750 PCI_DMA_TODEVICE);
2751
2752 if (control & BMU_EOF) {
2753 if (unlikely(netif_msg_tx_done(skge)))
2754 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2755 skge->netdev->name, e - skge->tx_ring.start);
2756
2757 dev_kfree_skb(e->skb);
2758 }
2759 }
2760
2761 /* Free all buffers in transmit ring */
2762 static void skge_tx_clean(struct net_device *dev)
2763 {
2764 struct skge_port *skge = netdev_priv(dev);
2765 struct skge_element *e;
2766
2767 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2768 struct skge_tx_desc *td = e->desc;
2769 skge_tx_free(skge, e, td->control);
2770 td->control = 0;
2771 }
2772
2773 skge->tx_ring.to_clean = e;
2774 netif_wake_queue(dev);
2775 }
2776
2777 static void skge_tx_timeout(struct net_device *dev)
2778 {
2779 struct skge_port *skge = netdev_priv(dev);
2780
2781 if (netif_msg_timer(skge))
2782 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2783
2784 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2785 skge_tx_clean(dev);
2786 }
2787
2788 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2789 {
2790 int err;
2791
2792 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2793 return -EINVAL;
2794
2795 if (!netif_running(dev)) {
2796 dev->mtu = new_mtu;
2797 return 0;
2798 }
2799
2800 skge_down(dev);
2801
2802 dev->mtu = new_mtu;
2803
2804 err = skge_up(dev);
2805 if (err)
2806 dev_close(dev);
2807
2808 return err;
2809 }
2810
2811 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2812
2813 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2814 {
2815 u32 crc, bit;
2816
2817 crc = ether_crc_le(ETH_ALEN, addr);
2818 bit = ~crc & 0x3f;
2819 filter[bit/8] |= 1 << (bit%8);
2820 }
2821
2822 static void genesis_set_multicast(struct net_device *dev)
2823 {
2824 struct skge_port *skge = netdev_priv(dev);
2825 struct skge_hw *hw = skge->hw;
2826 int port = skge->port;
2827 int i, count = dev->mc_count;
2828 struct dev_mc_list *list = dev->mc_list;
2829 u32 mode;
2830 u8 filter[8];
2831
2832 mode = xm_read32(hw, port, XM_MODE);
2833 mode |= XM_MD_ENA_HASH;
2834 if (dev->flags & IFF_PROMISC)
2835 mode |= XM_MD_ENA_PROM;
2836 else
2837 mode &= ~XM_MD_ENA_PROM;
2838
2839 if (dev->flags & IFF_ALLMULTI)
2840 memset(filter, 0xff, sizeof(filter));
2841 else {
2842 memset(filter, 0, sizeof(filter));
2843
2844 if (skge->flow_status == FLOW_STAT_REM_SEND
2845 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2846 genesis_add_filter(filter, pause_mc_addr);
2847
2848 for (i = 0; list && i < count; i++, list = list->next)
2849 genesis_add_filter(filter, list->dmi_addr);
2850 }
2851
2852 xm_write32(hw, port, XM_MODE, mode);
2853 xm_outhash(hw, port, XM_HSM, filter);
2854 }
2855
2856 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2857 {
2858 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2859 filter[bit/8] |= 1 << (bit%8);
2860 }
2861
2862 static void yukon_set_multicast(struct net_device *dev)
2863 {
2864 struct skge_port *skge = netdev_priv(dev);
2865 struct skge_hw *hw = skge->hw;
2866 int port = skge->port;
2867 struct dev_mc_list *list = dev->mc_list;
2868 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2869 || skge->flow_status == FLOW_STAT_SYMMETRIC);
2870 u16 reg;
2871 u8 filter[8];
2872
2873 memset(filter, 0, sizeof(filter));
2874
2875 reg = gma_read16(hw, port, GM_RX_CTRL);
2876 reg |= GM_RXCR_UCF_ENA;
2877
2878 if (dev->flags & IFF_PROMISC) /* promiscuous */
2879 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2880 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2881 memset(filter, 0xff, sizeof(filter));
2882 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
2883 reg &= ~GM_RXCR_MCF_ENA;
2884 else {
2885 int i;
2886 reg |= GM_RXCR_MCF_ENA;
2887
2888 if (rx_pause)
2889 yukon_add_filter(filter, pause_mc_addr);
2890
2891 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2892 yukon_add_filter(filter, list->dmi_addr);
2893 }
2894
2895
2896 gma_write16(hw, port, GM_MC_ADDR_H1,
2897 (u16)filter[0] | ((u16)filter[1] << 8));
2898 gma_write16(hw, port, GM_MC_ADDR_H2,
2899 (u16)filter[2] | ((u16)filter[3] << 8));
2900 gma_write16(hw, port, GM_MC_ADDR_H3,
2901 (u16)filter[4] | ((u16)filter[5] << 8));
2902 gma_write16(hw, port, GM_MC_ADDR_H4,
2903 (u16)filter[6] | ((u16)filter[7] << 8));
2904
2905 gma_write16(hw, port, GM_RX_CTRL, reg);
2906 }
2907
2908 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2909 {
2910 if (hw->chip_id == CHIP_ID_GENESIS)
2911 return status >> XMR_FS_LEN_SHIFT;
2912 else
2913 return status >> GMR_FS_LEN_SHIFT;
2914 }
2915
2916 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2917 {
2918 if (hw->chip_id == CHIP_ID_GENESIS)
2919 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2920 else
2921 return (status & GMR_FS_ANY_ERR) ||
2922 (status & GMR_FS_RX_OK) == 0;
2923 }
2924
2925
2926 /* Get receive buffer from descriptor.
2927 * Handles copy of small buffers and reallocation failures
2928 */
2929 static struct sk_buff *skge_rx_get(struct net_device *dev,
2930 struct skge_element *e,
2931 u32 control, u32 status, u16 csum)
2932 {
2933 struct skge_port *skge = netdev_priv(dev);
2934 struct sk_buff *skb;
2935 u16 len = control & BMU_BBC;
2936
2937 if (unlikely(netif_msg_rx_status(skge)))
2938 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2939 dev->name, e - skge->rx_ring.start,
2940 status, len);
2941
2942 if (len > skge->rx_buf_size)
2943 goto error;
2944
2945 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2946 goto error;
2947
2948 if (bad_phy_status(skge->hw, status))
2949 goto error;
2950
2951 if (phy_length(skge->hw, status) != len)
2952 goto error;
2953
2954 if (len < RX_COPY_THRESHOLD) {
2955 skb = netdev_alloc_skb(dev, len + 2);
2956 if (!skb)
2957 goto resubmit;
2958
2959 skb_reserve(skb, 2);
2960 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2961 pci_unmap_addr(e, mapaddr),
2962 len, PCI_DMA_FROMDEVICE);
2963 skb_copy_from_linear_data(e->skb, skb->data, len);
2964 pci_dma_sync_single_for_device(skge->hw->pdev,
2965 pci_unmap_addr(e, mapaddr),
2966 len, PCI_DMA_FROMDEVICE);
2967 skge_rx_reuse(e, skge->rx_buf_size);
2968 } else {
2969 struct sk_buff *nskb;
2970 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2971 if (!nskb)
2972 goto resubmit;
2973
2974 skb_reserve(nskb, NET_IP_ALIGN);
2975 pci_unmap_single(skge->hw->pdev,
2976 pci_unmap_addr(e, mapaddr),
2977 pci_unmap_len(e, maplen),
2978 PCI_DMA_FROMDEVICE);
2979 skb = e->skb;
2980 prefetch(skb->data);
2981 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2982 }
2983
2984 skb_put(skb, len);
2985 if (skge->rx_csum) {
2986 skb->csum = csum;
2987 skb->ip_summed = CHECKSUM_COMPLETE;
2988 }
2989
2990 skb->protocol = eth_type_trans(skb, dev);
2991
2992 return skb;
2993 error:
2994
2995 if (netif_msg_rx_err(skge))
2996 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2997 dev->name, e - skge->rx_ring.start,
2998 control, status);
2999
3000 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3001 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3002 skge->net_stats.rx_length_errors++;
3003 if (status & XMR_FS_FRA_ERR)
3004 skge->net_stats.rx_frame_errors++;
3005 if (status & XMR_FS_FCS_ERR)
3006 skge->net_stats.rx_crc_errors++;
3007 } else {
3008 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3009 skge->net_stats.rx_length_errors++;
3010 if (status & GMR_FS_FRAGMENT)
3011 skge->net_stats.rx_frame_errors++;
3012 if (status & GMR_FS_CRC_ERR)
3013 skge->net_stats.rx_crc_errors++;
3014 }
3015
3016 resubmit:
3017 skge_rx_reuse(e, skge->rx_buf_size);
3018 return NULL;
3019 }
3020
3021 /* Free all buffers in Tx ring which are no longer owned by device */
3022 static void skge_tx_done(struct net_device *dev)
3023 {
3024 struct skge_port *skge = netdev_priv(dev);
3025 struct skge_ring *ring = &skge->tx_ring;
3026 struct skge_element *e;
3027
3028 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3029
3030 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3031 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3032
3033 if (control & BMU_OWN)
3034 break;
3035
3036 skge_tx_free(skge, e, control);
3037 }
3038 skge->tx_ring.to_clean = e;
3039
3040 /* Can run lockless until we need to synchronize to restart queue. */
3041 smp_mb();
3042
3043 if (unlikely(netif_queue_stopped(dev) &&
3044 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3045 netif_tx_lock(dev);
3046 if (unlikely(netif_queue_stopped(dev) &&
3047 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3048 netif_wake_queue(dev);
3049
3050 }
3051 netif_tx_unlock(dev);
3052 }
3053 }
3054
3055 static int skge_poll(struct net_device *dev, int *budget)
3056 {
3057 struct skge_port *skge = netdev_priv(dev);
3058 struct skge_hw *hw = skge->hw;
3059 struct skge_ring *ring = &skge->rx_ring;
3060 struct skge_element *e;
3061 unsigned long flags;
3062 int to_do = min(dev->quota, *budget);
3063 int work_done = 0;
3064
3065 skge_tx_done(dev);
3066
3067 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3068
3069 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3070 struct skge_rx_desc *rd = e->desc;
3071 struct sk_buff *skb;
3072 u32 control;
3073
3074 rmb();
3075 control = rd->control;
3076 if (control & BMU_OWN)
3077 break;
3078
3079 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3080 if (likely(skb)) {
3081 dev->last_rx = jiffies;
3082 netif_receive_skb(skb);
3083
3084 ++work_done;
3085 }
3086 }
3087 ring->to_clean = e;
3088
3089 /* restart receiver */
3090 wmb();
3091 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3092
3093 *budget -= work_done;
3094 dev->quota -= work_done;
3095
3096 if (work_done >= to_do)
3097 return 1; /* not done */
3098
3099 spin_lock_irqsave(&hw->hw_lock, flags);
3100 __netif_rx_complete(dev);
3101 hw->intr_mask |= napimask[skge->port];
3102 skge_write32(hw, B0_IMSK, hw->intr_mask);
3103 skge_read32(hw, B0_IMSK);
3104 spin_unlock_irqrestore(&hw->hw_lock, flags);
3105
3106 return 0;
3107 }
3108
3109 /* Parity errors seem to happen when Genesis is connected to a switch
3110 * with no other ports present. Heartbeat error??
3111 */
3112 static void skge_mac_parity(struct skge_hw *hw, int port)
3113 {
3114 struct net_device *dev = hw->dev[port];
3115
3116 if (dev) {
3117 struct skge_port *skge = netdev_priv(dev);
3118 ++skge->net_stats.tx_heartbeat_errors;
3119 }
3120
3121 if (hw->chip_id == CHIP_ID_GENESIS)
3122 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3123 MFF_CLR_PERR);
3124 else
3125 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3126 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3127 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3128 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3129 }
3130
3131 static void skge_mac_intr(struct skge_hw *hw, int port)
3132 {
3133 if (hw->chip_id == CHIP_ID_GENESIS)
3134 genesis_mac_intr(hw, port);
3135 else
3136 yukon_mac_intr(hw, port);
3137 }
3138
3139 /* Handle device specific framing and timeout interrupts */
3140 static void skge_error_irq(struct skge_hw *hw)
3141 {
3142 struct pci_dev *pdev = hw->pdev;
3143 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3144
3145 if (hw->chip_id == CHIP_ID_GENESIS) {
3146 /* clear xmac errors */
3147 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3148 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3149 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3150 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3151 } else {
3152 /* Timestamp (unused) overflow */
3153 if (hwstatus & IS_IRQ_TIST_OV)
3154 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3155 }
3156
3157 if (hwstatus & IS_RAM_RD_PAR) {
3158 dev_err(&pdev->dev, "Ram read data parity error\n");
3159 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3160 }
3161
3162 if (hwstatus & IS_RAM_WR_PAR) {
3163 dev_err(&pdev->dev, "Ram write data parity error\n");
3164 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3165 }
3166
3167 if (hwstatus & IS_M1_PAR_ERR)
3168 skge_mac_parity(hw, 0);
3169
3170 if (hwstatus & IS_M2_PAR_ERR)
3171 skge_mac_parity(hw, 1);
3172
3173 if (hwstatus & IS_R1_PAR_ERR) {
3174 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3175 hw->dev[0]->name);
3176 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3177 }
3178
3179 if (hwstatus & IS_R2_PAR_ERR) {
3180 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3181 hw->dev[1]->name);
3182 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3183 }
3184
3185 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3186 u16 pci_status, pci_cmd;
3187
3188 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3189 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3190
3191 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3192 pci_cmd, pci_status);
3193
3194 /* Write the error bits back to clear them. */
3195 pci_status &= PCI_STATUS_ERROR_BITS;
3196 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3197 pci_write_config_word(pdev, PCI_COMMAND,
3198 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3199 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3200 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3201
3202 /* if error still set then just ignore it */
3203 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3204 if (hwstatus & IS_IRQ_STAT) {
3205 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3206 hw->intr_mask &= ~IS_HW_ERR;
3207 }
3208 }
3209 }
3210
3211 /*
3212 * Interrupt from PHY are handled in tasklet (softirq)
3213 * because accessing phy registers requires spin wait which might
3214 * cause excess interrupt latency.
3215 */
3216 static void skge_extirq(unsigned long arg)
3217 {
3218 struct skge_hw *hw = (struct skge_hw *) arg;
3219 int port;
3220
3221 for (port = 0; port < hw->ports; port++) {
3222 struct net_device *dev = hw->dev[port];
3223
3224 if (netif_running(dev)) {
3225 struct skge_port *skge = netdev_priv(dev);
3226
3227 spin_lock(&hw->phy_lock);
3228 if (hw->chip_id != CHIP_ID_GENESIS)
3229 yukon_phy_intr(skge);
3230 else if (hw->phy_type == SK_PHY_BCOM)
3231 bcom_phy_intr(skge);
3232 spin_unlock(&hw->phy_lock);
3233 }
3234 }
3235
3236 spin_lock_irq(&hw->hw_lock);
3237 hw->intr_mask |= IS_EXT_REG;
3238 skge_write32(hw, B0_IMSK, hw->intr_mask);
3239 skge_read32(hw, B0_IMSK);
3240 spin_unlock_irq(&hw->hw_lock);
3241 }
3242
3243 static irqreturn_t skge_intr(int irq, void *dev_id)
3244 {
3245 struct skge_hw *hw = dev_id;
3246 u32 status;
3247 int handled = 0;
3248
3249 spin_lock(&hw->hw_lock);
3250 /* Reading this register masks IRQ */
3251 status = skge_read32(hw, B0_SP_ISRC);
3252 if (status == 0 || status == ~0)
3253 goto out;
3254
3255 handled = 1;
3256 status &= hw->intr_mask;
3257 if (status & IS_EXT_REG) {
3258 hw->intr_mask &= ~IS_EXT_REG;
3259 tasklet_schedule(&hw->phy_task);
3260 }
3261
3262 if (status & (IS_XA1_F|IS_R1_F)) {
3263 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3264 netif_rx_schedule(hw->dev[0]);
3265 }
3266
3267 if (status & IS_PA_TO_TX1)
3268 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3269
3270 if (status & IS_PA_TO_RX1) {
3271 struct skge_port *skge = netdev_priv(hw->dev[0]);
3272
3273 ++skge->net_stats.rx_over_errors;
3274 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3275 }
3276
3277
3278 if (status & IS_MAC1)
3279 skge_mac_intr(hw, 0);
3280
3281 if (hw->dev[1]) {
3282 if (status & (IS_XA2_F|IS_R2_F)) {
3283 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3284 netif_rx_schedule(hw->dev[1]);
3285 }
3286
3287 if (status & IS_PA_TO_RX2) {
3288 struct skge_port *skge = netdev_priv(hw->dev[1]);
3289 ++skge->net_stats.rx_over_errors;
3290 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3291 }
3292
3293 if (status & IS_PA_TO_TX2)
3294 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3295
3296 if (status & IS_MAC2)
3297 skge_mac_intr(hw, 1);
3298 }
3299
3300 if (status & IS_HW_ERR)
3301 skge_error_irq(hw);
3302
3303 skge_write32(hw, B0_IMSK, hw->intr_mask);
3304 skge_read32(hw, B0_IMSK);
3305 out:
3306 spin_unlock(&hw->hw_lock);
3307
3308 return IRQ_RETVAL(handled);
3309 }
3310
3311 #ifdef CONFIG_NET_POLL_CONTROLLER
3312 static void skge_netpoll(struct net_device *dev)
3313 {
3314 struct skge_port *skge = netdev_priv(dev);
3315
3316 disable_irq(dev->irq);
3317 skge_intr(dev->irq, skge->hw);
3318 enable_irq(dev->irq);
3319 }
3320 #endif
3321
3322 static int skge_set_mac_address(struct net_device *dev, void *p)
3323 {
3324 struct skge_port *skge = netdev_priv(dev);
3325 struct skge_hw *hw = skge->hw;
3326 unsigned port = skge->port;
3327 const struct sockaddr *addr = p;
3328 u16 ctrl;
3329
3330 if (!is_valid_ether_addr(addr->sa_data))
3331 return -EADDRNOTAVAIL;
3332
3333 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3334
3335 if (!netif_running(dev)) {
3336 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3337 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3338 } else {
3339 /* disable Rx */
3340 spin_lock_bh(&hw->phy_lock);
3341 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3342 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3343
3344 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3345 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3346
3347 if (hw->chip_id == CHIP_ID_GENESIS)
3348 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3349 else {
3350 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3351 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3352 }
3353
3354 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3355 spin_unlock_bh(&hw->phy_lock);
3356 }
3357
3358 return 0;
3359 }
3360
3361 static const struct {
3362 u8 id;
3363 const char *name;
3364 } skge_chips[] = {
3365 { CHIP_ID_GENESIS, "Genesis" },
3366 { CHIP_ID_YUKON, "Yukon" },
3367 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3368 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3369 };
3370
3371 static const char *skge_board_name(const struct skge_hw *hw)
3372 {
3373 int i;
3374 static char buf[16];
3375
3376 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3377 if (skge_chips[i].id == hw->chip_id)
3378 return skge_chips[i].name;
3379
3380 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3381 return buf;
3382 }
3383
3384
3385 /*
3386 * Setup the board data structure, but don't bring up
3387 * the port(s)
3388 */
3389 static int skge_reset(struct skge_hw *hw)
3390 {
3391 u32 reg;
3392 u16 ctst, pci_status;
3393 u8 t8, mac_cfg, pmd_type;
3394 int i;
3395
3396 ctst = skge_read16(hw, B0_CTST);
3397
3398 /* do a SW reset */
3399 skge_write8(hw, B0_CTST, CS_RST_SET);
3400 skge_write8(hw, B0_CTST, CS_RST_CLR);
3401
3402 /* clear PCI errors, if any */
3403 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3404 skge_write8(hw, B2_TST_CTRL2, 0);
3405
3406 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3407 pci_write_config_word(hw->pdev, PCI_STATUS,
3408 pci_status | PCI_STATUS_ERROR_BITS);
3409 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3410 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3411
3412 /* restore CLK_RUN bits (for Yukon-Lite) */
3413 skge_write16(hw, B0_CTST,
3414 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3415
3416 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3417 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3418 pmd_type = skge_read8(hw, B2_PMD_TYP);
3419 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3420
3421 switch (hw->chip_id) {
3422 case CHIP_ID_GENESIS:
3423 switch (hw->phy_type) {
3424 case SK_PHY_XMAC:
3425 hw->phy_addr = PHY_ADDR_XMAC;
3426 break;
3427 case SK_PHY_BCOM:
3428 hw->phy_addr = PHY_ADDR_BCOM;
3429 break;
3430 default:
3431 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3432 hw->phy_type);
3433 return -EOPNOTSUPP;
3434 }
3435 break;
3436
3437 case CHIP_ID_YUKON:
3438 case CHIP_ID_YUKON_LITE:
3439 case CHIP_ID_YUKON_LP:
3440 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3441 hw->copper = 1;
3442
3443 hw->phy_addr = PHY_ADDR_MARV;
3444 break;
3445
3446 default:
3447 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3448 hw->chip_id);
3449 return -EOPNOTSUPP;
3450 }
3451
3452 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3453 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3454 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3455
3456 /* read the adapters RAM size */
3457 t8 = skge_read8(hw, B2_E_0);
3458 if (hw->chip_id == CHIP_ID_GENESIS) {
3459 if (t8 == 3) {
3460 /* special case: 4 x 64k x 36, offset = 0x80000 */
3461 hw->ram_size = 0x100000;
3462 hw->ram_offset = 0x80000;
3463 } else
3464 hw->ram_size = t8 * 512;
3465 }
3466 else if (t8 == 0)
3467 hw->ram_size = 0x20000;
3468 else
3469 hw->ram_size = t8 * 4096;
3470
3471 hw->intr_mask = IS_HW_ERR;
3472
3473 /* Use PHY IRQ for all but fiber based Genesis board */
3474 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3475 hw->intr_mask |= IS_EXT_REG;
3476
3477 if (hw->chip_id == CHIP_ID_GENESIS)
3478 genesis_init(hw);
3479 else {
3480 /* switch power to VCC (WA for VAUX problem) */
3481 skge_write8(hw, B0_POWER_CTRL,
3482 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3483
3484 /* avoid boards with stuck Hardware error bits */
3485 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3486 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3487 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3488 hw->intr_mask &= ~IS_HW_ERR;
3489 }
3490
3491 /* Clear PHY COMA */
3492 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3493 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3494 reg &= ~PCI_PHY_COMA;
3495 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3496 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3497
3498
3499 for (i = 0; i < hw->ports; i++) {
3500 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3501 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3502 }
3503 }
3504
3505 /* turn off hardware timer (unused) */
3506 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3507 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3508 skge_write8(hw, B0_LED, LED_STAT_ON);
3509
3510 /* enable the Tx Arbiters */
3511 for (i = 0; i < hw->ports; i++)
3512 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3513
3514 /* Initialize ram interface */
3515 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3516
3517 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3518 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3519 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3520 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3521 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3522 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3523 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3524 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3525 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3526 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3527 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3528 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3529
3530 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3531
3532 /* Set interrupt moderation for Transmit only
3533 * Receive interrupts avoided by NAPI
3534 */
3535 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3536 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3537 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3538
3539 skge_write32(hw, B0_IMSK, hw->intr_mask);
3540
3541 for (i = 0; i < hw->ports; i++) {
3542 if (hw->chip_id == CHIP_ID_GENESIS)
3543 genesis_reset(hw, i);
3544 else
3545 yukon_reset(hw, i);
3546 }
3547
3548 return 0;
3549 }
3550
3551 /* Initialize network device */
3552 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3553 int highmem)
3554 {
3555 struct skge_port *skge;
3556 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3557
3558 if (!dev) {
3559 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3560 return NULL;
3561 }
3562
3563 SET_MODULE_OWNER(dev);
3564 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3565 dev->open = skge_up;
3566 dev->stop = skge_down;
3567 dev->do_ioctl = skge_ioctl;
3568 dev->hard_start_xmit = skge_xmit_frame;
3569 dev->get_stats = skge_get_stats;
3570 if (hw->chip_id == CHIP_ID_GENESIS)
3571 dev->set_multicast_list = genesis_set_multicast;
3572 else
3573 dev->set_multicast_list = yukon_set_multicast;
3574
3575 dev->set_mac_address = skge_set_mac_address;
3576 dev->change_mtu = skge_change_mtu;
3577 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3578 dev->tx_timeout = skge_tx_timeout;
3579 dev->watchdog_timeo = TX_WATCHDOG;
3580 dev->poll = skge_poll;
3581 dev->weight = NAPI_WEIGHT;
3582 #ifdef CONFIG_NET_POLL_CONTROLLER
3583 dev->poll_controller = skge_netpoll;
3584 #endif
3585 dev->irq = hw->pdev->irq;
3586
3587 if (highmem)
3588 dev->features |= NETIF_F_HIGHDMA;
3589
3590 skge = netdev_priv(dev);
3591 skge->netdev = dev;
3592 skge->hw = hw;
3593 skge->msg_enable = netif_msg_init(debug, default_msg);
3594
3595 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3596 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3597
3598 /* Auto speed and flow control */
3599 skge->autoneg = AUTONEG_ENABLE;
3600 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3601 skge->duplex = -1;
3602 skge->speed = -1;
3603 skge->advertising = skge_supported_modes(hw);
3604
3605 if (pci_wake_enabled(hw->pdev))
3606 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3607
3608 hw->dev[port] = dev;
3609
3610 skge->port = port;
3611
3612 /* Only used for Genesis XMAC */
3613 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3614
3615 if (hw->chip_id != CHIP_ID_GENESIS) {
3616 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3617 skge->rx_csum = 1;
3618 }
3619
3620 /* read the mac address */
3621 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3622 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3623
3624 /* device is off until link detection */
3625 netif_carrier_off(dev);
3626 netif_stop_queue(dev);
3627
3628 return dev;
3629 }
3630
3631 static void __devinit skge_show_addr(struct net_device *dev)
3632 {
3633 const struct skge_port *skge = netdev_priv(dev);
3634
3635 if (netif_msg_probe(skge))
3636 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3637 dev->name,
3638 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3639 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3640 }
3641
3642 static int __devinit skge_probe(struct pci_dev *pdev,
3643 const struct pci_device_id *ent)
3644 {
3645 struct net_device *dev, *dev1;
3646 struct skge_hw *hw;
3647 int err, using_dac = 0;
3648
3649 err = pci_enable_device(pdev);
3650 if (err) {
3651 dev_err(&pdev->dev, "cannot enable PCI device\n");
3652 goto err_out;
3653 }
3654
3655 err = pci_request_regions(pdev, DRV_NAME);
3656 if (err) {
3657 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3658 goto err_out_disable_pdev;
3659 }
3660
3661 pci_set_master(pdev);
3662
3663 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3664 using_dac = 1;
3665 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3666 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3667 using_dac = 0;
3668 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3669 }
3670
3671 if (err) {
3672 dev_err(&pdev->dev, "no usable DMA configuration\n");
3673 goto err_out_free_regions;
3674 }
3675
3676 #ifdef __BIG_ENDIAN
3677 /* byte swap descriptors in hardware */
3678 {
3679 u32 reg;
3680
3681 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3682 reg |= PCI_REV_DESC;
3683 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3684 }
3685 #endif
3686
3687 err = -ENOMEM;
3688 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3689 if (!hw) {
3690 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3691 goto err_out_free_regions;
3692 }
3693
3694 hw->pdev = pdev;
3695 spin_lock_init(&hw->hw_lock);
3696 spin_lock_init(&hw->phy_lock);
3697 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3698
3699 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3700 if (!hw->regs) {
3701 dev_err(&pdev->dev, "cannot map device registers\n");
3702 goto err_out_free_hw;
3703 }
3704
3705 err = skge_reset(hw);
3706 if (err)
3707 goto err_out_iounmap;
3708
3709 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3710 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3711 skge_board_name(hw), hw->chip_rev);
3712
3713 dev = skge_devinit(hw, 0, using_dac);
3714 if (!dev)
3715 goto err_out_led_off;
3716
3717 /* Some motherboards are broken and has zero in ROM. */
3718 if (!is_valid_ether_addr(dev->dev_addr))
3719 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3720
3721 err = register_netdev(dev);
3722 if (err) {
3723 dev_err(&pdev->dev, "cannot register net device\n");
3724 goto err_out_free_netdev;
3725 }
3726
3727 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3728 if (err) {
3729 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3730 dev->name, pdev->irq);
3731 goto err_out_unregister;
3732 }
3733 skge_show_addr(dev);
3734
3735 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3736 if (register_netdev(dev1) == 0)
3737 skge_show_addr(dev1);
3738 else {
3739 /* Failure to register second port need not be fatal */
3740 dev_warn(&pdev->dev, "register of second port failed\n");
3741 hw->dev[1] = NULL;
3742 free_netdev(dev1);
3743 }
3744 }
3745 pci_set_drvdata(pdev, hw);
3746
3747 return 0;
3748
3749 err_out_unregister:
3750 unregister_netdev(dev);
3751 err_out_free_netdev:
3752 free_netdev(dev);
3753 err_out_led_off:
3754 skge_write16(hw, B0_LED, LED_STAT_OFF);
3755 err_out_iounmap:
3756 iounmap(hw->regs);
3757 err_out_free_hw:
3758 kfree(hw);
3759 err_out_free_regions:
3760 pci_release_regions(pdev);
3761 err_out_disable_pdev:
3762 pci_disable_device(pdev);
3763 pci_set_drvdata(pdev, NULL);
3764 err_out:
3765 return err;
3766 }
3767
3768 static void __devexit skge_remove(struct pci_dev *pdev)
3769 {
3770 struct skge_hw *hw = pci_get_drvdata(pdev);
3771 struct net_device *dev0, *dev1;
3772
3773 if (!hw)
3774 return;
3775
3776 flush_scheduled_work();
3777
3778 if ((dev1 = hw->dev[1]))
3779 unregister_netdev(dev1);
3780 dev0 = hw->dev[0];
3781 unregister_netdev(dev0);
3782
3783 tasklet_disable(&hw->phy_task);
3784
3785 spin_lock_irq(&hw->hw_lock);
3786 hw->intr_mask = 0;
3787 skge_write32(hw, B0_IMSK, 0);
3788 skge_read32(hw, B0_IMSK);
3789 spin_unlock_irq(&hw->hw_lock);
3790
3791 skge_write16(hw, B0_LED, LED_STAT_OFF);
3792 skge_write8(hw, B0_CTST, CS_RST_SET);
3793
3794 free_irq(pdev->irq, hw);
3795 pci_release_regions(pdev);
3796 pci_disable_device(pdev);
3797 if (dev1)
3798 free_netdev(dev1);
3799 free_netdev(dev0);
3800
3801 iounmap(hw->regs);
3802 kfree(hw);
3803 pci_set_drvdata(pdev, NULL);
3804 }
3805
3806 #ifdef CONFIG_PM
3807 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3808 {
3809 struct skge_hw *hw = pci_get_drvdata(pdev);
3810 int i, err, wol = 0;
3811
3812 if (!hw)
3813 return 0;
3814
3815 err = pci_save_state(pdev);
3816 if (err)
3817 return err;
3818
3819 for (i = 0; i < hw->ports; i++) {
3820 struct net_device *dev = hw->dev[i];
3821 struct skge_port *skge = netdev_priv(dev);
3822
3823 if (netif_running(dev))
3824 skge_down(dev);
3825 if (skge->wol)
3826 skge_wol_init(skge);
3827
3828 wol |= skge->wol;
3829 }
3830
3831 skge_write32(hw, B0_IMSK, 0);
3832 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3833 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3834
3835 return 0;
3836 }
3837
3838 static int skge_resume(struct pci_dev *pdev)
3839 {
3840 struct skge_hw *hw = pci_get_drvdata(pdev);
3841 int i, err;
3842
3843 if (!hw)
3844 return 0;
3845
3846 err = pci_set_power_state(pdev, PCI_D0);
3847 if (err)
3848 goto out;
3849
3850 err = pci_restore_state(pdev);
3851 if (err)
3852 goto out;
3853
3854 pci_enable_wake(pdev, PCI_D0, 0);
3855
3856 err = skge_reset(hw);
3857 if (err)
3858 goto out;
3859
3860 for (i = 0; i < hw->ports; i++) {
3861 struct net_device *dev = hw->dev[i];
3862
3863 if (netif_running(dev)) {
3864 err = skge_up(dev);
3865
3866 if (err) {
3867 printk(KERN_ERR PFX "%s: could not up: %d\n",
3868 dev->name, err);
3869 dev_close(dev);
3870 goto out;
3871 }
3872 }
3873 }
3874 out:
3875 return err;
3876 }
3877 #endif
3878
3879 static void skge_shutdown(struct pci_dev *pdev)
3880 {
3881 struct skge_hw *hw = pci_get_drvdata(pdev);
3882 int i, wol = 0;
3883
3884 if (!hw)
3885 return;
3886
3887 for (i = 0; i < hw->ports; i++) {
3888 struct net_device *dev = hw->dev[i];
3889 struct skge_port *skge = netdev_priv(dev);
3890
3891 if (skge->wol)
3892 skge_wol_init(skge);
3893 wol |= skge->wol;
3894 }
3895
3896 pci_enable_wake(pdev, PCI_D3hot, wol);
3897 pci_enable_wake(pdev, PCI_D3cold, wol);
3898
3899 pci_disable_device(pdev);
3900 pci_set_power_state(pdev, PCI_D3hot);
3901
3902 }
3903
3904 static struct pci_driver skge_driver = {
3905 .name = DRV_NAME,
3906 .id_table = skge_id_table,
3907 .probe = skge_probe,
3908 .remove = __devexit_p(skge_remove),
3909 #ifdef CONFIG_PM
3910 .suspend = skge_suspend,
3911 .resume = skge_resume,
3912 #endif
3913 .shutdown = skge_shutdown,
3914 };
3915
3916 static int __init skge_init_module(void)
3917 {
3918 return pci_register_driver(&skge_driver);
3919 }
3920
3921 static void __exit skge_cleanup_module(void)
3922 {
3923 pci_unregister_driver(&skge_driver);
3924 }
3925
3926 module_init(skge_init_module);
3927 module_exit(skge_cleanup_module);
Compression patch for TCP for Linux kernel