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Force reset on decompression error
[linux-2.6/tcp-comp.git] / drivers / net / tg3.c
blobf80721ecd3376c470ecb86e6809bd4d601aa9890
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.81.1"
68 #define DRV_MODULE_RELDATE "October 18, 2007"
69
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86 #define TG3_TX_TIMEOUT (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST 6
134
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
209 };
210
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
213 static const struct {
214 const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292 };
293
294 static const struct {
295 const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303 };
304
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306 {
307 writel(val, tp->regs + off);
308 }
309
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
311 {
312 return (readl(tp->regs + off));
313 }
314
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316 {
317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
323 }
324
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326 {
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
329 }
330
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
332 {
333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341 }
342
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344 {
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
356 }
357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371 }
372
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374 {
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383 }
384
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
391 {
392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
408 }
409
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411 {
412 tp->write32_mbox(tp, off, val);
413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
416 }
417
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
419 {
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426 }
427
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429 {
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431 }
432
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434 {
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436 }
437
438 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
443
444 #define tw32(reg,val) tp->write32(tp, reg, val)
445 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg) tp->read32(tp, reg)
448
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450 {
451 unsigned long flags;
452
453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
461
462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
467
468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 }
473
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475 {
476 unsigned long flags;
477
478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
488
489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
499 }
500
501 static void tg3_disable_ints(struct tg3 *tp)
502 {
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
506 }
507
508 static inline void tg3_cond_int(struct tg3 *tp)
509 {
510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
516 }
517
518 static void tg3_enable_ints(struct tg3 *tp)
519 {
520 tp->irq_sync = 0;
521 wmb();
522
523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
530 tg3_cond_int(tp);
531 }
532
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
534 {
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551 }
552
553 /* tg3_restart_ints
554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
556 * which reenables interrupts
557 */
558 static void tg3_restart_ints(struct tg3 *tp)
559 {
560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
562 mmiowb();
563
564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
572 }
573
574 static inline void tg3_netif_stop(struct tg3 *tp)
575 {
576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579 }
580
581 static inline void tg3_netif_start(struct tg3 *tp)
582 {
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
591 }
592
593 static void tg3_switch_clocks(struct tg3 *tp)
594 {
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
599 return;
600
601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
620 }
621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
622 }
623
624 #define PHY_BUSY_LOOPS 5000
625
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627 {
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
645
646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673 }
674
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676 {
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
697
698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722 }
723
724 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
725 {
726 u32 phy;
727
728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
729 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
730 return;
731
732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
733 u32 ephy;
734
735 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
736 tg3_writephy(tp, MII_TG3_EPHY_TEST,
737 ephy | MII_TG3_EPHY_SHADOW_EN);
738 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
739 if (enable)
740 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
741 else
742 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
743 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
744 }
745 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
746 }
747 } else {
748 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
749 MII_TG3_AUXCTL_SHDWSEL_MISC;
750 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
751 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
752 if (enable)
753 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
754 else
755 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
756 phy |= MII_TG3_AUXCTL_MISC_WREN;
757 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
758 }
759 }
760 }
761
762 static void tg3_phy_set_wirespeed(struct tg3 *tp)
763 {
764 u32 val;
765
766 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
767 return;
768
769 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
770 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
771 tg3_writephy(tp, MII_TG3_AUX_CTRL,
772 (val | (1 << 15) | (1 << 4)));
773 }
774
775 static int tg3_bmcr_reset(struct tg3 *tp)
776 {
777 u32 phy_control;
778 int limit, err;
779
780 /* OK, reset it, and poll the BMCR_RESET bit until it
781 * clears or we time out.
782 */
783 phy_control = BMCR_RESET;
784 err = tg3_writephy(tp, MII_BMCR, phy_control);
785 if (err != 0)
786 return -EBUSY;
787
788 limit = 5000;
789 while (limit--) {
790 err = tg3_readphy(tp, MII_BMCR, &phy_control);
791 if (err != 0)
792 return -EBUSY;
793
794 if ((phy_control & BMCR_RESET) == 0) {
795 udelay(40);
796 break;
797 }
798 udelay(10);
799 }
800 if (limit <= 0)
801 return -EBUSY;
802
803 return 0;
804 }
805
806 static int tg3_wait_macro_done(struct tg3 *tp)
807 {
808 int limit = 100;
809
810 while (limit--) {
811 u32 tmp32;
812
813 if (!tg3_readphy(tp, 0x16, &tmp32)) {
814 if ((tmp32 & 0x1000) == 0)
815 break;
816 }
817 }
818 if (limit <= 0)
819 return -EBUSY;
820
821 return 0;
822 }
823
824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
825 {
826 static const u32 test_pat[4][6] = {
827 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
828 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
829 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
830 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
831 };
832 int chan;
833
834 for (chan = 0; chan < 4; chan++) {
835 int i;
836
837 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
838 (chan * 0x2000) | 0x0200);
839 tg3_writephy(tp, 0x16, 0x0002);
840
841 for (i = 0; i < 6; i++)
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
843 test_pat[chan][i]);
844
845 tg3_writephy(tp, 0x16, 0x0202);
846 if (tg3_wait_macro_done(tp)) {
847 *resetp = 1;
848 return -EBUSY;
849 }
850
851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
852 (chan * 0x2000) | 0x0200);
853 tg3_writephy(tp, 0x16, 0x0082);
854 if (tg3_wait_macro_done(tp)) {
855 *resetp = 1;
856 return -EBUSY;
857 }
858
859 tg3_writephy(tp, 0x16, 0x0802);
860 if (tg3_wait_macro_done(tp)) {
861 *resetp = 1;
862 return -EBUSY;
863 }
864
865 for (i = 0; i < 6; i += 2) {
866 u32 low, high;
867
868 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
869 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
870 tg3_wait_macro_done(tp)) {
871 *resetp = 1;
872 return -EBUSY;
873 }
874 low &= 0x7fff;
875 high &= 0x000f;
876 if (low != test_pat[chan][i] ||
877 high != test_pat[chan][i+1]) {
878 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
880 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
881
882 return -EBUSY;
883 }
884 }
885 }
886
887 return 0;
888 }
889
890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
891 {
892 int chan;
893
894 for (chan = 0; chan < 4; chan++) {
895 int i;
896
897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
898 (chan * 0x2000) | 0x0200);
899 tg3_writephy(tp, 0x16, 0x0002);
900 for (i = 0; i < 6; i++)
901 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
902 tg3_writephy(tp, 0x16, 0x0202);
903 if (tg3_wait_macro_done(tp))
904 return -EBUSY;
905 }
906
907 return 0;
908 }
909
910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
911 {
912 u32 reg32, phy9_orig;
913 int retries, do_phy_reset, err;
914
915 retries = 10;
916 do_phy_reset = 1;
917 do {
918 if (do_phy_reset) {
919 err = tg3_bmcr_reset(tp);
920 if (err)
921 return err;
922 do_phy_reset = 0;
923 }
924
925 /* Disable transmitter and interrupt. */
926 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
927 continue;
928
929 reg32 |= 0x3000;
930 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
931
932 /* Set full-duplex, 1000 mbps. */
933 tg3_writephy(tp, MII_BMCR,
934 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
935
936 /* Set to master mode. */
937 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
938 continue;
939
940 tg3_writephy(tp, MII_TG3_CTRL,
941 (MII_TG3_CTRL_AS_MASTER |
942 MII_TG3_CTRL_ENABLE_AS_MASTER));
943
944 /* Enable SM_DSP_CLOCK and 6dB. */
945 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
946
947 /* Block the PHY control access. */
948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
950
951 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
952 if (!err)
953 break;
954 } while (--retries);
955
956 err = tg3_phy_reset_chanpat(tp);
957 if (err)
958 return err;
959
960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
962
963 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
964 tg3_writephy(tp, 0x16, 0x0000);
965
966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
968 /* Set Extended packet length bit for jumbo frames */
969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
970 }
971 else {
972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
973 }
974
975 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
976
977 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
978 reg32 &= ~0x3000;
979 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
980 } else if (!err)
981 err = -EBUSY;
982
983 return err;
984 }
985
986 static void tg3_link_report(struct tg3 *);
987
988 /* This will reset the tigon3 PHY if there is no valid
989 * link unless the FORCE argument is non-zero.
990 */
991 static int tg3_phy_reset(struct tg3 *tp)
992 {
993 u32 phy_status;
994 int err;
995
996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
997 u32 val;
998
999 val = tr32(GRC_MISC_CFG);
1000 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1001 udelay(40);
1002 }
1003 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1004 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1005 if (err != 0)
1006 return -EBUSY;
1007
1008 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1009 netif_carrier_off(tp->dev);
1010 tg3_link_report(tp);
1011 }
1012
1013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1016 err = tg3_phy_reset_5703_4_5(tp);
1017 if (err)
1018 return err;
1019 goto out;
1020 }
1021
1022 err = tg3_bmcr_reset(tp);
1023 if (err)
1024 return err;
1025
1026 out:
1027 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1028 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1032 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1034 }
1035 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1036 tg3_writephy(tp, 0x1c, 0x8d68);
1037 tg3_writephy(tp, 0x1c, 0x8d68);
1038 }
1039 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1040 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1041 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1042 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1044 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1045 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1046 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1047 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1048 }
1049 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1050 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1051 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1052 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1053 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1054 tg3_writephy(tp, MII_TG3_TEST1,
1055 MII_TG3_TEST1_TRIM_EN | 0x4);
1056 } else
1057 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1058 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1059 }
1060 /* Set Extended packet length bit (bit 14) on all chips that */
1061 /* support jumbo frames */
1062 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1063 /* Cannot do read-modify-write on 5401 */
1064 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1065 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1066 u32 phy_reg;
1067
1068 /* Set bit 14 with read-modify-write to preserve other bits */
1069 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1070 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1071 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1072 }
1073
1074 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1075 * jumbo frames transmission.
1076 */
1077 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1078 u32 phy_reg;
1079
1080 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1081 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1082 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1083 }
1084
1085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1086 /* adjust output voltage */
1087 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1088 }
1089
1090 tg3_phy_toggle_automdix(tp, 1);
1091 tg3_phy_set_wirespeed(tp);
1092 return 0;
1093 }
1094
1095 static void tg3_frob_aux_power(struct tg3 *tp)
1096 {
1097 struct tg3 *tp_peer = tp;
1098
1099 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1100 return;
1101
1102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1103 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1104 struct net_device *dev_peer;
1105
1106 dev_peer = pci_get_drvdata(tp->pdev_peer);
1107 /* remove_one() may have been run on the peer. */
1108 if (!dev_peer)
1109 tp_peer = tp;
1110 else
1111 tp_peer = netdev_priv(dev_peer);
1112 }
1113
1114 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1115 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1116 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1117 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1121 (GRC_LCLCTRL_GPIO_OE0 |
1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT0 |
1125 GRC_LCLCTRL_GPIO_OUTPUT1),
1126 100);
1127 } else {
1128 u32 no_gpio2;
1129 u32 grc_local_ctrl = 0;
1130
1131 if (tp_peer != tp &&
1132 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1133 return;
1134
1135 /* Workaround to prevent overdrawing Amps. */
1136 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1137 ASIC_REV_5714) {
1138 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140 grc_local_ctrl, 100);
1141 }
1142
1143 /* On 5753 and variants, GPIO2 cannot be used. */
1144 no_gpio2 = tp->nic_sram_data_cfg &
1145 NIC_SRAM_DATA_CFG_NO_GPIO2;
1146
1147 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1148 GRC_LCLCTRL_GPIO_OE1 |
1149 GRC_LCLCTRL_GPIO_OE2 |
1150 GRC_LCLCTRL_GPIO_OUTPUT1 |
1151 GRC_LCLCTRL_GPIO_OUTPUT2;
1152 if (no_gpio2) {
1153 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1154 GRC_LCLCTRL_GPIO_OUTPUT2);
1155 }
1156 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157 grc_local_ctrl, 100);
1158
1159 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1160
1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1162 grc_local_ctrl, 100);
1163
1164 if (!no_gpio2) {
1165 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1166 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1167 grc_local_ctrl, 100);
1168 }
1169 }
1170 } else {
1171 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1172 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1173 if (tp_peer != tp &&
1174 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1175 return;
1176
1177 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1178 (GRC_LCLCTRL_GPIO_OE1 |
1179 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1180
1181 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1182 GRC_LCLCTRL_GPIO_OE1, 100);
1183
1184 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1185 (GRC_LCLCTRL_GPIO_OE1 |
1186 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1187 }
1188 }
1189 }
1190
1191 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1192 {
1193 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1194 return 1;
1195 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1196 if (speed != SPEED_10)
1197 return 1;
1198 } else if (speed == SPEED_10)
1199 return 1;
1200
1201 return 0;
1202 }
1203
1204 static int tg3_setup_phy(struct tg3 *, int);
1205
1206 #define RESET_KIND_SHUTDOWN 0
1207 #define RESET_KIND_INIT 1
1208 #define RESET_KIND_SUSPEND 2
1209
1210 static void tg3_write_sig_post_reset(struct tg3 *, int);
1211 static int tg3_halt_cpu(struct tg3 *, u32);
1212 static int tg3_nvram_lock(struct tg3 *);
1213 static void tg3_nvram_unlock(struct tg3 *);
1214
1215 static void tg3_power_down_phy(struct tg3 *tp)
1216 {
1217 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1219 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1220 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1221
1222 sg_dig_ctrl |=
1223 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1224 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1225 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1226 }
1227 return;
1228 }
1229
1230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1231 u32 val;
1232
1233 tg3_bmcr_reset(tp);
1234 val = tr32(GRC_MISC_CFG);
1235 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1236 udelay(40);
1237 return;
1238 } else {
1239 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1240 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1241 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1242 }
1243
1244 /* The PHY should not be powered down on some chips because
1245 * of bugs.
1246 */
1247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1249 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1250 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1251 return;
1252 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1253 }
1254
1255 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1256 {
1257 u32 misc_host_ctrl;
1258 u16 power_control, power_caps;
1259 int pm = tp->pm_cap;
1260
1261 /* Make sure register accesses (indirect or otherwise)
1262 * will function correctly.
1263 */
1264 pci_write_config_dword(tp->pdev,
1265 TG3PCI_MISC_HOST_CTRL,
1266 tp->misc_host_ctrl);
1267
1268 pci_read_config_word(tp->pdev,
1269 pm + PCI_PM_CTRL,
1270 &power_control);
1271 power_control |= PCI_PM_CTRL_PME_STATUS;
1272 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1273 switch (state) {
1274 case PCI_D0:
1275 power_control |= 0;
1276 pci_write_config_word(tp->pdev,
1277 pm + PCI_PM_CTRL,
1278 power_control);
1279 udelay(100); /* Delay after power state change */
1280
1281 /* Switch out of Vaux if it is a NIC */
1282 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1283 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1284
1285 return 0;
1286
1287 case PCI_D1:
1288 power_control |= 1;
1289 break;
1290
1291 case PCI_D2:
1292 power_control |= 2;
1293 break;
1294
1295 case PCI_D3hot:
1296 power_control |= 3;
1297 break;
1298
1299 default:
1300 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1301 "requested.\n",
1302 tp->dev->name, state);
1303 return -EINVAL;
1304 };
1305
1306 power_control |= PCI_PM_CTRL_PME_ENABLE;
1307
1308 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1309 tw32(TG3PCI_MISC_HOST_CTRL,
1310 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1311
1312 if (tp->link_config.phy_is_low_power == 0) {
1313 tp->link_config.phy_is_low_power = 1;
1314 tp->link_config.orig_speed = tp->link_config.speed;
1315 tp->link_config.orig_duplex = tp->link_config.duplex;
1316 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1317 }
1318
1319 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1320 tp->link_config.speed = SPEED_10;
1321 tp->link_config.duplex = DUPLEX_HALF;
1322 tp->link_config.autoneg = AUTONEG_ENABLE;
1323 tg3_setup_phy(tp, 0);
1324 }
1325
1326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1327 u32 val;
1328
1329 val = tr32(GRC_VCPU_EXT_CTRL);
1330 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1331 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1332 int i;
1333 u32 val;
1334
1335 for (i = 0; i < 200; i++) {
1336 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1337 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1338 break;
1339 msleep(1);
1340 }
1341 }
1342 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1343 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1344 WOL_DRV_STATE_SHUTDOWN |
1345 WOL_DRV_WOL |
1346 WOL_SET_MAGIC_PKT);
1347
1348 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1349
1350 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1351 u32 mac_mode;
1352
1353 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1354 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1355 udelay(40);
1356
1357 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1358 mac_mode = MAC_MODE_PORT_MODE_GMII;
1359 else
1360 mac_mode = MAC_MODE_PORT_MODE_MII;
1361
1362 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1363 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1364 ASIC_REV_5700) {
1365 u32 speed = (tp->tg3_flags &
1366 TG3_FLAG_WOL_SPEED_100MB) ?
1367 SPEED_100 : SPEED_10;
1368 if (tg3_5700_link_polarity(tp, speed))
1369 mac_mode |= MAC_MODE_LINK_POLARITY;
1370 else
1371 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1372 }
1373 } else {
1374 mac_mode = MAC_MODE_PORT_MODE_TBI;
1375 }
1376
1377 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1378 tw32(MAC_LED_CTRL, tp->led_ctrl);
1379
1380 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1381 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1382 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1383
1384 tw32_f(MAC_MODE, mac_mode);
1385 udelay(100);
1386
1387 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1388 udelay(10);
1389 }
1390
1391 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1392 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1393 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1394 u32 base_val;
1395
1396 base_val = tp->pci_clock_ctrl;
1397 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1398 CLOCK_CTRL_TXCLK_DISABLE);
1399
1400 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1401 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1402 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1403 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1404 /* do nothing */
1405 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1406 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1407 u32 newbits1, newbits2;
1408
1409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1411 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1412 CLOCK_CTRL_TXCLK_DISABLE |
1413 CLOCK_CTRL_ALTCLK);
1414 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1415 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1416 newbits1 = CLOCK_CTRL_625_CORE;
1417 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1418 } else {
1419 newbits1 = CLOCK_CTRL_ALTCLK;
1420 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1421 }
1422
1423 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1424 40);
1425
1426 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1427 40);
1428
1429 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1430 u32 newbits3;
1431
1432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1434 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1435 CLOCK_CTRL_TXCLK_DISABLE |
1436 CLOCK_CTRL_44MHZ_CORE);
1437 } else {
1438 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1439 }
1440
1441 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1442 tp->pci_clock_ctrl | newbits3, 40);
1443 }
1444 }
1445
1446 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1447 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1448 tg3_power_down_phy(tp);
1449
1450 tg3_frob_aux_power(tp);
1451
1452 /* Workaround for unstable PLL clock */
1453 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1454 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1455 u32 val = tr32(0x7d00);
1456
1457 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1458 tw32(0x7d00, val);
1459 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1460 int err;
1461
1462 err = tg3_nvram_lock(tp);
1463 tg3_halt_cpu(tp, RX_CPU_BASE);
1464 if (!err)
1465 tg3_nvram_unlock(tp);
1466 }
1467 }
1468
1469 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1470
1471 /* Finally, set the new power state. */
1472 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1473 udelay(100); /* Delay after power state change */
1474
1475 return 0;
1476 }
1477
1478 static void tg3_link_report(struct tg3 *tp)
1479 {
1480 if (!netif_carrier_ok(tp->dev)) {
1481 if (netif_msg_link(tp))
1482 printk(KERN_INFO PFX "%s: Link is down.\n",
1483 tp->dev->name);
1484 } else if (netif_msg_link(tp)) {
1485 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1486 tp->dev->name,
1487 (tp->link_config.active_speed == SPEED_1000 ?
1488 1000 :
1489 (tp->link_config.active_speed == SPEED_100 ?
1490 100 : 10)),
1491 (tp->link_config.active_duplex == DUPLEX_FULL ?
1492 "full" : "half"));
1493
1494 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1495 "%s for RX.\n",
1496 tp->dev->name,
1497 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1498 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1499 }
1500 }
1501
1502 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1503 {
1504 u32 new_tg3_flags = 0;
1505 u32 old_rx_mode = tp->rx_mode;
1506 u32 old_tx_mode = tp->tx_mode;
1507
1508 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1509
1510 /* Convert 1000BaseX flow control bits to 1000BaseT
1511 * bits before resolving flow control.
1512 */
1513 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1514 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1515 ADVERTISE_PAUSE_ASYM);
1516 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1517
1518 if (local_adv & ADVERTISE_1000XPAUSE)
1519 local_adv |= ADVERTISE_PAUSE_CAP;
1520 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1521 local_adv |= ADVERTISE_PAUSE_ASYM;
1522 if (remote_adv & LPA_1000XPAUSE)
1523 remote_adv |= LPA_PAUSE_CAP;
1524 if (remote_adv & LPA_1000XPAUSE_ASYM)
1525 remote_adv |= LPA_PAUSE_ASYM;
1526 }
1527
1528 if (local_adv & ADVERTISE_PAUSE_CAP) {
1529 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1530 if (remote_adv & LPA_PAUSE_CAP)
1531 new_tg3_flags |=
1532 (TG3_FLAG_RX_PAUSE |
1533 TG3_FLAG_TX_PAUSE);
1534 else if (remote_adv & LPA_PAUSE_ASYM)
1535 new_tg3_flags |=
1536 (TG3_FLAG_RX_PAUSE);
1537 } else {
1538 if (remote_adv & LPA_PAUSE_CAP)
1539 new_tg3_flags |=
1540 (TG3_FLAG_RX_PAUSE |
1541 TG3_FLAG_TX_PAUSE);
1542 }
1543 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1544 if ((remote_adv & LPA_PAUSE_CAP) &&
1545 (remote_adv & LPA_PAUSE_ASYM))
1546 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1547 }
1548
1549 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1550 tp->tg3_flags |= new_tg3_flags;
1551 } else {
1552 new_tg3_flags = tp->tg3_flags;
1553 }
1554
1555 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1556 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1557 else
1558 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1559
1560 if (old_rx_mode != tp->rx_mode) {
1561 tw32_f(MAC_RX_MODE, tp->rx_mode);
1562 }
1563
1564 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1565 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1566 else
1567 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1568
1569 if (old_tx_mode != tp->tx_mode) {
1570 tw32_f(MAC_TX_MODE, tp->tx_mode);
1571 }
1572 }
1573
1574 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1575 {
1576 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1577 case MII_TG3_AUX_STAT_10HALF:
1578 *speed = SPEED_10;
1579 *duplex = DUPLEX_HALF;
1580 break;
1581
1582 case MII_TG3_AUX_STAT_10FULL:
1583 *speed = SPEED_10;
1584 *duplex = DUPLEX_FULL;
1585 break;
1586
1587 case MII_TG3_AUX_STAT_100HALF:
1588 *speed = SPEED_100;
1589 *duplex = DUPLEX_HALF;
1590 break;
1591
1592 case MII_TG3_AUX_STAT_100FULL:
1593 *speed = SPEED_100;
1594 *duplex = DUPLEX_FULL;
1595 break;
1596
1597 case MII_TG3_AUX_STAT_1000HALF:
1598 *speed = SPEED_1000;
1599 *duplex = DUPLEX_HALF;
1600 break;
1601
1602 case MII_TG3_AUX_STAT_1000FULL:
1603 *speed = SPEED_1000;
1604 *duplex = DUPLEX_FULL;
1605 break;
1606
1607 default:
1608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1609 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1610 SPEED_10;
1611 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1612 DUPLEX_HALF;
1613 break;
1614 }
1615 *speed = SPEED_INVALID;
1616 *duplex = DUPLEX_INVALID;
1617 break;
1618 };
1619 }
1620
1621 static void tg3_phy_copper_begin(struct tg3 *tp)
1622 {
1623 u32 new_adv;
1624 int i;
1625
1626 if (tp->link_config.phy_is_low_power) {
1627 /* Entering low power mode. Disable gigabit and
1628 * 100baseT advertisements.
1629 */
1630 tg3_writephy(tp, MII_TG3_CTRL, 0);
1631
1632 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1633 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1634 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1635 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1636
1637 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1638 } else if (tp->link_config.speed == SPEED_INVALID) {
1639 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1640 tp->link_config.advertising &=
1641 ~(ADVERTISED_1000baseT_Half |
1642 ADVERTISED_1000baseT_Full);
1643
1644 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1645 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1646 new_adv |= ADVERTISE_10HALF;
1647 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1648 new_adv |= ADVERTISE_10FULL;
1649 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1650 new_adv |= ADVERTISE_100HALF;
1651 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1652 new_adv |= ADVERTISE_100FULL;
1653 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1654
1655 if (tp->link_config.advertising &
1656 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1657 new_adv = 0;
1658 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1659 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1660 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1661 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1662 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1663 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1664 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1665 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1666 MII_TG3_CTRL_ENABLE_AS_MASTER);
1667 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1668 } else {
1669 tg3_writephy(tp, MII_TG3_CTRL, 0);
1670 }
1671 } else {
1672 /* Asking for a specific link mode. */
1673 if (tp->link_config.speed == SPEED_1000) {
1674 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1675 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1676
1677 if (tp->link_config.duplex == DUPLEX_FULL)
1678 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1679 else
1680 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1681 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1682 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1683 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1684 MII_TG3_CTRL_ENABLE_AS_MASTER);
1685 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1686 } else {
1687 tg3_writephy(tp, MII_TG3_CTRL, 0);
1688
1689 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1690 if (tp->link_config.speed == SPEED_100) {
1691 if (tp->link_config.duplex == DUPLEX_FULL)
1692 new_adv |= ADVERTISE_100FULL;
1693 else
1694 new_adv |= ADVERTISE_100HALF;
1695 } else {
1696 if (tp->link_config.duplex == DUPLEX_FULL)
1697 new_adv |= ADVERTISE_10FULL;
1698 else
1699 new_adv |= ADVERTISE_10HALF;
1700 }
1701 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1702 }
1703 }
1704
1705 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1706 tp->link_config.speed != SPEED_INVALID) {
1707 u32 bmcr, orig_bmcr;
1708
1709 tp->link_config.active_speed = tp->link_config.speed;
1710 tp->link_config.active_duplex = tp->link_config.duplex;
1711
1712 bmcr = 0;
1713 switch (tp->link_config.speed) {
1714 default:
1715 case SPEED_10:
1716 break;
1717
1718 case SPEED_100:
1719 bmcr |= BMCR_SPEED100;
1720 break;
1721
1722 case SPEED_1000:
1723 bmcr |= TG3_BMCR_SPEED1000;
1724 break;
1725 };
1726
1727 if (tp->link_config.duplex == DUPLEX_FULL)
1728 bmcr |= BMCR_FULLDPLX;
1729
1730 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1731 (bmcr != orig_bmcr)) {
1732 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1733 for (i = 0; i < 1500; i++) {
1734 u32 tmp;
1735
1736 udelay(10);
1737 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1738 tg3_readphy(tp, MII_BMSR, &tmp))
1739 continue;
1740 if (!(tmp & BMSR_LSTATUS)) {
1741 udelay(40);
1742 break;
1743 }
1744 }
1745 tg3_writephy(tp, MII_BMCR, bmcr);
1746 udelay(40);
1747 }
1748 } else {
1749 tg3_writephy(tp, MII_BMCR,
1750 BMCR_ANENABLE | BMCR_ANRESTART);
1751 }
1752 }
1753
1754 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1755 {
1756 int err;
1757
1758 /* Turn off tap power management. */
1759 /* Set Extended packet length bit */
1760 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1761
1762 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1763 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1764
1765 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1766 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1767
1768 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1769 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1770
1771 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1772 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1773
1774 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1775 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1776
1777 udelay(40);
1778
1779 return err;
1780 }
1781
1782 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1783 {
1784 u32 adv_reg, all_mask = 0;
1785
1786 if (mask & ADVERTISED_10baseT_Half)
1787 all_mask |= ADVERTISE_10HALF;
1788 if (mask & ADVERTISED_10baseT_Full)
1789 all_mask |= ADVERTISE_10FULL;
1790 if (mask & ADVERTISED_100baseT_Half)
1791 all_mask |= ADVERTISE_100HALF;
1792 if (mask & ADVERTISED_100baseT_Full)
1793 all_mask |= ADVERTISE_100FULL;
1794
1795 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1796 return 0;
1797
1798 if ((adv_reg & all_mask) != all_mask)
1799 return 0;
1800 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1801 u32 tg3_ctrl;
1802
1803 all_mask = 0;
1804 if (mask & ADVERTISED_1000baseT_Half)
1805 all_mask |= ADVERTISE_1000HALF;
1806 if (mask & ADVERTISED_1000baseT_Full)
1807 all_mask |= ADVERTISE_1000FULL;
1808
1809 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1810 return 0;
1811
1812 if ((tg3_ctrl & all_mask) != all_mask)
1813 return 0;
1814 }
1815 return 1;
1816 }
1817
1818 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1819 {
1820 int current_link_up;
1821 u32 bmsr, dummy;
1822 u16 current_speed;
1823 u8 current_duplex;
1824 int i, err;
1825
1826 tw32(MAC_EVENT, 0);
1827
1828 tw32_f(MAC_STATUS,
1829 (MAC_STATUS_SYNC_CHANGED |
1830 MAC_STATUS_CFG_CHANGED |
1831 MAC_STATUS_MI_COMPLETION |
1832 MAC_STATUS_LNKSTATE_CHANGED));
1833 udelay(40);
1834
1835 tp->mi_mode = MAC_MI_MODE_BASE;
1836 tw32_f(MAC_MI_MODE, tp->mi_mode);
1837 udelay(80);
1838
1839 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1840
1841 /* Some third-party PHYs need to be reset on link going
1842 * down.
1843 */
1844 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1847 netif_carrier_ok(tp->dev)) {
1848 tg3_readphy(tp, MII_BMSR, &bmsr);
1849 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850 !(bmsr & BMSR_LSTATUS))
1851 force_reset = 1;
1852 }
1853 if (force_reset)
1854 tg3_phy_reset(tp);
1855
1856 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1857 tg3_readphy(tp, MII_BMSR, &bmsr);
1858 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1859 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1860 bmsr = 0;
1861
1862 if (!(bmsr & BMSR_LSTATUS)) {
1863 err = tg3_init_5401phy_dsp(tp);
1864 if (err)
1865 return err;
1866
1867 tg3_readphy(tp, MII_BMSR, &bmsr);
1868 for (i = 0; i < 1000; i++) {
1869 udelay(10);
1870 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1871 (bmsr & BMSR_LSTATUS)) {
1872 udelay(40);
1873 break;
1874 }
1875 }
1876
1877 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1878 !(bmsr & BMSR_LSTATUS) &&
1879 tp->link_config.active_speed == SPEED_1000) {
1880 err = tg3_phy_reset(tp);
1881 if (!err)
1882 err = tg3_init_5401phy_dsp(tp);
1883 if (err)
1884 return err;
1885 }
1886 }
1887 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1888 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1889 /* 5701 {A0,B0} CRC bug workaround */
1890 tg3_writephy(tp, 0x15, 0x0a75);
1891 tg3_writephy(tp, 0x1c, 0x8c68);
1892 tg3_writephy(tp, 0x1c, 0x8d68);
1893 tg3_writephy(tp, 0x1c, 0x8c68);
1894 }
1895
1896 /* Clear pending interrupts... */
1897 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1898 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1899
1900 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1901 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1902 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1903 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1904
1905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1907 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1908 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1909 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1910 else
1911 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1912 }
1913
1914 current_link_up = 0;
1915 current_speed = SPEED_INVALID;
1916 current_duplex = DUPLEX_INVALID;
1917
1918 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1919 u32 val;
1920
1921 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1922 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1923 if (!(val & (1 << 10))) {
1924 val |= (1 << 10);
1925 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1926 goto relink;
1927 }
1928 }
1929
1930 bmsr = 0;
1931 for (i = 0; i < 100; i++) {
1932 tg3_readphy(tp, MII_BMSR, &bmsr);
1933 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1934 (bmsr & BMSR_LSTATUS))
1935 break;
1936 udelay(40);
1937 }
1938
1939 if (bmsr & BMSR_LSTATUS) {
1940 u32 aux_stat, bmcr;
1941
1942 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1943 for (i = 0; i < 2000; i++) {
1944 udelay(10);
1945 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1946 aux_stat)
1947 break;
1948 }
1949
1950 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1951 &current_speed,
1952 &current_duplex);
1953
1954 bmcr = 0;
1955 for (i = 0; i < 200; i++) {
1956 tg3_readphy(tp, MII_BMCR, &bmcr);
1957 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1958 continue;
1959 if (bmcr && bmcr != 0x7fff)
1960 break;
1961 udelay(10);
1962 }
1963
1964 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1965 if (bmcr & BMCR_ANENABLE) {
1966 current_link_up = 1;
1967
1968 /* Force autoneg restart if we are exiting
1969 * low power mode.
1970 */
1971 if (!tg3_copper_is_advertising_all(tp,
1972 tp->link_config.advertising))
1973 current_link_up = 0;
1974 } else {
1975 current_link_up = 0;
1976 }
1977 } else {
1978 if (!(bmcr & BMCR_ANENABLE) &&
1979 tp->link_config.speed == current_speed &&
1980 tp->link_config.duplex == current_duplex) {
1981 current_link_up = 1;
1982 } else {
1983 current_link_up = 0;
1984 }
1985 }
1986
1987 tp->link_config.active_speed = current_speed;
1988 tp->link_config.active_duplex = current_duplex;
1989 }
1990
1991 if (current_link_up == 1 &&
1992 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1993 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1994 u32 local_adv, remote_adv;
1995
1996 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1997 local_adv = 0;
1998 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1999
2000 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2001 remote_adv = 0;
2002
2003 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2004
2005 /* If we are not advertising full pause capability,
2006 * something is wrong. Bring the link down and reconfigure.
2007 */
2008 if (local_adv != ADVERTISE_PAUSE_CAP) {
2009 current_link_up = 0;
2010 } else {
2011 tg3_setup_flow_control(tp, local_adv, remote_adv);
2012 }
2013 }
2014 relink:
2015 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2016 u32 tmp;
2017
2018 tg3_phy_copper_begin(tp);
2019
2020 tg3_readphy(tp, MII_BMSR, &tmp);
2021 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2022 (tmp & BMSR_LSTATUS))
2023 current_link_up = 1;
2024 }
2025
2026 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2027 if (current_link_up == 1) {
2028 if (tp->link_config.active_speed == SPEED_100 ||
2029 tp->link_config.active_speed == SPEED_10)
2030 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2031 else
2032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2033 } else
2034 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2035
2036 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2037 if (tp->link_config.active_duplex == DUPLEX_HALF)
2038 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2039
2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2041 if (current_link_up == 1 &&
2042 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2043 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2044 else
2045 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2046 }
2047
2048 /* ??? Without this setting Netgear GA302T PHY does not
2049 * ??? send/receive packets...
2050 */
2051 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2052 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2053 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2054 tw32_f(MAC_MI_MODE, tp->mi_mode);
2055 udelay(80);
2056 }
2057
2058 tw32_f(MAC_MODE, tp->mac_mode);
2059 udelay(40);
2060
2061 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2062 /* Polled via timer. */
2063 tw32_f(MAC_EVENT, 0);
2064 } else {
2065 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2066 }
2067 udelay(40);
2068
2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2070 current_link_up == 1 &&
2071 tp->link_config.active_speed == SPEED_1000 &&
2072 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2073 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2074 udelay(120);
2075 tw32_f(MAC_STATUS,
2076 (MAC_STATUS_SYNC_CHANGED |
2077 MAC_STATUS_CFG_CHANGED));
2078 udelay(40);
2079 tg3_write_mem(tp,
2080 NIC_SRAM_FIRMWARE_MBOX,
2081 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2082 }
2083
2084 if (current_link_up != netif_carrier_ok(tp->dev)) {
2085 if (current_link_up)
2086 netif_carrier_on(tp->dev);
2087 else
2088 netif_carrier_off(tp->dev);
2089 tg3_link_report(tp);
2090 }
2091
2092 return 0;
2093 }
2094
2095 struct tg3_fiber_aneginfo {
2096 int state;
2097 #define ANEG_STATE_UNKNOWN 0
2098 #define ANEG_STATE_AN_ENABLE 1
2099 #define ANEG_STATE_RESTART_INIT 2
2100 #define ANEG_STATE_RESTART 3
2101 #define ANEG_STATE_DISABLE_LINK_OK 4
2102 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2103 #define ANEG_STATE_ABILITY_DETECT 6
2104 #define ANEG_STATE_ACK_DETECT_INIT 7
2105 #define ANEG_STATE_ACK_DETECT 8
2106 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2107 #define ANEG_STATE_COMPLETE_ACK 10
2108 #define ANEG_STATE_IDLE_DETECT_INIT 11
2109 #define ANEG_STATE_IDLE_DETECT 12
2110 #define ANEG_STATE_LINK_OK 13
2111 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2112 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2113
2114 u32 flags;
2115 #define MR_AN_ENABLE 0x00000001
2116 #define MR_RESTART_AN 0x00000002
2117 #define MR_AN_COMPLETE 0x00000004
2118 #define MR_PAGE_RX 0x00000008
2119 #define MR_NP_LOADED 0x00000010
2120 #define MR_TOGGLE_TX 0x00000020
2121 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2122 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2123 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2124 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2125 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2126 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2127 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2128 #define MR_TOGGLE_RX 0x00002000
2129 #define MR_NP_RX 0x00004000
2130
2131 #define MR_LINK_OK 0x80000000
2132
2133 unsigned long link_time, cur_time;
2134
2135 u32 ability_match_cfg;
2136 int ability_match_count;
2137
2138 char ability_match, idle_match, ack_match;
2139
2140 u32 txconfig, rxconfig;
2141 #define ANEG_CFG_NP 0x00000080
2142 #define ANEG_CFG_ACK 0x00000040
2143 #define ANEG_CFG_RF2 0x00000020
2144 #define ANEG_CFG_RF1 0x00000010
2145 #define ANEG_CFG_PS2 0x00000001
2146 #define ANEG_CFG_PS1 0x00008000
2147 #define ANEG_CFG_HD 0x00004000
2148 #define ANEG_CFG_FD 0x00002000
2149 #define ANEG_CFG_INVAL 0x00001f06
2150
2151 };
2152 #define ANEG_OK 0
2153 #define ANEG_DONE 1
2154 #define ANEG_TIMER_ENAB 2
2155 #define ANEG_FAILED -1
2156
2157 #define ANEG_STATE_SETTLE_TIME 10000
2158
2159 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2160 struct tg3_fiber_aneginfo *ap)
2161 {
2162 unsigned long delta;
2163 u32 rx_cfg_reg;
2164 int ret;
2165
2166 if (ap->state == ANEG_STATE_UNKNOWN) {
2167 ap->rxconfig = 0;
2168 ap->link_time = 0;
2169 ap->cur_time = 0;
2170 ap->ability_match_cfg = 0;
2171 ap->ability_match_count = 0;
2172 ap->ability_match = 0;
2173 ap->idle_match = 0;
2174 ap->ack_match = 0;
2175 }
2176 ap->cur_time++;
2177
2178 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2179 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2180
2181 if (rx_cfg_reg != ap->ability_match_cfg) {
2182 ap->ability_match_cfg = rx_cfg_reg;
2183 ap->ability_match = 0;
2184 ap->ability_match_count = 0;
2185 } else {
2186 if (++ap->ability_match_count > 1) {
2187 ap->ability_match = 1;
2188 ap->ability_match_cfg = rx_cfg_reg;
2189 }
2190 }
2191 if (rx_cfg_reg & ANEG_CFG_ACK)
2192 ap->ack_match = 1;
2193 else
2194 ap->ack_match = 0;
2195
2196 ap->idle_match = 0;
2197 } else {
2198 ap->idle_match = 1;
2199 ap->ability_match_cfg = 0;
2200 ap->ability_match_count = 0;
2201 ap->ability_match = 0;
2202 ap->ack_match = 0;
2203
2204 rx_cfg_reg = 0;
2205 }
2206
2207 ap->rxconfig = rx_cfg_reg;
2208 ret = ANEG_OK;
2209
2210 switch(ap->state) {
2211 case ANEG_STATE_UNKNOWN:
2212 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2213 ap->state = ANEG_STATE_AN_ENABLE;
2214
2215 /* fallthru */
2216 case ANEG_STATE_AN_ENABLE:
2217 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2218 if (ap->flags & MR_AN_ENABLE) {
2219 ap->link_time = 0;
2220 ap->cur_time = 0;
2221 ap->ability_match_cfg = 0;
2222 ap->ability_match_count = 0;
2223 ap->ability_match = 0;
2224 ap->idle_match = 0;
2225 ap->ack_match = 0;
2226
2227 ap->state = ANEG_STATE_RESTART_INIT;
2228 } else {
2229 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2230 }
2231 break;
2232
2233 case ANEG_STATE_RESTART_INIT:
2234 ap->link_time = ap->cur_time;
2235 ap->flags &= ~(MR_NP_LOADED);
2236 ap->txconfig = 0;
2237 tw32(MAC_TX_AUTO_NEG, 0);
2238 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2239 tw32_f(MAC_MODE, tp->mac_mode);
2240 udelay(40);
2241
2242 ret = ANEG_TIMER_ENAB;
2243 ap->state = ANEG_STATE_RESTART;
2244
2245 /* fallthru */
2246 case ANEG_STATE_RESTART:
2247 delta = ap->cur_time - ap->link_time;
2248 if (delta > ANEG_STATE_SETTLE_TIME) {
2249 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2250 } else {
2251 ret = ANEG_TIMER_ENAB;
2252 }
2253 break;
2254
2255 case ANEG_STATE_DISABLE_LINK_OK:
2256 ret = ANEG_DONE;
2257 break;
2258
2259 case ANEG_STATE_ABILITY_DETECT_INIT:
2260 ap->flags &= ~(MR_TOGGLE_TX);
2261 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2262 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2263 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2264 tw32_f(MAC_MODE, tp->mac_mode);
2265 udelay(40);
2266
2267 ap->state = ANEG_STATE_ABILITY_DETECT;
2268 break;
2269
2270 case ANEG_STATE_ABILITY_DETECT:
2271 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2272 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2273 }
2274 break;
2275
2276 case ANEG_STATE_ACK_DETECT_INIT:
2277 ap->txconfig |= ANEG_CFG_ACK;
2278 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2279 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2280 tw32_f(MAC_MODE, tp->mac_mode);
2281 udelay(40);
2282
2283 ap->state = ANEG_STATE_ACK_DETECT;
2284
2285 /* fallthru */
2286 case ANEG_STATE_ACK_DETECT:
2287 if (ap->ack_match != 0) {
2288 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2289 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2290 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2291 } else {
2292 ap->state = ANEG_STATE_AN_ENABLE;
2293 }
2294 } else if (ap->ability_match != 0 &&
2295 ap->rxconfig == 0) {
2296 ap->state = ANEG_STATE_AN_ENABLE;
2297 }
2298 break;
2299
2300 case ANEG_STATE_COMPLETE_ACK_INIT:
2301 if (ap->rxconfig & ANEG_CFG_INVAL) {
2302 ret = ANEG_FAILED;
2303 break;
2304 }
2305 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2306 MR_LP_ADV_HALF_DUPLEX |
2307 MR_LP_ADV_SYM_PAUSE |
2308 MR_LP_ADV_ASYM_PAUSE |
2309 MR_LP_ADV_REMOTE_FAULT1 |
2310 MR_LP_ADV_REMOTE_FAULT2 |
2311 MR_LP_ADV_NEXT_PAGE |
2312 MR_TOGGLE_RX |
2313 MR_NP_RX);
2314 if (ap->rxconfig & ANEG_CFG_FD)
2315 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2316 if (ap->rxconfig & ANEG_CFG_HD)
2317 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2318 if (ap->rxconfig & ANEG_CFG_PS1)
2319 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2320 if (ap->rxconfig & ANEG_CFG_PS2)
2321 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2322 if (ap->rxconfig & ANEG_CFG_RF1)
2323 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2324 if (ap->rxconfig & ANEG_CFG_RF2)
2325 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2326 if (ap->rxconfig & ANEG_CFG_NP)
2327 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2328
2329 ap->link_time = ap->cur_time;
2330
2331 ap->flags ^= (MR_TOGGLE_TX);
2332 if (ap->rxconfig & 0x0008)
2333 ap->flags |= MR_TOGGLE_RX;
2334 if (ap->rxconfig & ANEG_CFG_NP)
2335 ap->flags |= MR_NP_RX;
2336 ap->flags |= MR_PAGE_RX;
2337
2338 ap->state = ANEG_STATE_COMPLETE_ACK;
2339 ret = ANEG_TIMER_ENAB;
2340 break;
2341
2342 case ANEG_STATE_COMPLETE_ACK:
2343 if (ap->ability_match != 0 &&
2344 ap->rxconfig == 0) {
2345 ap->state = ANEG_STATE_AN_ENABLE;
2346 break;
2347 }
2348 delta = ap->cur_time - ap->link_time;
2349 if (delta > ANEG_STATE_SETTLE_TIME) {
2350 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2352 } else {
2353 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2354 !(ap->flags & MR_NP_RX)) {
2355 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2356 } else {
2357 ret = ANEG_FAILED;
2358 }
2359 }
2360 }
2361 break;
2362
2363 case ANEG_STATE_IDLE_DETECT_INIT:
2364 ap->link_time = ap->cur_time;
2365 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2366 tw32_f(MAC_MODE, tp->mac_mode);
2367 udelay(40);
2368
2369 ap->state = ANEG_STATE_IDLE_DETECT;
2370 ret = ANEG_TIMER_ENAB;
2371 break;
2372
2373 case ANEG_STATE_IDLE_DETECT:
2374 if (ap->ability_match != 0 &&
2375 ap->rxconfig == 0) {
2376 ap->state = ANEG_STATE_AN_ENABLE;
2377 break;
2378 }
2379 delta = ap->cur_time - ap->link_time;
2380 if (delta > ANEG_STATE_SETTLE_TIME) {
2381 /* XXX another gem from the Broadcom driver :( */
2382 ap->state = ANEG_STATE_LINK_OK;
2383 }
2384 break;
2385
2386 case ANEG_STATE_LINK_OK:
2387 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2388 ret = ANEG_DONE;
2389 break;
2390
2391 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2392 /* ??? unimplemented */
2393 break;
2394
2395 case ANEG_STATE_NEXT_PAGE_WAIT:
2396 /* ??? unimplemented */
2397 break;
2398
2399 default:
2400 ret = ANEG_FAILED;
2401 break;
2402 };
2403
2404 return ret;
2405 }
2406
2407 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2408 {
2409 int res = 0;
2410 struct tg3_fiber_aneginfo aninfo;
2411 int status = ANEG_FAILED;
2412 unsigned int tick;
2413 u32 tmp;
2414
2415 tw32_f(MAC_TX_AUTO_NEG, 0);
2416
2417 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2418 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2419 udelay(40);
2420
2421 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2422 udelay(40);
2423
2424 memset(&aninfo, 0, sizeof(aninfo));
2425 aninfo.flags |= MR_AN_ENABLE;
2426 aninfo.state = ANEG_STATE_UNKNOWN;
2427 aninfo.cur_time = 0;
2428 tick = 0;
2429 while (++tick < 195000) {
2430 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2431 if (status == ANEG_DONE || status == ANEG_FAILED)
2432 break;
2433
2434 udelay(1);
2435 }
2436
2437 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2438 tw32_f(MAC_MODE, tp->mac_mode);
2439 udelay(40);
2440
2441 *flags = aninfo.flags;
2442
2443 if (status == ANEG_DONE &&
2444 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2445 MR_LP_ADV_FULL_DUPLEX)))
2446 res = 1;
2447
2448 return res;
2449 }
2450
2451 static void tg3_init_bcm8002(struct tg3 *tp)
2452 {
2453 u32 mac_status = tr32(MAC_STATUS);
2454 int i;
2455
2456 /* Reset when initting first time or we have a link. */
2457 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2458 !(mac_status & MAC_STATUS_PCS_SYNCED))
2459 return;
2460
2461 /* Set PLL lock range. */
2462 tg3_writephy(tp, 0x16, 0x8007);
2463
2464 /* SW reset */
2465 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2466
2467 /* Wait for reset to complete. */
2468 /* XXX schedule_timeout() ... */
2469 for (i = 0; i < 500; i++)
2470 udelay(10);
2471
2472 /* Config mode; select PMA/Ch 1 regs. */
2473 tg3_writephy(tp, 0x10, 0x8411);
2474
2475 /* Enable auto-lock and comdet, select txclk for tx. */
2476 tg3_writephy(tp, 0x11, 0x0a10);
2477
2478 tg3_writephy(tp, 0x18, 0x00a0);
2479 tg3_writephy(tp, 0x16, 0x41ff);
2480
2481 /* Assert and deassert POR. */
2482 tg3_writephy(tp, 0x13, 0x0400);
2483 udelay(40);
2484 tg3_writephy(tp, 0x13, 0x0000);
2485
2486 tg3_writephy(tp, 0x11, 0x0a50);
2487 udelay(40);
2488 tg3_writephy(tp, 0x11, 0x0a10);
2489
2490 /* Wait for signal to stabilize */
2491 /* XXX schedule_timeout() ... */
2492 for (i = 0; i < 15000; i++)
2493 udelay(10);
2494
2495 /* Deselect the channel register so we can read the PHYID
2496 * later.
2497 */
2498 tg3_writephy(tp, 0x10, 0x8011);
2499 }
2500
2501 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2502 {
2503 u32 sg_dig_ctrl, sg_dig_status;
2504 u32 serdes_cfg, expected_sg_dig_ctrl;
2505 int workaround, port_a;
2506 int current_link_up;
2507
2508 serdes_cfg = 0;
2509 expected_sg_dig_ctrl = 0;
2510 workaround = 0;
2511 port_a = 1;
2512 current_link_up = 0;
2513
2514 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2515 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2516 workaround = 1;
2517 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2518 port_a = 0;
2519
2520 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2521 /* preserve bits 20-23 for voltage regulator */
2522 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2523 }
2524
2525 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2526
2527 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2528 if (sg_dig_ctrl & (1 << 31)) {
2529 if (workaround) {
2530 u32 val = serdes_cfg;
2531
2532 if (port_a)
2533 val |= 0xc010000;
2534 else
2535 val |= 0x4010000;
2536 tw32_f(MAC_SERDES_CFG, val);
2537 }
2538 tw32_f(SG_DIG_CTRL, 0x01388400);
2539 }
2540 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2541 tg3_setup_flow_control(tp, 0, 0);
2542 current_link_up = 1;
2543 }
2544 goto out;
2545 }
2546
2547 /* Want auto-negotiation. */
2548 expected_sg_dig_ctrl = 0x81388400;
2549
2550 /* Pause capability */
2551 expected_sg_dig_ctrl |= (1 << 11);
2552
2553 /* Asymettric pause */
2554 expected_sg_dig_ctrl |= (1 << 12);
2555
2556 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2557 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2558 tp->serdes_counter &&
2559 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2560 MAC_STATUS_RCVD_CFG)) ==
2561 MAC_STATUS_PCS_SYNCED)) {
2562 tp->serdes_counter--;
2563 current_link_up = 1;
2564 goto out;
2565 }
2566 restart_autoneg:
2567 if (workaround)
2568 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2569 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2570 udelay(5);
2571 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2572
2573 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2574 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2575 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2576 MAC_STATUS_SIGNAL_DET)) {
2577 sg_dig_status = tr32(SG_DIG_STATUS);
2578 mac_status = tr32(MAC_STATUS);
2579
2580 if ((sg_dig_status & (1 << 1)) &&
2581 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2582 u32 local_adv, remote_adv;
2583
2584 local_adv = ADVERTISE_PAUSE_CAP;
2585 remote_adv = 0;
2586 if (sg_dig_status & (1 << 19))
2587 remote_adv |= LPA_PAUSE_CAP;
2588 if (sg_dig_status & (1 << 20))
2589 remote_adv |= LPA_PAUSE_ASYM;
2590
2591 tg3_setup_flow_control(tp, local_adv, remote_adv);
2592 current_link_up = 1;
2593 tp->serdes_counter = 0;
2594 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2595 } else if (!(sg_dig_status & (1 << 1))) {
2596 if (tp->serdes_counter)
2597 tp->serdes_counter--;
2598 else {
2599 if (workaround) {
2600 u32 val = serdes_cfg;
2601
2602 if (port_a)
2603 val |= 0xc010000;
2604 else
2605 val |= 0x4010000;
2606
2607 tw32_f(MAC_SERDES_CFG, val);
2608 }
2609
2610 tw32_f(SG_DIG_CTRL, 0x01388400);
2611 udelay(40);
2612
2613 /* Link parallel detection - link is up */
2614 /* only if we have PCS_SYNC and not */
2615 /* receiving config code words */
2616 mac_status = tr32(MAC_STATUS);
2617 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2618 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2619 tg3_setup_flow_control(tp, 0, 0);
2620 current_link_up = 1;
2621 tp->tg3_flags2 |=
2622 TG3_FLG2_PARALLEL_DETECT;
2623 tp->serdes_counter =
2624 SERDES_PARALLEL_DET_TIMEOUT;
2625 } else
2626 goto restart_autoneg;
2627 }
2628 }
2629 } else {
2630 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2631 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2632 }
2633
2634 out:
2635 return current_link_up;
2636 }
2637
2638 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2639 {
2640 int current_link_up = 0;
2641
2642 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2643 goto out;
2644
2645 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2646 u32 flags;
2647 int i;
2648
2649 if (fiber_autoneg(tp, &flags)) {
2650 u32 local_adv, remote_adv;
2651
2652 local_adv = ADVERTISE_PAUSE_CAP;
2653 remote_adv = 0;
2654 if (flags & MR_LP_ADV_SYM_PAUSE)
2655 remote_adv |= LPA_PAUSE_CAP;
2656 if (flags & MR_LP_ADV_ASYM_PAUSE)
2657 remote_adv |= LPA_PAUSE_ASYM;
2658
2659 tg3_setup_flow_control(tp, local_adv, remote_adv);
2660
2661 current_link_up = 1;
2662 }
2663 for (i = 0; i < 30; i++) {
2664 udelay(20);
2665 tw32_f(MAC_STATUS,
2666 (MAC_STATUS_SYNC_CHANGED |
2667 MAC_STATUS_CFG_CHANGED));
2668 udelay(40);
2669 if ((tr32(MAC_STATUS) &
2670 (MAC_STATUS_SYNC_CHANGED |
2671 MAC_STATUS_CFG_CHANGED)) == 0)
2672 break;
2673 }
2674
2675 mac_status = tr32(MAC_STATUS);
2676 if (current_link_up == 0 &&
2677 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2678 !(mac_status & MAC_STATUS_RCVD_CFG))
2679 current_link_up = 1;
2680 } else {
2681 /* Forcing 1000FD link up. */
2682 current_link_up = 1;
2683
2684 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2685 udelay(40);
2686
2687 tw32_f(MAC_MODE, tp->mac_mode);
2688 udelay(40);
2689 }
2690
2691 out:
2692 return current_link_up;
2693 }
2694
2695 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2696 {
2697 u32 orig_pause_cfg;
2698 u16 orig_active_speed;
2699 u8 orig_active_duplex;
2700 u32 mac_status;
2701 int current_link_up;
2702 int i;
2703
2704 orig_pause_cfg =
2705 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2706 TG3_FLAG_TX_PAUSE));
2707 orig_active_speed = tp->link_config.active_speed;
2708 orig_active_duplex = tp->link_config.active_duplex;
2709
2710 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2711 netif_carrier_ok(tp->dev) &&
2712 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2713 mac_status = tr32(MAC_STATUS);
2714 mac_status &= (MAC_STATUS_PCS_SYNCED |
2715 MAC_STATUS_SIGNAL_DET |
2716 MAC_STATUS_CFG_CHANGED |
2717 MAC_STATUS_RCVD_CFG);
2718 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2719 MAC_STATUS_SIGNAL_DET)) {
2720 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2721 MAC_STATUS_CFG_CHANGED));
2722 return 0;
2723 }
2724 }
2725
2726 tw32_f(MAC_TX_AUTO_NEG, 0);
2727
2728 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2729 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2730 tw32_f(MAC_MODE, tp->mac_mode);
2731 udelay(40);
2732
2733 if (tp->phy_id == PHY_ID_BCM8002)
2734 tg3_init_bcm8002(tp);
2735
2736 /* Enable link change event even when serdes polling. */
2737 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2738 udelay(40);
2739
2740 current_link_up = 0;
2741 mac_status = tr32(MAC_STATUS);
2742
2743 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2744 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2745 else
2746 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2747
2748 tp->hw_status->status =
2749 (SD_STATUS_UPDATED |
2750 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2751
2752 for (i = 0; i < 100; i++) {
2753 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2754 MAC_STATUS_CFG_CHANGED));
2755 udelay(5);
2756 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2757 MAC_STATUS_CFG_CHANGED |
2758 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2759 break;
2760 }
2761
2762 mac_status = tr32(MAC_STATUS);
2763 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2764 current_link_up = 0;
2765 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2766 tp->serdes_counter == 0) {
2767 tw32_f(MAC_MODE, (tp->mac_mode |
2768 MAC_MODE_SEND_CONFIGS));
2769 udelay(1);
2770 tw32_f(MAC_MODE, tp->mac_mode);
2771 }
2772 }
2773
2774 if (current_link_up == 1) {
2775 tp->link_config.active_speed = SPEED_1000;
2776 tp->link_config.active_duplex = DUPLEX_FULL;
2777 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2778 LED_CTRL_LNKLED_OVERRIDE |
2779 LED_CTRL_1000MBPS_ON));
2780 } else {
2781 tp->link_config.active_speed = SPEED_INVALID;
2782 tp->link_config.active_duplex = DUPLEX_INVALID;
2783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2784 LED_CTRL_LNKLED_OVERRIDE |
2785 LED_CTRL_TRAFFIC_OVERRIDE));
2786 }
2787
2788 if (current_link_up != netif_carrier_ok(tp->dev)) {
2789 if (current_link_up)
2790 netif_carrier_on(tp->dev);
2791 else
2792 netif_carrier_off(tp->dev);
2793 tg3_link_report(tp);
2794 } else {
2795 u32 now_pause_cfg =
2796 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2797 TG3_FLAG_TX_PAUSE);
2798 if (orig_pause_cfg != now_pause_cfg ||
2799 orig_active_speed != tp->link_config.active_speed ||
2800 orig_active_duplex != tp->link_config.active_duplex)
2801 tg3_link_report(tp);
2802 }
2803
2804 return 0;
2805 }
2806
2807 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2808 {
2809 int current_link_up, err = 0;
2810 u32 bmsr, bmcr;
2811 u16 current_speed;
2812 u8 current_duplex;
2813
2814 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2815 tw32_f(MAC_MODE, tp->mac_mode);
2816 udelay(40);
2817
2818 tw32(MAC_EVENT, 0);
2819
2820 tw32_f(MAC_STATUS,
2821 (MAC_STATUS_SYNC_CHANGED |
2822 MAC_STATUS_CFG_CHANGED |
2823 MAC_STATUS_MI_COMPLETION |
2824 MAC_STATUS_LNKSTATE_CHANGED));
2825 udelay(40);
2826
2827 if (force_reset)
2828 tg3_phy_reset(tp);
2829
2830 current_link_up = 0;
2831 current_speed = SPEED_INVALID;
2832 current_duplex = DUPLEX_INVALID;
2833
2834 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2835 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2837 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2838 bmsr |= BMSR_LSTATUS;
2839 else
2840 bmsr &= ~BMSR_LSTATUS;
2841 }
2842
2843 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2844
2845 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2846 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2847 /* do nothing, just check for link up at the end */
2848 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2849 u32 adv, new_adv;
2850
2851 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2852 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2853 ADVERTISE_1000XPAUSE |
2854 ADVERTISE_1000XPSE_ASYM |
2855 ADVERTISE_SLCT);
2856
2857 /* Always advertise symmetric PAUSE just like copper */
2858 new_adv |= ADVERTISE_1000XPAUSE;
2859
2860 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2861 new_adv |= ADVERTISE_1000XHALF;
2862 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2863 new_adv |= ADVERTISE_1000XFULL;
2864
2865 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2868 tg3_writephy(tp, MII_BMCR, bmcr);
2869
2870 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2871 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2872 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2873
2874 return err;
2875 }
2876 } else {
2877 u32 new_bmcr;
2878
2879 bmcr &= ~BMCR_SPEED1000;
2880 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2881
2882 if (tp->link_config.duplex == DUPLEX_FULL)
2883 new_bmcr |= BMCR_FULLDPLX;
2884
2885 if (new_bmcr != bmcr) {
2886 /* BMCR_SPEED1000 is a reserved bit that needs
2887 * to be set on write.
2888 */
2889 new_bmcr |= BMCR_SPEED1000;
2890
2891 /* Force a linkdown */
2892 if (netif_carrier_ok(tp->dev)) {
2893 u32 adv;
2894
2895 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2896 adv &= ~(ADVERTISE_1000XFULL |
2897 ADVERTISE_1000XHALF |
2898 ADVERTISE_SLCT);
2899 tg3_writephy(tp, MII_ADVERTISE, adv);
2900 tg3_writephy(tp, MII_BMCR, bmcr |
2901 BMCR_ANRESTART |
2902 BMCR_ANENABLE);
2903 udelay(10);
2904 netif_carrier_off(tp->dev);
2905 }
2906 tg3_writephy(tp, MII_BMCR, new_bmcr);
2907 bmcr = new_bmcr;
2908 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2909 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2910 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2911 ASIC_REV_5714) {
2912 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2913 bmsr |= BMSR_LSTATUS;
2914 else
2915 bmsr &= ~BMSR_LSTATUS;
2916 }
2917 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2918 }
2919 }
2920
2921 if (bmsr & BMSR_LSTATUS) {
2922 current_speed = SPEED_1000;
2923 current_link_up = 1;
2924 if (bmcr & BMCR_FULLDPLX)
2925 current_duplex = DUPLEX_FULL;
2926 else
2927 current_duplex = DUPLEX_HALF;
2928
2929 if (bmcr & BMCR_ANENABLE) {
2930 u32 local_adv, remote_adv, common;
2931
2932 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2933 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2934 common = local_adv & remote_adv;
2935 if (common & (ADVERTISE_1000XHALF |
2936 ADVERTISE_1000XFULL)) {
2937 if (common & ADVERTISE_1000XFULL)
2938 current_duplex = DUPLEX_FULL;
2939 else
2940 current_duplex = DUPLEX_HALF;
2941
2942 tg3_setup_flow_control(tp, local_adv,
2943 remote_adv);
2944 }
2945 else
2946 current_link_up = 0;
2947 }
2948 }
2949
2950 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2951 if (tp->link_config.active_duplex == DUPLEX_HALF)
2952 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2953
2954 tw32_f(MAC_MODE, tp->mac_mode);
2955 udelay(40);
2956
2957 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2958
2959 tp->link_config.active_speed = current_speed;
2960 tp->link_config.active_duplex = current_duplex;
2961
2962 if (current_link_up != netif_carrier_ok(tp->dev)) {
2963 if (current_link_up)
2964 netif_carrier_on(tp->dev);
2965 else {
2966 netif_carrier_off(tp->dev);
2967 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2968 }
2969 tg3_link_report(tp);
2970 }
2971 return err;
2972 }
2973
2974 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2975 {
2976 if (tp->serdes_counter) {
2977 /* Give autoneg time to complete. */
2978 tp->serdes_counter--;
2979 return;
2980 }
2981 if (!netif_carrier_ok(tp->dev) &&
2982 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2983 u32 bmcr;
2984
2985 tg3_readphy(tp, MII_BMCR, &bmcr);
2986 if (bmcr & BMCR_ANENABLE) {
2987 u32 phy1, phy2;
2988
2989 /* Select shadow register 0x1f */
2990 tg3_writephy(tp, 0x1c, 0x7c00);
2991 tg3_readphy(tp, 0x1c, &phy1);
2992
2993 /* Select expansion interrupt status register */
2994 tg3_writephy(tp, 0x17, 0x0f01);
2995 tg3_readphy(tp, 0x15, &phy2);
2996 tg3_readphy(tp, 0x15, &phy2);
2997
2998 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2999 /* We have signal detect and not receiving
3000 * config code words, link is up by parallel
3001 * detection.
3002 */
3003
3004 bmcr &= ~BMCR_ANENABLE;
3005 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3006 tg3_writephy(tp, MII_BMCR, bmcr);
3007 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3008 }
3009 }
3010 }
3011 else if (netif_carrier_ok(tp->dev) &&
3012 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3013 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3014 u32 phy2;
3015
3016 /* Select expansion interrupt status register */
3017 tg3_writephy(tp, 0x17, 0x0f01);
3018 tg3_readphy(tp, 0x15, &phy2);
3019 if (phy2 & 0x20) {
3020 u32 bmcr;
3021
3022 /* Config code words received, turn on autoneg. */
3023 tg3_readphy(tp, MII_BMCR, &bmcr);
3024 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3025
3026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3027
3028 }
3029 }
3030 }
3031
3032 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3033 {
3034 int err;
3035
3036 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3037 err = tg3_setup_fiber_phy(tp, force_reset);
3038 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3039 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3040 } else {
3041 err = tg3_setup_copper_phy(tp, force_reset);
3042 }
3043
3044 if (tp->link_config.active_speed == SPEED_1000 &&
3045 tp->link_config.active_duplex == DUPLEX_HALF)
3046 tw32(MAC_TX_LENGTHS,
3047 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3048 (6 << TX_LENGTHS_IPG_SHIFT) |
3049 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3050 else
3051 tw32(MAC_TX_LENGTHS,
3052 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3053 (6 << TX_LENGTHS_IPG_SHIFT) |
3054 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3055
3056 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3057 if (netif_carrier_ok(tp->dev)) {
3058 tw32(HOSTCC_STAT_COAL_TICKS,
3059 tp->coal.stats_block_coalesce_usecs);
3060 } else {
3061 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3062 }
3063 }
3064
3065 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3066 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3067 if (!netif_carrier_ok(tp->dev))
3068 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3069 tp->pwrmgmt_thresh;
3070 else
3071 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3072 tw32(PCIE_PWR_MGMT_THRESH, val);
3073 }
3074
3075 return err;
3076 }
3077
3078 /* This is called whenever we suspect that the system chipset is re-
3079 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3080 * is bogus tx completions. We try to recover by setting the
3081 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3082 * in the workqueue.
3083 */
3084 static void tg3_tx_recover(struct tg3 *tp)
3085 {
3086 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3087 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3088
3089 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3090 "mapped I/O cycles to the network device, attempting to "
3091 "recover. Please report the problem to the driver maintainer "
3092 "and include system chipset information.\n", tp->dev->name);
3093
3094 spin_lock(&tp->lock);
3095 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3096 spin_unlock(&tp->lock);
3097 }
3098
3099 static inline u32 tg3_tx_avail(struct tg3 *tp)
3100 {
3101 smp_mb();
3102 return (tp->tx_pending -
3103 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3104 }
3105
3106 /* Tigon3 never reports partial packet sends. So we do not
3107 * need special logic to handle SKBs that have not had all
3108 * of their frags sent yet, like SunGEM does.
3109 */
3110 static void tg3_tx(struct tg3 *tp)
3111 {
3112 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3113 u32 sw_idx = tp->tx_cons;
3114
3115 while (sw_idx != hw_idx) {
3116 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3117 struct sk_buff *skb = ri->skb;
3118 int i, tx_bug = 0;
3119
3120 if (unlikely(skb == NULL)) {
3121 tg3_tx_recover(tp);
3122 return;
3123 }
3124
3125 pci_unmap_single(tp->pdev,
3126 pci_unmap_addr(ri, mapping),
3127 skb_headlen(skb),
3128 PCI_DMA_TODEVICE);
3129
3130 ri->skb = NULL;
3131
3132 sw_idx = NEXT_TX(sw_idx);
3133
3134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3135 ri = &tp->tx_buffers[sw_idx];
3136 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3137 tx_bug = 1;
3138
3139 pci_unmap_page(tp->pdev,
3140 pci_unmap_addr(ri, mapping),
3141 skb_shinfo(skb)->frags[i].size,
3142 PCI_DMA_TODEVICE);
3143
3144 sw_idx = NEXT_TX(sw_idx);
3145 }
3146
3147 dev_kfree_skb(skb);
3148
3149 if (unlikely(tx_bug)) {
3150 tg3_tx_recover(tp);
3151 return;
3152 }
3153 }
3154
3155 tp->tx_cons = sw_idx;
3156
3157 /* Need to make the tx_cons update visible to tg3_start_xmit()
3158 * before checking for netif_queue_stopped(). Without the
3159 * memory barrier, there is a small possibility that tg3_start_xmit()
3160 * will miss it and cause the queue to be stopped forever.
3161 */
3162 smp_mb();
3163
3164 if (unlikely(netif_queue_stopped(tp->dev) &&
3165 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3166 netif_tx_lock(tp->dev);
3167 if (netif_queue_stopped(tp->dev) &&
3168 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3169 netif_wake_queue(tp->dev);
3170 netif_tx_unlock(tp->dev);
3171 }
3172 }
3173
3174 /* Returns size of skb allocated or < 0 on error.
3175 *
3176 * We only need to fill in the address because the other members
3177 * of the RX descriptor are invariant, see tg3_init_rings.
3178 *
3179 * Note the purposeful assymetry of cpu vs. chip accesses. For
3180 * posting buffers we only dirty the first cache line of the RX
3181 * descriptor (containing the address). Whereas for the RX status
3182 * buffers the cpu only reads the last cacheline of the RX descriptor
3183 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3184 */
3185 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3186 int src_idx, u32 dest_idx_unmasked)
3187 {
3188 struct tg3_rx_buffer_desc *desc;
3189 struct ring_info *map, *src_map;
3190 struct sk_buff *skb;
3191 dma_addr_t mapping;
3192 int skb_size, dest_idx;
3193
3194 src_map = NULL;
3195 switch (opaque_key) {
3196 case RXD_OPAQUE_RING_STD:
3197 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3198 desc = &tp->rx_std[dest_idx];
3199 map = &tp->rx_std_buffers[dest_idx];
3200 if (src_idx >= 0)
3201 src_map = &tp->rx_std_buffers[src_idx];
3202 skb_size = tp->rx_pkt_buf_sz;
3203 break;
3204
3205 case RXD_OPAQUE_RING_JUMBO:
3206 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3207 desc = &tp->rx_jumbo[dest_idx];
3208 map = &tp->rx_jumbo_buffers[dest_idx];
3209 if (src_idx >= 0)
3210 src_map = &tp->rx_jumbo_buffers[src_idx];
3211 skb_size = RX_JUMBO_PKT_BUF_SZ;
3212 break;
3213
3214 default:
3215 return -EINVAL;
3216 };
3217
3218 /* Do not overwrite any of the map or rp information
3219 * until we are sure we can commit to a new buffer.
3220 *
3221 * Callers depend upon this behavior and assume that
3222 * we leave everything unchanged if we fail.
3223 */
3224 skb = netdev_alloc_skb(tp->dev, skb_size);
3225 if (skb == NULL)
3226 return -ENOMEM;
3227
3228 skb_reserve(skb, tp->rx_offset);
3229
3230 mapping = pci_map_single(tp->pdev, skb->data,
3231 skb_size - tp->rx_offset,
3232 PCI_DMA_FROMDEVICE);
3233
3234 map->skb = skb;
3235 pci_unmap_addr_set(map, mapping, mapping);
3236
3237 if (src_map != NULL)
3238 src_map->skb = NULL;
3239
3240 desc->addr_hi = ((u64)mapping >> 32);
3241 desc->addr_lo = ((u64)mapping & 0xffffffff);
3242
3243 return skb_size;
3244 }
3245
3246 /* We only need to move over in the address because the other
3247 * members of the RX descriptor are invariant. See notes above
3248 * tg3_alloc_rx_skb for full details.
3249 */
3250 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3251 int src_idx, u32 dest_idx_unmasked)
3252 {
3253 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3254 struct ring_info *src_map, *dest_map;
3255 int dest_idx;
3256
3257 switch (opaque_key) {
3258 case RXD_OPAQUE_RING_STD:
3259 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3260 dest_desc = &tp->rx_std[dest_idx];
3261 dest_map = &tp->rx_std_buffers[dest_idx];
3262 src_desc = &tp->rx_std[src_idx];
3263 src_map = &tp->rx_std_buffers[src_idx];
3264 break;
3265
3266 case RXD_OPAQUE_RING_JUMBO:
3267 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3268 dest_desc = &tp->rx_jumbo[dest_idx];
3269 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3270 src_desc = &tp->rx_jumbo[src_idx];
3271 src_map = &tp->rx_jumbo_buffers[src_idx];
3272 break;
3273
3274 default:
3275 return;
3276 };
3277
3278 dest_map->skb = src_map->skb;
3279 pci_unmap_addr_set(dest_map, mapping,
3280 pci_unmap_addr(src_map, mapping));
3281 dest_desc->addr_hi = src_desc->addr_hi;
3282 dest_desc->addr_lo = src_desc->addr_lo;
3283
3284 src_map->skb = NULL;
3285 }
3286
3287 #if TG3_VLAN_TAG_USED
3288 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3289 {
3290 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3291 }
3292 #endif
3293
3294 /* The RX ring scheme is composed of multiple rings which post fresh
3295 * buffers to the chip, and one special ring the chip uses to report
3296 * status back to the host.
3297 *
3298 * The special ring reports the status of received packets to the
3299 * host. The chip does not write into the original descriptor the
3300 * RX buffer was obtained from. The chip simply takes the original
3301 * descriptor as provided by the host, updates the status and length
3302 * field, then writes this into the next status ring entry.
3303 *
3304 * Each ring the host uses to post buffers to the chip is described
3305 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3306 * it is first placed into the on-chip ram. When the packet's length
3307 * is known, it walks down the TG3_BDINFO entries to select the ring.
3308 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3309 * which is within the range of the new packet's length is chosen.
3310 *
3311 * The "separate ring for rx status" scheme may sound queer, but it makes
3312 * sense from a cache coherency perspective. If only the host writes
3313 * to the buffer post rings, and only the chip writes to the rx status
3314 * rings, then cache lines never move beyond shared-modified state.
3315 * If both the host and chip were to write into the same ring, cache line
3316 * eviction could occur since both entities want it in an exclusive state.
3317 */
3318 static int tg3_rx(struct tg3 *tp, int budget)
3319 {
3320 u32 work_mask, rx_std_posted = 0;
3321 u32 sw_idx = tp->rx_rcb_ptr;
3322 u16 hw_idx;
3323 int received;
3324
3325 hw_idx = tp->hw_status->idx[0].rx_producer;
3326 /*
3327 * We need to order the read of hw_idx and the read of
3328 * the opaque cookie.
3329 */
3330 rmb();
3331 work_mask = 0;
3332 received = 0;
3333 while (sw_idx != hw_idx && budget > 0) {
3334 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3335 unsigned int len;
3336 struct sk_buff *skb;
3337 dma_addr_t dma_addr;
3338 u32 opaque_key, desc_idx, *post_ptr;
3339
3340 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3341 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3342 if (opaque_key == RXD_OPAQUE_RING_STD) {
3343 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3344 mapping);
3345 skb = tp->rx_std_buffers[desc_idx].skb;
3346 post_ptr = &tp->rx_std_ptr;
3347 rx_std_posted++;
3348 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3349 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3350 mapping);
3351 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3352 post_ptr = &tp->rx_jumbo_ptr;
3353 }
3354 else {
3355 goto next_pkt_nopost;
3356 }
3357
3358 work_mask |= opaque_key;
3359
3360 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3361 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3362 drop_it:
3363 tg3_recycle_rx(tp, opaque_key,
3364 desc_idx, *post_ptr);
3365 drop_it_no_recycle:
3366 /* Other statistics kept track of by card. */
3367 tp->net_stats.rx_dropped++;
3368 goto next_pkt;
3369 }
3370
3371 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3372
3373 if (len > RX_COPY_THRESHOLD
3374 && tp->rx_offset == 2
3375 /* rx_offset != 2 iff this is a 5701 card running
3376 * in PCI-X mode [see tg3_get_invariants()] */
3377 ) {
3378 int skb_size;
3379
3380 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3381 desc_idx, *post_ptr);
3382 if (skb_size < 0)
3383 goto drop_it;
3384
3385 pci_unmap_single(tp->pdev, dma_addr,
3386 skb_size - tp->rx_offset,
3387 PCI_DMA_FROMDEVICE);
3388
3389 skb_put(skb, len);
3390 } else {
3391 struct sk_buff *copy_skb;
3392
3393 tg3_recycle_rx(tp, opaque_key,
3394 desc_idx, *post_ptr);
3395
3396 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3397 if (copy_skb == NULL)
3398 goto drop_it_no_recycle;
3399
3400 skb_reserve(copy_skb, 2);
3401 skb_put(copy_skb, len);
3402 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3403 skb_copy_from_linear_data(skb, copy_skb->data, len);
3404 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3405
3406 /* We'll reuse the original ring buffer. */
3407 skb = copy_skb;
3408 }
3409
3410 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3411 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3412 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3413 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3414 skb->ip_summed = CHECKSUM_UNNECESSARY;
3415 else
3416 skb->ip_summed = CHECKSUM_NONE;
3417
3418 skb->protocol = eth_type_trans(skb, tp->dev);
3419 #if TG3_VLAN_TAG_USED
3420 if (tp->vlgrp != NULL &&
3421 desc->type_flags & RXD_FLAG_VLAN) {
3422 tg3_vlan_rx(tp, skb,
3423 desc->err_vlan & RXD_VLAN_MASK);
3424 } else
3425 #endif
3426 netif_receive_skb(skb);
3427
3428 tp->dev->last_rx = jiffies;
3429 received++;
3430 budget--;
3431
3432 next_pkt:
3433 (*post_ptr)++;
3434
3435 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3436 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3437
3438 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3439 TG3_64BIT_REG_LOW, idx);
3440 work_mask &= ~RXD_OPAQUE_RING_STD;
3441 rx_std_posted = 0;
3442 }
3443 next_pkt_nopost:
3444 sw_idx++;
3445 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3446
3447 /* Refresh hw_idx to see if there is new work */
3448 if (sw_idx == hw_idx) {
3449 hw_idx = tp->hw_status->idx[0].rx_producer;
3450 rmb();
3451 }
3452 }
3453
3454 /* ACK the status ring. */
3455 tp->rx_rcb_ptr = sw_idx;
3456 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3457
3458 /* Refill RX ring(s). */
3459 if (work_mask & RXD_OPAQUE_RING_STD) {
3460 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3461 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3462 sw_idx);
3463 }
3464 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3465 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3466 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3467 sw_idx);
3468 }
3469 mmiowb();
3470
3471 return received;
3472 }
3473
3474 static int tg3_poll(struct net_device *netdev, int *budget)
3475 {
3476 struct tg3 *tp = netdev_priv(netdev);
3477 struct tg3_hw_status *sblk = tp->hw_status;
3478 int done;
3479
3480 /* handle link change and other phy events */
3481 if (!(tp->tg3_flags &
3482 (TG3_FLAG_USE_LINKCHG_REG |
3483 TG3_FLAG_POLL_SERDES))) {
3484 if (sblk->status & SD_STATUS_LINK_CHG) {
3485 sblk->status = SD_STATUS_UPDATED |
3486 (sblk->status & ~SD_STATUS_LINK_CHG);
3487 spin_lock(&tp->lock);
3488 tg3_setup_phy(tp, 0);
3489 spin_unlock(&tp->lock);
3490 }
3491 }
3492
3493 /* run TX completion thread */
3494 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3495 tg3_tx(tp);
3496 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3497 netif_rx_complete(netdev);
3498 schedule_work(&tp->reset_task);
3499 return 0;
3500 }
3501 }
3502
3503 /* run RX thread, within the bounds set by NAPI.
3504 * All RX "locking" is done by ensuring outside
3505 * code synchronizes with dev->poll()
3506 */
3507 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3508 int orig_budget = *budget;
3509 int work_done;
3510
3511 if (orig_budget > netdev->quota)
3512 orig_budget = netdev->quota;
3513
3514 work_done = tg3_rx(tp, orig_budget);
3515
3516 *budget -= work_done;
3517 netdev->quota -= work_done;
3518 }
3519
3520 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3521 tp->last_tag = sblk->status_tag;
3522 rmb();
3523 } else
3524 sblk->status &= ~SD_STATUS_UPDATED;
3525
3526 /* if no more work, tell net stack and NIC we're done */
3527 done = !tg3_has_work(tp);
3528 if (done) {
3529 netif_rx_complete(netdev);
3530 tg3_restart_ints(tp);
3531 }
3532
3533 return (done ? 0 : 1);
3534 }
3535
3536 static void tg3_irq_quiesce(struct tg3 *tp)
3537 {
3538 BUG_ON(tp->irq_sync);
3539
3540 tp->irq_sync = 1;
3541 smp_mb();
3542
3543 synchronize_irq(tp->pdev->irq);
3544 }
3545
3546 static inline int tg3_irq_sync(struct tg3 *tp)
3547 {
3548 return tp->irq_sync;
3549 }
3550
3551 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3552 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3553 * with as well. Most of the time, this is not necessary except when
3554 * shutting down the device.
3555 */
3556 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3557 {
3558 spin_lock_bh(&tp->lock);
3559 if (irq_sync)
3560 tg3_irq_quiesce(tp);
3561 }
3562
3563 static inline void tg3_full_unlock(struct tg3 *tp)
3564 {
3565 spin_unlock_bh(&tp->lock);
3566 }
3567
3568 /* One-shot MSI handler - Chip automatically disables interrupt
3569 * after sending MSI so driver doesn't have to do it.
3570 */
3571 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3572 {
3573 struct net_device *dev = dev_id;
3574 struct tg3 *tp = netdev_priv(dev);
3575
3576 prefetch(tp->hw_status);
3577 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3578
3579 if (likely(!tg3_irq_sync(tp)))
3580 netif_rx_schedule(dev); /* schedule NAPI poll */
3581
3582 return IRQ_HANDLED;
3583 }
3584
3585 /* MSI ISR - No need to check for interrupt sharing and no need to
3586 * flush status block and interrupt mailbox. PCI ordering rules
3587 * guarantee that MSI will arrive after the status block.
3588 */
3589 static irqreturn_t tg3_msi(int irq, void *dev_id)
3590 {
3591 struct net_device *dev = dev_id;
3592 struct tg3 *tp = netdev_priv(dev);
3593
3594 prefetch(tp->hw_status);
3595 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3596 /*
3597 * Writing any value to intr-mbox-0 clears PCI INTA# and
3598 * chip-internal interrupt pending events.
3599 * Writing non-zero to intr-mbox-0 additional tells the
3600 * NIC to stop sending us irqs, engaging "in-intr-handler"
3601 * event coalescing.
3602 */
3603 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3604 if (likely(!tg3_irq_sync(tp)))
3605 netif_rx_schedule(dev); /* schedule NAPI poll */
3606
3607 return IRQ_RETVAL(1);
3608 }
3609
3610 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3611 {
3612 struct net_device *dev = dev_id;
3613 struct tg3 *tp = netdev_priv(dev);
3614 struct tg3_hw_status *sblk = tp->hw_status;
3615 unsigned int handled = 1;
3616
3617 /* In INTx mode, it is possible for the interrupt to arrive at
3618 * the CPU before the status block posted prior to the interrupt.
3619 * Reading the PCI State register will confirm whether the
3620 * interrupt is ours and will flush the status block.
3621 */
3622 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3623 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3624 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3625 handled = 0;
3626 goto out;
3627 }
3628 }
3629
3630 /*
3631 * Writing any value to intr-mbox-0 clears PCI INTA# and
3632 * chip-internal interrupt pending events.
3633 * Writing non-zero to intr-mbox-0 additional tells the
3634 * NIC to stop sending us irqs, engaging "in-intr-handler"
3635 * event coalescing.
3636 *
3637 * Flush the mailbox to de-assert the IRQ immediately to prevent
3638 * spurious interrupts. The flush impacts performance but
3639 * excessive spurious interrupts can be worse in some cases.
3640 */
3641 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3642 if (tg3_irq_sync(tp))
3643 goto out;
3644 sblk->status &= ~SD_STATUS_UPDATED;
3645 if (likely(tg3_has_work(tp))) {
3646 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3647 netif_rx_schedule(dev); /* schedule NAPI poll */
3648 } else {
3649 /* No work, shared interrupt perhaps? re-enable
3650 * interrupts, and flush that PCI write
3651 */
3652 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3653 0x00000000);
3654 }
3655 out:
3656 return IRQ_RETVAL(handled);
3657 }
3658
3659 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3660 {
3661 struct net_device *dev = dev_id;
3662 struct tg3 *tp = netdev_priv(dev);
3663 struct tg3_hw_status *sblk = tp->hw_status;
3664 unsigned int handled = 1;
3665
3666 /* In INTx mode, it is possible for the interrupt to arrive at
3667 * the CPU before the status block posted prior to the interrupt.
3668 * Reading the PCI State register will confirm whether the
3669 * interrupt is ours and will flush the status block.
3670 */
3671 if (unlikely(sblk->status_tag == tp->last_tag)) {
3672 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3673 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3674 handled = 0;
3675 goto out;
3676 }
3677 }
3678
3679 /*
3680 * writing any value to intr-mbox-0 clears PCI INTA# and
3681 * chip-internal interrupt pending events.
3682 * writing non-zero to intr-mbox-0 additional tells the
3683 * NIC to stop sending us irqs, engaging "in-intr-handler"
3684 * event coalescing.
3685 *
3686 * Flush the mailbox to de-assert the IRQ immediately to prevent
3687 * spurious interrupts. The flush impacts performance but
3688 * excessive spurious interrupts can be worse in some cases.
3689 */
3690 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3691 if (tg3_irq_sync(tp))
3692 goto out;
3693 if (netif_rx_schedule_prep(dev)) {
3694 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3695 /* Update last_tag to mark that this status has been
3696 * seen. Because interrupt may be shared, we may be
3697 * racing with tg3_poll(), so only update last_tag
3698 * if tg3_poll() is not scheduled.
3699 */
3700 tp->last_tag = sblk->status_tag;
3701 __netif_rx_schedule(dev);
3702 }
3703 out:
3704 return IRQ_RETVAL(handled);
3705 }
3706
3707 /* ISR for interrupt test */
3708 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3709 {
3710 struct net_device *dev = dev_id;
3711 struct tg3 *tp = netdev_priv(dev);
3712 struct tg3_hw_status *sblk = tp->hw_status;
3713
3714 if ((sblk->status & SD_STATUS_UPDATED) ||
3715 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3716 tg3_disable_ints(tp);
3717 return IRQ_RETVAL(1);
3718 }
3719 return IRQ_RETVAL(0);
3720 }
3721
3722 static int tg3_init_hw(struct tg3 *, int);
3723 static int tg3_halt(struct tg3 *, int, int);
3724
3725 /* Restart hardware after configuration changes, self-test, etc.
3726 * Invoked with tp->lock held.
3727 */
3728 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3729 {
3730 int err;
3731
3732 err = tg3_init_hw(tp, reset_phy);
3733 if (err) {
3734 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3735 "aborting.\n", tp->dev->name);
3736 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3737 tg3_full_unlock(tp);
3738 del_timer_sync(&tp->timer);
3739 tp->irq_sync = 0;
3740 netif_poll_enable(tp->dev);
3741 dev_close(tp->dev);
3742 tg3_full_lock(tp, 0);
3743 }
3744 return err;
3745 }
3746
3747 #ifdef CONFIG_NET_POLL_CONTROLLER
3748 static void tg3_poll_controller(struct net_device *dev)
3749 {
3750 struct tg3 *tp = netdev_priv(dev);
3751
3752 tg3_interrupt(tp->pdev->irq, dev);
3753 }
3754 #endif
3755
3756 static void tg3_reset_task(struct work_struct *work)
3757 {
3758 struct tg3 *tp = container_of(work, struct tg3, reset_task);
3759 unsigned int restart_timer;
3760
3761 tg3_full_lock(tp, 0);
3762
3763 if (!netif_running(tp->dev)) {
3764 tg3_full_unlock(tp);
3765 return;
3766 }
3767
3768 tg3_full_unlock(tp);
3769
3770 tg3_netif_stop(tp);
3771
3772 tg3_full_lock(tp, 1);
3773
3774 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3775 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3776
3777 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3778 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3779 tp->write32_rx_mbox = tg3_write_flush_reg32;
3780 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3781 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3782 }
3783
3784 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3785 if (tg3_init_hw(tp, 1))
3786 goto out;
3787
3788 tg3_netif_start(tp);
3789
3790 if (restart_timer)
3791 mod_timer(&tp->timer, jiffies + 1);
3792
3793 out:
3794 tg3_full_unlock(tp);
3795 }
3796
3797 static void tg3_dump_short_state(struct tg3 *tp)
3798 {
3799 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3800 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3801 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3802 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3803 }
3804
3805 static void tg3_tx_timeout(struct net_device *dev)
3806 {
3807 struct tg3 *tp = netdev_priv(dev);
3808
3809 if (netif_msg_tx_err(tp)) {
3810 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3811 dev->name);
3812 tg3_dump_short_state(tp);
3813 }
3814
3815 schedule_work(&tp->reset_task);
3816 }
3817
3818 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3819 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3820 {
3821 u32 base = (u32) mapping & 0xffffffff;
3822
3823 return ((base > 0xffffdcc0) &&
3824 (base + len + 8 < base));
3825 }
3826
3827 /* Test for DMA addresses > 40-bit */
3828 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3829 int len)
3830 {
3831 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3832 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3833 return (((u64) mapping + len) > DMA_40BIT_MASK);
3834 return 0;
3835 #else
3836 return 0;
3837 #endif
3838 }
3839
3840 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3841
3842 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3843 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3844 u32 last_plus_one, u32 *start,
3845 u32 base_flags, u32 mss)
3846 {
3847 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3848 dma_addr_t new_addr = 0;
3849 u32 entry = *start;
3850 int i, ret = 0;
3851
3852 if (!new_skb) {
3853 ret = -1;
3854 } else {
3855 /* New SKB is guaranteed to be linear. */
3856 entry = *start;
3857 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3858 PCI_DMA_TODEVICE);
3859 /* Make sure new skb does not cross any 4G boundaries.
3860 * Drop the packet if it does.
3861 */
3862 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3863 ret = -1;
3864 dev_kfree_skb(new_skb);
3865 new_skb = NULL;
3866 } else {
3867 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3868 base_flags, 1 | (mss << 1));
3869 *start = NEXT_TX(entry);
3870 }
3871 }
3872
3873 /* Now clean up the sw ring entries. */
3874 i = 0;
3875 while (entry != last_plus_one) {
3876 int len;
3877
3878 if (i == 0)
3879 len = skb_headlen(skb);
3880 else
3881 len = skb_shinfo(skb)->frags[i-1].size;
3882 pci_unmap_single(tp->pdev,
3883 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3884 len, PCI_DMA_TODEVICE);
3885 if (i == 0) {
3886 tp->tx_buffers[entry].skb = new_skb;
3887 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3888 } else {
3889 tp->tx_buffers[entry].skb = NULL;
3890 }
3891 entry = NEXT_TX(entry);
3892 i++;
3893 }
3894
3895 dev_kfree_skb(skb);
3896
3897 return ret;
3898 }
3899
3900 static void tg3_set_txd(struct tg3 *tp, int entry,
3901 dma_addr_t mapping, int len, u32 flags,
3902 u32 mss_and_is_end)
3903 {
3904 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3905 int is_end = (mss_and_is_end & 0x1);
3906 u32 mss = (mss_and_is_end >> 1);
3907 u32 vlan_tag = 0;
3908
3909 if (is_end)
3910 flags |= TXD_FLAG_END;
3911 if (flags & TXD_FLAG_VLAN) {
3912 vlan_tag = flags >> 16;
3913 flags &= 0xffff;
3914 }
3915 vlan_tag |= (mss << TXD_MSS_SHIFT);
3916
3917 txd->addr_hi = ((u64) mapping >> 32);
3918 txd->addr_lo = ((u64) mapping & 0xffffffff);
3919 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3920 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3921 }
3922
3923 /* hard_start_xmit for devices that don't have any bugs and
3924 * support TG3_FLG2_HW_TSO_2 only.
3925 */
3926 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3927 {
3928 struct tg3 *tp = netdev_priv(dev);
3929 dma_addr_t mapping;
3930 u32 len, entry, base_flags, mss;
3931
3932 len = skb_headlen(skb);
3933
3934 /* We are running in BH disabled context with netif_tx_lock
3935 * and TX reclaim runs via tp->poll inside of a software
3936 * interrupt. Furthermore, IRQ processing runs lockless so we have
3937 * no IRQ context deadlocks to worry about either. Rejoice!
3938 */
3939 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3940 if (!netif_queue_stopped(dev)) {
3941 netif_stop_queue(dev);
3942
3943 /* This is a hard error, log it. */
3944 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3945 "queue awake!\n", dev->name);
3946 }
3947 return NETDEV_TX_BUSY;
3948 }
3949
3950 entry = tp->tx_prod;
3951 base_flags = 0;
3952 mss = 0;
3953 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3954 int tcp_opt_len, ip_tcp_len;
3955
3956 if (skb_header_cloned(skb) &&
3957 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3958 dev_kfree_skb(skb);
3959 goto out_unlock;
3960 }
3961
3962 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3963 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3964 else {
3965 struct iphdr *iph = ip_hdr(skb);
3966
3967 tcp_opt_len = tcp_optlen(skb);
3968 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3969
3970 iph->check = 0;
3971 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3972 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3973 }
3974
3975 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3976 TXD_FLAG_CPU_POST_DMA);
3977
3978 tcp_hdr(skb)->check = 0;
3979
3980 }
3981 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3982 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3983 #if TG3_VLAN_TAG_USED
3984 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3985 base_flags |= (TXD_FLAG_VLAN |
3986 (vlan_tx_tag_get(skb) << 16));
3987 #endif
3988
3989 /* Queue skb data, a.k.a. the main skb fragment. */
3990 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3991
3992 tp->tx_buffers[entry].skb = skb;
3993 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3994
3995 tg3_set_txd(tp, entry, mapping, len, base_flags,
3996 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3997
3998 entry = NEXT_TX(entry);
3999
4000 /* Now loop through additional data fragments, and queue them. */
4001 if (skb_shinfo(skb)->nr_frags > 0) {
4002 unsigned int i, last;
4003
4004 last = skb_shinfo(skb)->nr_frags - 1;
4005 for (i = 0; i <= last; i++) {
4006 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4007
4008 len = frag->size;
4009 mapping = pci_map_page(tp->pdev,
4010 frag->page,
4011 frag->page_offset,
4012 len, PCI_DMA_TODEVICE);
4013
4014 tp->tx_buffers[entry].skb = NULL;
4015 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4016
4017 tg3_set_txd(tp, entry, mapping, len,
4018 base_flags, (i == last) | (mss << 1));
4019
4020 entry = NEXT_TX(entry);
4021 }
4022 }
4023
4024 /* Packets are ready, update Tx producer idx local and on card. */
4025 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4026
4027 tp->tx_prod = entry;
4028 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4029 netif_stop_queue(dev);
4030 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4031 netif_wake_queue(tp->dev);
4032 }
4033
4034 out_unlock:
4035 mmiowb();
4036
4037 dev->trans_start = jiffies;
4038
4039 return NETDEV_TX_OK;
4040 }
4041
4042 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4043
4044 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4045 * TSO header is greater than 80 bytes.
4046 */
4047 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4048 {
4049 struct sk_buff *segs, *nskb;
4050
4051 /* Estimate the number of fragments in the worst case */
4052 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4053 netif_stop_queue(tp->dev);
4054 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4055 return NETDEV_TX_BUSY;
4056
4057 netif_wake_queue(tp->dev);
4058 }
4059
4060 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4061 if (unlikely(IS_ERR(segs)))
4062 goto tg3_tso_bug_end;
4063
4064 do {
4065 nskb = segs;
4066 segs = segs->next;
4067 nskb->next = NULL;
4068 tg3_start_xmit_dma_bug(nskb, tp->dev);
4069 } while (segs);
4070
4071 tg3_tso_bug_end:
4072 dev_kfree_skb(skb);
4073
4074 return NETDEV_TX_OK;
4075 }
4076
4077 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4078 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4079 */
4080 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4081 {
4082 struct tg3 *tp = netdev_priv(dev);
4083 dma_addr_t mapping;
4084 u32 len, entry, base_flags, mss;
4085 int would_hit_hwbug;
4086
4087 len = skb_headlen(skb);
4088
4089 /* We are running in BH disabled context with netif_tx_lock
4090 * and TX reclaim runs via tp->poll inside of a software
4091 * interrupt. Furthermore, IRQ processing runs lockless so we have
4092 * no IRQ context deadlocks to worry about either. Rejoice!
4093 */
4094 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4095 if (!netif_queue_stopped(dev)) {
4096 netif_stop_queue(dev);
4097
4098 /* This is a hard error, log it. */
4099 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4100 "queue awake!\n", dev->name);
4101 }
4102 return NETDEV_TX_BUSY;
4103 }
4104
4105 entry = tp->tx_prod;
4106 base_flags = 0;
4107 if (skb->ip_summed == CHECKSUM_PARTIAL)
4108 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4109 mss = 0;
4110 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4111 struct iphdr *iph;
4112 int tcp_opt_len, ip_tcp_len, hdr_len;
4113
4114 if (skb_header_cloned(skb) &&
4115 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4116 dev_kfree_skb(skb);
4117 goto out_unlock;
4118 }
4119
4120 tcp_opt_len = tcp_optlen(skb);
4121 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4122
4123 hdr_len = ip_tcp_len + tcp_opt_len;
4124 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4125 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4126 return (tg3_tso_bug(tp, skb));
4127
4128 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4129 TXD_FLAG_CPU_POST_DMA);
4130
4131 iph = ip_hdr(skb);
4132 iph->check = 0;
4133 iph->tot_len = htons(mss + hdr_len);
4134 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4135 tcp_hdr(skb)->check = 0;
4136 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4137 } else
4138 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4139 iph->daddr, 0,
4140 IPPROTO_TCP,
4141 0);
4142
4143 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4144 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4145 if (tcp_opt_len || iph->ihl > 5) {
4146 int tsflags;
4147
4148 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4149 mss |= (tsflags << 11);
4150 }
4151 } else {
4152 if (tcp_opt_len || iph->ihl > 5) {
4153 int tsflags;
4154
4155 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4156 base_flags |= tsflags << 12;
4157 }
4158 }
4159 }
4160 #if TG3_VLAN_TAG_USED
4161 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4162 base_flags |= (TXD_FLAG_VLAN |
4163 (vlan_tx_tag_get(skb) << 16));
4164 #endif
4165
4166 /* Queue skb data, a.k.a. the main skb fragment. */
4167 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4168
4169 tp->tx_buffers[entry].skb = skb;
4170 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4171
4172 would_hit_hwbug = 0;
4173
4174 if (tg3_4g_overflow_test(mapping, len))
4175 would_hit_hwbug = 1;
4176
4177 tg3_set_txd(tp, entry, mapping, len, base_flags,
4178 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4179
4180 entry = NEXT_TX(entry);
4181
4182 /* Now loop through additional data fragments, and queue them. */
4183 if (skb_shinfo(skb)->nr_frags > 0) {
4184 unsigned int i, last;
4185
4186 last = skb_shinfo(skb)->nr_frags - 1;
4187 for (i = 0; i <= last; i++) {
4188 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4189
4190 len = frag->size;
4191 mapping = pci_map_page(tp->pdev,
4192 frag->page,
4193 frag->page_offset,
4194 len, PCI_DMA_TODEVICE);
4195
4196 tp->tx_buffers[entry].skb = NULL;
4197 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4198
4199 if (tg3_4g_overflow_test(mapping, len))
4200 would_hit_hwbug = 1;
4201
4202 if (tg3_40bit_overflow_test(tp, mapping, len))
4203 would_hit_hwbug = 1;
4204
4205 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4206 tg3_set_txd(tp, entry, mapping, len,
4207 base_flags, (i == last)|(mss << 1));
4208 else
4209 tg3_set_txd(tp, entry, mapping, len,
4210 base_flags, (i == last));
4211
4212 entry = NEXT_TX(entry);
4213 }
4214 }
4215
4216 if (would_hit_hwbug) {
4217 u32 last_plus_one = entry;
4218 u32 start;
4219
4220 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4221 start &= (TG3_TX_RING_SIZE - 1);
4222
4223 /* If the workaround fails due to memory/mapping
4224 * failure, silently drop this packet.
4225 */
4226 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4227 &start, base_flags, mss))
4228 goto out_unlock;
4229
4230 entry = start;
4231 }
4232
4233 /* Packets are ready, update Tx producer idx local and on card. */
4234 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4235
4236 tp->tx_prod = entry;
4237 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4238 netif_stop_queue(dev);
4239 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4240 netif_wake_queue(tp->dev);
4241 }
4242
4243 out_unlock:
4244 mmiowb();
4245
4246 dev->trans_start = jiffies;
4247
4248 return NETDEV_TX_OK;
4249 }
4250
4251 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4252 int new_mtu)
4253 {
4254 dev->mtu = new_mtu;
4255
4256 if (new_mtu > ETH_DATA_LEN) {
4257 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4258 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4259 ethtool_op_set_tso(dev, 0);
4260 }
4261 else
4262 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4263 } else {
4264 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4265 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4266 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4267 }
4268 }
4269
4270 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4271 {
4272 struct tg3 *tp = netdev_priv(dev);
4273 int err;
4274
4275 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4276 return -EINVAL;
4277
4278 if (!netif_running(dev)) {
4279 /* We'll just catch it later when the
4280 * device is up'd.
4281 */
4282 tg3_set_mtu(dev, tp, new_mtu);
4283 return 0;
4284 }
4285
4286 tg3_netif_stop(tp);
4287
4288 tg3_full_lock(tp, 1);
4289
4290 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4291
4292 tg3_set_mtu(dev, tp, new_mtu);
4293
4294 err = tg3_restart_hw(tp, 0);
4295
4296 if (!err)
4297 tg3_netif_start(tp);
4298
4299 tg3_full_unlock(tp);
4300
4301 return err;
4302 }
4303
4304 /* Free up pending packets in all rx/tx rings.
4305 *
4306 * The chip has been shut down and the driver detached from
4307 * the networking, so no interrupts or new tx packets will
4308 * end up in the driver. tp->{tx,}lock is not held and we are not
4309 * in an interrupt context and thus may sleep.
4310 */
4311 static void tg3_free_rings(struct tg3 *tp)
4312 {
4313 struct ring_info *rxp;
4314 int i;
4315
4316 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4317 rxp = &tp->rx_std_buffers[i];
4318
4319 if (rxp->skb == NULL)
4320 continue;
4321 pci_unmap_single(tp->pdev,
4322 pci_unmap_addr(rxp, mapping),
4323 tp->rx_pkt_buf_sz - tp->rx_offset,
4324 PCI_DMA_FROMDEVICE);
4325 dev_kfree_skb_any(rxp->skb);
4326 rxp->skb = NULL;
4327 }
4328
4329 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4330 rxp = &tp->rx_jumbo_buffers[i];
4331
4332 if (rxp->skb == NULL)
4333 continue;
4334 pci_unmap_single(tp->pdev,
4335 pci_unmap_addr(rxp, mapping),
4336 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4337 PCI_DMA_FROMDEVICE);
4338 dev_kfree_skb_any(rxp->skb);
4339 rxp->skb = NULL;
4340 }
4341
4342 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4343 struct tx_ring_info *txp;
4344 struct sk_buff *skb;
4345 int j;
4346
4347 txp = &tp->tx_buffers[i];
4348 skb = txp->skb;
4349
4350 if (skb == NULL) {
4351 i++;
4352 continue;
4353 }
4354
4355 pci_unmap_single(tp->pdev,
4356 pci_unmap_addr(txp, mapping),
4357 skb_headlen(skb),
4358 PCI_DMA_TODEVICE);
4359 txp->skb = NULL;
4360
4361 i++;
4362
4363 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4364 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4365 pci_unmap_page(tp->pdev,
4366 pci_unmap_addr(txp, mapping),
4367 skb_shinfo(skb)->frags[j].size,
4368 PCI_DMA_TODEVICE);
4369 i++;
4370 }
4371
4372 dev_kfree_skb_any(skb);
4373 }
4374 }
4375
4376 /* Initialize tx/rx rings for packet processing.
4377 *
4378 * The chip has been shut down and the driver detached from
4379 * the networking, so no interrupts or new tx packets will
4380 * end up in the driver. tp->{tx,}lock are held and thus
4381 * we may not sleep.
4382 */
4383 static int tg3_init_rings(struct tg3 *tp)
4384 {
4385 u32 i;
4386
4387 /* Free up all the SKBs. */
4388 tg3_free_rings(tp);
4389
4390 /* Zero out all descriptors. */
4391 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4392 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4393 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4394 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4395
4396 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4397 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4398 (tp->dev->mtu > ETH_DATA_LEN))
4399 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4400
4401 /* Initialize invariants of the rings, we only set this
4402 * stuff once. This works because the card does not
4403 * write into the rx buffer posting rings.
4404 */
4405 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4406 struct tg3_rx_buffer_desc *rxd;
4407
4408 rxd = &tp->rx_std[i];
4409 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4410 << RXD_LEN_SHIFT;
4411 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4412 rxd->opaque = (RXD_OPAQUE_RING_STD |
4413 (i << RXD_OPAQUE_INDEX_SHIFT));
4414 }
4415
4416 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4417 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4418 struct tg3_rx_buffer_desc *rxd;
4419
4420 rxd = &tp->rx_jumbo[i];
4421 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4422 << RXD_LEN_SHIFT;
4423 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4424 RXD_FLAG_JUMBO;
4425 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4426 (i << RXD_OPAQUE_INDEX_SHIFT));
4427 }
4428 }
4429
4430 /* Now allocate fresh SKBs for each rx ring. */
4431 for (i = 0; i < tp->rx_pending; i++) {
4432 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4433 printk(KERN_WARNING PFX
4434 "%s: Using a smaller RX standard ring, "
4435 "only %d out of %d buffers were allocated "
4436 "successfully.\n",
4437 tp->dev->name, i, tp->rx_pending);
4438 if (i == 0)
4439 return -ENOMEM;
4440 tp->rx_pending = i;
4441 break;
4442 }
4443 }
4444
4445 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4446 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4447 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4448 -1, i) < 0) {
4449 printk(KERN_WARNING PFX
4450 "%s: Using a smaller RX jumbo ring, "
4451 "only %d out of %d buffers were "
4452 "allocated successfully.\n",
4453 tp->dev->name, i, tp->rx_jumbo_pending);
4454 if (i == 0) {
4455 tg3_free_rings(tp);
4456 return -ENOMEM;
4457 }
4458 tp->rx_jumbo_pending = i;
4459 break;
4460 }
4461 }
4462 }
4463 return 0;
4464 }
4465
4466 /*
4467 * Must not be invoked with interrupt sources disabled and
4468 * the hardware shutdown down.
4469 */
4470 static void tg3_free_consistent(struct tg3 *tp)
4471 {
4472 kfree(tp->rx_std_buffers);
4473 tp->rx_std_buffers = NULL;
4474 if (tp->rx_std) {
4475 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4476 tp->rx_std, tp->rx_std_mapping);
4477 tp->rx_std = NULL;
4478 }
4479 if (tp->rx_jumbo) {
4480 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4481 tp->rx_jumbo, tp->rx_jumbo_mapping);
4482 tp->rx_jumbo = NULL;
4483 }
4484 if (tp->rx_rcb) {
4485 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4486 tp->rx_rcb, tp->rx_rcb_mapping);
4487 tp->rx_rcb = NULL;
4488 }
4489 if (tp->tx_ring) {
4490 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4491 tp->tx_ring, tp->tx_desc_mapping);
4492 tp->tx_ring = NULL;
4493 }
4494 if (tp->hw_status) {
4495 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4496 tp->hw_status, tp->status_mapping);
4497 tp->hw_status = NULL;
4498 }
4499 if (tp->hw_stats) {
4500 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4501 tp->hw_stats, tp->stats_mapping);
4502 tp->hw_stats = NULL;
4503 }
4504 }
4505
4506 /*
4507 * Must not be invoked with interrupt sources disabled and
4508 * the hardware shutdown down. Can sleep.
4509 */
4510 static int tg3_alloc_consistent(struct tg3 *tp)
4511 {
4512 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4513 (TG3_RX_RING_SIZE +
4514 TG3_RX_JUMBO_RING_SIZE)) +
4515 (sizeof(struct tx_ring_info) *
4516 TG3_TX_RING_SIZE),
4517 GFP_KERNEL);
4518 if (!tp->rx_std_buffers)
4519 return -ENOMEM;
4520
4521 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4522 tp->tx_buffers = (struct tx_ring_info *)
4523 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4524
4525 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4526 &tp->rx_std_mapping);
4527 if (!tp->rx_std)
4528 goto err_out;
4529
4530 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4531 &tp->rx_jumbo_mapping);
4532
4533 if (!tp->rx_jumbo)
4534 goto err_out;
4535
4536 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4537 &tp->rx_rcb_mapping);
4538 if (!tp->rx_rcb)
4539 goto err_out;
4540
4541 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4542 &tp->tx_desc_mapping);
4543 if (!tp->tx_ring)
4544 goto err_out;
4545
4546 tp->hw_status = pci_alloc_consistent(tp->pdev,
4547 TG3_HW_STATUS_SIZE,
4548 &tp->status_mapping);
4549 if (!tp->hw_status)
4550 goto err_out;
4551
4552 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4553 sizeof(struct tg3_hw_stats),
4554 &tp->stats_mapping);
4555 if (!tp->hw_stats)
4556 goto err_out;
4557
4558 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4559 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4560
4561 return 0;
4562
4563 err_out:
4564 tg3_free_consistent(tp);
4565 return -ENOMEM;
4566 }
4567
4568 #define MAX_WAIT_CNT 1000
4569
4570 /* To stop a block, clear the enable bit and poll till it
4571 * clears. tp->lock is held.
4572 */
4573 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4574 {
4575 unsigned int i;
4576 u32 val;
4577
4578 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4579 switch (ofs) {
4580 case RCVLSC_MODE:
4581 case DMAC_MODE:
4582 case MBFREE_MODE:
4583 case BUFMGR_MODE:
4584 case MEMARB_MODE:
4585 /* We can't enable/disable these bits of the
4586 * 5705/5750, just say success.
4587 */
4588 return 0;
4589
4590 default:
4591 break;
4592 };
4593 }
4594
4595 val = tr32(ofs);
4596 val &= ~enable_bit;
4597 tw32_f(ofs, val);
4598
4599 for (i = 0; i < MAX_WAIT_CNT; i++) {
4600 udelay(100);
4601 val = tr32(ofs);
4602 if ((val & enable_bit) == 0)
4603 break;
4604 }
4605
4606 if (i == MAX_WAIT_CNT && !silent) {
4607 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4608 "ofs=%lx enable_bit=%x\n",
4609 ofs, enable_bit);
4610 return -ENODEV;
4611 }
4612
4613 return 0;
4614 }
4615
4616 /* tp->lock is held. */
4617 static int tg3_abort_hw(struct tg3 *tp, int silent)
4618 {
4619 int i, err;
4620
4621 tg3_disable_ints(tp);
4622
4623 tp->rx_mode &= ~RX_MODE_ENABLE;
4624 tw32_f(MAC_RX_MODE, tp->rx_mode);
4625 udelay(10);
4626
4627 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4628 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4629 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4630 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4631 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4632 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4633
4634 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4635 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4636 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4637 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4638 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4639 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4640 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4641
4642 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4643 tw32_f(MAC_MODE, tp->mac_mode);
4644 udelay(40);
4645
4646 tp->tx_mode &= ~TX_MODE_ENABLE;
4647 tw32_f(MAC_TX_MODE, tp->tx_mode);
4648
4649 for (i = 0; i < MAX_WAIT_CNT; i++) {
4650 udelay(100);
4651 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4652 break;
4653 }
4654 if (i >= MAX_WAIT_CNT) {
4655 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4656 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4657 tp->dev->name, tr32(MAC_TX_MODE));
4658 err |= -ENODEV;
4659 }
4660
4661 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4662 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4663 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4664
4665 tw32(FTQ_RESET, 0xffffffff);
4666 tw32(FTQ_RESET, 0x00000000);
4667
4668 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4669 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4670
4671 if (tp->hw_status)
4672 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4673 if (tp->hw_stats)
4674 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4675
4676 return err;
4677 }
4678
4679 /* tp->lock is held. */
4680 static int tg3_nvram_lock(struct tg3 *tp)
4681 {
4682 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4683 int i;
4684
4685 if (tp->nvram_lock_cnt == 0) {
4686 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4687 for (i = 0; i < 8000; i++) {
4688 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4689 break;
4690 udelay(20);
4691 }
4692 if (i == 8000) {
4693 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4694 return -ENODEV;
4695 }
4696 }
4697 tp->nvram_lock_cnt++;
4698 }
4699 return 0;
4700 }
4701
4702 /* tp->lock is held. */
4703 static void tg3_nvram_unlock(struct tg3 *tp)
4704 {
4705 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4706 if (tp->nvram_lock_cnt > 0)
4707 tp->nvram_lock_cnt--;
4708 if (tp->nvram_lock_cnt == 0)
4709 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4710 }
4711 }
4712
4713 /* tp->lock is held. */
4714 static void tg3_enable_nvram_access(struct tg3 *tp)
4715 {
4716 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4717 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4718 u32 nvaccess = tr32(NVRAM_ACCESS);
4719
4720 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4721 }
4722 }
4723
4724 /* tp->lock is held. */
4725 static void tg3_disable_nvram_access(struct tg3 *tp)
4726 {
4727 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4728 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4729 u32 nvaccess = tr32(NVRAM_ACCESS);
4730
4731 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4732 }
4733 }
4734
4735 /* tp->lock is held. */
4736 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4737 {
4738 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4739 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4740
4741 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4742 switch (kind) {
4743 case RESET_KIND_INIT:
4744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4745 DRV_STATE_START);
4746 break;
4747
4748 case RESET_KIND_SHUTDOWN:
4749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4750 DRV_STATE_UNLOAD);
4751 break;
4752
4753 case RESET_KIND_SUSPEND:
4754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4755 DRV_STATE_SUSPEND);
4756 break;
4757
4758 default:
4759 break;
4760 };
4761 }
4762 }
4763
4764 /* tp->lock is held. */
4765 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4766 {
4767 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4768 switch (kind) {
4769 case RESET_KIND_INIT:
4770 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4771 DRV_STATE_START_DONE);
4772 break;
4773
4774 case RESET_KIND_SHUTDOWN:
4775 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4776 DRV_STATE_UNLOAD_DONE);
4777 break;
4778
4779 default:
4780 break;
4781 };
4782 }
4783 }
4784
4785 /* tp->lock is held. */
4786 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4787 {
4788 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4789 switch (kind) {
4790 case RESET_KIND_INIT:
4791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4792 DRV_STATE_START);
4793 break;
4794
4795 case RESET_KIND_SHUTDOWN:
4796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4797 DRV_STATE_UNLOAD);
4798 break;
4799
4800 case RESET_KIND_SUSPEND:
4801 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4802 DRV_STATE_SUSPEND);
4803 break;
4804
4805 default:
4806 break;
4807 };
4808 }
4809 }
4810
4811 static int tg3_poll_fw(struct tg3 *tp)
4812 {
4813 int i;
4814 u32 val;
4815
4816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4817 /* Wait up to 20ms for init done. */
4818 for (i = 0; i < 200; i++) {
4819 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4820 return 0;
4821 udelay(100);
4822 }
4823 return -ENODEV;
4824 }
4825
4826 /* Wait for firmware initialization to complete. */
4827 for (i = 0; i < 100000; i++) {
4828 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4829 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4830 break;
4831 udelay(10);
4832 }
4833
4834 /* Chip might not be fitted with firmware. Some Sun onboard
4835 * parts are configured like that. So don't signal the timeout
4836 * of the above loop as an error, but do report the lack of
4837 * running firmware once.
4838 */
4839 if (i >= 100000 &&
4840 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4841 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4842
4843 printk(KERN_INFO PFX "%s: No firmware running.\n",
4844 tp->dev->name);
4845 }
4846
4847 return 0;
4848 }
4849
4850 /* Save PCI command register before chip reset */
4851 static void tg3_save_pci_state(struct tg3 *tp)
4852 {
4853 u32 val;
4854
4855 pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
4856 tp->pci_cmd = val;
4857 }
4858
4859 /* Restore PCI state after chip reset */
4860 static void tg3_restore_pci_state(struct tg3 *tp)
4861 {
4862 u32 val;
4863
4864 /* Re-enable indirect register accesses. */
4865 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4866 tp->misc_host_ctrl);
4867
4868 /* Set MAX PCI retry to zero. */
4869 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4870 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4871 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4872 val |= PCISTATE_RETRY_SAME_DMA;
4873 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4874
4875 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
4876
4877 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
4878 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
4879 tp->pci_cacheline_sz);
4880 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
4881 tp->pci_lat_timer);
4882 }
4883 /* Make sure PCI-X relaxed ordering bit is clear. */
4884 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4885 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4886 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4887
4888 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4889 u32 val;
4890
4891 /* Chip reset on 5780 will reset MSI enable bit,
4892 * so need to restore it.
4893 */
4894 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4895 u16 ctrl;
4896
4897 pci_read_config_word(tp->pdev,
4898 tp->msi_cap + PCI_MSI_FLAGS,
4899 &ctrl);
4900 pci_write_config_word(tp->pdev,
4901 tp->msi_cap + PCI_MSI_FLAGS,
4902 ctrl | PCI_MSI_FLAGS_ENABLE);
4903 val = tr32(MSGINT_MODE);
4904 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4905 }
4906 }
4907 }
4908
4909 static void tg3_stop_fw(struct tg3 *);
4910
4911 /* tp->lock is held. */
4912 static int tg3_chip_reset(struct tg3 *tp)
4913 {
4914 u32 val;
4915 void (*write_op)(struct tg3 *, u32, u32);
4916 int err;
4917
4918 tg3_nvram_lock(tp);
4919
4920 /* No matching tg3_nvram_unlock() after this because
4921 * chip reset below will undo the nvram lock.
4922 */
4923 tp->nvram_lock_cnt = 0;
4924
4925 /* GRC_MISC_CFG core clock reset will clear the memory
4926 * enable bit in PCI register 4 and the MSI enable bit
4927 * on some chips, so we save relevant registers here.
4928 */
4929 tg3_save_pci_state(tp);
4930
4931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4934 tw32(GRC_FASTBOOT_PC, 0);
4935
4936 /*
4937 * We must avoid the readl() that normally takes place.
4938 * It locks machines, causes machine checks, and other
4939 * fun things. So, temporarily disable the 5701
4940 * hardware workaround, while we do the reset.
4941 */
4942 write_op = tp->write32;
4943 if (write_op == tg3_write_flush_reg32)
4944 tp->write32 = tg3_write32;
4945
4946 /* Prevent the irq handler from reading or writing PCI registers
4947 * during chip reset when the memory enable bit in the PCI command
4948 * register may be cleared. The chip does not generate interrupt
4949 * at this time, but the irq handler may still be called due to irq
4950 * sharing or irqpoll.
4951 */
4952 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4953 if (tp->hw_status) {
4954 tp->hw_status->status = 0;
4955 tp->hw_status->status_tag = 0;
4956 }
4957 tp->last_tag = 0;
4958 smp_mb();
4959 synchronize_irq(tp->pdev->irq);
4960
4961 /* do the reset */
4962 val = GRC_MISC_CFG_CORECLK_RESET;
4963
4964 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4965 if (tr32(0x7e2c) == 0x60) {
4966 tw32(0x7e2c, 0x20);
4967 }
4968 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4969 tw32(GRC_MISC_CFG, (1 << 29));
4970 val |= (1 << 29);
4971 }
4972 }
4973
4974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4975 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4976 tw32(GRC_VCPU_EXT_CTRL,
4977 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4978 }
4979
4980 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4981 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4982 tw32(GRC_MISC_CFG, val);
4983
4984 /* restore 5701 hardware bug workaround write method */
4985 tp->write32 = write_op;
4986
4987 /* Unfortunately, we have to delay before the PCI read back.
4988 * Some 575X chips even will not respond to a PCI cfg access
4989 * when the reset command is given to the chip.
4990 *
4991 * How do these hardware designers expect things to work
4992 * properly if the PCI write is posted for a long period
4993 * of time? It is always necessary to have some method by
4994 * which a register read back can occur to push the write
4995 * out which does the reset.
4996 *
4997 * For most tg3 variants the trick below was working.
4998 * Ho hum...
4999 */
5000 udelay(120);
5001
5002 /* Flush PCI posted writes. The normal MMIO registers
5003 * are inaccessible at this time so this is the only
5004 * way to make this reliably (actually, this is no longer
5005 * the case, see above). I tried to use indirect
5006 * register read/write but this upset some 5701 variants.
5007 */
5008 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5009
5010 udelay(120);
5011
5012 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5013 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5014 int i;
5015 u32 cfg_val;
5016
5017 /* Wait for link training to complete. */
5018 for (i = 0; i < 5000; i++)
5019 udelay(100);
5020
5021 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5022 pci_write_config_dword(tp->pdev, 0xc4,
5023 cfg_val | (1 << 15));
5024 }
5025 /* Set PCIE max payload size and clear error status. */
5026 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5027 }
5028
5029 tg3_restore_pci_state(tp);
5030
5031 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5032
5033 val = 0;
5034 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5035 val = tr32(MEMARB_MODE);
5036 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5037
5038 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5039 tg3_stop_fw(tp);
5040 tw32(0x5000, 0x400);
5041 }
5042
5043 tw32(GRC_MODE, tp->grc_mode);
5044
5045 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5046 u32 val = tr32(0xc4);
5047
5048 tw32(0xc4, val | (1 << 15));
5049 }
5050
5051 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5053 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5054 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5055 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5056 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5057 }
5058
5059 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5060 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5061 tw32_f(MAC_MODE, tp->mac_mode);
5062 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5063 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5064 tw32_f(MAC_MODE, tp->mac_mode);
5065 } else
5066 tw32_f(MAC_MODE, 0);
5067 udelay(40);
5068
5069 err = tg3_poll_fw(tp);
5070 if (err)
5071 return err;
5072
5073 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5074 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5075 u32 val = tr32(0x7c00);
5076
5077 tw32(0x7c00, val | (1 << 25));
5078 }
5079
5080 /* Reprobe ASF enable state. */
5081 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5082 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5083 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5084 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5085 u32 nic_cfg;
5086
5087 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5088 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5089 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5090 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5091 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5092 }
5093 }
5094
5095 return 0;
5096 }
5097
5098 /* tp->lock is held. */
5099 static void tg3_stop_fw(struct tg3 *tp)
5100 {
5101 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5102 u32 val;
5103 int i;
5104
5105 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5106 val = tr32(GRC_RX_CPU_EVENT);
5107 val |= (1 << 14);
5108 tw32(GRC_RX_CPU_EVENT, val);
5109
5110 /* Wait for RX cpu to ACK the event. */
5111 for (i = 0; i < 100; i++) {
5112 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5113 break;
5114 udelay(1);
5115 }
5116 }
5117 }
5118
5119 /* tp->lock is held. */
5120 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5121 {
5122 int err;
5123
5124 tg3_stop_fw(tp);
5125
5126 tg3_write_sig_pre_reset(tp, kind);
5127
5128 tg3_abort_hw(tp, silent);
5129 err = tg3_chip_reset(tp);
5130
5131 tg3_write_sig_legacy(tp, kind);
5132 tg3_write_sig_post_reset(tp, kind);
5133
5134 if (err)
5135 return err;
5136
5137 return 0;
5138 }
5139
5140 #define TG3_FW_RELEASE_MAJOR 0x0
5141 #define TG3_FW_RELASE_MINOR 0x0
5142 #define TG3_FW_RELEASE_FIX 0x0
5143 #define TG3_FW_START_ADDR 0x08000000
5144 #define TG3_FW_TEXT_ADDR 0x08000000
5145 #define TG3_FW_TEXT_LEN 0x9c0
5146 #define TG3_FW_RODATA_ADDR 0x080009c0
5147 #define TG3_FW_RODATA_LEN 0x60
5148 #define TG3_FW_DATA_ADDR 0x08000a40
5149 #define TG3_FW_DATA_LEN 0x20
5150 #define TG3_FW_SBSS_ADDR 0x08000a60
5151 #define TG3_FW_SBSS_LEN 0xc
5152 #define TG3_FW_BSS_ADDR 0x08000a70
5153 #define TG3_FW_BSS_LEN 0x10
5154
5155 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5156 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5157 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5158 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5159 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5160 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5161 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5162 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5163 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5164 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5165 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5166 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5167 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5168 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5169 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5170 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5171 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5172 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5173 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5174 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5175 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5176 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5177 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5178 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5179 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5180 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5181 0, 0, 0, 0, 0, 0,
5182 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5183 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5184 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5185 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5186 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5187 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5188 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5189 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5190 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5191 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5192 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5194 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5195 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5196 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5197 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5198 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5199 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5200 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5201 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5202 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5203 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5204 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5205 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5206 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5207 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5208 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5209 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5210 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5211 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5212 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5213 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5214 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5215 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5216 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5217 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5218 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5219 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5220 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5221 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5222 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5223 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5224 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5225 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5226 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5227 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5228 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5229 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5230 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5231 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5232 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5233 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5234 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5235 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5236 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5237 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5238 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5239 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5240 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5241 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5242 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5243 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5244 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5245 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5246 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5247 };
5248
5249 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5250 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5251 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5252 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5253 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5254 0x00000000
5255 };
5256
5257 #if 0 /* All zeros, don't eat up space with it. */
5258 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5259 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5260 0x00000000, 0x00000000, 0x00000000, 0x00000000
5261 };
5262 #endif
5263
5264 #define RX_CPU_SCRATCH_BASE 0x30000
5265 #define RX_CPU_SCRATCH_SIZE 0x04000
5266 #define TX_CPU_SCRATCH_BASE 0x34000
5267 #define TX_CPU_SCRATCH_SIZE 0x04000
5268
5269 /* tp->lock is held. */
5270 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5271 {
5272 int i;
5273
5274 BUG_ON(offset == TX_CPU_BASE &&
5275 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5276
5277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5278 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5279
5280 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5281 return 0;
5282 }
5283 if (offset == RX_CPU_BASE) {
5284 for (i = 0; i < 10000; i++) {
5285 tw32(offset + CPU_STATE, 0xffffffff);
5286 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5287 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5288 break;
5289 }
5290
5291 tw32(offset + CPU_STATE, 0xffffffff);
5292 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5293 udelay(10);
5294 } else {
5295 for (i = 0; i < 10000; i++) {
5296 tw32(offset + CPU_STATE, 0xffffffff);
5297 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5298 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5299 break;
5300 }
5301 }
5302
5303 if (i >= 10000) {
5304 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5305 "and %s CPU\n",
5306 tp->dev->name,
5307 (offset == RX_CPU_BASE ? "RX" : "TX"));
5308 return -ENODEV;
5309 }
5310
5311 /* Clear firmware's nvram arbitration. */
5312 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5313 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5314 return 0;
5315 }
5316
5317 struct fw_info {
5318 unsigned int text_base;
5319 unsigned int text_len;
5320 const u32 *text_data;
5321 unsigned int rodata_base;
5322 unsigned int rodata_len;
5323 const u32 *rodata_data;
5324 unsigned int data_base;
5325 unsigned int data_len;
5326 const u32 *data_data;
5327 };
5328
5329 /* tp->lock is held. */
5330 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5331 int cpu_scratch_size, struct fw_info *info)
5332 {
5333 int err, lock_err, i;
5334 void (*write_op)(struct tg3 *, u32, u32);
5335
5336 if (cpu_base == TX_CPU_BASE &&
5337 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5338 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5339 "TX cpu firmware on %s which is 5705.\n",
5340 tp->dev->name);
5341 return -EINVAL;
5342 }
5343
5344 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5345 write_op = tg3_write_mem;
5346 else
5347 write_op = tg3_write_indirect_reg32;
5348
5349 /* It is possible that bootcode is still loading at this point.
5350 * Get the nvram lock first before halting the cpu.
5351 */
5352 lock_err = tg3_nvram_lock(tp);
5353 err = tg3_halt_cpu(tp, cpu_base);
5354 if (!lock_err)
5355 tg3_nvram_unlock(tp);
5356 if (err)
5357 goto out;
5358
5359 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5360 write_op(tp, cpu_scratch_base + i, 0);
5361 tw32(cpu_base + CPU_STATE, 0xffffffff);
5362 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5363 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5364 write_op(tp, (cpu_scratch_base +
5365 (info->text_base & 0xffff) +
5366 (i * sizeof(u32))),
5367 (info->text_data ?
5368 info->text_data[i] : 0));
5369 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5370 write_op(tp, (cpu_scratch_base +
5371 (info->rodata_base & 0xffff) +
5372 (i * sizeof(u32))),
5373 (info->rodata_data ?
5374 info->rodata_data[i] : 0));
5375 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5376 write_op(tp, (cpu_scratch_base +
5377 (info->data_base & 0xffff) +
5378 (i * sizeof(u32))),
5379 (info->data_data ?
5380 info->data_data[i] : 0));
5381
5382 err = 0;
5383
5384 out:
5385 return err;
5386 }
5387
5388 /* tp->lock is held. */
5389 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5390 {
5391 struct fw_info info;
5392 int err, i;
5393
5394 info.text_base = TG3_FW_TEXT_ADDR;
5395 info.text_len = TG3_FW_TEXT_LEN;
5396 info.text_data = &tg3FwText[0];
5397 info.rodata_base = TG3_FW_RODATA_ADDR;
5398 info.rodata_len = TG3_FW_RODATA_LEN;
5399 info.rodata_data = &tg3FwRodata[0];
5400 info.data_base = TG3_FW_DATA_ADDR;
5401 info.data_len = TG3_FW_DATA_LEN;
5402 info.data_data = NULL;
5403
5404 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5405 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5406 &info);
5407 if (err)
5408 return err;
5409
5410 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5411 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5412 &info);
5413 if (err)
5414 return err;
5415
5416 /* Now startup only the RX cpu. */
5417 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5418 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5419
5420 for (i = 0; i < 5; i++) {
5421 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5422 break;
5423 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5424 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5425 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5426 udelay(1000);
5427 }
5428 if (i >= 5) {
5429 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5430 "to set RX CPU PC, is %08x should be %08x\n",
5431 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5432 TG3_FW_TEXT_ADDR);
5433 return -ENODEV;
5434 }
5435 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5436 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5437
5438 return 0;
5439 }
5440
5441
5442 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5443 #define TG3_TSO_FW_RELASE_MINOR 0x6
5444 #define TG3_TSO_FW_RELEASE_FIX 0x0
5445 #define TG3_TSO_FW_START_ADDR 0x08000000
5446 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5447 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5448 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5449 #define TG3_TSO_FW_RODATA_LEN 0x60
5450 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5451 #define TG3_TSO_FW_DATA_LEN 0x30
5452 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5453 #define TG3_TSO_FW_SBSS_LEN 0x2c
5454 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5455 #define TG3_TSO_FW_BSS_LEN 0x894
5456
5457 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5458 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5459 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5460 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5461 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5462 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5463 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5464 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5465 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5466 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5467 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5468 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5469 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5470 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5471 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5472 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5473 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5474 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5475 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5476 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5477 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5478 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5479 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5480 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5481 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5482 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5483 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5484 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5485 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5486 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5487 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5488 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5489 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5490 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5491 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5492 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5493 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5494 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5495 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5496 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5497 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5498 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5499 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5500 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5501 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5502 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5503 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5504 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5505 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5506 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5507 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5508 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5509 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5510 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5511 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5512 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5513 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5514 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5515 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5516 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5517 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5518 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5519 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5520 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5521 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5522 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5523 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5524 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5525 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5526 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5527 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5528 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5529 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5530 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5531 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5532 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5533 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5534 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5535 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5536 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5537 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5538 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5539 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5540 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5541 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5542 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5543 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5544 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5545 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5546 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5547 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5548 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5549 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5550 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5551 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5552 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5553 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5554 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5555 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5556 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5557 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5558 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5559 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5560 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5561 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5562 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5563 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5564 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5565 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5566 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5567 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5568 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5569 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5570 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5571 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5572 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5573 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5574 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5575 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5576 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5577 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5578 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5579 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5580 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5581 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5582 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5583 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5584 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5585 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5586 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5587 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5588 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5589 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5590 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5591 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5592 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5593 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5594 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5595 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5596 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5597 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5598 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5599 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5600 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5601 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5602 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5603 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5604 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5605 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5606 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5607 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5608 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5609 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5610 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5611 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5612 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5613 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5614 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5615 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5616 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5617 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5618 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5619 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5620 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5621 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5622 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5623 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5624 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5625 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5626 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5627 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5628 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5629 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5630 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5631 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5632 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5633 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5634 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5635 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5636 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5637 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5638 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5639 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5640 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5641 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5642 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5643 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5644 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5645 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5646 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5647 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5648 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5649 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5650 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5651 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5652 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5653 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5654 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5655 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5656 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5657 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5658 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5659 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5660 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5661 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5662 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5663 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5664 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5665 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5666 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5667 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5668 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5669 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5670 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5671 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5672 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5673 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5674 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5675 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5676 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5677 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5678 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5679 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5680 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5681 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5682 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5683 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5684 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5685 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5686 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5687 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5688 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5689 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5690 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5691 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5692 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5693 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5694 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5695 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5696 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5697 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5698 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5699 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5700 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5701 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5702 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5703 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5704 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5705 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5706 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5707 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5708 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5709 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5710 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5711 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5712 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5713 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5714 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5715 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5716 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5717 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5718 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5719 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5720 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5721 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5722 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5723 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5724 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5725 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5726 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5727 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5728 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5729 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5730 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5731 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5732 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5733 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5734 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5735 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5736 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5737 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5738 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5739 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5740 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5741 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5742 };
5743
5744 static const u32 tg3TsoFwRodata[] = {
5745 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5746 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5747 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5748 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5749 0x00000000,
5750 };
5751
5752 static const u32 tg3TsoFwData[] = {
5753 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5754 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5755 0x00000000,
5756 };
5757
5758 /* 5705 needs a special version of the TSO firmware. */
5759 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5760 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5761 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5762 #define TG3_TSO5_FW_START_ADDR 0x00010000
5763 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5764 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5765 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5766 #define TG3_TSO5_FW_RODATA_LEN 0x50
5767 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5768 #define TG3_TSO5_FW_DATA_LEN 0x20
5769 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5770 #define TG3_TSO5_FW_SBSS_LEN 0x28
5771 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5772 #define TG3_TSO5_FW_BSS_LEN 0x88
5773
5774 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5775 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5776 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5777 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5778 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5779 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5780 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5781 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5782 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5783 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5784 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5785 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5786 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5787 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5788 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5789 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5790 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5791 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5792 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5793 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5794 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5795 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5796 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5797 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5798 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5799 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5800 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5801 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5802 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5803 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5804 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5805 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5806 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5807 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5808 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5809 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5810 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5811 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5812 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5813 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5814 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5815 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5816 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5817 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5818 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5819 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5820 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5821 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5822 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5823 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5824 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5825 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5826 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5827 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5828 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5829 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5830 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5831 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5832 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5833 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5834 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5835 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5836 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5837 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5838 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5839 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5840 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5841 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5842 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5843 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5844 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5845 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5846 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5847 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5848 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5849 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5850 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5851 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5852 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5853 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5854 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5855 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5856 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5857 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5858 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5859 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5860 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5861 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5862 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5863 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5864 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5865 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5866 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5867 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5868 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5869 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5870 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5871 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5872 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5873 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5874 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5875 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5876 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5877 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5878 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5879 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5880 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5881 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5882 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5883 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5884 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5885 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5886 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5887 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5888 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5889 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5890 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5891 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5892 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5893 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5894 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5895 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5896 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5897 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5898 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5899 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5900 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5901 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5902 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5903 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5904 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5905 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5906 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5907 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5908 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5909 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5910 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5911 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5912 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5913 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5914 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5915 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5916 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5917 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5918 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5919 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5920 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5921 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5922 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5923 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5924 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5925 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5926 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5927 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5928 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5929 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5930 0x00000000, 0x00000000, 0x00000000,
5931 };
5932
5933 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5934 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5935 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5936 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5937 0x00000000, 0x00000000, 0x00000000,
5938 };
5939
5940 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5941 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5942 0x00000000, 0x00000000, 0x00000000,
5943 };
5944
5945 /* tp->lock is held. */
5946 static int tg3_load_tso_firmware(struct tg3 *tp)
5947 {
5948 struct fw_info info;
5949 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5950 int err, i;
5951
5952 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5953 return 0;
5954
5955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5956 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5957 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5958 info.text_data = &tg3Tso5FwText[0];
5959 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5960 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5961 info.rodata_data = &tg3Tso5FwRodata[0];
5962 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5963 info.data_len = TG3_TSO5_FW_DATA_LEN;
5964 info.data_data = &tg3Tso5FwData[0];
5965 cpu_base = RX_CPU_BASE;
5966 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5967 cpu_scratch_size = (info.text_len +
5968 info.rodata_len +
5969 info.data_len +
5970 TG3_TSO5_FW_SBSS_LEN +
5971 TG3_TSO5_FW_BSS_LEN);
5972 } else {
5973 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5974 info.text_len = TG3_TSO_FW_TEXT_LEN;
5975 info.text_data = &tg3TsoFwText[0];
5976 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5977 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5978 info.rodata_data = &tg3TsoFwRodata[0];
5979 info.data_base = TG3_TSO_FW_DATA_ADDR;
5980 info.data_len = TG3_TSO_FW_DATA_LEN;
5981 info.data_data = &tg3TsoFwData[0];
5982 cpu_base = TX_CPU_BASE;
5983 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5984 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5985 }
5986
5987 err = tg3_load_firmware_cpu(tp, cpu_base,
5988 cpu_scratch_base, cpu_scratch_size,
5989 &info);
5990 if (err)
5991 return err;
5992
5993 /* Now startup the cpu. */
5994 tw32(cpu_base + CPU_STATE, 0xffffffff);
5995 tw32_f(cpu_base + CPU_PC, info.text_base);
5996
5997 for (i = 0; i < 5; i++) {
5998 if (tr32(cpu_base + CPU_PC) == info.text_base)
5999 break;
6000 tw32(cpu_base + CPU_STATE, 0xffffffff);
6001 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6002 tw32_f(cpu_base + CPU_PC, info.text_base);
6003 udelay(1000);
6004 }
6005 if (i >= 5) {
6006 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6007 "to set CPU PC, is %08x should be %08x\n",
6008 tp->dev->name, tr32(cpu_base + CPU_PC),
6009 info.text_base);
6010 return -ENODEV;
6011 }
6012 tw32(cpu_base + CPU_STATE, 0xffffffff);
6013 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6014 return 0;
6015 }
6016
6017
6018 /* tp->lock is held. */
6019 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6020 {
6021 u32 addr_high, addr_low;
6022 int i;
6023
6024 addr_high = ((tp->dev->dev_addr[0] << 8) |
6025 tp->dev->dev_addr[1]);
6026 addr_low = ((tp->dev->dev_addr[2] << 24) |
6027 (tp->dev->dev_addr[3] << 16) |
6028 (tp->dev->dev_addr[4] << 8) |
6029 (tp->dev->dev_addr[5] << 0));
6030 for (i = 0; i < 4; i++) {
6031 if (i == 1 && skip_mac_1)
6032 continue;
6033 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6034 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6035 }
6036
6037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6039 for (i = 0; i < 12; i++) {
6040 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6041 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6042 }
6043 }
6044
6045 addr_high = (tp->dev->dev_addr[0] +
6046 tp->dev->dev_addr[1] +
6047 tp->dev->dev_addr[2] +
6048 tp->dev->dev_addr[3] +
6049 tp->dev->dev_addr[4] +
6050 tp->dev->dev_addr[5]) &
6051 TX_BACKOFF_SEED_MASK;
6052 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6053 }
6054
6055 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6056 {
6057 struct tg3 *tp = netdev_priv(dev);
6058 struct sockaddr *addr = p;
6059 int err = 0, skip_mac_1 = 0;
6060
6061 if (!is_valid_ether_addr(addr->sa_data))
6062 return -EINVAL;
6063
6064 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6065
6066 if (!netif_running(dev))
6067 return 0;
6068
6069 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6070 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6071
6072 addr0_high = tr32(MAC_ADDR_0_HIGH);
6073 addr0_low = tr32(MAC_ADDR_0_LOW);
6074 addr1_high = tr32(MAC_ADDR_1_HIGH);
6075 addr1_low = tr32(MAC_ADDR_1_LOW);
6076
6077 /* Skip MAC addr 1 if ASF is using it. */
6078 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6079 !(addr1_high == 0 && addr1_low == 0))
6080 skip_mac_1 = 1;
6081 }
6082 spin_lock_bh(&tp->lock);
6083 __tg3_set_mac_addr(tp, skip_mac_1);
6084 spin_unlock_bh(&tp->lock);
6085
6086 return err;
6087 }
6088
6089 /* tp->lock is held. */
6090 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6091 dma_addr_t mapping, u32 maxlen_flags,
6092 u32 nic_addr)
6093 {
6094 tg3_write_mem(tp,
6095 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6096 ((u64) mapping >> 32));
6097 tg3_write_mem(tp,
6098 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6099 ((u64) mapping & 0xffffffff));
6100 tg3_write_mem(tp,
6101 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6102 maxlen_flags);
6103
6104 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6105 tg3_write_mem(tp,
6106 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6107 nic_addr);
6108 }
6109
6110 static void __tg3_set_rx_mode(struct net_device *);
6111 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6112 {
6113 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6114 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6115 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6116 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6117 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6118 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6119 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6120 }
6121 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6122 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6123 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6124 u32 val = ec->stats_block_coalesce_usecs;
6125
6126 if (!netif_carrier_ok(tp->dev))
6127 val = 0;
6128
6129 tw32(HOSTCC_STAT_COAL_TICKS, val);
6130 }
6131 }
6132
6133 /* tp->lock is held. */
6134 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6135 {
6136 u32 val, rdmac_mode;
6137 int i, err, limit;
6138
6139 tg3_disable_ints(tp);
6140
6141 tg3_stop_fw(tp);
6142
6143 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6144
6145 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6146 tg3_abort_hw(tp, 1);
6147 }
6148
6149 if (reset_phy)
6150 tg3_phy_reset(tp);
6151
6152 err = tg3_chip_reset(tp);
6153 if (err)
6154 return err;
6155
6156 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6157
6158 /* This works around an issue with Athlon chipsets on
6159 * B3 tigon3 silicon. This bit has no effect on any
6160 * other revision. But do not set this on PCI Express
6161 * chips.
6162 */
6163 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6164 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6165 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6166
6167 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6168 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6169 val = tr32(TG3PCI_PCISTATE);
6170 val |= PCISTATE_RETRY_SAME_DMA;
6171 tw32(TG3PCI_PCISTATE, val);
6172 }
6173
6174 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6175 /* Enable some hw fixes. */
6176 val = tr32(TG3PCI_MSI_DATA);
6177 val |= (1 << 26) | (1 << 28) | (1 << 29);
6178 tw32(TG3PCI_MSI_DATA, val);
6179 }
6180
6181 /* Descriptor ring init may make accesses to the
6182 * NIC SRAM area to setup the TX descriptors, so we
6183 * can only do this after the hardware has been
6184 * successfully reset.
6185 */
6186 err = tg3_init_rings(tp);
6187 if (err)
6188 return err;
6189
6190 /* This value is determined during the probe time DMA
6191 * engine test, tg3_test_dma.
6192 */
6193 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6194
6195 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6196 GRC_MODE_4X_NIC_SEND_RINGS |
6197 GRC_MODE_NO_TX_PHDR_CSUM |
6198 GRC_MODE_NO_RX_PHDR_CSUM);
6199 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6200
6201 /* Pseudo-header checksum is done by hardware logic and not
6202 * the offload processers, so make the chip do the pseudo-
6203 * header checksums on receive. For transmit it is more
6204 * convenient to do the pseudo-header checksum in software
6205 * as Linux does that on transmit for us in all cases.
6206 */
6207 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6208
6209 tw32(GRC_MODE,
6210 tp->grc_mode |
6211 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6212
6213 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6214 val = tr32(GRC_MISC_CFG);
6215 val &= ~0xff;
6216 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6217 tw32(GRC_MISC_CFG, val);
6218
6219 /* Initialize MBUF/DESC pool. */
6220 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6221 /* Do nothing. */
6222 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6223 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6225 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6226 else
6227 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6228 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6229 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6230 }
6231 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6232 int fw_len;
6233
6234 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6235 TG3_TSO5_FW_RODATA_LEN +
6236 TG3_TSO5_FW_DATA_LEN +
6237 TG3_TSO5_FW_SBSS_LEN +
6238 TG3_TSO5_FW_BSS_LEN);
6239 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6240 tw32(BUFMGR_MB_POOL_ADDR,
6241 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6242 tw32(BUFMGR_MB_POOL_SIZE,
6243 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6244 }
6245
6246 if (tp->dev->mtu <= ETH_DATA_LEN) {
6247 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6248 tp->bufmgr_config.mbuf_read_dma_low_water);
6249 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6250 tp->bufmgr_config.mbuf_mac_rx_low_water);
6251 tw32(BUFMGR_MB_HIGH_WATER,
6252 tp->bufmgr_config.mbuf_high_water);
6253 } else {
6254 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6255 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6256 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6257 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6258 tw32(BUFMGR_MB_HIGH_WATER,
6259 tp->bufmgr_config.mbuf_high_water_jumbo);
6260 }
6261 tw32(BUFMGR_DMA_LOW_WATER,
6262 tp->bufmgr_config.dma_low_water);
6263 tw32(BUFMGR_DMA_HIGH_WATER,
6264 tp->bufmgr_config.dma_high_water);
6265
6266 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6267 for (i = 0; i < 2000; i++) {
6268 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6269 break;
6270 udelay(10);
6271 }
6272 if (i >= 2000) {
6273 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6274 tp->dev->name);
6275 return -ENODEV;
6276 }
6277
6278 /* Setup replenish threshold. */
6279 val = tp->rx_pending / 8;
6280 if (val == 0)
6281 val = 1;
6282 else if (val > tp->rx_std_max_post)
6283 val = tp->rx_std_max_post;
6284 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6285 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6286 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6287
6288 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6289 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6290 }
6291
6292 tw32(RCVBDI_STD_THRESH, val);
6293
6294 /* Initialize TG3_BDINFO's at:
6295 * RCVDBDI_STD_BD: standard eth size rx ring
6296 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6297 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6298 *
6299 * like so:
6300 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6301 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6302 * ring attribute flags
6303 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6304 *
6305 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6306 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6307 *
6308 * The size of each ring is fixed in the firmware, but the location is
6309 * configurable.
6310 */
6311 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6312 ((u64) tp->rx_std_mapping >> 32));
6313 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6314 ((u64) tp->rx_std_mapping & 0xffffffff));
6315 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6316 NIC_SRAM_RX_BUFFER_DESC);
6317
6318 /* Don't even try to program the JUMBO/MINI buffer descriptor
6319 * configs on 5705.
6320 */
6321 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6322 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6323 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6324 } else {
6325 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6326 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6327
6328 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6329 BDINFO_FLAGS_DISABLED);
6330
6331 /* Setup replenish threshold. */
6332 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6333
6334 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6335 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6336 ((u64) tp->rx_jumbo_mapping >> 32));
6337 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6338 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6339 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6340 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6341 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6342 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6343 } else {
6344 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6345 BDINFO_FLAGS_DISABLED);
6346 }
6347
6348 }
6349
6350 /* There is only one send ring on 5705/5750, no need to explicitly
6351 * disable the others.
6352 */
6353 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6354 /* Clear out send RCB ring in SRAM. */
6355 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6356 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6357 BDINFO_FLAGS_DISABLED);
6358 }
6359
6360 tp->tx_prod = 0;
6361 tp->tx_cons = 0;
6362 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6363 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6364
6365 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6366 tp->tx_desc_mapping,
6367 (TG3_TX_RING_SIZE <<
6368 BDINFO_FLAGS_MAXLEN_SHIFT),
6369 NIC_SRAM_TX_BUFFER_DESC);
6370
6371 /* There is only one receive return ring on 5705/5750, no need
6372 * to explicitly disable the others.
6373 */
6374 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6375 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6376 i += TG3_BDINFO_SIZE) {
6377 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6378 BDINFO_FLAGS_DISABLED);
6379 }
6380 }
6381
6382 tp->rx_rcb_ptr = 0;
6383 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6384
6385 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6386 tp->rx_rcb_mapping,
6387 (TG3_RX_RCB_RING_SIZE(tp) <<
6388 BDINFO_FLAGS_MAXLEN_SHIFT),
6389 0);
6390
6391 tp->rx_std_ptr = tp->rx_pending;
6392 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6393 tp->rx_std_ptr);
6394
6395 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6396 tp->rx_jumbo_pending : 0;
6397 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6398 tp->rx_jumbo_ptr);
6399
6400 /* Initialize MAC address and backoff seed. */
6401 __tg3_set_mac_addr(tp, 0);
6402
6403 /* MTU + ethernet header + FCS + optional VLAN tag */
6404 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6405
6406 /* The slot time is changed by tg3_setup_phy if we
6407 * run at gigabit with half duplex.
6408 */
6409 tw32(MAC_TX_LENGTHS,
6410 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6411 (6 << TX_LENGTHS_IPG_SHIFT) |
6412 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6413
6414 /* Receive rules. */
6415 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6416 tw32(RCVLPC_CONFIG, 0x0181);
6417
6418 /* Calculate RDMAC_MODE setting early, we need it to determine
6419 * the RCVLPC_STATE_ENABLE mask.
6420 */
6421 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6422 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6423 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6424 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6425 RDMAC_MODE_LNGREAD_ENAB);
6426
6427 /* If statement applies to 5705 and 5750 PCI devices only */
6428 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6429 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6430 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6431 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6432 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6433 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6434 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6435 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6436 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6437 }
6438 }
6439
6440 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6441 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6442
6443 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6444 rdmac_mode |= (1 << 27);
6445
6446 /* Receive/send statistics. */
6447 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6448 val = tr32(RCVLPC_STATS_ENABLE);
6449 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6450 tw32(RCVLPC_STATS_ENABLE, val);
6451 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6452 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6453 val = tr32(RCVLPC_STATS_ENABLE);
6454 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6455 tw32(RCVLPC_STATS_ENABLE, val);
6456 } else {
6457 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6458 }
6459 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6460 tw32(SNDDATAI_STATSENAB, 0xffffff);
6461 tw32(SNDDATAI_STATSCTRL,
6462 (SNDDATAI_SCTRL_ENABLE |
6463 SNDDATAI_SCTRL_FASTUPD));
6464
6465 /* Setup host coalescing engine. */
6466 tw32(HOSTCC_MODE, 0);
6467 for (i = 0; i < 2000; i++) {
6468 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6469 break;
6470 udelay(10);
6471 }
6472
6473 __tg3_set_coalesce(tp, &tp->coal);
6474
6475 /* set status block DMA address */
6476 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6477 ((u64) tp->status_mapping >> 32));
6478 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6479 ((u64) tp->status_mapping & 0xffffffff));
6480
6481 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6482 /* Status/statistics block address. See tg3_timer,
6483 * the tg3_periodic_fetch_stats call there, and
6484 * tg3_get_stats to see how this works for 5705/5750 chips.
6485 */
6486 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6487 ((u64) tp->stats_mapping >> 32));
6488 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6489 ((u64) tp->stats_mapping & 0xffffffff));
6490 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6491 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6492 }
6493
6494 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6495
6496 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6497 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6498 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6499 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6500
6501 /* Clear statistics/status block in chip, and status block in ram. */
6502 for (i = NIC_SRAM_STATS_BLK;
6503 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6504 i += sizeof(u32)) {
6505 tg3_write_mem(tp, i, 0);
6506 udelay(40);
6507 }
6508 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6509
6510 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6511 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6512 /* reset to prevent losing 1st rx packet intermittently */
6513 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6514 udelay(10);
6515 }
6516
6517 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6518 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6519 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6520 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6521 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6522 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6523 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6524 udelay(40);
6525
6526 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6527 * If TG3_FLG2_IS_NIC is zero, we should read the
6528 * register to preserve the GPIO settings for LOMs. The GPIOs,
6529 * whether used as inputs or outputs, are set by boot code after
6530 * reset.
6531 */
6532 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6533 u32 gpio_mask;
6534
6535 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6536 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6537 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6538
6539 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6540 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6541 GRC_LCLCTRL_GPIO_OUTPUT3;
6542
6543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6544 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6545
6546 tp->grc_local_ctrl &= ~gpio_mask;
6547 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6548
6549 /* GPIO1 must be driven high for eeprom write protect */
6550 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6551 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6552 GRC_LCLCTRL_GPIO_OUTPUT1);
6553 }
6554 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6555 udelay(100);
6556
6557 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6558 tp->last_tag = 0;
6559
6560 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6561 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6562 udelay(40);
6563 }
6564
6565 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6566 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6567 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6568 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6569 WDMAC_MODE_LNGREAD_ENAB);
6570
6571 /* If statement applies to 5705 and 5750 PCI devices only */
6572 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6573 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6575 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6576 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6577 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6578 /* nothing */
6579 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6580 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6581 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6582 val |= WDMAC_MODE_RX_ACCEL;
6583 }
6584 }
6585
6586 /* Enable host coalescing bug fix */
6587 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6588 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6589 val |= (1 << 29);
6590
6591 tw32_f(WDMAC_MODE, val);
6592 udelay(40);
6593
6594 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6595 val = tr32(TG3PCI_X_CAPS);
6596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6597 val &= ~PCIX_CAPS_BURST_MASK;
6598 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6599 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6600 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6601 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6602 }
6603 tw32(TG3PCI_X_CAPS, val);
6604 }
6605
6606 tw32_f(RDMAC_MODE, rdmac_mode);
6607 udelay(40);
6608
6609 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6610 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6611 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6612 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6613 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6614 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6615 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6616 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6617 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6618 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6619 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6620 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6621
6622 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6623 err = tg3_load_5701_a0_firmware_fix(tp);
6624 if (err)
6625 return err;
6626 }
6627
6628 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6629 err = tg3_load_tso_firmware(tp);
6630 if (err)
6631 return err;
6632 }
6633
6634 tp->tx_mode = TX_MODE_ENABLE;
6635 tw32_f(MAC_TX_MODE, tp->tx_mode);
6636 udelay(100);
6637
6638 tp->rx_mode = RX_MODE_ENABLE;
6639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6640 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6641
6642 tw32_f(MAC_RX_MODE, tp->rx_mode);
6643 udelay(10);
6644
6645 if (tp->link_config.phy_is_low_power) {
6646 tp->link_config.phy_is_low_power = 0;
6647 tp->link_config.speed = tp->link_config.orig_speed;
6648 tp->link_config.duplex = tp->link_config.orig_duplex;
6649 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6650 }
6651
6652 tp->mi_mode = MAC_MI_MODE_BASE;
6653 tw32_f(MAC_MI_MODE, tp->mi_mode);
6654 udelay(80);
6655
6656 tw32(MAC_LED_CTRL, tp->led_ctrl);
6657
6658 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6659 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6660 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6661 udelay(10);
6662 }
6663 tw32_f(MAC_RX_MODE, tp->rx_mode);
6664 udelay(10);
6665
6666 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6667 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6668 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6669 /* Set drive transmission level to 1.2V */
6670 /* only if the signal pre-emphasis bit is not set */
6671 val = tr32(MAC_SERDES_CFG);
6672 val &= 0xfffff000;
6673 val |= 0x880;
6674 tw32(MAC_SERDES_CFG, val);
6675 }
6676 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6677 tw32(MAC_SERDES_CFG, 0x616000);
6678 }
6679
6680 /* Prevent chip from dropping frames when flow control
6681 * is enabled.
6682 */
6683 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6684
6685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6686 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6687 /* Use hardware link auto-negotiation */
6688 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6689 }
6690
6691 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6692 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6693 u32 tmp;
6694
6695 tmp = tr32(SERDES_RX_CTRL);
6696 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6697 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6698 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6699 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6700 }
6701
6702 err = tg3_setup_phy(tp, 0);
6703 if (err)
6704 return err;
6705
6706 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6707 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6708 u32 tmp;
6709
6710 /* Clear CRC stats. */
6711 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6712 tg3_writephy(tp, MII_TG3_TEST1,
6713 tmp | MII_TG3_TEST1_CRC_EN);
6714 tg3_readphy(tp, 0x14, &tmp);
6715 }
6716 }
6717
6718 __tg3_set_rx_mode(tp->dev);
6719
6720 /* Initialize receive rules. */
6721 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6722 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6723 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6724 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6725
6726 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6727 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6728 limit = 8;
6729 else
6730 limit = 16;
6731 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6732 limit -= 4;
6733 switch (limit) {
6734 case 16:
6735 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6736 case 15:
6737 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6738 case 14:
6739 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6740 case 13:
6741 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6742 case 12:
6743 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6744 case 11:
6745 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6746 case 10:
6747 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6748 case 9:
6749 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6750 case 8:
6751 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6752 case 7:
6753 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6754 case 6:
6755 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6756 case 5:
6757 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6758 case 4:
6759 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6760 case 3:
6761 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6762 case 2:
6763 case 1:
6764
6765 default:
6766 break;
6767 };
6768
6769 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6770
6771 return 0;
6772 }
6773
6774 /* Called at device open time to get the chip ready for
6775 * packet processing. Invoked with tp->lock held.
6776 */
6777 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6778 {
6779 int err;
6780
6781 /* Force the chip into D0. */
6782 err = tg3_set_power_state(tp, PCI_D0);
6783 if (err)
6784 goto out;
6785
6786 tg3_switch_clocks(tp);
6787
6788 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6789
6790 err = tg3_reset_hw(tp, reset_phy);
6791
6792 out:
6793 return err;
6794 }
6795
6796 #define TG3_STAT_ADD32(PSTAT, REG) \
6797 do { u32 __val = tr32(REG); \
6798 (PSTAT)->low += __val; \
6799 if ((PSTAT)->low < __val) \
6800 (PSTAT)->high += 1; \
6801 } while (0)
6802
6803 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6804 {
6805 struct tg3_hw_stats *sp = tp->hw_stats;
6806
6807 if (!netif_carrier_ok(tp->dev))
6808 return;
6809
6810 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6811 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6812 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6813 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6814 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6815 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6816 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6817 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6818 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6819 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6820 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6821 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6822 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6823
6824 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6825 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6826 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6827 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6828 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6829 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6830 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6831 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6832 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6833 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6834 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6835 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6836 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6837 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6838
6839 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6840 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6841 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6842 }
6843
6844 static void tg3_timer(unsigned long __opaque)
6845 {
6846 struct tg3 *tp = (struct tg3 *) __opaque;
6847
6848 if (tp->irq_sync)
6849 goto restart_timer;
6850
6851 spin_lock(&tp->lock);
6852
6853 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6854 /* All of this garbage is because when using non-tagged
6855 * IRQ status the mailbox/status_block protocol the chip
6856 * uses with the cpu is race prone.
6857 */
6858 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6859 tw32(GRC_LOCAL_CTRL,
6860 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6861 } else {
6862 tw32(HOSTCC_MODE, tp->coalesce_mode |
6863 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6864 }
6865
6866 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6867 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6868 spin_unlock(&tp->lock);
6869 schedule_work(&tp->reset_task);
6870 return;
6871 }
6872 }
6873
6874 /* This part only runs once per second. */
6875 if (!--tp->timer_counter) {
6876 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6877 tg3_periodic_fetch_stats(tp);
6878
6879 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6880 u32 mac_stat;
6881 int phy_event;
6882
6883 mac_stat = tr32(MAC_STATUS);
6884
6885 phy_event = 0;
6886 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6887 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6888 phy_event = 1;
6889 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6890 phy_event = 1;
6891
6892 if (phy_event)
6893 tg3_setup_phy(tp, 0);
6894 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6895 u32 mac_stat = tr32(MAC_STATUS);
6896 int need_setup = 0;
6897
6898 if (netif_carrier_ok(tp->dev) &&
6899 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6900 need_setup = 1;
6901 }
6902 if (! netif_carrier_ok(tp->dev) &&
6903 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6904 MAC_STATUS_SIGNAL_DET))) {
6905 need_setup = 1;
6906 }
6907 if (need_setup) {
6908 if (!tp->serdes_counter) {
6909 tw32_f(MAC_MODE,
6910 (tp->mac_mode &
6911 ~MAC_MODE_PORT_MODE_MASK));
6912 udelay(40);
6913 tw32_f(MAC_MODE, tp->mac_mode);
6914 udelay(40);
6915 }
6916 tg3_setup_phy(tp, 0);
6917 }
6918 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6919 tg3_serdes_parallel_detect(tp);
6920
6921 tp->timer_counter = tp->timer_multiplier;
6922 }
6923
6924 /* Heartbeat is only sent once every 2 seconds.
6925 *
6926 * The heartbeat is to tell the ASF firmware that the host
6927 * driver is still alive. In the event that the OS crashes,
6928 * ASF needs to reset the hardware to free up the FIFO space
6929 * that may be filled with rx packets destined for the host.
6930 * If the FIFO is full, ASF will no longer function properly.
6931 *
6932 * Unintended resets have been reported on real time kernels
6933 * where the timer doesn't run on time. Netpoll will also have
6934 * same problem.
6935 *
6936 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6937 * to check the ring condition when the heartbeat is expiring
6938 * before doing the reset. This will prevent most unintended
6939 * resets.
6940 */
6941 if (!--tp->asf_counter) {
6942 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6943 u32 val;
6944
6945 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6946 FWCMD_NICDRV_ALIVE3);
6947 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6948 /* 5 seconds timeout */
6949 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6950 val = tr32(GRC_RX_CPU_EVENT);
6951 val |= (1 << 14);
6952 tw32(GRC_RX_CPU_EVENT, val);
6953 }
6954 tp->asf_counter = tp->asf_multiplier;
6955 }
6956
6957 spin_unlock(&tp->lock);
6958
6959 restart_timer:
6960 tp->timer.expires = jiffies + tp->timer_offset;
6961 add_timer(&tp->timer);
6962 }
6963
6964 static int tg3_request_irq(struct tg3 *tp)
6965 {
6966 irq_handler_t fn;
6967 unsigned long flags;
6968 struct net_device *dev = tp->dev;
6969
6970 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6971 fn = tg3_msi;
6972 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6973 fn = tg3_msi_1shot;
6974 flags = IRQF_SAMPLE_RANDOM;
6975 } else {
6976 fn = tg3_interrupt;
6977 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6978 fn = tg3_interrupt_tagged;
6979 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6980 }
6981 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6982 }
6983
6984 static int tg3_test_interrupt(struct tg3 *tp)
6985 {
6986 struct net_device *dev = tp->dev;
6987 int err, i, intr_ok = 0;
6988
6989 if (!netif_running(dev))
6990 return -ENODEV;
6991
6992 tg3_disable_ints(tp);
6993
6994 free_irq(tp->pdev->irq, dev);
6995
6996 err = request_irq(tp->pdev->irq, tg3_test_isr,
6997 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6998 if (err)
6999 return err;
7000
7001 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7002 tg3_enable_ints(tp);
7003
7004 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7005 HOSTCC_MODE_NOW);
7006
7007 for (i = 0; i < 5; i++) {
7008 u32 int_mbox, misc_host_ctrl;
7009
7010 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7011 TG3_64BIT_REG_LOW);
7012 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7013
7014 if ((int_mbox != 0) ||
7015 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7016 intr_ok = 1;
7017 break;
7018 }
7019
7020 msleep(10);
7021 }
7022
7023 tg3_disable_ints(tp);
7024
7025 free_irq(tp->pdev->irq, dev);
7026
7027 err = tg3_request_irq(tp);
7028
7029 if (err)
7030 return err;
7031
7032 if (intr_ok)
7033 return 0;
7034
7035 return -EIO;
7036 }
7037
7038 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7039 * successfully restored
7040 */
7041 static int tg3_test_msi(struct tg3 *tp)
7042 {
7043 struct net_device *dev = tp->dev;
7044 int err;
7045 u16 pci_cmd;
7046
7047 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7048 return 0;
7049
7050 /* Turn off SERR reporting in case MSI terminates with Master
7051 * Abort.
7052 */
7053 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7054 pci_write_config_word(tp->pdev, PCI_COMMAND,
7055 pci_cmd & ~PCI_COMMAND_SERR);
7056
7057 err = tg3_test_interrupt(tp);
7058
7059 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7060
7061 if (!err)
7062 return 0;
7063
7064 /* other failures */
7065 if (err != -EIO)
7066 return err;
7067
7068 /* MSI test failed, go back to INTx mode */
7069 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7070 "switching to INTx mode. Please report this failure to "
7071 "the PCI maintainer and include system chipset information.\n",
7072 tp->dev->name);
7073
7074 free_irq(tp->pdev->irq, dev);
7075 pci_disable_msi(tp->pdev);
7076
7077 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7078
7079 err = tg3_request_irq(tp);
7080 if (err)
7081 return err;
7082
7083 /* Need to reset the chip because the MSI cycle may have terminated
7084 * with Master Abort.
7085 */
7086 tg3_full_lock(tp, 1);
7087
7088 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7089 err = tg3_init_hw(tp, 1);
7090
7091 tg3_full_unlock(tp);
7092
7093 if (err)
7094 free_irq(tp->pdev->irq, dev);
7095
7096 return err;
7097 }
7098
7099 static int tg3_open(struct net_device *dev)
7100 {
7101 struct tg3 *tp = netdev_priv(dev);
7102 int err;
7103
7104 netif_carrier_off(tp->dev);
7105
7106 tg3_full_lock(tp, 0);
7107
7108 err = tg3_set_power_state(tp, PCI_D0);
7109 if (err) {
7110 tg3_full_unlock(tp);
7111 return err;
7112 }
7113
7114 tg3_disable_ints(tp);
7115 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7116
7117 tg3_full_unlock(tp);
7118
7119 /* The placement of this call is tied
7120 * to the setup and use of Host TX descriptors.
7121 */
7122 err = tg3_alloc_consistent(tp);
7123 if (err)
7124 return err;
7125
7126 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7127 /* All MSI supporting chips should support tagged
7128 * status. Assert that this is the case.
7129 */
7130 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7131 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7132 "Not using MSI.\n", tp->dev->name);
7133 } else if (pci_enable_msi(tp->pdev) == 0) {
7134 u32 msi_mode;
7135
7136 /* Hardware bug - MSI won't work if INTX disabled. */
7137 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7138 pci_intx(tp->pdev, 1);
7139
7140 msi_mode = tr32(MSGINT_MODE);
7141 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7142 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7143 }
7144 }
7145 err = tg3_request_irq(tp);
7146
7147 if (err) {
7148 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7149 pci_disable_msi(tp->pdev);
7150 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7151 }
7152 tg3_free_consistent(tp);
7153 return err;
7154 }
7155
7156 tg3_full_lock(tp, 0);
7157
7158 err = tg3_init_hw(tp, 1);
7159 if (err) {
7160 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7161 tg3_free_rings(tp);
7162 } else {
7163 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7164 tp->timer_offset = HZ;
7165 else
7166 tp->timer_offset = HZ / 10;
7167
7168 BUG_ON(tp->timer_offset > HZ);
7169 tp->timer_counter = tp->timer_multiplier =
7170 (HZ / tp->timer_offset);
7171 tp->asf_counter = tp->asf_multiplier =
7172 ((HZ / tp->timer_offset) * 2);
7173
7174 init_timer(&tp->timer);
7175 tp->timer.expires = jiffies + tp->timer_offset;
7176 tp->timer.data = (unsigned long) tp;
7177 tp->timer.function = tg3_timer;
7178 }
7179
7180 tg3_full_unlock(tp);
7181
7182 if (err) {
7183 free_irq(tp->pdev->irq, dev);
7184 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7185 pci_disable_msi(tp->pdev);
7186 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7187 }
7188 tg3_free_consistent(tp);
7189 return err;
7190 }
7191
7192 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7193 err = tg3_test_msi(tp);
7194
7195 if (err) {
7196 tg3_full_lock(tp, 0);
7197
7198 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7199 pci_disable_msi(tp->pdev);
7200 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7201 }
7202 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7203 tg3_free_rings(tp);
7204 tg3_free_consistent(tp);
7205
7206 tg3_full_unlock(tp);
7207
7208 return err;
7209 }
7210
7211 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7212 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7213 u32 val = tr32(PCIE_TRANSACTION_CFG);
7214
7215 tw32(PCIE_TRANSACTION_CFG,
7216 val | PCIE_TRANS_CFG_1SHOT_MSI);
7217 }
7218 }
7219 }
7220
7221 tg3_full_lock(tp, 0);
7222
7223 add_timer(&tp->timer);
7224 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7225 tg3_enable_ints(tp);
7226
7227 tg3_full_unlock(tp);
7228
7229 netif_start_queue(dev);
7230
7231 return 0;
7232 }
7233
7234 #if 0
7235 /*static*/ void tg3_dump_state(struct tg3 *tp)
7236 {
7237 u32 val32, val32_2, val32_3, val32_4, val32_5;
7238 u16 val16;
7239 int i;
7240
7241 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7242 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7243 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7244 val16, val32);
7245
7246 /* MAC block */
7247 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7248 tr32(MAC_MODE), tr32(MAC_STATUS));
7249 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7250 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7251 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7252 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7253 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7254 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7255
7256 /* Send data initiator control block */
7257 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7258 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7259 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7260 tr32(SNDDATAI_STATSCTRL));
7261
7262 /* Send data completion control block */
7263 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7264
7265 /* Send BD ring selector block */
7266 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7267 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7268
7269 /* Send BD initiator control block */
7270 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7271 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7272
7273 /* Send BD completion control block */
7274 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7275
7276 /* Receive list placement control block */
7277 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7278 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7279 printk(" RCVLPC_STATSCTRL[%08x]\n",
7280 tr32(RCVLPC_STATSCTRL));
7281
7282 /* Receive data and receive BD initiator control block */
7283 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7284 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7285
7286 /* Receive data completion control block */
7287 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7288 tr32(RCVDCC_MODE));
7289
7290 /* Receive BD initiator control block */
7291 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7292 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7293
7294 /* Receive BD completion control block */
7295 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7296 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7297
7298 /* Receive list selector control block */
7299 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7300 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7301
7302 /* Mbuf cluster free block */
7303 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7304 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7305
7306 /* Host coalescing control block */
7307 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7308 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7309 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7310 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7311 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7312 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7313 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7314 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7315 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7316 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7317 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7318 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7319
7320 /* Memory arbiter control block */
7321 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7322 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7323
7324 /* Buffer manager control block */
7325 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7326 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7327 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7328 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7329 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7330 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7331 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7332 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7333
7334 /* Read DMA control block */
7335 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7336 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7337
7338 /* Write DMA control block */
7339 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7340 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7341
7342 /* DMA completion block */
7343 printk("DEBUG: DMAC_MODE[%08x]\n",
7344 tr32(DMAC_MODE));
7345
7346 /* GRC block */
7347 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7348 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7349 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7350 tr32(GRC_LOCAL_CTRL));
7351
7352 /* TG3_BDINFOs */
7353 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7354 tr32(RCVDBDI_JUMBO_BD + 0x0),
7355 tr32(RCVDBDI_JUMBO_BD + 0x4),
7356 tr32(RCVDBDI_JUMBO_BD + 0x8),
7357 tr32(RCVDBDI_JUMBO_BD + 0xc));
7358 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7359 tr32(RCVDBDI_STD_BD + 0x0),
7360 tr32(RCVDBDI_STD_BD + 0x4),
7361 tr32(RCVDBDI_STD_BD + 0x8),
7362 tr32(RCVDBDI_STD_BD + 0xc));
7363 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7364 tr32(RCVDBDI_MINI_BD + 0x0),
7365 tr32(RCVDBDI_MINI_BD + 0x4),
7366 tr32(RCVDBDI_MINI_BD + 0x8),
7367 tr32(RCVDBDI_MINI_BD + 0xc));
7368
7369 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7370 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7371 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7372 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7373 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7374 val32, val32_2, val32_3, val32_4);
7375
7376 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7377 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7378 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7379 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7380 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7381 val32, val32_2, val32_3, val32_4);
7382
7383 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7384 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7385 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7386 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7387 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7388 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7389 val32, val32_2, val32_3, val32_4, val32_5);
7390
7391 /* SW status block */
7392 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7393 tp->hw_status->status,
7394 tp->hw_status->status_tag,
7395 tp->hw_status->rx_jumbo_consumer,
7396 tp->hw_status->rx_consumer,
7397 tp->hw_status->rx_mini_consumer,
7398 tp->hw_status->idx[0].rx_producer,
7399 tp->hw_status->idx[0].tx_consumer);
7400
7401 /* SW statistics block */
7402 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7403 ((u32 *)tp->hw_stats)[0],
7404 ((u32 *)tp->hw_stats)[1],
7405 ((u32 *)tp->hw_stats)[2],
7406 ((u32 *)tp->hw_stats)[3]);
7407
7408 /* Mailboxes */
7409 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7410 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7411 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7412 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7413 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7414
7415 /* NIC side send descriptors. */
7416 for (i = 0; i < 6; i++) {
7417 unsigned long txd;
7418
7419 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7420 + (i * sizeof(struct tg3_tx_buffer_desc));
7421 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7422 i,
7423 readl(txd + 0x0), readl(txd + 0x4),
7424 readl(txd + 0x8), readl(txd + 0xc));
7425 }
7426
7427 /* NIC side RX descriptors. */
7428 for (i = 0; i < 6; i++) {
7429 unsigned long rxd;
7430
7431 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7432 + (i * sizeof(struct tg3_rx_buffer_desc));
7433 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7434 i,
7435 readl(rxd + 0x0), readl(rxd + 0x4),
7436 readl(rxd + 0x8), readl(rxd + 0xc));
7437 rxd += (4 * sizeof(u32));
7438 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7439 i,
7440 readl(rxd + 0x0), readl(rxd + 0x4),
7441 readl(rxd + 0x8), readl(rxd + 0xc));
7442 }
7443
7444 for (i = 0; i < 6; i++) {
7445 unsigned long rxd;
7446
7447 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7448 + (i * sizeof(struct tg3_rx_buffer_desc));
7449 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7450 i,
7451 readl(rxd + 0x0), readl(rxd + 0x4),
7452 readl(rxd + 0x8), readl(rxd + 0xc));
7453 rxd += (4 * sizeof(u32));
7454 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7455 i,
7456 readl(rxd + 0x0), readl(rxd + 0x4),
7457 readl(rxd + 0x8), readl(rxd + 0xc));
7458 }
7459 }
7460 #endif
7461
7462 static struct net_device_stats *tg3_get_stats(struct net_device *);
7463 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7464
7465 static int tg3_close(struct net_device *dev)
7466 {
7467 struct tg3 *tp = netdev_priv(dev);
7468
7469 cancel_work_sync(&tp->reset_task);
7470
7471 netif_stop_queue(dev);
7472
7473 del_timer_sync(&tp->timer);
7474
7475 tg3_full_lock(tp, 1);
7476 #if 0
7477 tg3_dump_state(tp);
7478 #endif
7479
7480 tg3_disable_ints(tp);
7481
7482 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7483 tg3_free_rings(tp);
7484 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7485
7486 tg3_full_unlock(tp);
7487
7488 free_irq(tp->pdev->irq, dev);
7489 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7490 pci_disable_msi(tp->pdev);
7491 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7492 }
7493
7494 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7495 sizeof(tp->net_stats_prev));
7496 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7497 sizeof(tp->estats_prev));
7498
7499 tg3_free_consistent(tp);
7500
7501 tg3_set_power_state(tp, PCI_D3hot);
7502
7503 netif_carrier_off(tp->dev);
7504
7505 return 0;
7506 }
7507
7508 static inline unsigned long get_stat64(tg3_stat64_t *val)
7509 {
7510 unsigned long ret;
7511
7512 #if (BITS_PER_LONG == 32)
7513 ret = val->low;
7514 #else
7515 ret = ((u64)val->high << 32) | ((u64)val->low);
7516 #endif
7517 return ret;
7518 }
7519
7520 static unsigned long calc_crc_errors(struct tg3 *tp)
7521 {
7522 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7523
7524 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7525 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7526 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7527 u32 val;
7528
7529 spin_lock_bh(&tp->lock);
7530 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7531 tg3_writephy(tp, MII_TG3_TEST1,
7532 val | MII_TG3_TEST1_CRC_EN);
7533 tg3_readphy(tp, 0x14, &val);
7534 } else
7535 val = 0;
7536 spin_unlock_bh(&tp->lock);
7537
7538 tp->phy_crc_errors += val;
7539
7540 return tp->phy_crc_errors;
7541 }
7542
7543 return get_stat64(&hw_stats->rx_fcs_errors);
7544 }
7545
7546 #define ESTAT_ADD(member) \
7547 estats->member = old_estats->member + \
7548 get_stat64(&hw_stats->member)
7549
7550 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7551 {
7552 struct tg3_ethtool_stats *estats = &tp->estats;
7553 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7554 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7555
7556 if (!hw_stats)
7557 return old_estats;
7558
7559 ESTAT_ADD(rx_octets);
7560 ESTAT_ADD(rx_fragments);
7561 ESTAT_ADD(rx_ucast_packets);
7562 ESTAT_ADD(rx_mcast_packets);
7563 ESTAT_ADD(rx_bcast_packets);
7564 ESTAT_ADD(rx_fcs_errors);
7565 ESTAT_ADD(rx_align_errors);
7566 ESTAT_ADD(rx_xon_pause_rcvd);
7567 ESTAT_ADD(rx_xoff_pause_rcvd);
7568 ESTAT_ADD(rx_mac_ctrl_rcvd);
7569 ESTAT_ADD(rx_xoff_entered);
7570 ESTAT_ADD(rx_frame_too_long_errors);
7571 ESTAT_ADD(rx_jabbers);
7572 ESTAT_ADD(rx_undersize_packets);
7573 ESTAT_ADD(rx_in_length_errors);
7574 ESTAT_ADD(rx_out_length_errors);
7575 ESTAT_ADD(rx_64_or_less_octet_packets);
7576 ESTAT_ADD(rx_65_to_127_octet_packets);
7577 ESTAT_ADD(rx_128_to_255_octet_packets);
7578 ESTAT_ADD(rx_256_to_511_octet_packets);
7579 ESTAT_ADD(rx_512_to_1023_octet_packets);
7580 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7581 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7582 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7583 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7584 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7585
7586 ESTAT_ADD(tx_octets);
7587 ESTAT_ADD(tx_collisions);
7588 ESTAT_ADD(tx_xon_sent);
7589 ESTAT_ADD(tx_xoff_sent);
7590 ESTAT_ADD(tx_flow_control);
7591 ESTAT_ADD(tx_mac_errors);
7592 ESTAT_ADD(tx_single_collisions);
7593 ESTAT_ADD(tx_mult_collisions);
7594 ESTAT_ADD(tx_deferred);
7595 ESTAT_ADD(tx_excessive_collisions);
7596 ESTAT_ADD(tx_late_collisions);
7597 ESTAT_ADD(tx_collide_2times);
7598 ESTAT_ADD(tx_collide_3times);
7599 ESTAT_ADD(tx_collide_4times);
7600 ESTAT_ADD(tx_collide_5times);
7601 ESTAT_ADD(tx_collide_6times);
7602 ESTAT_ADD(tx_collide_7times);
7603 ESTAT_ADD(tx_collide_8times);
7604 ESTAT_ADD(tx_collide_9times);
7605 ESTAT_ADD(tx_collide_10times);
7606 ESTAT_ADD(tx_collide_11times);
7607 ESTAT_ADD(tx_collide_12times);
7608 ESTAT_ADD(tx_collide_13times);
7609 ESTAT_ADD(tx_collide_14times);
7610 ESTAT_ADD(tx_collide_15times);
7611 ESTAT_ADD(tx_ucast_packets);
7612 ESTAT_ADD(tx_mcast_packets);
7613 ESTAT_ADD(tx_bcast_packets);
7614 ESTAT_ADD(tx_carrier_sense_errors);
7615 ESTAT_ADD(tx_discards);
7616 ESTAT_ADD(tx_errors);
7617
7618 ESTAT_ADD(dma_writeq_full);
7619 ESTAT_ADD(dma_write_prioq_full);
7620 ESTAT_ADD(rxbds_empty);
7621 ESTAT_ADD(rx_discards);
7622 ESTAT_ADD(rx_errors);
7623 ESTAT_ADD(rx_threshold_hit);
7624
7625 ESTAT_ADD(dma_readq_full);
7626 ESTAT_ADD(dma_read_prioq_full);
7627 ESTAT_ADD(tx_comp_queue_full);
7628
7629 ESTAT_ADD(ring_set_send_prod_index);
7630 ESTAT_ADD(ring_status_update);
7631 ESTAT_ADD(nic_irqs);
7632 ESTAT_ADD(nic_avoided_irqs);
7633 ESTAT_ADD(nic_tx_threshold_hit);
7634
7635 return estats;
7636 }
7637
7638 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7639 {
7640 struct tg3 *tp = netdev_priv(dev);
7641 struct net_device_stats *stats = &tp->net_stats;
7642 struct net_device_stats *old_stats = &tp->net_stats_prev;
7643 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7644
7645 if (!hw_stats)
7646 return old_stats;
7647
7648 stats->rx_packets = old_stats->rx_packets +
7649 get_stat64(&hw_stats->rx_ucast_packets) +
7650 get_stat64(&hw_stats->rx_mcast_packets) +
7651 get_stat64(&hw_stats->rx_bcast_packets);
7652
7653 stats->tx_packets = old_stats->tx_packets +
7654 get_stat64(&hw_stats->tx_ucast_packets) +
7655 get_stat64(&hw_stats->tx_mcast_packets) +
7656 get_stat64(&hw_stats->tx_bcast_packets);
7657
7658 stats->rx_bytes = old_stats->rx_bytes +
7659 get_stat64(&hw_stats->rx_octets);
7660 stats->tx_bytes = old_stats->tx_bytes +
7661 get_stat64(&hw_stats->tx_octets);
7662
7663 stats->rx_errors = old_stats->rx_errors +
7664 get_stat64(&hw_stats->rx_errors);
7665 stats->tx_errors = old_stats->tx_errors +
7666 get_stat64(&hw_stats->tx_errors) +
7667 get_stat64(&hw_stats->tx_mac_errors) +
7668 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7669 get_stat64(&hw_stats->tx_discards);
7670
7671 stats->multicast = old_stats->multicast +
7672 get_stat64(&hw_stats->rx_mcast_packets);
7673 stats->collisions = old_stats->collisions +
7674 get_stat64(&hw_stats->tx_collisions);
7675
7676 stats->rx_length_errors = old_stats->rx_length_errors +
7677 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7678 get_stat64(&hw_stats->rx_undersize_packets);
7679
7680 stats->rx_over_errors = old_stats->rx_over_errors +
7681 get_stat64(&hw_stats->rxbds_empty);
7682 stats->rx_frame_errors = old_stats->rx_frame_errors +
7683 get_stat64(&hw_stats->rx_align_errors);
7684 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7685 get_stat64(&hw_stats->tx_discards);
7686 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7687 get_stat64(&hw_stats->tx_carrier_sense_errors);
7688
7689 stats->rx_crc_errors = old_stats->rx_crc_errors +
7690 calc_crc_errors(tp);
7691
7692 stats->rx_missed_errors = old_stats->rx_missed_errors +
7693 get_stat64(&hw_stats->rx_discards);
7694
7695 return stats;
7696 }
7697
7698 static inline u32 calc_crc(unsigned char *buf, int len)
7699 {
7700 u32 reg;
7701 u32 tmp;
7702 int j, k;
7703
7704 reg = 0xffffffff;
7705
7706 for (j = 0; j < len; j++) {
7707 reg ^= buf[j];
7708
7709 for (k = 0; k < 8; k++) {
7710 tmp = reg & 0x01;
7711
7712 reg >>= 1;
7713
7714 if (tmp) {
7715 reg ^= 0xedb88320;
7716 }
7717 }
7718 }
7719
7720 return ~reg;
7721 }
7722
7723 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7724 {
7725 /* accept or reject all multicast frames */
7726 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7727 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7728 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7729 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7730 }
7731
7732 static void __tg3_set_rx_mode(struct net_device *dev)
7733 {
7734 struct tg3 *tp = netdev_priv(dev);
7735 u32 rx_mode;
7736
7737 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7738 RX_MODE_KEEP_VLAN_TAG);
7739
7740 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7741 * flag clear.
7742 */
7743 #if TG3_VLAN_TAG_USED
7744 if (!tp->vlgrp &&
7745 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7746 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7747 #else
7748 /* By definition, VLAN is disabled always in this
7749 * case.
7750 */
7751 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7752 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7753 #endif
7754
7755 if (dev->flags & IFF_PROMISC) {
7756 /* Promiscuous mode. */
7757 rx_mode |= RX_MODE_PROMISC;
7758 } else if (dev->flags & IFF_ALLMULTI) {
7759 /* Accept all multicast. */
7760 tg3_set_multi (tp, 1);
7761 } else if (dev->mc_count < 1) {
7762 /* Reject all multicast. */
7763 tg3_set_multi (tp, 0);
7764 } else {
7765 /* Accept one or more multicast(s). */
7766 struct dev_mc_list *mclist;
7767 unsigned int i;
7768 u32 mc_filter[4] = { 0, };
7769 u32 regidx;
7770 u32 bit;
7771 u32 crc;
7772
7773 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7774 i++, mclist = mclist->next) {
7775
7776 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7777 bit = ~crc & 0x7f;
7778 regidx = (bit & 0x60) >> 5;
7779 bit &= 0x1f;
7780 mc_filter[regidx] |= (1 << bit);
7781 }
7782
7783 tw32(MAC_HASH_REG_0, mc_filter[0]);
7784 tw32(MAC_HASH_REG_1, mc_filter[1]);
7785 tw32(MAC_HASH_REG_2, mc_filter[2]);
7786 tw32(MAC_HASH_REG_3, mc_filter[3]);
7787 }
7788
7789 if (rx_mode != tp->rx_mode) {
7790 tp->rx_mode = rx_mode;
7791 tw32_f(MAC_RX_MODE, rx_mode);
7792 udelay(10);
7793 }
7794 }
7795
7796 static void tg3_set_rx_mode(struct net_device *dev)
7797 {
7798 struct tg3 *tp = netdev_priv(dev);
7799
7800 if (!netif_running(dev))
7801 return;
7802
7803 tg3_full_lock(tp, 0);
7804 __tg3_set_rx_mode(dev);
7805 tg3_full_unlock(tp);
7806 }
7807
7808 #define TG3_REGDUMP_LEN (32 * 1024)
7809
7810 static int tg3_get_regs_len(struct net_device *dev)
7811 {
7812 return TG3_REGDUMP_LEN;
7813 }
7814
7815 static void tg3_get_regs(struct net_device *dev,
7816 struct ethtool_regs *regs, void *_p)
7817 {
7818 u32 *p = _p;
7819 struct tg3 *tp = netdev_priv(dev);
7820 u8 *orig_p = _p;
7821 int i;
7822
7823 regs->version = 0;
7824
7825 memset(p, 0, TG3_REGDUMP_LEN);
7826
7827 if (tp->link_config.phy_is_low_power)
7828 return;
7829
7830 tg3_full_lock(tp, 0);
7831
7832 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7833 #define GET_REG32_LOOP(base,len) \
7834 do { p = (u32 *)(orig_p + (base)); \
7835 for (i = 0; i < len; i += 4) \
7836 __GET_REG32((base) + i); \
7837 } while (0)
7838 #define GET_REG32_1(reg) \
7839 do { p = (u32 *)(orig_p + (reg)); \
7840 __GET_REG32((reg)); \
7841 } while (0)
7842
7843 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7844 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7845 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7846 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7847 GET_REG32_1(SNDDATAC_MODE);
7848 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7849 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7850 GET_REG32_1(SNDBDC_MODE);
7851 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7852 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7853 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7854 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7855 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7856 GET_REG32_1(RCVDCC_MODE);
7857 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7858 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7859 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7860 GET_REG32_1(MBFREE_MODE);
7861 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7862 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7863 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7864 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7865 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7866 GET_REG32_1(RX_CPU_MODE);
7867 GET_REG32_1(RX_CPU_STATE);
7868 GET_REG32_1(RX_CPU_PGMCTR);
7869 GET_REG32_1(RX_CPU_HWBKPT);
7870 GET_REG32_1(TX_CPU_MODE);
7871 GET_REG32_1(TX_CPU_STATE);
7872 GET_REG32_1(TX_CPU_PGMCTR);
7873 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7874 GET_REG32_LOOP(FTQ_RESET, 0x120);
7875 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7876 GET_REG32_1(DMAC_MODE);
7877 GET_REG32_LOOP(GRC_MODE, 0x4c);
7878 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7879 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7880
7881 #undef __GET_REG32
7882 #undef GET_REG32_LOOP
7883 #undef GET_REG32_1
7884
7885 tg3_full_unlock(tp);
7886 }
7887
7888 static int tg3_get_eeprom_len(struct net_device *dev)
7889 {
7890 struct tg3 *tp = netdev_priv(dev);
7891
7892 return tp->nvram_size;
7893 }
7894
7895 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7896 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7897
7898 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7899 {
7900 struct tg3 *tp = netdev_priv(dev);
7901 int ret;
7902 u8 *pd;
7903 u32 i, offset, len, val, b_offset, b_count;
7904
7905 if (tp->link_config.phy_is_low_power)
7906 return -EAGAIN;
7907
7908 offset = eeprom->offset;
7909 len = eeprom->len;
7910 eeprom->len = 0;
7911
7912 eeprom->magic = TG3_EEPROM_MAGIC;
7913
7914 if (offset & 3) {
7915 /* adjustments to start on required 4 byte boundary */
7916 b_offset = offset & 3;
7917 b_count = 4 - b_offset;
7918 if (b_count > len) {
7919 /* i.e. offset=1 len=2 */
7920 b_count = len;
7921 }
7922 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7923 if (ret)
7924 return ret;
7925 val = cpu_to_le32(val);
7926 memcpy(data, ((char*)&val) + b_offset, b_count);
7927 len -= b_count;
7928 offset += b_count;
7929 eeprom->len += b_count;
7930 }
7931
7932 /* read bytes upto the last 4 byte boundary */
7933 pd = &data[eeprom->len];
7934 for (i = 0; i < (len - (len & 3)); i += 4) {
7935 ret = tg3_nvram_read(tp, offset + i, &val);
7936 if (ret) {
7937 eeprom->len += i;
7938 return ret;
7939 }
7940 val = cpu_to_le32(val);
7941 memcpy(pd + i, &val, 4);
7942 }
7943 eeprom->len += i;
7944
7945 if (len & 3) {
7946 /* read last bytes not ending on 4 byte boundary */
7947 pd = &data[eeprom->len];
7948 b_count = len & 3;
7949 b_offset = offset + len - b_count;
7950 ret = tg3_nvram_read(tp, b_offset, &val);
7951 if (ret)
7952 return ret;
7953 val = cpu_to_le32(val);
7954 memcpy(pd, ((char*)&val), b_count);
7955 eeprom->len += b_count;
7956 }
7957 return 0;
7958 }
7959
7960 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7961
7962 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7963 {
7964 struct tg3 *tp = netdev_priv(dev);
7965 int ret;
7966 u32 offset, len, b_offset, odd_len, start, end;
7967 u8 *buf;
7968
7969 if (tp->link_config.phy_is_low_power)
7970 return -EAGAIN;
7971
7972 if (eeprom->magic != TG3_EEPROM_MAGIC)
7973 return -EINVAL;
7974
7975 offset = eeprom->offset;
7976 len = eeprom->len;
7977
7978 if ((b_offset = (offset & 3))) {
7979 /* adjustments to start on required 4 byte boundary */
7980 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7981 if (ret)
7982 return ret;
7983 start = cpu_to_le32(start);
7984 len += b_offset;
7985 offset &= ~3;
7986 if (len < 4)
7987 len = 4;
7988 }
7989
7990 odd_len = 0;
7991 if (len & 3) {
7992 /* adjustments to end on required 4 byte boundary */
7993 odd_len = 1;
7994 len = (len + 3) & ~3;
7995 ret = tg3_nvram_read(tp, offset+len-4, &end);
7996 if (ret)
7997 return ret;
7998 end = cpu_to_le32(end);
7999 }
8000
8001 buf = data;
8002 if (b_offset || odd_len) {
8003 buf = kmalloc(len, GFP_KERNEL);
8004 if (buf == 0)
8005 return -ENOMEM;
8006 if (b_offset)
8007 memcpy(buf, &start, 4);
8008 if (odd_len)
8009 memcpy(buf+len-4, &end, 4);
8010 memcpy(buf + b_offset, data, eeprom->len);
8011 }
8012
8013 ret = tg3_nvram_write_block(tp, offset, len, buf);
8014
8015 if (buf != data)
8016 kfree(buf);
8017
8018 return ret;
8019 }
8020
8021 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8022 {
8023 struct tg3 *tp = netdev_priv(dev);
8024
8025 cmd->supported = (SUPPORTED_Autoneg);
8026
8027 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8028 cmd->supported |= (SUPPORTED_1000baseT_Half |
8029 SUPPORTED_1000baseT_Full);
8030
8031 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8032 cmd->supported |= (SUPPORTED_100baseT_Half |
8033 SUPPORTED_100baseT_Full |
8034 SUPPORTED_10baseT_Half |
8035 SUPPORTED_10baseT_Full |
8036 SUPPORTED_MII);
8037 cmd->port = PORT_TP;
8038 } else {
8039 cmd->supported |= SUPPORTED_FIBRE;
8040 cmd->port = PORT_FIBRE;
8041 }
8042
8043 cmd->advertising = tp->link_config.advertising;
8044 if (netif_running(dev)) {
8045 cmd->speed = tp->link_config.active_speed;
8046 cmd->duplex = tp->link_config.active_duplex;
8047 }
8048 cmd->phy_address = PHY_ADDR;
8049 cmd->transceiver = 0;
8050 cmd->autoneg = tp->link_config.autoneg;
8051 cmd->maxtxpkt = 0;
8052 cmd->maxrxpkt = 0;
8053 return 0;
8054 }
8055
8056 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8057 {
8058 struct tg3 *tp = netdev_priv(dev);
8059
8060 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8061 /* These are the only valid advertisement bits allowed. */
8062 if (cmd->autoneg == AUTONEG_ENABLE &&
8063 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8064 ADVERTISED_1000baseT_Full |
8065 ADVERTISED_Autoneg |
8066 ADVERTISED_FIBRE)))
8067 return -EINVAL;
8068 /* Fiber can only do SPEED_1000. */
8069 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8070 (cmd->speed != SPEED_1000))
8071 return -EINVAL;
8072 /* Copper cannot force SPEED_1000. */
8073 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8074 (cmd->speed == SPEED_1000))
8075 return -EINVAL;
8076 else if ((cmd->speed == SPEED_1000) &&
8077 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8078 return -EINVAL;
8079
8080 tg3_full_lock(tp, 0);
8081
8082 tp->link_config.autoneg = cmd->autoneg;
8083 if (cmd->autoneg == AUTONEG_ENABLE) {
8084 tp->link_config.advertising = cmd->advertising;
8085 tp->link_config.speed = SPEED_INVALID;
8086 tp->link_config.duplex = DUPLEX_INVALID;
8087 } else {
8088 tp->link_config.advertising = 0;
8089 tp->link_config.speed = cmd->speed;
8090 tp->link_config.duplex = cmd->duplex;
8091 }
8092
8093 tp->link_config.orig_speed = tp->link_config.speed;
8094 tp->link_config.orig_duplex = tp->link_config.duplex;
8095 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8096
8097 if (netif_running(dev))
8098 tg3_setup_phy(tp, 1);
8099
8100 tg3_full_unlock(tp);
8101
8102 return 0;
8103 }
8104
8105 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8106 {
8107 struct tg3 *tp = netdev_priv(dev);
8108
8109 strcpy(info->driver, DRV_MODULE_NAME);
8110 strcpy(info->version, DRV_MODULE_VERSION);
8111 strcpy(info->fw_version, tp->fw_ver);
8112 strcpy(info->bus_info, pci_name(tp->pdev));
8113 }
8114
8115 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8116 {
8117 struct tg3 *tp = netdev_priv(dev);
8118
8119 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8120 wol->supported = WAKE_MAGIC;
8121 else
8122 wol->supported = 0;
8123 wol->wolopts = 0;
8124 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8125 wol->wolopts = WAKE_MAGIC;
8126 memset(&wol->sopass, 0, sizeof(wol->sopass));
8127 }
8128
8129 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8130 {
8131 struct tg3 *tp = netdev_priv(dev);
8132
8133 if (wol->wolopts & ~WAKE_MAGIC)
8134 return -EINVAL;
8135 if ((wol->wolopts & WAKE_MAGIC) &&
8136 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8137 return -EINVAL;
8138
8139 spin_lock_bh(&tp->lock);
8140 if (wol->wolopts & WAKE_MAGIC)
8141 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8142 else
8143 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8144 spin_unlock_bh(&tp->lock);
8145
8146 return 0;
8147 }
8148
8149 static u32 tg3_get_msglevel(struct net_device *dev)
8150 {
8151 struct tg3 *tp = netdev_priv(dev);
8152 return tp->msg_enable;
8153 }
8154
8155 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8156 {
8157 struct tg3 *tp = netdev_priv(dev);
8158 tp->msg_enable = value;
8159 }
8160
8161 static int tg3_set_tso(struct net_device *dev, u32 value)
8162 {
8163 struct tg3 *tp = netdev_priv(dev);
8164
8165 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8166 if (value)
8167 return -EINVAL;
8168 return 0;
8169 }
8170 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8171 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8172 if (value)
8173 dev->features |= NETIF_F_TSO6;
8174 else
8175 dev->features &= ~NETIF_F_TSO6;
8176 }
8177 return ethtool_op_set_tso(dev, value);
8178 }
8179
8180 static int tg3_nway_reset(struct net_device *dev)
8181 {
8182 struct tg3 *tp = netdev_priv(dev);
8183 u32 bmcr;
8184 int r;
8185
8186 if (!netif_running(dev))
8187 return -EAGAIN;
8188
8189 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8190 return -EINVAL;
8191
8192 spin_lock_bh(&tp->lock);
8193 r = -EINVAL;
8194 tg3_readphy(tp, MII_BMCR, &bmcr);
8195 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8196 ((bmcr & BMCR_ANENABLE) ||
8197 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8198 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8199 BMCR_ANENABLE);
8200 r = 0;
8201 }
8202 spin_unlock_bh(&tp->lock);
8203
8204 return r;
8205 }
8206
8207 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8208 {
8209 struct tg3 *tp = netdev_priv(dev);
8210
8211 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8212 ering->rx_mini_max_pending = 0;
8213 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8214 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8215 else
8216 ering->rx_jumbo_max_pending = 0;
8217
8218 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8219
8220 ering->rx_pending = tp->rx_pending;
8221 ering->rx_mini_pending = 0;
8222 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8223 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8224 else
8225 ering->rx_jumbo_pending = 0;
8226
8227 ering->tx_pending = tp->tx_pending;
8228 }
8229
8230 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8231 {
8232 struct tg3 *tp = netdev_priv(dev);
8233 int irq_sync = 0, err = 0;
8234
8235 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8236 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8237 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8238 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8239 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8240 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8241 return -EINVAL;
8242
8243 if (netif_running(dev)) {
8244 tg3_netif_stop(tp);
8245 irq_sync = 1;
8246 }
8247
8248 tg3_full_lock(tp, irq_sync);
8249
8250 tp->rx_pending = ering->rx_pending;
8251
8252 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8253 tp->rx_pending > 63)
8254 tp->rx_pending = 63;
8255 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8256 tp->tx_pending = ering->tx_pending;
8257
8258 if (netif_running(dev)) {
8259 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8260 err = tg3_restart_hw(tp, 1);
8261 if (!err)
8262 tg3_netif_start(tp);
8263 }
8264
8265 tg3_full_unlock(tp);
8266
8267 return err;
8268 }
8269
8270 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8271 {
8272 struct tg3 *tp = netdev_priv(dev);
8273
8274 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8275 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8276 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8277 }
8278
8279 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8280 {
8281 struct tg3 *tp = netdev_priv(dev);
8282 int irq_sync = 0, err = 0;
8283
8284 if (netif_running(dev)) {
8285 tg3_netif_stop(tp);
8286 irq_sync = 1;
8287 }
8288
8289 tg3_full_lock(tp, irq_sync);
8290
8291 if (epause->autoneg)
8292 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8293 else
8294 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8295 if (epause->rx_pause)
8296 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8297 else
8298 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8299 if (epause->tx_pause)
8300 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8301 else
8302 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8303
8304 if (netif_running(dev)) {
8305 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8306 err = tg3_restart_hw(tp, 1);
8307 if (!err)
8308 tg3_netif_start(tp);
8309 }
8310
8311 tg3_full_unlock(tp);
8312
8313 return err;
8314 }
8315
8316 static u32 tg3_get_rx_csum(struct net_device *dev)
8317 {
8318 struct tg3 *tp = netdev_priv(dev);
8319 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8320 }
8321
8322 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8323 {
8324 struct tg3 *tp = netdev_priv(dev);
8325
8326 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8327 if (data != 0)
8328 return -EINVAL;
8329 return 0;
8330 }
8331
8332 spin_lock_bh(&tp->lock);
8333 if (data)
8334 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8335 else
8336 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8337 spin_unlock_bh(&tp->lock);
8338
8339 return 0;
8340 }
8341
8342 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8343 {
8344 struct tg3 *tp = netdev_priv(dev);
8345
8346 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8347 if (data != 0)
8348 return -EINVAL;
8349 return 0;
8350 }
8351
8352 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8353 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8354 ethtool_op_set_tx_ipv6_csum(dev, data);
8355 else
8356 ethtool_op_set_tx_csum(dev, data);
8357
8358 return 0;
8359 }
8360
8361 static int tg3_get_stats_count (struct net_device *dev)
8362 {
8363 return TG3_NUM_STATS;
8364 }
8365
8366 static int tg3_get_test_count (struct net_device *dev)
8367 {
8368 return TG3_NUM_TEST;
8369 }
8370
8371 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8372 {
8373 switch (stringset) {
8374 case ETH_SS_STATS:
8375 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8376 break;
8377 case ETH_SS_TEST:
8378 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8379 break;
8380 default:
8381 WARN_ON(1); /* we need a WARN() */
8382 break;
8383 }
8384 }
8385
8386 static int tg3_phys_id(struct net_device *dev, u32 data)
8387 {
8388 struct tg3 *tp = netdev_priv(dev);
8389 int i;
8390
8391 if (!netif_running(tp->dev))
8392 return -EAGAIN;
8393
8394 if (data == 0)
8395 data = 2;
8396
8397 for (i = 0; i < (data * 2); i++) {
8398 if ((i % 2) == 0)
8399 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8400 LED_CTRL_1000MBPS_ON |
8401 LED_CTRL_100MBPS_ON |
8402 LED_CTRL_10MBPS_ON |
8403 LED_CTRL_TRAFFIC_OVERRIDE |
8404 LED_CTRL_TRAFFIC_BLINK |
8405 LED_CTRL_TRAFFIC_LED);
8406
8407 else
8408 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8409 LED_CTRL_TRAFFIC_OVERRIDE);
8410
8411 if (msleep_interruptible(500))
8412 break;
8413 }
8414 tw32(MAC_LED_CTRL, tp->led_ctrl);
8415 return 0;
8416 }
8417
8418 static void tg3_get_ethtool_stats (struct net_device *dev,
8419 struct ethtool_stats *estats, u64 *tmp_stats)
8420 {
8421 struct tg3 *tp = netdev_priv(dev);
8422 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8423 }
8424
8425 #define NVRAM_TEST_SIZE 0x100
8426 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8427 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8428 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8429
8430 static int tg3_test_nvram(struct tg3 *tp)
8431 {
8432 u32 *buf, csum, magic;
8433 int i, j, err = 0, size;
8434
8435 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8436 return -EIO;
8437
8438 if (magic == TG3_EEPROM_MAGIC)
8439 size = NVRAM_TEST_SIZE;
8440 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8441 if ((magic & 0xe00000) == 0x200000)
8442 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8443 else
8444 return 0;
8445 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8446 size = NVRAM_SELFBOOT_HW_SIZE;
8447 else
8448 return -EIO;
8449
8450 buf = kmalloc(size, GFP_KERNEL);
8451 if (buf == NULL)
8452 return -ENOMEM;
8453
8454 err = -EIO;
8455 for (i = 0, j = 0; i < size; i += 4, j++) {
8456 u32 val;
8457
8458 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8459 break;
8460 buf[j] = cpu_to_le32(val);
8461 }
8462 if (i < size)
8463 goto out;
8464
8465 /* Selfboot format */
8466 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8467 TG3_EEPROM_MAGIC_FW) {
8468 u8 *buf8 = (u8 *) buf, csum8 = 0;
8469
8470 for (i = 0; i < size; i++)
8471 csum8 += buf8[i];
8472
8473 if (csum8 == 0) {
8474 err = 0;
8475 goto out;
8476 }
8477
8478 err = -EIO;
8479 goto out;
8480 }
8481
8482 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8483 TG3_EEPROM_MAGIC_HW) {
8484 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8485 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8486 u8 *buf8 = (u8 *) buf;
8487 int j, k;
8488
8489 /* Separate the parity bits and the data bytes. */
8490 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8491 if ((i == 0) || (i == 8)) {
8492 int l;
8493 u8 msk;
8494
8495 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8496 parity[k++] = buf8[i] & msk;
8497 i++;
8498 }
8499 else if (i == 16) {
8500 int l;
8501 u8 msk;
8502
8503 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8504 parity[k++] = buf8[i] & msk;
8505 i++;
8506
8507 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8508 parity[k++] = buf8[i] & msk;
8509 i++;
8510 }
8511 data[j++] = buf8[i];
8512 }
8513
8514 err = -EIO;
8515 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8516 u8 hw8 = hweight8(data[i]);
8517
8518 if ((hw8 & 0x1) && parity[i])
8519 goto out;
8520 else if (!(hw8 & 0x1) && !parity[i])
8521 goto out;
8522 }
8523 err = 0;
8524 goto out;
8525 }
8526
8527 /* Bootstrap checksum at offset 0x10 */
8528 csum = calc_crc((unsigned char *) buf, 0x10);
8529 if(csum != cpu_to_le32(buf[0x10/4]))
8530 goto out;
8531
8532 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8533 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8534 if (csum != cpu_to_le32(buf[0xfc/4]))
8535 goto out;
8536
8537 err = 0;
8538
8539 out:
8540 kfree(buf);
8541 return err;
8542 }
8543
8544 #define TG3_SERDES_TIMEOUT_SEC 2
8545 #define TG3_COPPER_TIMEOUT_SEC 6
8546
8547 static int tg3_test_link(struct tg3 *tp)
8548 {
8549 int i, max;
8550
8551 if (!netif_running(tp->dev))
8552 return -ENODEV;
8553
8554 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8555 max = TG3_SERDES_TIMEOUT_SEC;
8556 else
8557 max = TG3_COPPER_TIMEOUT_SEC;
8558
8559 for (i = 0; i < max; i++) {
8560 if (netif_carrier_ok(tp->dev))
8561 return 0;
8562
8563 if (msleep_interruptible(1000))
8564 break;
8565 }
8566
8567 return -EIO;
8568 }
8569
8570 /* Only test the commonly used registers */
8571 static int tg3_test_registers(struct tg3 *tp)
8572 {
8573 int i, is_5705, is_5750;
8574 u32 offset, read_mask, write_mask, val, save_val, read_val;
8575 static struct {
8576 u16 offset;
8577 u16 flags;
8578 #define TG3_FL_5705 0x1
8579 #define TG3_FL_NOT_5705 0x2
8580 #define TG3_FL_NOT_5788 0x4
8581 #define TG3_FL_NOT_5750 0x8
8582 u32 read_mask;
8583 u32 write_mask;
8584 } reg_tbl[] = {
8585 /* MAC Control Registers */
8586 { MAC_MODE, TG3_FL_NOT_5705,
8587 0x00000000, 0x00ef6f8c },
8588 { MAC_MODE, TG3_FL_5705,
8589 0x00000000, 0x01ef6b8c },
8590 { MAC_STATUS, TG3_FL_NOT_5705,
8591 0x03800107, 0x00000000 },
8592 { MAC_STATUS, TG3_FL_5705,
8593 0x03800100, 0x00000000 },
8594 { MAC_ADDR_0_HIGH, 0x0000,
8595 0x00000000, 0x0000ffff },
8596 { MAC_ADDR_0_LOW, 0x0000,
8597 0x00000000, 0xffffffff },
8598 { MAC_RX_MTU_SIZE, 0x0000,
8599 0x00000000, 0x0000ffff },
8600 { MAC_TX_MODE, 0x0000,
8601 0x00000000, 0x00000070 },
8602 { MAC_TX_LENGTHS, 0x0000,
8603 0x00000000, 0x00003fff },
8604 { MAC_RX_MODE, TG3_FL_NOT_5705,
8605 0x00000000, 0x000007fc },
8606 { MAC_RX_MODE, TG3_FL_5705,
8607 0x00000000, 0x000007dc },
8608 { MAC_HASH_REG_0, 0x0000,
8609 0x00000000, 0xffffffff },
8610 { MAC_HASH_REG_1, 0x0000,
8611 0x00000000, 0xffffffff },
8612 { MAC_HASH_REG_2, 0x0000,
8613 0x00000000, 0xffffffff },
8614 { MAC_HASH_REG_3, 0x0000,
8615 0x00000000, 0xffffffff },
8616
8617 /* Receive Data and Receive BD Initiator Control Registers. */
8618 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8619 0x00000000, 0xffffffff },
8620 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8621 0x00000000, 0xffffffff },
8622 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8623 0x00000000, 0x00000003 },
8624 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8625 0x00000000, 0xffffffff },
8626 { RCVDBDI_STD_BD+0, 0x0000,
8627 0x00000000, 0xffffffff },
8628 { RCVDBDI_STD_BD+4, 0x0000,
8629 0x00000000, 0xffffffff },
8630 { RCVDBDI_STD_BD+8, 0x0000,
8631 0x00000000, 0xffff0002 },
8632 { RCVDBDI_STD_BD+0xc, 0x0000,
8633 0x00000000, 0xffffffff },
8634
8635 /* Receive BD Initiator Control Registers. */
8636 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8637 0x00000000, 0xffffffff },
8638 { RCVBDI_STD_THRESH, TG3_FL_5705,
8639 0x00000000, 0x000003ff },
8640 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8641 0x00000000, 0xffffffff },
8642
8643 /* Host Coalescing Control Registers. */
8644 { HOSTCC_MODE, TG3_FL_NOT_5705,
8645 0x00000000, 0x00000004 },
8646 { HOSTCC_MODE, TG3_FL_5705,
8647 0x00000000, 0x000000f6 },
8648 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8649 0x00000000, 0xffffffff },
8650 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8651 0x00000000, 0x000003ff },
8652 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8653 0x00000000, 0xffffffff },
8654 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8655 0x00000000, 0x000003ff },
8656 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8657 0x00000000, 0xffffffff },
8658 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8659 0x00000000, 0x000000ff },
8660 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8661 0x00000000, 0xffffffff },
8662 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8663 0x00000000, 0x000000ff },
8664 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8665 0x00000000, 0xffffffff },
8666 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8667 0x00000000, 0xffffffff },
8668 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8669 0x00000000, 0xffffffff },
8670 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8671 0x00000000, 0x000000ff },
8672 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8673 0x00000000, 0xffffffff },
8674 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8675 0x00000000, 0x000000ff },
8676 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8677 0x00000000, 0xffffffff },
8678 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8679 0x00000000, 0xffffffff },
8680 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8681 0x00000000, 0xffffffff },
8682 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8683 0x00000000, 0xffffffff },
8684 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8685 0x00000000, 0xffffffff },
8686 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8687 0xffffffff, 0x00000000 },
8688 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8689 0xffffffff, 0x00000000 },
8690
8691 /* Buffer Manager Control Registers. */
8692 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8693 0x00000000, 0x007fff80 },
8694 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8695 0x00000000, 0x007fffff },
8696 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8697 0x00000000, 0x0000003f },
8698 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8699 0x00000000, 0x000001ff },
8700 { BUFMGR_MB_HIGH_WATER, 0x0000,
8701 0x00000000, 0x000001ff },
8702 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8703 0xffffffff, 0x00000000 },
8704 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8705 0xffffffff, 0x00000000 },
8706
8707 /* Mailbox Registers */
8708 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8709 0x00000000, 0x000001ff },
8710 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8711 0x00000000, 0x000001ff },
8712 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8713 0x00000000, 0x000007ff },
8714 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8715 0x00000000, 0x000001ff },
8716
8717 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8718 };
8719
8720 is_5705 = is_5750 = 0;
8721 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8722 is_5705 = 1;
8723 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8724 is_5750 = 1;
8725 }
8726
8727 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8728 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8729 continue;
8730
8731 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8732 continue;
8733
8734 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8735 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8736 continue;
8737
8738 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8739 continue;
8740
8741 offset = (u32) reg_tbl[i].offset;
8742 read_mask = reg_tbl[i].read_mask;
8743 write_mask = reg_tbl[i].write_mask;
8744
8745 /* Save the original register content */
8746 save_val = tr32(offset);
8747
8748 /* Determine the read-only value. */
8749 read_val = save_val & read_mask;
8750
8751 /* Write zero to the register, then make sure the read-only bits
8752 * are not changed and the read/write bits are all zeros.
8753 */
8754 tw32(offset, 0);
8755
8756 val = tr32(offset);
8757
8758 /* Test the read-only and read/write bits. */
8759 if (((val & read_mask) != read_val) || (val & write_mask))
8760 goto out;
8761
8762 /* Write ones to all the bits defined by RdMask and WrMask, then
8763 * make sure the read-only bits are not changed and the
8764 * read/write bits are all ones.
8765 */
8766 tw32(offset, read_mask | write_mask);
8767
8768 val = tr32(offset);
8769
8770 /* Test the read-only bits. */
8771 if ((val & read_mask) != read_val)
8772 goto out;
8773
8774 /* Test the read/write bits. */
8775 if ((val & write_mask) != write_mask)
8776 goto out;
8777
8778 tw32(offset, save_val);
8779 }
8780
8781 return 0;
8782
8783 out:
8784 if (netif_msg_hw(tp))
8785 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8786 offset);
8787 tw32(offset, save_val);
8788 return -EIO;
8789 }
8790
8791 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8792 {
8793 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8794 int i;
8795 u32 j;
8796
8797 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8798 for (j = 0; j < len; j += 4) {
8799 u32 val;
8800
8801 tg3_write_mem(tp, offset + j, test_pattern[i]);
8802 tg3_read_mem(tp, offset + j, &val);
8803 if (val != test_pattern[i])
8804 return -EIO;
8805 }
8806 }
8807 return 0;
8808 }
8809
8810 static int tg3_test_memory(struct tg3 *tp)
8811 {
8812 static struct mem_entry {
8813 u32 offset;
8814 u32 len;
8815 } mem_tbl_570x[] = {
8816 { 0x00000000, 0x00b50},
8817 { 0x00002000, 0x1c000},
8818 { 0xffffffff, 0x00000}
8819 }, mem_tbl_5705[] = {
8820 { 0x00000100, 0x0000c},
8821 { 0x00000200, 0x00008},
8822 { 0x00004000, 0x00800},
8823 { 0x00006000, 0x01000},
8824 { 0x00008000, 0x02000},
8825 { 0x00010000, 0x0e000},
8826 { 0xffffffff, 0x00000}
8827 }, mem_tbl_5755[] = {
8828 { 0x00000200, 0x00008},
8829 { 0x00004000, 0x00800},
8830 { 0x00006000, 0x00800},
8831 { 0x00008000, 0x02000},
8832 { 0x00010000, 0x0c000},
8833 { 0xffffffff, 0x00000}
8834 }, mem_tbl_5906[] = {
8835 { 0x00000200, 0x00008},
8836 { 0x00004000, 0x00400},
8837 { 0x00006000, 0x00400},
8838 { 0x00008000, 0x01000},
8839 { 0x00010000, 0x01000},
8840 { 0xffffffff, 0x00000}
8841 };
8842 struct mem_entry *mem_tbl;
8843 int err = 0;
8844 int i;
8845
8846 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8848 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8849 mem_tbl = mem_tbl_5755;
8850 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8851 mem_tbl = mem_tbl_5906;
8852 else
8853 mem_tbl = mem_tbl_5705;
8854 } else
8855 mem_tbl = mem_tbl_570x;
8856
8857 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8858 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8859 mem_tbl[i].len)) != 0)
8860 break;
8861 }
8862
8863 return err;
8864 }
8865
8866 #define TG3_MAC_LOOPBACK 0
8867 #define TG3_PHY_LOOPBACK 1
8868
8869 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8870 {
8871 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8872 u32 desc_idx;
8873 struct sk_buff *skb, *rx_skb;
8874 u8 *tx_data;
8875 dma_addr_t map;
8876 int num_pkts, tx_len, rx_len, i, err;
8877 struct tg3_rx_buffer_desc *desc;
8878
8879 if (loopback_mode == TG3_MAC_LOOPBACK) {
8880 /* HW errata - mac loopback fails in some cases on 5780.
8881 * Normal traffic and PHY loopback are not affected by
8882 * errata.
8883 */
8884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8885 return 0;
8886
8887 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8888 MAC_MODE_PORT_INT_LPBACK;
8889 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8890 mac_mode |= MAC_MODE_LINK_POLARITY;
8891 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8892 mac_mode |= MAC_MODE_PORT_MODE_MII;
8893 else
8894 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8895 tw32(MAC_MODE, mac_mode);
8896 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8897 u32 val;
8898
8899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8900 u32 phytest;
8901
8902 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8903 u32 phy;
8904
8905 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8906 phytest | MII_TG3_EPHY_SHADOW_EN);
8907 if (!tg3_readphy(tp, 0x1b, &phy))
8908 tg3_writephy(tp, 0x1b, phy & ~0x20);
8909 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8910 }
8911 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8912 } else
8913 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8914
8915 tg3_phy_toggle_automdix(tp, 0);
8916
8917 tg3_writephy(tp, MII_BMCR, val);
8918 udelay(40);
8919
8920 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
8921 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8922 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8923 mac_mode |= MAC_MODE_PORT_MODE_MII;
8924 } else
8925 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8926
8927 /* reset to prevent losing 1st rx packet intermittently */
8928 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8929 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8930 udelay(10);
8931 tw32_f(MAC_RX_MODE, tp->rx_mode);
8932 }
8933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
8934 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8935 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8936 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
8937 mac_mode |= MAC_MODE_LINK_POLARITY;
8938 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8939 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8940 }
8941 tw32(MAC_MODE, mac_mode);
8942 }
8943 else
8944 return -EINVAL;
8945
8946 err = -EIO;
8947
8948 tx_len = 1514;
8949 skb = netdev_alloc_skb(tp->dev, tx_len);
8950 if (!skb)
8951 return -ENOMEM;
8952
8953 tx_data = skb_put(skb, tx_len);
8954 memcpy(tx_data, tp->dev->dev_addr, 6);
8955 memset(tx_data + 6, 0x0, 8);
8956
8957 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8958
8959 for (i = 14; i < tx_len; i++)
8960 tx_data[i] = (u8) (i & 0xff);
8961
8962 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8963
8964 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8965 HOSTCC_MODE_NOW);
8966
8967 udelay(10);
8968
8969 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8970
8971 num_pkts = 0;
8972
8973 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8974
8975 tp->tx_prod++;
8976 num_pkts++;
8977
8978 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8979 tp->tx_prod);
8980 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8981
8982 udelay(10);
8983
8984 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8985 for (i = 0; i < 25; i++) {
8986 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8987 HOSTCC_MODE_NOW);
8988
8989 udelay(10);
8990
8991 tx_idx = tp->hw_status->idx[0].tx_consumer;
8992 rx_idx = tp->hw_status->idx[0].rx_producer;
8993 if ((tx_idx == tp->tx_prod) &&
8994 (rx_idx == (rx_start_idx + num_pkts)))
8995 break;
8996 }
8997
8998 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8999 dev_kfree_skb(skb);
9000
9001 if (tx_idx != tp->tx_prod)
9002 goto out;
9003
9004 if (rx_idx != rx_start_idx + num_pkts)
9005 goto out;
9006
9007 desc = &tp->rx_rcb[rx_start_idx];
9008 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9009 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9010 if (opaque_key != RXD_OPAQUE_RING_STD)
9011 goto out;
9012
9013 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9014 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9015 goto out;
9016
9017 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9018 if (rx_len != tx_len)
9019 goto out;
9020
9021 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9022
9023 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9024 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9025
9026 for (i = 14; i < tx_len; i++) {
9027 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9028 goto out;
9029 }
9030 err = 0;
9031
9032 /* tg3_free_rings will unmap and free the rx_skb */
9033 out:
9034 return err;
9035 }
9036
9037 #define TG3_MAC_LOOPBACK_FAILED 1
9038 #define TG3_PHY_LOOPBACK_FAILED 2
9039 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9040 TG3_PHY_LOOPBACK_FAILED)
9041
9042 static int tg3_test_loopback(struct tg3 *tp)
9043 {
9044 int err = 0;
9045
9046 if (!netif_running(tp->dev))
9047 return TG3_LOOPBACK_FAILED;
9048
9049 err = tg3_reset_hw(tp, 1);
9050 if (err)
9051 return TG3_LOOPBACK_FAILED;
9052
9053 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9054 err |= TG3_MAC_LOOPBACK_FAILED;
9055 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9056 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9057 err |= TG3_PHY_LOOPBACK_FAILED;
9058 }
9059
9060 return err;
9061 }
9062
9063 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9064 u64 *data)
9065 {
9066 struct tg3 *tp = netdev_priv(dev);
9067
9068 if (tp->link_config.phy_is_low_power)
9069 tg3_set_power_state(tp, PCI_D0);
9070
9071 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9072
9073 if (tg3_test_nvram(tp) != 0) {
9074 etest->flags |= ETH_TEST_FL_FAILED;
9075 data[0] = 1;
9076 }
9077 if (tg3_test_link(tp) != 0) {
9078 etest->flags |= ETH_TEST_FL_FAILED;
9079 data[1] = 1;
9080 }
9081 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9082 int err, irq_sync = 0;
9083
9084 if (netif_running(dev)) {
9085 tg3_netif_stop(tp);
9086 irq_sync = 1;
9087 }
9088
9089 tg3_full_lock(tp, irq_sync);
9090
9091 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9092 err = tg3_nvram_lock(tp);
9093 tg3_halt_cpu(tp, RX_CPU_BASE);
9094 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9095 tg3_halt_cpu(tp, TX_CPU_BASE);
9096 if (!err)
9097 tg3_nvram_unlock(tp);
9098
9099 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9100 tg3_phy_reset(tp);
9101
9102 if (tg3_test_registers(tp) != 0) {
9103 etest->flags |= ETH_TEST_FL_FAILED;
9104 data[2] = 1;
9105 }
9106 if (tg3_test_memory(tp) != 0) {
9107 etest->flags |= ETH_TEST_FL_FAILED;
9108 data[3] = 1;
9109 }
9110 if ((data[4] = tg3_test_loopback(tp)) != 0)
9111 etest->flags |= ETH_TEST_FL_FAILED;
9112
9113 tg3_full_unlock(tp);
9114
9115 if (tg3_test_interrupt(tp) != 0) {
9116 etest->flags |= ETH_TEST_FL_FAILED;
9117 data[5] = 1;
9118 }
9119
9120 tg3_full_lock(tp, 0);
9121
9122 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9123 if (netif_running(dev)) {
9124 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9125 if (!tg3_restart_hw(tp, 1))
9126 tg3_netif_start(tp);
9127 }
9128
9129 tg3_full_unlock(tp);
9130 }
9131 if (tp->link_config.phy_is_low_power)
9132 tg3_set_power_state(tp, PCI_D3hot);
9133
9134 }
9135
9136 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9137 {
9138 struct mii_ioctl_data *data = if_mii(ifr);
9139 struct tg3 *tp = netdev_priv(dev);
9140 int err;
9141
9142 switch(cmd) {
9143 case SIOCGMIIPHY:
9144 data->phy_id = PHY_ADDR;
9145
9146 /* fallthru */
9147 case SIOCGMIIREG: {
9148 u32 mii_regval;
9149
9150 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9151 break; /* We have no PHY */
9152
9153 if (tp->link_config.phy_is_low_power)
9154 return -EAGAIN;
9155
9156 spin_lock_bh(&tp->lock);
9157 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9158 spin_unlock_bh(&tp->lock);
9159
9160 data->val_out = mii_regval;
9161
9162 return err;
9163 }
9164
9165 case SIOCSMIIREG:
9166 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9167 break; /* We have no PHY */
9168
9169 if (!capable(CAP_NET_ADMIN))
9170 return -EPERM;
9171
9172 if (tp->link_config.phy_is_low_power)
9173 return -EAGAIN;
9174
9175 spin_lock_bh(&tp->lock);
9176 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9177 spin_unlock_bh(&tp->lock);
9178
9179 return err;
9180
9181 default:
9182 /* do nothing */
9183 break;
9184 }
9185 return -EOPNOTSUPP;
9186 }
9187
9188 #if TG3_VLAN_TAG_USED
9189 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9190 {
9191 struct tg3 *tp = netdev_priv(dev);
9192
9193 if (netif_running(dev))
9194 tg3_netif_stop(tp);
9195
9196 tg3_full_lock(tp, 0);
9197
9198 tp->vlgrp = grp;
9199
9200 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9201 __tg3_set_rx_mode(dev);
9202
9203 if (netif_running(dev))
9204 tg3_netif_start(tp);
9205
9206 tg3_full_unlock(tp);
9207 }
9208 #endif
9209
9210 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9211 {
9212 struct tg3 *tp = netdev_priv(dev);
9213
9214 memcpy(ec, &tp->coal, sizeof(*ec));
9215 return 0;
9216 }
9217
9218 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9219 {
9220 struct tg3 *tp = netdev_priv(dev);
9221 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9222 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9223
9224 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9225 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9226 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9227 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9228 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9229 }
9230
9231 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9232 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9233 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9234 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9235 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9236 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9237 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9238 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9239 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9240 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9241 return -EINVAL;
9242
9243 /* No rx interrupts will be generated if both are zero */
9244 if ((ec->rx_coalesce_usecs == 0) &&
9245 (ec->rx_max_coalesced_frames == 0))
9246 return -EINVAL;
9247
9248 /* No tx interrupts will be generated if both are zero */
9249 if ((ec->tx_coalesce_usecs == 0) &&
9250 (ec->tx_max_coalesced_frames == 0))
9251 return -EINVAL;
9252
9253 /* Only copy relevant parameters, ignore all others. */
9254 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9255 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9256 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9257 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9258 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9259 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9260 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9261 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9262 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9263
9264 if (netif_running(dev)) {
9265 tg3_full_lock(tp, 0);
9266 __tg3_set_coalesce(tp, &tp->coal);
9267 tg3_full_unlock(tp);
9268 }
9269 return 0;
9270 }
9271
9272 static const struct ethtool_ops tg3_ethtool_ops = {
9273 .get_settings = tg3_get_settings,
9274 .set_settings = tg3_set_settings,
9275 .get_drvinfo = tg3_get_drvinfo,
9276 .get_regs_len = tg3_get_regs_len,
9277 .get_regs = tg3_get_regs,
9278 .get_wol = tg3_get_wol,
9279 .set_wol = tg3_set_wol,
9280 .get_msglevel = tg3_get_msglevel,
9281 .set_msglevel = tg3_set_msglevel,
9282 .nway_reset = tg3_nway_reset,
9283 .get_link = ethtool_op_get_link,
9284 .get_eeprom_len = tg3_get_eeprom_len,
9285 .get_eeprom = tg3_get_eeprom,
9286 .set_eeprom = tg3_set_eeprom,
9287 .get_ringparam = tg3_get_ringparam,
9288 .set_ringparam = tg3_set_ringparam,
9289 .get_pauseparam = tg3_get_pauseparam,
9290 .set_pauseparam = tg3_set_pauseparam,
9291 .get_rx_csum = tg3_get_rx_csum,
9292 .set_rx_csum = tg3_set_rx_csum,
9293 .get_tx_csum = ethtool_op_get_tx_csum,
9294 .set_tx_csum = tg3_set_tx_csum,
9295 .get_sg = ethtool_op_get_sg,
9296 .set_sg = ethtool_op_set_sg,
9297 .get_tso = ethtool_op_get_tso,
9298 .set_tso = tg3_set_tso,
9299 .self_test_count = tg3_get_test_count,
9300 .self_test = tg3_self_test,
9301 .get_strings = tg3_get_strings,
9302 .phys_id = tg3_phys_id,
9303 .get_stats_count = tg3_get_stats_count,
9304 .get_ethtool_stats = tg3_get_ethtool_stats,
9305 .get_coalesce = tg3_get_coalesce,
9306 .set_coalesce = tg3_set_coalesce,
9307 };
9308
9309 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9310 {
9311 u32 cursize, val, magic;
9312
9313 tp->nvram_size = EEPROM_CHIP_SIZE;
9314
9315 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9316 return;
9317
9318 if ((magic != TG3_EEPROM_MAGIC) &&
9319 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9320 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9321 return;
9322
9323 /*
9324 * Size the chip by reading offsets at increasing powers of two.
9325 * When we encounter our validation signature, we know the addressing
9326 * has wrapped around, and thus have our chip size.
9327 */
9328 cursize = 0x10;
9329
9330 while (cursize < tp->nvram_size) {
9331 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9332 return;
9333
9334 if (val == magic)
9335 break;
9336
9337 cursize <<= 1;
9338 }
9339
9340 tp->nvram_size = cursize;
9341 }
9342
9343 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9344 {
9345 u32 val;
9346
9347 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9348 return;
9349
9350 /* Selfboot format */
9351 if (val != TG3_EEPROM_MAGIC) {
9352 tg3_get_eeprom_size(tp);
9353 return;
9354 }
9355
9356 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9357 if (val != 0) {
9358 tp->nvram_size = (val >> 16) * 1024;
9359 return;
9360 }
9361 }
9362 tp->nvram_size = 0x80000;
9363 }
9364
9365 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9366 {
9367 u32 nvcfg1;
9368
9369 nvcfg1 = tr32(NVRAM_CFG1);
9370 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9371 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9372 }
9373 else {
9374 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9375 tw32(NVRAM_CFG1, nvcfg1);
9376 }
9377
9378 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9379 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9380 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9381 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9382 tp->nvram_jedecnum = JEDEC_ATMEL;
9383 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9384 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9385 break;
9386 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9387 tp->nvram_jedecnum = JEDEC_ATMEL;
9388 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9389 break;
9390 case FLASH_VENDOR_ATMEL_EEPROM:
9391 tp->nvram_jedecnum = JEDEC_ATMEL;
9392 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9393 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9394 break;
9395 case FLASH_VENDOR_ST:
9396 tp->nvram_jedecnum = JEDEC_ST;
9397 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9398 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9399 break;
9400 case FLASH_VENDOR_SAIFUN:
9401 tp->nvram_jedecnum = JEDEC_SAIFUN;
9402 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9403 break;
9404 case FLASH_VENDOR_SST_SMALL:
9405 case FLASH_VENDOR_SST_LARGE:
9406 tp->nvram_jedecnum = JEDEC_SST;
9407 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9408 break;
9409 }
9410 }
9411 else {
9412 tp->nvram_jedecnum = JEDEC_ATMEL;
9413 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9414 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9415 }
9416 }
9417
9418 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9419 {
9420 u32 nvcfg1;
9421
9422 nvcfg1 = tr32(NVRAM_CFG1);
9423
9424 /* NVRAM protection for TPM */
9425 if (nvcfg1 & (1 << 27))
9426 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9427
9428 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9429 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9430 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9431 tp->nvram_jedecnum = JEDEC_ATMEL;
9432 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9433 break;
9434 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9435 tp->nvram_jedecnum = JEDEC_ATMEL;
9436 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9437 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9438 break;
9439 case FLASH_5752VENDOR_ST_M45PE10:
9440 case FLASH_5752VENDOR_ST_M45PE20:
9441 case FLASH_5752VENDOR_ST_M45PE40:
9442 tp->nvram_jedecnum = JEDEC_ST;
9443 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9444 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9445 break;
9446 }
9447
9448 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9449 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9450 case FLASH_5752PAGE_SIZE_256:
9451 tp->nvram_pagesize = 256;
9452 break;
9453 case FLASH_5752PAGE_SIZE_512:
9454 tp->nvram_pagesize = 512;
9455 break;
9456 case FLASH_5752PAGE_SIZE_1K:
9457 tp->nvram_pagesize = 1024;
9458 break;
9459 case FLASH_5752PAGE_SIZE_2K:
9460 tp->nvram_pagesize = 2048;
9461 break;
9462 case FLASH_5752PAGE_SIZE_4K:
9463 tp->nvram_pagesize = 4096;
9464 break;
9465 case FLASH_5752PAGE_SIZE_264:
9466 tp->nvram_pagesize = 264;
9467 break;
9468 }
9469 }
9470 else {
9471 /* For eeprom, set pagesize to maximum eeprom size */
9472 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9473
9474 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9475 tw32(NVRAM_CFG1, nvcfg1);
9476 }
9477 }
9478
9479 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9480 {
9481 u32 nvcfg1, protect = 0;
9482
9483 nvcfg1 = tr32(NVRAM_CFG1);
9484
9485 /* NVRAM protection for TPM */
9486 if (nvcfg1 & (1 << 27)) {
9487 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9488 protect = 1;
9489 }
9490
9491 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9492 switch (nvcfg1) {
9493 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9494 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9495 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9496 case FLASH_5755VENDOR_ATMEL_FLASH_5:
9497 tp->nvram_jedecnum = JEDEC_ATMEL;
9498 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9499 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9500 tp->nvram_pagesize = 264;
9501 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
9502 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
9503 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9504 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9505 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9506 else
9507 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9508 break;
9509 case FLASH_5752VENDOR_ST_M45PE10:
9510 case FLASH_5752VENDOR_ST_M45PE20:
9511 case FLASH_5752VENDOR_ST_M45PE40:
9512 tp->nvram_jedecnum = JEDEC_ST;
9513 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9514 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9515 tp->nvram_pagesize = 256;
9516 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9517 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9518 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9519 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9520 else
9521 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9522 break;
9523 }
9524 }
9525
9526 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9527 {
9528 u32 nvcfg1;
9529
9530 nvcfg1 = tr32(NVRAM_CFG1);
9531
9532 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9533 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9534 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9535 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9536 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9537 tp->nvram_jedecnum = JEDEC_ATMEL;
9538 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9539 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9540
9541 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9542 tw32(NVRAM_CFG1, nvcfg1);
9543 break;
9544 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9545 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9546 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9547 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9548 tp->nvram_jedecnum = JEDEC_ATMEL;
9549 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9550 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9551 tp->nvram_pagesize = 264;
9552 break;
9553 case FLASH_5752VENDOR_ST_M45PE10:
9554 case FLASH_5752VENDOR_ST_M45PE20:
9555 case FLASH_5752VENDOR_ST_M45PE40:
9556 tp->nvram_jedecnum = JEDEC_ST;
9557 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9558 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9559 tp->nvram_pagesize = 256;
9560 break;
9561 }
9562 }
9563
9564 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9565 {
9566 tp->nvram_jedecnum = JEDEC_ATMEL;
9567 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9568 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9569 }
9570
9571 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9572 static void __devinit tg3_nvram_init(struct tg3 *tp)
9573 {
9574 tw32_f(GRC_EEPROM_ADDR,
9575 (EEPROM_ADDR_FSM_RESET |
9576 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9577 EEPROM_ADDR_CLKPERD_SHIFT)));
9578
9579 msleep(1);
9580
9581 /* Enable seeprom accesses. */
9582 tw32_f(GRC_LOCAL_CTRL,
9583 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9584 udelay(100);
9585
9586 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9587 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9588 tp->tg3_flags |= TG3_FLAG_NVRAM;
9589
9590 if (tg3_nvram_lock(tp)) {
9591 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9592 "tg3_nvram_init failed.\n", tp->dev->name);
9593 return;
9594 }
9595 tg3_enable_nvram_access(tp);
9596
9597 tp->nvram_size = 0;
9598
9599 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9600 tg3_get_5752_nvram_info(tp);
9601 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9602 tg3_get_5755_nvram_info(tp);
9603 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9604 tg3_get_5787_nvram_info(tp);
9605 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9606 tg3_get_5906_nvram_info(tp);
9607 else
9608 tg3_get_nvram_info(tp);
9609
9610 if (tp->nvram_size == 0)
9611 tg3_get_nvram_size(tp);
9612
9613 tg3_disable_nvram_access(tp);
9614 tg3_nvram_unlock(tp);
9615
9616 } else {
9617 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9618
9619 tg3_get_eeprom_size(tp);
9620 }
9621 }
9622
9623 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9624 u32 offset, u32 *val)
9625 {
9626 u32 tmp;
9627 int i;
9628
9629 if (offset > EEPROM_ADDR_ADDR_MASK ||
9630 (offset % 4) != 0)
9631 return -EINVAL;
9632
9633 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9634 EEPROM_ADDR_DEVID_MASK |
9635 EEPROM_ADDR_READ);
9636 tw32(GRC_EEPROM_ADDR,
9637 tmp |
9638 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9639 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9640 EEPROM_ADDR_ADDR_MASK) |
9641 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9642
9643 for (i = 0; i < 1000; i++) {
9644 tmp = tr32(GRC_EEPROM_ADDR);
9645
9646 if (tmp & EEPROM_ADDR_COMPLETE)
9647 break;
9648 msleep(1);
9649 }
9650 if (!(tmp & EEPROM_ADDR_COMPLETE))
9651 return -EBUSY;
9652
9653 *val = tr32(GRC_EEPROM_DATA);
9654 return 0;
9655 }
9656
9657 #define NVRAM_CMD_TIMEOUT 10000
9658
9659 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9660 {
9661 int i;
9662
9663 tw32(NVRAM_CMD, nvram_cmd);
9664 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9665 udelay(10);
9666 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9667 udelay(10);
9668 break;
9669 }
9670 }
9671 if (i == NVRAM_CMD_TIMEOUT) {
9672 return -EBUSY;
9673 }
9674 return 0;
9675 }
9676
9677 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9678 {
9679 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9680 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9681 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9682 (tp->nvram_jedecnum == JEDEC_ATMEL))
9683
9684 addr = ((addr / tp->nvram_pagesize) <<
9685 ATMEL_AT45DB0X1B_PAGE_POS) +
9686 (addr % tp->nvram_pagesize);
9687
9688 return addr;
9689 }
9690
9691 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9692 {
9693 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9694 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9695 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9696 (tp->nvram_jedecnum == JEDEC_ATMEL))
9697
9698 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9699 tp->nvram_pagesize) +
9700 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9701
9702 return addr;
9703 }
9704
9705 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9706 {
9707 int ret;
9708
9709 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9710 return tg3_nvram_read_using_eeprom(tp, offset, val);
9711
9712 offset = tg3_nvram_phys_addr(tp, offset);
9713
9714 if (offset > NVRAM_ADDR_MSK)
9715 return -EINVAL;
9716
9717 ret = tg3_nvram_lock(tp);
9718 if (ret)
9719 return ret;
9720
9721 tg3_enable_nvram_access(tp);
9722
9723 tw32(NVRAM_ADDR, offset);
9724 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9725 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9726
9727 if (ret == 0)
9728 *val = swab32(tr32(NVRAM_RDDATA));
9729
9730 tg3_disable_nvram_access(tp);
9731
9732 tg3_nvram_unlock(tp);
9733
9734 return ret;
9735 }
9736
9737 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9738 {
9739 int err;
9740 u32 tmp;
9741
9742 err = tg3_nvram_read(tp, offset, &tmp);
9743 *val = swab32(tmp);
9744 return err;
9745 }
9746
9747 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9748 u32 offset, u32 len, u8 *buf)
9749 {
9750 int i, j, rc = 0;
9751 u32 val;
9752
9753 for (i = 0; i < len; i += 4) {
9754 u32 addr, data;
9755
9756 addr = offset + i;
9757
9758 memcpy(&data, buf + i, 4);
9759
9760 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9761
9762 val = tr32(GRC_EEPROM_ADDR);
9763 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9764
9765 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9766 EEPROM_ADDR_READ);
9767 tw32(GRC_EEPROM_ADDR, val |
9768 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9769 (addr & EEPROM_ADDR_ADDR_MASK) |
9770 EEPROM_ADDR_START |
9771 EEPROM_ADDR_WRITE);
9772
9773 for (j = 0; j < 1000; j++) {
9774 val = tr32(GRC_EEPROM_ADDR);
9775
9776 if (val & EEPROM_ADDR_COMPLETE)
9777 break;
9778 msleep(1);
9779 }
9780 if (!(val & EEPROM_ADDR_COMPLETE)) {
9781 rc = -EBUSY;
9782 break;
9783 }
9784 }
9785
9786 return rc;
9787 }
9788
9789 /* offset and length are dword aligned */
9790 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9791 u8 *buf)
9792 {
9793 int ret = 0;
9794 u32 pagesize = tp->nvram_pagesize;
9795 u32 pagemask = pagesize - 1;
9796 u32 nvram_cmd;
9797 u8 *tmp;
9798
9799 tmp = kmalloc(pagesize, GFP_KERNEL);
9800 if (tmp == NULL)
9801 return -ENOMEM;
9802
9803 while (len) {
9804 int j;
9805 u32 phy_addr, page_off, size;
9806
9807 phy_addr = offset & ~pagemask;
9808
9809 for (j = 0; j < pagesize; j += 4) {
9810 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9811 (u32 *) (tmp + j))))
9812 break;
9813 }
9814 if (ret)
9815 break;
9816
9817 page_off = offset & pagemask;
9818 size = pagesize;
9819 if (len < size)
9820 size = len;
9821
9822 len -= size;
9823
9824 memcpy(tmp + page_off, buf, size);
9825
9826 offset = offset + (pagesize - page_off);
9827
9828 tg3_enable_nvram_access(tp);
9829
9830 /*
9831 * Before we can erase the flash page, we need
9832 * to issue a special "write enable" command.
9833 */
9834 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9835
9836 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9837 break;
9838
9839 /* Erase the target page */
9840 tw32(NVRAM_ADDR, phy_addr);
9841
9842 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9843 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9844
9845 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9846 break;
9847
9848 /* Issue another write enable to start the write. */
9849 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9850
9851 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9852 break;
9853
9854 for (j = 0; j < pagesize; j += 4) {
9855 u32 data;
9856
9857 data = *((u32 *) (tmp + j));
9858 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9859
9860 tw32(NVRAM_ADDR, phy_addr + j);
9861
9862 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9863 NVRAM_CMD_WR;
9864
9865 if (j == 0)
9866 nvram_cmd |= NVRAM_CMD_FIRST;
9867 else if (j == (pagesize - 4))
9868 nvram_cmd |= NVRAM_CMD_LAST;
9869
9870 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9871 break;
9872 }
9873 if (ret)
9874 break;
9875 }
9876
9877 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9878 tg3_nvram_exec_cmd(tp, nvram_cmd);
9879
9880 kfree(tmp);
9881
9882 return ret;
9883 }
9884
9885 /* offset and length are dword aligned */
9886 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9887 u8 *buf)
9888 {
9889 int i, ret = 0;
9890
9891 for (i = 0; i < len; i += 4, offset += 4) {
9892 u32 data, page_off, phy_addr, nvram_cmd;
9893
9894 memcpy(&data, buf + i, 4);
9895 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9896
9897 page_off = offset % tp->nvram_pagesize;
9898
9899 phy_addr = tg3_nvram_phys_addr(tp, offset);
9900
9901 tw32(NVRAM_ADDR, phy_addr);
9902
9903 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9904
9905 if ((page_off == 0) || (i == 0))
9906 nvram_cmd |= NVRAM_CMD_FIRST;
9907 if (page_off == (tp->nvram_pagesize - 4))
9908 nvram_cmd |= NVRAM_CMD_LAST;
9909
9910 if (i == (len - 4))
9911 nvram_cmd |= NVRAM_CMD_LAST;
9912
9913 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9914 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9915 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9916 (tp->nvram_jedecnum == JEDEC_ST) &&
9917 (nvram_cmd & NVRAM_CMD_FIRST)) {
9918
9919 if ((ret = tg3_nvram_exec_cmd(tp,
9920 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9921 NVRAM_CMD_DONE)))
9922
9923 break;
9924 }
9925 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9926 /* We always do complete word writes to eeprom. */
9927 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9928 }
9929
9930 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9931 break;
9932 }
9933 return ret;
9934 }
9935
9936 /* offset and length are dword aligned */
9937 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9938 {
9939 int ret;
9940
9941 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9942 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9943 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9944 udelay(40);
9945 }
9946
9947 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9948 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9949 }
9950 else {
9951 u32 grc_mode;
9952
9953 ret = tg3_nvram_lock(tp);
9954 if (ret)
9955 return ret;
9956
9957 tg3_enable_nvram_access(tp);
9958 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9959 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9960 tw32(NVRAM_WRITE1, 0x406);
9961
9962 grc_mode = tr32(GRC_MODE);
9963 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9964
9965 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9966 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9967
9968 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9969 buf);
9970 }
9971 else {
9972 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9973 buf);
9974 }
9975
9976 grc_mode = tr32(GRC_MODE);
9977 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9978
9979 tg3_disable_nvram_access(tp);
9980 tg3_nvram_unlock(tp);
9981 }
9982
9983 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9984 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9985 udelay(40);
9986 }
9987
9988 return ret;
9989 }
9990
9991 struct subsys_tbl_ent {
9992 u16 subsys_vendor, subsys_devid;
9993 u32 phy_id;
9994 };
9995
9996 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9997 /* Broadcom boards. */
9998 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9999 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10000 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10001 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10002 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10003 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10004 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10005 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10006 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10007 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10008 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10009
10010 /* 3com boards. */
10011 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10012 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10013 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10014 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10015 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10016
10017 /* DELL boards. */
10018 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10019 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10020 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10021 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10022
10023 /* Compaq boards. */
10024 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10025 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10026 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10027 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10028 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10029
10030 /* IBM boards. */
10031 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10032 };
10033
10034 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10035 {
10036 int i;
10037
10038 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10039 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10040 tp->pdev->subsystem_vendor) &&
10041 (subsys_id_to_phy_id[i].subsys_devid ==
10042 tp->pdev->subsystem_device))
10043 return &subsys_id_to_phy_id[i];
10044 }
10045 return NULL;
10046 }
10047
10048 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10049 {
10050 u32 val;
10051 u16 pmcsr;
10052
10053 /* On some early chips the SRAM cannot be accessed in D3hot state,
10054 * so need make sure we're in D0.
10055 */
10056 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10057 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10058 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10059 msleep(1);
10060
10061 /* Make sure register accesses (indirect or otherwise)
10062 * will function correctly.
10063 */
10064 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10065 tp->misc_host_ctrl);
10066
10067 /* The memory arbiter has to be enabled in order for SRAM accesses
10068 * to succeed. Normally on powerup the tg3 chip firmware will make
10069 * sure it is enabled, but other entities such as system netboot
10070 * code might disable it.
10071 */
10072 val = tr32(MEMARB_MODE);
10073 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10074
10075 tp->phy_id = PHY_ID_INVALID;
10076 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10077
10078 /* Assume an onboard device and WOL capable by default. */
10079 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10080
10081 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10082 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10083 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10084 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10085 }
10086 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10087 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10088 return;
10089 }
10090
10091 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10092 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10093 u32 nic_cfg, led_cfg;
10094 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10095 int eeprom_phy_serdes = 0;
10096
10097 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10098 tp->nic_sram_data_cfg = nic_cfg;
10099
10100 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10101 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10103 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10104 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10105 (ver > 0) && (ver < 0x100))
10106 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10107
10108 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10109 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10110 eeprom_phy_serdes = 1;
10111
10112 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10113 if (nic_phy_id != 0) {
10114 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10115 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10116
10117 eeprom_phy_id = (id1 >> 16) << 10;
10118 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10119 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10120 } else
10121 eeprom_phy_id = 0;
10122
10123 tp->phy_id = eeprom_phy_id;
10124 if (eeprom_phy_serdes) {
10125 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10126 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10127 else
10128 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10129 }
10130
10131 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10132 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10133 SHASTA_EXT_LED_MODE_MASK);
10134 else
10135 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10136
10137 switch (led_cfg) {
10138 default:
10139 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10140 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10141 break;
10142
10143 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10144 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10145 break;
10146
10147 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10148 tp->led_ctrl = LED_CTRL_MODE_MAC;
10149
10150 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10151 * read on some older 5700/5701 bootcode.
10152 */
10153 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10154 ASIC_REV_5700 ||
10155 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10156 ASIC_REV_5701)
10157 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10158
10159 break;
10160
10161 case SHASTA_EXT_LED_SHARED:
10162 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10163 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10164 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10165 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10166 LED_CTRL_MODE_PHY_2);
10167 break;
10168
10169 case SHASTA_EXT_LED_MAC:
10170 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10171 break;
10172
10173 case SHASTA_EXT_LED_COMBO:
10174 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10175 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10176 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10177 LED_CTRL_MODE_PHY_2);
10178 break;
10179
10180 };
10181
10182 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10183 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10184 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10185 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10186
10187 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10188 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10189 if ((tp->pdev->subsystem_vendor ==
10190 PCI_VENDOR_ID_ARIMA) &&
10191 (tp->pdev->subsystem_device == 0x205a ||
10192 tp->pdev->subsystem_device == 0x2063))
10193 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10194 } else {
10195 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10196 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10197 }
10198
10199 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10200 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10201 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10202 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10203 }
10204 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10205 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10206 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10207
10208 if (cfg2 & (1 << 17))
10209 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10210
10211 /* serdes signal pre-emphasis in register 0x590 set by */
10212 /* bootcode if bit 18 is set */
10213 if (cfg2 & (1 << 18))
10214 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10215
10216 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10217 u32 cfg3;
10218
10219 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10220 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10221 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10222 }
10223 }
10224 }
10225
10226 static int __devinit tg3_phy_probe(struct tg3 *tp)
10227 {
10228 u32 hw_phy_id_1, hw_phy_id_2;
10229 u32 hw_phy_id, hw_phy_id_masked;
10230 int err;
10231
10232 /* Reading the PHY ID register can conflict with ASF
10233 * firwmare access to the PHY hardware.
10234 */
10235 err = 0;
10236 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10237 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10238 } else {
10239 /* Now read the physical PHY_ID from the chip and verify
10240 * that it is sane. If it doesn't look good, we fall back
10241 * to either the hard-coded table based PHY_ID and failing
10242 * that the value found in the eeprom area.
10243 */
10244 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10245 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10246
10247 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10248 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10249 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10250
10251 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10252 }
10253
10254 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10255 tp->phy_id = hw_phy_id;
10256 if (hw_phy_id_masked == PHY_ID_BCM8002)
10257 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10258 else
10259 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10260 } else {
10261 if (tp->phy_id != PHY_ID_INVALID) {
10262 /* Do nothing, phy ID already set up in
10263 * tg3_get_eeprom_hw_cfg().
10264 */
10265 } else {
10266 struct subsys_tbl_ent *p;
10267
10268 /* No eeprom signature? Try the hardcoded
10269 * subsys device table.
10270 */
10271 p = lookup_by_subsys(tp);
10272 if (!p)
10273 return -ENODEV;
10274
10275 tp->phy_id = p->phy_id;
10276 if (!tp->phy_id ||
10277 tp->phy_id == PHY_ID_BCM8002)
10278 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10279 }
10280 }
10281
10282 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10283 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10284 u32 bmsr, adv_reg, tg3_ctrl, mask;
10285
10286 tg3_readphy(tp, MII_BMSR, &bmsr);
10287 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10288 (bmsr & BMSR_LSTATUS))
10289 goto skip_phy_reset;
10290
10291 err = tg3_phy_reset(tp);
10292 if (err)
10293 return err;
10294
10295 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10296 ADVERTISE_100HALF | ADVERTISE_100FULL |
10297 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10298 tg3_ctrl = 0;
10299 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10300 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10301 MII_TG3_CTRL_ADV_1000_FULL);
10302 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10303 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10304 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10305 MII_TG3_CTRL_ENABLE_AS_MASTER);
10306 }
10307
10308 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10309 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10310 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10311 if (!tg3_copper_is_advertising_all(tp, mask)) {
10312 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10313
10314 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10315 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10316
10317 tg3_writephy(tp, MII_BMCR,
10318 BMCR_ANENABLE | BMCR_ANRESTART);
10319 }
10320 tg3_phy_set_wirespeed(tp);
10321
10322 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10323 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10324 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10325 }
10326
10327 skip_phy_reset:
10328 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10329 err = tg3_init_5401phy_dsp(tp);
10330 if (err)
10331 return err;
10332 }
10333
10334 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10335 err = tg3_init_5401phy_dsp(tp);
10336 }
10337
10338 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10339 tp->link_config.advertising =
10340 (ADVERTISED_1000baseT_Half |
10341 ADVERTISED_1000baseT_Full |
10342 ADVERTISED_Autoneg |
10343 ADVERTISED_FIBRE);
10344 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10345 tp->link_config.advertising &=
10346 ~(ADVERTISED_1000baseT_Half |
10347 ADVERTISED_1000baseT_Full);
10348
10349 return err;
10350 }
10351
10352 static void __devinit tg3_read_partno(struct tg3 *tp)
10353 {
10354 unsigned char vpd_data[256];
10355 unsigned int i;
10356 u32 magic;
10357
10358 if (tg3_nvram_read_swab(tp, 0x0, &magic))
10359 goto out_not_found;
10360
10361 if (magic == TG3_EEPROM_MAGIC) {
10362 for (i = 0; i < 256; i += 4) {
10363 u32 tmp;
10364
10365 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10366 goto out_not_found;
10367
10368 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10369 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10370 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10371 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10372 }
10373 } else {
10374 int vpd_cap;
10375
10376 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10377 for (i = 0; i < 256; i += 4) {
10378 u32 tmp, j = 0;
10379 u16 tmp16;
10380
10381 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10382 i);
10383 while (j++ < 100) {
10384 pci_read_config_word(tp->pdev, vpd_cap +
10385 PCI_VPD_ADDR, &tmp16);
10386 if (tmp16 & 0x8000)
10387 break;
10388 msleep(1);
10389 }
10390 if (!(tmp16 & 0x8000))
10391 goto out_not_found;
10392
10393 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10394 &tmp);
10395 tmp = cpu_to_le32(tmp);
10396 memcpy(&vpd_data[i], &tmp, 4);
10397 }
10398 }
10399
10400 /* Now parse and find the part number. */
10401 for (i = 0; i < 254; ) {
10402 unsigned char val = vpd_data[i];
10403 unsigned int block_end;
10404
10405 if (val == 0x82 || val == 0x91) {
10406 i = (i + 3 +
10407 (vpd_data[i + 1] +
10408 (vpd_data[i + 2] << 8)));
10409 continue;
10410 }
10411
10412 if (val != 0x90)
10413 goto out_not_found;
10414
10415 block_end = (i + 3 +
10416 (vpd_data[i + 1] +
10417 (vpd_data[i + 2] << 8)));
10418 i += 3;
10419
10420 if (block_end > 256)
10421 goto out_not_found;
10422
10423 while (i < (block_end - 2)) {
10424 if (vpd_data[i + 0] == 'P' &&
10425 vpd_data[i + 1] == 'N') {
10426 int partno_len = vpd_data[i + 2];
10427
10428 i += 3;
10429 if (partno_len > 24 || (partno_len + i) > 256)
10430 goto out_not_found;
10431
10432 memcpy(tp->board_part_number,
10433 &vpd_data[i], partno_len);
10434
10435 /* Success. */
10436 return;
10437 }
10438 i += 3 + vpd_data[i + 2];
10439 }
10440
10441 /* Part number not found. */
10442 goto out_not_found;
10443 }
10444
10445 out_not_found:
10446 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10447 strcpy(tp->board_part_number, "BCM95906");
10448 else
10449 strcpy(tp->board_part_number, "none");
10450 }
10451
10452 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10453 {
10454 u32 val, offset, start;
10455
10456 if (tg3_nvram_read_swab(tp, 0, &val))
10457 return;
10458
10459 if (val != TG3_EEPROM_MAGIC)
10460 return;
10461
10462 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10463 tg3_nvram_read_swab(tp, 0x4, &start))
10464 return;
10465
10466 offset = tg3_nvram_logical_addr(tp, offset);
10467 if (tg3_nvram_read_swab(tp, offset, &val))
10468 return;
10469
10470 if ((val & 0xfc000000) == 0x0c000000) {
10471 u32 ver_offset, addr;
10472 int i;
10473
10474 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10475 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10476 return;
10477
10478 if (val != 0)
10479 return;
10480
10481 addr = offset + ver_offset - start;
10482 for (i = 0; i < 16; i += 4) {
10483 if (tg3_nvram_read(tp, addr + i, &val))
10484 return;
10485
10486 val = cpu_to_le32(val);
10487 memcpy(tp->fw_ver + i, &val, 4);
10488 }
10489 }
10490 }
10491
10492 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10493
10494 static int __devinit tg3_get_invariants(struct tg3 *tp)
10495 {
10496 static struct pci_device_id write_reorder_chipsets[] = {
10497 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10498 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10499 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10500 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10501 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10502 PCI_DEVICE_ID_VIA_8385_0) },
10503 { },
10504 };
10505 u32 misc_ctrl_reg;
10506 u32 cacheline_sz_reg;
10507 u32 pci_state_reg, grc_misc_cfg;
10508 u32 val;
10509 u16 pci_cmd;
10510 int err, pcie_cap;
10511
10512 /* Force memory write invalidate off. If we leave it on,
10513 * then on 5700_BX chips we have to enable a workaround.
10514 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10515 * to match the cacheline size. The Broadcom driver have this
10516 * workaround but turns MWI off all the times so never uses
10517 * it. This seems to suggest that the workaround is insufficient.
10518 */
10519 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10520 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10521 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10522
10523 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10524 * has the register indirect write enable bit set before
10525 * we try to access any of the MMIO registers. It is also
10526 * critical that the PCI-X hw workaround situation is decided
10527 * before that as well.
10528 */
10529 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10530 &misc_ctrl_reg);
10531
10532 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10533 MISC_HOST_CTRL_CHIPREV_SHIFT);
10534
10535 /* Wrong chip ID in 5752 A0. This code can be removed later
10536 * as A0 is not in production.
10537 */
10538 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10539 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10540
10541 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10542 * we need to disable memory and use config. cycles
10543 * only to access all registers. The 5702/03 chips
10544 * can mistakenly decode the special cycles from the
10545 * ICH chipsets as memory write cycles, causing corruption
10546 * of register and memory space. Only certain ICH bridges
10547 * will drive special cycles with non-zero data during the
10548 * address phase which can fall within the 5703's address
10549 * range. This is not an ICH bug as the PCI spec allows
10550 * non-zero address during special cycles. However, only
10551 * these ICH bridges are known to drive non-zero addresses
10552 * during special cycles.
10553 *
10554 * Since special cycles do not cross PCI bridges, we only
10555 * enable this workaround if the 5703 is on the secondary
10556 * bus of these ICH bridges.
10557 */
10558 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10559 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10560 static struct tg3_dev_id {
10561 u32 vendor;
10562 u32 device;
10563 u32 rev;
10564 } ich_chipsets[] = {
10565 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10566 PCI_ANY_ID },
10567 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10568 PCI_ANY_ID },
10569 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10570 0xa },
10571 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10572 PCI_ANY_ID },
10573 { },
10574 };
10575 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10576 struct pci_dev *bridge = NULL;
10577
10578 while (pci_id->vendor != 0) {
10579 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10580 bridge);
10581 if (!bridge) {
10582 pci_id++;
10583 continue;
10584 }
10585 if (pci_id->rev != PCI_ANY_ID) {
10586 if (bridge->revision > pci_id->rev)
10587 continue;
10588 }
10589 if (bridge->subordinate &&
10590 (bridge->subordinate->number ==
10591 tp->pdev->bus->number)) {
10592
10593 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10594 pci_dev_put(bridge);
10595 break;
10596 }
10597 }
10598 }
10599
10600 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10601 * DMA addresses > 40-bit. This bridge may have other additional
10602 * 57xx devices behind it in some 4-port NIC designs for example.
10603 * Any tg3 device found behind the bridge will also need the 40-bit
10604 * DMA workaround.
10605 */
10606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10607 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10608 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10609 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10610 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10611 }
10612 else {
10613 struct pci_dev *bridge = NULL;
10614
10615 do {
10616 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10617 PCI_DEVICE_ID_SERVERWORKS_EPB,
10618 bridge);
10619 if (bridge && bridge->subordinate &&
10620 (bridge->subordinate->number <=
10621 tp->pdev->bus->number) &&
10622 (bridge->subordinate->subordinate >=
10623 tp->pdev->bus->number)) {
10624 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10625 pci_dev_put(bridge);
10626 break;
10627 }
10628 } while (bridge);
10629 }
10630
10631 /* Initialize misc host control in PCI block. */
10632 tp->misc_host_ctrl |= (misc_ctrl_reg &
10633 MISC_HOST_CTRL_CHIPREV);
10634 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10635 tp->misc_host_ctrl);
10636
10637 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10638 &cacheline_sz_reg);
10639
10640 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10641 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10642 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10643 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10644
10645 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10646 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10647 tp->pdev_peer = tg3_find_peer(tp);
10648
10649 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10653 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10654 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10655 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10656
10657 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10658 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10659 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10660
10661 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10662 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10663 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10664 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10665 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10666 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10667 tp->pdev_peer == tp->pdev))
10668 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10669
10670 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10672 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10673 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10674 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10675 } else {
10676 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10677 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10678 ASIC_REV_5750 &&
10679 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10680 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10681 }
10682 }
10683
10684 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10685 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10686 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10687 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10688 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10689 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10690 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10691
10692 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10693 if (pcie_cap != 0) {
10694 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10696 u16 lnkctl;
10697
10698 pci_read_config_word(tp->pdev,
10699 pcie_cap + PCI_EXP_LNKCTL,
10700 &lnkctl);
10701 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10702 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10703 }
10704 }
10705
10706 /* If we have an AMD 762 or VIA K8T800 chipset, write
10707 * reordering to the mailbox registers done by the host
10708 * controller can cause major troubles. We read back from
10709 * every mailbox register write to force the writes to be
10710 * posted to the chip in order.
10711 */
10712 if (pci_dev_present(write_reorder_chipsets) &&
10713 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10714 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10715
10716 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10717 tp->pci_lat_timer < 64) {
10718 tp->pci_lat_timer = 64;
10719
10720 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10721 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10722 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10723 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10724
10725 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10726 cacheline_sz_reg);
10727 }
10728
10729 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10730 &pci_state_reg);
10731
10732 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10733 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10734
10735 /* If this is a 5700 BX chipset, and we are in PCI-X
10736 * mode, enable register write workaround.
10737 *
10738 * The workaround is to use indirect register accesses
10739 * for all chip writes not to mailbox registers.
10740 */
10741 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10742 u32 pm_reg;
10743 u16 pci_cmd;
10744
10745 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10746
10747 /* The chip can have it's power management PCI config
10748 * space registers clobbered due to this bug.
10749 * So explicitly force the chip into D0 here.
10750 */
10751 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10752 &pm_reg);
10753 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10754 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10755 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10756 pm_reg);
10757
10758 /* Also, force SERR#/PERR# in PCI command. */
10759 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10760 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10761 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10762 }
10763 }
10764
10765 /* 5700 BX chips need to have their TX producer index mailboxes
10766 * written twice to workaround a bug.
10767 */
10768 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10769 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10770
10771 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10772 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10773 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10774 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10775
10776 /* Chip-specific fixup from Broadcom driver */
10777 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10778 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10779 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10780 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10781 }
10782
10783 /* Default fast path register access methods */
10784 tp->read32 = tg3_read32;
10785 tp->write32 = tg3_write32;
10786 tp->read32_mbox = tg3_read32;
10787 tp->write32_mbox = tg3_write32;
10788 tp->write32_tx_mbox = tg3_write32;
10789 tp->write32_rx_mbox = tg3_write32;
10790
10791 /* Various workaround register access methods */
10792 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10793 tp->write32 = tg3_write_indirect_reg32;
10794 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10795 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10796 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10797 /*
10798 * Back to back register writes can cause problems on these
10799 * chips, the workaround is to read back all reg writes
10800 * except those to mailbox regs.
10801 *
10802 * See tg3_write_indirect_reg32().
10803 */
10804 tp->write32 = tg3_write_flush_reg32;
10805 }
10806
10807
10808 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10809 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10810 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10811 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10812 tp->write32_rx_mbox = tg3_write_flush_reg32;
10813 }
10814
10815 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10816 tp->read32 = tg3_read_indirect_reg32;
10817 tp->write32 = tg3_write_indirect_reg32;
10818 tp->read32_mbox = tg3_read_indirect_mbox;
10819 tp->write32_mbox = tg3_write_indirect_mbox;
10820 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10821 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10822
10823 iounmap(tp->regs);
10824 tp->regs = NULL;
10825
10826 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10827 pci_cmd &= ~PCI_COMMAND_MEMORY;
10828 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10829 }
10830 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10831 tp->read32_mbox = tg3_read32_mbox_5906;
10832 tp->write32_mbox = tg3_write32_mbox_5906;
10833 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10834 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10835 }
10836
10837 if (tp->write32 == tg3_write_indirect_reg32 ||
10838 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10839 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10841 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10842
10843 /* Get eeprom hw config before calling tg3_set_power_state().
10844 * In particular, the TG3_FLG2_IS_NIC flag must be
10845 * determined before calling tg3_set_power_state() so that
10846 * we know whether or not to switch out of Vaux power.
10847 * When the flag is set, it means that GPIO1 is used for eeprom
10848 * write protect and also implies that it is a LOM where GPIOs
10849 * are not used to switch power.
10850 */
10851 tg3_get_eeprom_hw_cfg(tp);
10852
10853 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10854 * GPIO1 driven high will bring 5700's external PHY out of reset.
10855 * It is also used as eeprom write protect on LOMs.
10856 */
10857 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10858 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10859 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10860 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10861 GRC_LCLCTRL_GPIO_OUTPUT1);
10862 /* Unused GPIO3 must be driven as output on 5752 because there
10863 * are no pull-up resistors on unused GPIO pins.
10864 */
10865 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10866 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10867
10868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10869 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10870
10871 /* Force the chip into D0. */
10872 err = tg3_set_power_state(tp, PCI_D0);
10873 if (err) {
10874 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10875 pci_name(tp->pdev));
10876 return err;
10877 }
10878
10879 /* 5700 B0 chips do not support checksumming correctly due
10880 * to hardware bugs.
10881 */
10882 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10883 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10884
10885 /* Derive initial jumbo mode from MTU assigned in
10886 * ether_setup() via the alloc_etherdev() call
10887 */
10888 if (tp->dev->mtu > ETH_DATA_LEN &&
10889 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10890 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10891
10892 /* Determine WakeOnLan speed to use. */
10893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10894 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10895 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10896 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10897 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10898 } else {
10899 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10900 }
10901
10902 /* A few boards don't want Ethernet@WireSpeed phy feature */
10903 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10904 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10905 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10906 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10907 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10908 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10909 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10910
10911 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10912 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10913 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10914 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10915 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10916
10917 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10919 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10920 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10921 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10922 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10923 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10924 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10925 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10926 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10927 }
10928
10929 tp->coalesce_mode = 0;
10930 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10931 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10932 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10933
10934 /* Initialize MAC MI mode, polling disabled. */
10935 tw32_f(MAC_MI_MODE, tp->mi_mode);
10936 udelay(80);
10937
10938 /* Initialize data/descriptor byte/word swapping. */
10939 val = tr32(GRC_MODE);
10940 val &= GRC_MODE_HOST_STACKUP;
10941 tw32(GRC_MODE, val | tp->grc_mode);
10942
10943 tg3_switch_clocks(tp);
10944
10945 /* Clear this out for sanity. */
10946 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10947
10948 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10949 &pci_state_reg);
10950 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10951 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10952 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10953
10954 if (chiprevid == CHIPREV_ID_5701_A0 ||
10955 chiprevid == CHIPREV_ID_5701_B0 ||
10956 chiprevid == CHIPREV_ID_5701_B2 ||
10957 chiprevid == CHIPREV_ID_5701_B5) {
10958 void __iomem *sram_base;
10959
10960 /* Write some dummy words into the SRAM status block
10961 * area, see if it reads back correctly. If the return
10962 * value is bad, force enable the PCIX workaround.
10963 */
10964 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10965
10966 writel(0x00000000, sram_base);
10967 writel(0x00000000, sram_base + 4);
10968 writel(0xffffffff, sram_base + 4);
10969 if (readl(sram_base) != 0x00000000)
10970 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10971 }
10972 }
10973
10974 udelay(50);
10975 tg3_nvram_init(tp);
10976
10977 grc_misc_cfg = tr32(GRC_MISC_CFG);
10978 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10979
10980 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10981 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10982 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10983 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10984
10985 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10986 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10987 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10988 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10989 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10990 HOSTCC_MODE_CLRTICK_TXBD);
10991
10992 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10993 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10994 tp->misc_host_ctrl);
10995 }
10996
10997 /* these are limited to 10/100 only */
10998 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10999 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
11000 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11001 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11002 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
11003 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
11004 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
11005 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11006 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
11007 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11008 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
11009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11010 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11011
11012 err = tg3_phy_probe(tp);
11013 if (err) {
11014 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11015 pci_name(tp->pdev), err);
11016 /* ... but do not return immediately ... */
11017 }
11018
11019 tg3_read_partno(tp);
11020 tg3_read_fw_ver(tp);
11021
11022 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11023 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11024 } else {
11025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11026 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11027 else
11028 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11029 }
11030
11031 /* 5700 {AX,BX} chips have a broken status block link
11032 * change bit implementation, so we must use the
11033 * status register in those cases.
11034 */
11035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11036 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11037 else
11038 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11039
11040 /* The led_ctrl is set during tg3_phy_probe, here we might
11041 * have to force the link status polling mechanism based
11042 * upon subsystem IDs.
11043 */
11044 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11046 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11047 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11048 TG3_FLAG_USE_LINKCHG_REG);
11049 }
11050
11051 /* For all SERDES we poll the MAC status register. */
11052 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11053 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11054 else
11055 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11056
11057 /* All chips before 5787 can get confused if TX buffers
11058 * straddle the 4GB address boundary in some cases.
11059 */
11060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11061 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11063 tp->dev->hard_start_xmit = tg3_start_xmit;
11064 else
11065 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11066
11067 tp->rx_offset = 2;
11068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11069 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11070 tp->rx_offset = 0;
11071
11072 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11073
11074 /* Increment the rx prod index on the rx std ring by at most
11075 * 8 for these chips to workaround hw errata.
11076 */
11077 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11080 tp->rx_std_max_post = 8;
11081
11082 /* By default, disable wake-on-lan. User can change this
11083 * using ETHTOOL_SWOL.
11084 */
11085 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11086
11087 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11088 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11089 PCIE_PWR_MGMT_L1_THRESH_MSK;
11090
11091 return err;
11092 }
11093
11094 #ifdef CONFIG_SPARC
11095 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11096 {
11097 struct net_device *dev = tp->dev;
11098 struct pci_dev *pdev = tp->pdev;
11099 struct device_node *dp = pci_device_to_OF_node(pdev);
11100 const unsigned char *addr;
11101 int len;
11102
11103 addr = of_get_property(dp, "local-mac-address", &len);
11104 if (addr && len == 6) {
11105 memcpy(dev->dev_addr, addr, 6);
11106 memcpy(dev->perm_addr, dev->dev_addr, 6);
11107 return 0;
11108 }
11109 return -ENODEV;
11110 }
11111
11112 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11113 {
11114 struct net_device *dev = tp->dev;
11115
11116 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11117 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11118 return 0;
11119 }
11120 #endif
11121
11122 static int __devinit tg3_get_device_address(struct tg3 *tp)
11123 {
11124 struct net_device *dev = tp->dev;
11125 u32 hi, lo, mac_offset;
11126 int addr_ok = 0;
11127
11128 #ifdef CONFIG_SPARC
11129 if (!tg3_get_macaddr_sparc(tp))
11130 return 0;
11131 #endif
11132
11133 mac_offset = 0x7c;
11134 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11135 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11136 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11137 mac_offset = 0xcc;
11138 if (tg3_nvram_lock(tp))
11139 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11140 else
11141 tg3_nvram_unlock(tp);
11142 }
11143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11144 mac_offset = 0x10;
11145
11146 /* First try to get it from MAC address mailbox. */
11147 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11148 if ((hi >> 16) == 0x484b) {
11149 dev->dev_addr[0] = (hi >> 8) & 0xff;
11150 dev->dev_addr[1] = (hi >> 0) & 0xff;
11151
11152 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11153 dev->dev_addr[2] = (lo >> 24) & 0xff;
11154 dev->dev_addr[3] = (lo >> 16) & 0xff;
11155 dev->dev_addr[4] = (lo >> 8) & 0xff;
11156 dev->dev_addr[5] = (lo >> 0) & 0xff;
11157
11158 /* Some old bootcode may report a 0 MAC address in SRAM */
11159 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11160 }
11161 if (!addr_ok) {
11162 /* Next, try NVRAM. */
11163 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11164 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11165 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11166 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11167 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11168 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11169 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11170 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11171 }
11172 /* Finally just fetch it out of the MAC control regs. */
11173 else {
11174 hi = tr32(MAC_ADDR_0_HIGH);
11175 lo = tr32(MAC_ADDR_0_LOW);
11176
11177 dev->dev_addr[5] = lo & 0xff;
11178 dev->dev_addr[4] = (lo >> 8) & 0xff;
11179 dev->dev_addr[3] = (lo >> 16) & 0xff;
11180 dev->dev_addr[2] = (lo >> 24) & 0xff;
11181 dev->dev_addr[1] = hi & 0xff;
11182 dev->dev_addr[0] = (hi >> 8) & 0xff;
11183 }
11184 }
11185
11186 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11187 #ifdef CONFIG_SPARC64
11188 if (!tg3_get_default_macaddr_sparc(tp))
11189 return 0;
11190 #endif
11191 return -EINVAL;
11192 }
11193 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11194 return 0;
11195 }
11196
11197 #define BOUNDARY_SINGLE_CACHELINE 1
11198 #define BOUNDARY_MULTI_CACHELINE 2
11199
11200 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11201 {
11202 int cacheline_size;
11203 u8 byte;
11204 int goal;
11205
11206 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11207 if (byte == 0)
11208 cacheline_size = 1024;
11209 else
11210 cacheline_size = (int) byte * 4;
11211
11212 /* On 5703 and later chips, the boundary bits have no
11213 * effect.
11214 */
11215 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11216 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11217 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11218 goto out;
11219
11220 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11221 goal = BOUNDARY_MULTI_CACHELINE;
11222 #else
11223 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11224 goal = BOUNDARY_SINGLE_CACHELINE;
11225 #else
11226 goal = 0;
11227 #endif
11228 #endif
11229
11230 if (!goal)
11231 goto out;
11232
11233 /* PCI controllers on most RISC systems tend to disconnect
11234 * when a device tries to burst across a cache-line boundary.
11235 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11236 *
11237 * Unfortunately, for PCI-E there are only limited
11238 * write-side controls for this, and thus for reads
11239 * we will still get the disconnects. We'll also waste
11240 * these PCI cycles for both read and write for chips
11241 * other than 5700 and 5701 which do not implement the
11242 * boundary bits.
11243 */
11244 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11245 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11246 switch (cacheline_size) {
11247 case 16:
11248 case 32:
11249 case 64:
11250 case 128:
11251 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11252 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11253 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11254 } else {
11255 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11256 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11257 }
11258 break;
11259
11260 case 256:
11261 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11262 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11263 break;
11264
11265 default:
11266 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11267 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11268 break;
11269 };
11270 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11271 switch (cacheline_size) {
11272 case 16:
11273 case 32:
11274 case 64:
11275 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11276 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11277 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11278 break;
11279 }
11280 /* fallthrough */
11281 case 128:
11282 default:
11283 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11284 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11285 break;
11286 };
11287 } else {
11288 switch (cacheline_size) {
11289 case 16:
11290 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11291 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11292 DMA_RWCTRL_WRITE_BNDRY_16);
11293 break;
11294 }
11295 /* fallthrough */
11296 case 32:
11297 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11298 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11299 DMA_RWCTRL_WRITE_BNDRY_32);
11300 break;
11301 }
11302 /* fallthrough */
11303 case 64:
11304 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11305 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11306 DMA_RWCTRL_WRITE_BNDRY_64);
11307 break;
11308 }
11309 /* fallthrough */
11310 case 128:
11311 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11312 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11313 DMA_RWCTRL_WRITE_BNDRY_128);
11314 break;
11315 }
11316 /* fallthrough */
11317 case 256:
11318 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11319 DMA_RWCTRL_WRITE_BNDRY_256);
11320 break;
11321 case 512:
11322 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11323 DMA_RWCTRL_WRITE_BNDRY_512);
11324 break;
11325 case 1024:
11326 default:
11327 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11328 DMA_RWCTRL_WRITE_BNDRY_1024);
11329 break;
11330 };
11331 }
11332
11333 out:
11334 return val;
11335 }
11336
11337 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11338 {
11339 struct tg3_internal_buffer_desc test_desc;
11340 u32 sram_dma_descs;
11341 int i, ret;
11342
11343 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11344
11345 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11346 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11347 tw32(RDMAC_STATUS, 0);
11348 tw32(WDMAC_STATUS, 0);
11349
11350 tw32(BUFMGR_MODE, 0);
11351 tw32(FTQ_RESET, 0);
11352
11353 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11354 test_desc.addr_lo = buf_dma & 0xffffffff;
11355 test_desc.nic_mbuf = 0x00002100;
11356 test_desc.len = size;
11357
11358 /*
11359 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11360 * the *second* time the tg3 driver was getting loaded after an
11361 * initial scan.
11362 *
11363 * Broadcom tells me:
11364 * ...the DMA engine is connected to the GRC block and a DMA
11365 * reset may affect the GRC block in some unpredictable way...
11366 * The behavior of resets to individual blocks has not been tested.
11367 *
11368 * Broadcom noted the GRC reset will also reset all sub-components.
11369 */
11370 if (to_device) {
11371 test_desc.cqid_sqid = (13 << 8) | 2;
11372
11373 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11374 udelay(40);
11375 } else {
11376 test_desc.cqid_sqid = (16 << 8) | 7;
11377
11378 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11379 udelay(40);
11380 }
11381 test_desc.flags = 0x00000005;
11382
11383 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11384 u32 val;
11385
11386 val = *(((u32 *)&test_desc) + i);
11387 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11388 sram_dma_descs + (i * sizeof(u32)));
11389 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11390 }
11391 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11392
11393 if (to_device) {
11394 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11395 } else {
11396 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11397 }
11398
11399 ret = -ENODEV;
11400 for (i = 0; i < 40; i++) {
11401 u32 val;
11402
11403 if (to_device)
11404 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11405 else
11406 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11407 if ((val & 0xffff) == sram_dma_descs) {
11408 ret = 0;
11409 break;
11410 }
11411
11412 udelay(100);
11413 }
11414
11415 return ret;
11416 }
11417
11418 #define TEST_BUFFER_SIZE 0x2000
11419
11420 static int __devinit tg3_test_dma(struct tg3 *tp)
11421 {
11422 dma_addr_t buf_dma;
11423 u32 *buf, saved_dma_rwctrl;
11424 int ret;
11425
11426 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11427 if (!buf) {
11428 ret = -ENOMEM;
11429 goto out_nofree;
11430 }
11431
11432 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11433 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11434
11435 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11436
11437 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11438 /* DMA read watermark not used on PCIE */
11439 tp->dma_rwctrl |= 0x00180000;
11440 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11441 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11443 tp->dma_rwctrl |= 0x003f0000;
11444 else
11445 tp->dma_rwctrl |= 0x003f000f;
11446 } else {
11447 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11448 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11449 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11450 u32 read_water = 0x7;
11451
11452 /* If the 5704 is behind the EPB bridge, we can
11453 * do the less restrictive ONE_DMA workaround for
11454 * better performance.
11455 */
11456 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11457 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11458 tp->dma_rwctrl |= 0x8000;
11459 else if (ccval == 0x6 || ccval == 0x7)
11460 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11461
11462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11463 read_water = 4;
11464 /* Set bit 23 to enable PCIX hw bug fix */
11465 tp->dma_rwctrl |=
11466 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11467 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11468 (1 << 23);
11469 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11470 /* 5780 always in PCIX mode */
11471 tp->dma_rwctrl |= 0x00144000;
11472 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11473 /* 5714 always in PCIX mode */
11474 tp->dma_rwctrl |= 0x00148000;
11475 } else {
11476 tp->dma_rwctrl |= 0x001b000f;
11477 }
11478 }
11479
11480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11481 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11482 tp->dma_rwctrl &= 0xfffffff0;
11483
11484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11486 /* Remove this if it causes problems for some boards. */
11487 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11488
11489 /* On 5700/5701 chips, we need to set this bit.
11490 * Otherwise the chip will issue cacheline transactions
11491 * to streamable DMA memory with not all the byte
11492 * enables turned on. This is an error on several
11493 * RISC PCI controllers, in particular sparc64.
11494 *
11495 * On 5703/5704 chips, this bit has been reassigned
11496 * a different meaning. In particular, it is used
11497 * on those chips to enable a PCI-X workaround.
11498 */
11499 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11500 }
11501
11502 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11503
11504 #if 0
11505 /* Unneeded, already done by tg3_get_invariants. */
11506 tg3_switch_clocks(tp);
11507 #endif
11508
11509 ret = 0;
11510 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11511 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11512 goto out;
11513
11514 /* It is best to perform DMA test with maximum write burst size
11515 * to expose the 5700/5701 write DMA bug.
11516 */
11517 saved_dma_rwctrl = tp->dma_rwctrl;
11518 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11519 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11520
11521 while (1) {
11522 u32 *p = buf, i;
11523
11524 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11525 p[i] = i;
11526
11527 /* Send the buffer to the chip. */
11528 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11529 if (ret) {
11530 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11531 break;
11532 }
11533
11534 #if 0
11535 /* validate data reached card RAM correctly. */
11536 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11537 u32 val;
11538 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11539 if (le32_to_cpu(val) != p[i]) {
11540 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11541 /* ret = -ENODEV here? */
11542 }
11543 p[i] = 0;
11544 }
11545 #endif
11546 /* Now read it back. */
11547 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11548 if (ret) {
11549 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11550
11551 break;
11552 }
11553
11554 /* Verify it. */
11555 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11556 if (p[i] == i)
11557 continue;
11558
11559 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11560 DMA_RWCTRL_WRITE_BNDRY_16) {
11561 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11562 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11563 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11564 break;
11565 } else {
11566 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11567 ret = -ENODEV;
11568 goto out;
11569 }
11570 }
11571
11572 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11573 /* Success. */
11574 ret = 0;
11575 break;
11576 }
11577 }
11578 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11579 DMA_RWCTRL_WRITE_BNDRY_16) {
11580 static struct pci_device_id dma_wait_state_chipsets[] = {
11581 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11582 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11583 { },
11584 };
11585
11586 /* DMA test passed without adjusting DMA boundary,
11587 * now look for chipsets that are known to expose the
11588 * DMA bug without failing the test.
11589 */
11590 if (pci_dev_present(dma_wait_state_chipsets)) {
11591 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11592 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11593 }
11594 else
11595 /* Safe to use the calculated DMA boundary. */
11596 tp->dma_rwctrl = saved_dma_rwctrl;
11597
11598 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11599 }
11600
11601 out:
11602 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11603 out_nofree:
11604 return ret;
11605 }
11606
11607 static void __devinit tg3_init_link_config(struct tg3 *tp)
11608 {
11609 tp->link_config.advertising =
11610 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11611 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11612 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11613 ADVERTISED_Autoneg | ADVERTISED_MII);
11614 tp->link_config.speed = SPEED_INVALID;
11615 tp->link_config.duplex = DUPLEX_INVALID;
11616 tp->link_config.autoneg = AUTONEG_ENABLE;
11617 tp->link_config.active_speed = SPEED_INVALID;
11618 tp->link_config.active_duplex = DUPLEX_INVALID;
11619 tp->link_config.phy_is_low_power = 0;
11620 tp->link_config.orig_speed = SPEED_INVALID;
11621 tp->link_config.orig_duplex = DUPLEX_INVALID;
11622 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11623 }
11624
11625 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11626 {
11627 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11628 tp->bufmgr_config.mbuf_read_dma_low_water =
11629 DEFAULT_MB_RDMA_LOW_WATER_5705;
11630 tp->bufmgr_config.mbuf_mac_rx_low_water =
11631 DEFAULT_MB_MACRX_LOW_WATER_5705;
11632 tp->bufmgr_config.mbuf_high_water =
11633 DEFAULT_MB_HIGH_WATER_5705;
11634 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11635 tp->bufmgr_config.mbuf_mac_rx_low_water =
11636 DEFAULT_MB_MACRX_LOW_WATER_5906;
11637 tp->bufmgr_config.mbuf_high_water =
11638 DEFAULT_MB_HIGH_WATER_5906;
11639 }
11640
11641 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11642 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11643 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11644 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11645 tp->bufmgr_config.mbuf_high_water_jumbo =
11646 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11647 } else {
11648 tp->bufmgr_config.mbuf_read_dma_low_water =
11649 DEFAULT_MB_RDMA_LOW_WATER;
11650 tp->bufmgr_config.mbuf_mac_rx_low_water =
11651 DEFAULT_MB_MACRX_LOW_WATER;
11652 tp->bufmgr_config.mbuf_high_water =
11653 DEFAULT_MB_HIGH_WATER;
11654
11655 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11656 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11657 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11658 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11659 tp->bufmgr_config.mbuf_high_water_jumbo =
11660 DEFAULT_MB_HIGH_WATER_JUMBO;
11661 }
11662
11663 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11664 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11665 }
11666
11667 static char * __devinit tg3_phy_string(struct tg3 *tp)
11668 {
11669 switch (tp->phy_id & PHY_ID_MASK) {
11670 case PHY_ID_BCM5400: return "5400";
11671 case PHY_ID_BCM5401: return "5401";
11672 case PHY_ID_BCM5411: return "5411";
11673 case PHY_ID_BCM5701: return "5701";
11674 case PHY_ID_BCM5703: return "5703";
11675 case PHY_ID_BCM5704: return "5704";
11676 case PHY_ID_BCM5705: return "5705";
11677 case PHY_ID_BCM5750: return "5750";
11678 case PHY_ID_BCM5752: return "5752";
11679 case PHY_ID_BCM5714: return "5714";
11680 case PHY_ID_BCM5780: return "5780";
11681 case PHY_ID_BCM5755: return "5755";
11682 case PHY_ID_BCM5787: return "5787";
11683 case PHY_ID_BCM5756: return "5722/5756";
11684 case PHY_ID_BCM5906: return "5906";
11685 case PHY_ID_BCM8002: return "8002/serdes";
11686 case 0: return "serdes";
11687 default: return "unknown";
11688 };
11689 }
11690
11691 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11692 {
11693 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11694 strcpy(str, "PCI Express");
11695 return str;
11696 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11697 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11698
11699 strcpy(str, "PCIX:");
11700
11701 if ((clock_ctrl == 7) ||
11702 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11703 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11704 strcat(str, "133MHz");
11705 else if (clock_ctrl == 0)
11706 strcat(str, "33MHz");
11707 else if (clock_ctrl == 2)
11708 strcat(str, "50MHz");
11709 else if (clock_ctrl == 4)
11710 strcat(str, "66MHz");
11711 else if (clock_ctrl == 6)
11712 strcat(str, "100MHz");
11713 } else {
11714 strcpy(str, "PCI:");
11715 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11716 strcat(str, "66MHz");
11717 else
11718 strcat(str, "33MHz");
11719 }
11720 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11721 strcat(str, ":32-bit");
11722 else
11723 strcat(str, ":64-bit");
11724 return str;
11725 }
11726
11727 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11728 {
11729 struct pci_dev *peer;
11730 unsigned int func, devnr = tp->pdev->devfn & ~7;
11731
11732 for (func = 0; func < 8; func++) {
11733 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11734 if (peer && peer != tp->pdev)
11735 break;
11736 pci_dev_put(peer);
11737 }
11738 /* 5704 can be configured in single-port mode, set peer to
11739 * tp->pdev in that case.
11740 */
11741 if (!peer) {
11742 peer = tp->pdev;
11743 return peer;
11744 }
11745
11746 /*
11747 * We don't need to keep the refcount elevated; there's no way
11748 * to remove one half of this device without removing the other
11749 */
11750 pci_dev_put(peer);
11751
11752 return peer;
11753 }
11754
11755 static void __devinit tg3_init_coal(struct tg3 *tp)
11756 {
11757 struct ethtool_coalesce *ec = &tp->coal;
11758
11759 memset(ec, 0, sizeof(*ec));
11760 ec->cmd = ETHTOOL_GCOALESCE;
11761 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11762 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11763 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11764 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11765 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11766 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11767 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11768 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11769 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11770
11771 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11772 HOSTCC_MODE_CLRTICK_TXBD)) {
11773 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11774 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11775 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11776 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11777 }
11778
11779 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11780 ec->rx_coalesce_usecs_irq = 0;
11781 ec->tx_coalesce_usecs_irq = 0;
11782 ec->stats_block_coalesce_usecs = 0;
11783 }
11784 }
11785
11786 static int __devinit tg3_init_one(struct pci_dev *pdev,
11787 const struct pci_device_id *ent)
11788 {
11789 static int tg3_version_printed = 0;
11790 unsigned long tg3reg_base, tg3reg_len;
11791 struct net_device *dev;
11792 struct tg3 *tp;
11793 int i, err, pm_cap;
11794 char str[40];
11795 u64 dma_mask, persist_dma_mask;
11796
11797 if (tg3_version_printed++ == 0)
11798 printk(KERN_INFO "%s", version);
11799
11800 err = pci_enable_device(pdev);
11801 if (err) {
11802 printk(KERN_ERR PFX "Cannot enable PCI device, "
11803 "aborting.\n");
11804 return err;
11805 }
11806
11807 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11808 printk(KERN_ERR PFX "Cannot find proper PCI device "
11809 "base address, aborting.\n");
11810 err = -ENODEV;
11811 goto err_out_disable_pdev;
11812 }
11813
11814 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11815 if (err) {
11816 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11817 "aborting.\n");
11818 goto err_out_disable_pdev;
11819 }
11820
11821 pci_set_master(pdev);
11822
11823 /* Find power-management capability. */
11824 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11825 if (pm_cap == 0) {
11826 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11827 "aborting.\n");
11828 err = -EIO;
11829 goto err_out_free_res;
11830 }
11831
11832 tg3reg_base = pci_resource_start(pdev, 0);
11833 tg3reg_len = pci_resource_len(pdev, 0);
11834
11835 dev = alloc_etherdev(sizeof(*tp));
11836 if (!dev) {
11837 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11838 err = -ENOMEM;
11839 goto err_out_free_res;
11840 }
11841
11842 SET_MODULE_OWNER(dev);
11843 SET_NETDEV_DEV(dev, &pdev->dev);
11844
11845 #if TG3_VLAN_TAG_USED
11846 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11847 dev->vlan_rx_register = tg3_vlan_rx_register;
11848 #endif
11849
11850 tp = netdev_priv(dev);
11851 tp->pdev = pdev;
11852 tp->dev = dev;
11853 tp->pm_cap = pm_cap;
11854 tp->mac_mode = TG3_DEF_MAC_MODE;
11855 tp->rx_mode = TG3_DEF_RX_MODE;
11856 tp->tx_mode = TG3_DEF_TX_MODE;
11857 tp->mi_mode = MAC_MI_MODE_BASE;
11858 if (tg3_debug > 0)
11859 tp->msg_enable = tg3_debug;
11860 else
11861 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11862
11863 /* The word/byte swap controls here control register access byte
11864 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11865 * setting below.
11866 */
11867 tp->misc_host_ctrl =
11868 MISC_HOST_CTRL_MASK_PCI_INT |
11869 MISC_HOST_CTRL_WORD_SWAP |
11870 MISC_HOST_CTRL_INDIR_ACCESS |
11871 MISC_HOST_CTRL_PCISTATE_RW;
11872
11873 /* The NONFRM (non-frame) byte/word swap controls take effect
11874 * on descriptor entries, anything which isn't packet data.
11875 *
11876 * The StrongARM chips on the board (one for tx, one for rx)
11877 * are running in big-endian mode.
11878 */
11879 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11880 GRC_MODE_WSWAP_NONFRM_DATA);
11881 #ifdef __BIG_ENDIAN
11882 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11883 #endif
11884 spin_lock_init(&tp->lock);
11885 spin_lock_init(&tp->indirect_lock);
11886 INIT_WORK(&tp->reset_task, tg3_reset_task);
11887
11888 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11889 if (tp->regs == 0UL) {
11890 printk(KERN_ERR PFX "Cannot map device registers, "
11891 "aborting.\n");
11892 err = -ENOMEM;
11893 goto err_out_free_dev;
11894 }
11895
11896 tg3_init_link_config(tp);
11897
11898 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11899 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11900 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11901
11902 dev->open = tg3_open;
11903 dev->stop = tg3_close;
11904 dev->get_stats = tg3_get_stats;
11905 dev->set_multicast_list = tg3_set_rx_mode;
11906 dev->set_mac_address = tg3_set_mac_addr;
11907 dev->do_ioctl = tg3_ioctl;
11908 dev->tx_timeout = tg3_tx_timeout;
11909 dev->poll = tg3_poll;
11910 dev->ethtool_ops = &tg3_ethtool_ops;
11911 dev->weight = 64;
11912 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11913 dev->change_mtu = tg3_change_mtu;
11914 dev->irq = pdev->irq;
11915 #ifdef CONFIG_NET_POLL_CONTROLLER
11916 dev->poll_controller = tg3_poll_controller;
11917 #endif
11918
11919 err = tg3_get_invariants(tp);
11920 if (err) {
11921 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11922 "aborting.\n");
11923 goto err_out_iounmap;
11924 }
11925
11926 /* The EPB bridge inside 5714, 5715, and 5780 and any
11927 * device behind the EPB cannot support DMA addresses > 40-bit.
11928 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11929 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11930 * do DMA address check in tg3_start_xmit().
11931 */
11932 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11933 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11934 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11935 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11936 #ifdef CONFIG_HIGHMEM
11937 dma_mask = DMA_64BIT_MASK;
11938 #endif
11939 } else
11940 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11941
11942 /* Configure DMA attributes. */
11943 if (dma_mask > DMA_32BIT_MASK) {
11944 err = pci_set_dma_mask(pdev, dma_mask);
11945 if (!err) {
11946 dev->features |= NETIF_F_HIGHDMA;
11947 err = pci_set_consistent_dma_mask(pdev,
11948 persist_dma_mask);
11949 if (err < 0) {
11950 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11951 "DMA for consistent allocations\n");
11952 goto err_out_iounmap;
11953 }
11954 }
11955 }
11956 if (err || dma_mask == DMA_32BIT_MASK) {
11957 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11958 if (err) {
11959 printk(KERN_ERR PFX "No usable DMA configuration, "
11960 "aborting.\n");
11961 goto err_out_iounmap;
11962 }
11963 }
11964
11965 tg3_init_bufmgr_config(tp);
11966
11967 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11968 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11969 }
11970 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11972 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11974 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11975 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11976 } else {
11977 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11978 }
11979
11980 /* TSO is on by default on chips that support hardware TSO.
11981 * Firmware TSO on older chips gives lower performance, so it
11982 * is off by default, but can be enabled using ethtool.
11983 */
11984 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11985 dev->features |= NETIF_F_TSO;
11986 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11987 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11988 dev->features |= NETIF_F_TSO6;
11989 }
11990
11991
11992 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11993 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11994 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11995 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11996 tp->rx_pending = 63;
11997 }
11998
11999 err = tg3_get_device_address(tp);
12000 if (err) {
12001 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
12002 "aborting.\n");
12003 goto err_out_iounmap;
12004 }
12005
12006 /*
12007 * Reset chip in case UNDI or EFI driver did not shutdown
12008 * DMA self test will enable WDMAC and we'll see (spurious)
12009 * pending DMA on the PCI bus at that point.
12010 */
12011 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12012 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
12013 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
12014 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12015 }
12016
12017 err = tg3_test_dma(tp);
12018 if (err) {
12019 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
12020 goto err_out_iounmap;
12021 }
12022
12023 /* Tigon3 can do ipv4 only... and some chips have buggy
12024 * checksumming.
12025 */
12026 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
12027 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
12030 dev->features |= NETIF_F_IPV6_CSUM;
12031
12032 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12033 } else
12034 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12035
12036 /* flow control autonegotiation is default behavior */
12037 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12038
12039 tg3_init_coal(tp);
12040
12041 pci_set_drvdata(pdev, dev);
12042
12043 err = register_netdev(dev);
12044 if (err) {
12045 printk(KERN_ERR PFX "Cannot register net device, "
12046 "aborting.\n");
12047 goto err_out_iounmap;
12048 }
12049
12050 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
12051 dev->name,
12052 tp->board_part_number,
12053 tp->pci_chip_rev_id,
12054 tg3_phy_string(tp),
12055 tg3_bus_string(tp, str),
12056 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12057 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12058 "10/100/1000Base-T")));
12059
12060 for (i = 0; i < 6; i++)
12061 printk("%2.2x%c", dev->dev_addr[i],
12062 i == 5 ? '\n' : ':');
12063
12064 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
12065 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
12066 dev->name,
12067 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12068 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12069 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12070 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
12071 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12072 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12073 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12074 dev->name, tp->dma_rwctrl,
12075 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12076 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12077
12078 return 0;
12079
12080 err_out_iounmap:
12081 if (tp->regs) {
12082 iounmap(tp->regs);
12083 tp->regs = NULL;
12084 }
12085
12086 err_out_free_dev:
12087 free_netdev(dev);
12088
12089 err_out_free_res:
12090 pci_release_regions(pdev);
12091
12092 err_out_disable_pdev:
12093 pci_disable_device(pdev);
12094 pci_set_drvdata(pdev, NULL);
12095 return err;
12096 }
12097
12098 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12099 {
12100 struct net_device *dev = pci_get_drvdata(pdev);
12101
12102 if (dev) {
12103 struct tg3 *tp = netdev_priv(dev);
12104
12105 flush_scheduled_work();
12106 unregister_netdev(dev);
12107 if (tp->regs) {
12108 iounmap(tp->regs);
12109 tp->regs = NULL;
12110 }
12111 free_netdev(dev);
12112 pci_release_regions(pdev);
12113 pci_disable_device(pdev);
12114 pci_set_drvdata(pdev, NULL);
12115 }
12116 }
12117
12118 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12119 {
12120 struct net_device *dev = pci_get_drvdata(pdev);
12121 struct tg3 *tp = netdev_priv(dev);
12122 int err;
12123
12124 /* PCI register 4 needs to be saved whether netif_running() or not.
12125 * MSI address and data need to be saved if using MSI and
12126 * netif_running().
12127 */
12128 pci_save_state(pdev);
12129
12130 if (!netif_running(dev))
12131 return 0;
12132
12133 flush_scheduled_work();
12134 tg3_netif_stop(tp);
12135
12136 del_timer_sync(&tp->timer);
12137
12138 tg3_full_lock(tp, 1);
12139 tg3_disable_ints(tp);
12140 tg3_full_unlock(tp);
12141
12142 netif_device_detach(dev);
12143
12144 tg3_full_lock(tp, 0);
12145 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12146 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12147 tg3_full_unlock(tp);
12148
12149 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12150 if (err) {
12151 tg3_full_lock(tp, 0);
12152
12153 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12154 if (tg3_restart_hw(tp, 1))
12155 goto out;
12156
12157 tp->timer.expires = jiffies + tp->timer_offset;
12158 add_timer(&tp->timer);
12159
12160 netif_device_attach(dev);
12161 tg3_netif_start(tp);
12162
12163 out:
12164 tg3_full_unlock(tp);
12165 }
12166
12167 return err;
12168 }
12169
12170 static int tg3_resume(struct pci_dev *pdev)
12171 {
12172 struct net_device *dev = pci_get_drvdata(pdev);
12173 struct tg3 *tp = netdev_priv(dev);
12174 int err;
12175
12176 pci_restore_state(tp->pdev);
12177
12178 if (!netif_running(dev))
12179 return 0;
12180
12181 err = tg3_set_power_state(tp, PCI_D0);
12182 if (err)
12183 return err;
12184
12185 /* Hardware bug - MSI won't work if INTX disabled. */
12186 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
12187 (tp->tg3_flags2 & TG3_FLG2_USING_MSI))
12188 pci_intx(tp->pdev, 1);
12189
12190 netif_device_attach(dev);
12191
12192 tg3_full_lock(tp, 0);
12193
12194 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12195 err = tg3_restart_hw(tp, 1);
12196 if (err)
12197 goto out;
12198
12199 tp->timer.expires = jiffies + tp->timer_offset;
12200 add_timer(&tp->timer);
12201
12202 tg3_netif_start(tp);
12203
12204 out:
12205 tg3_full_unlock(tp);
12206
12207 return err;
12208 }
12209
12210 static struct pci_driver tg3_driver = {
12211 .name = DRV_MODULE_NAME,
12212 .id_table = tg3_pci_tbl,
12213 .probe = tg3_init_one,
12214 .remove = __devexit_p(tg3_remove_one),
12215 .suspend = tg3_suspend,
12216 .resume = tg3_resume
12217 };
12218
12219 static int __init tg3_init(void)
12220 {
12221 return pci_register_driver(&tg3_driver);
12222 }
12223
12224 static void __exit tg3_cleanup(void)
12225 {
12226 pci_unregister_driver(&tg3_driver);
12227 }
12228
12229 module_init(tg3_init);
12230 module_exit(tg3_cleanup);
Compression patch for TCP for Linux kernel