drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for tuning/monitoring */
  41 #ifdef DEBUG
  42 #define EHCI_STATS
  43 #endif
  44
  45 struct ehci_stats {
  46         /* irq usage */
  47         unsigned long           normal;
  48         unsigned long           error;
  49         unsigned long           iaa;
  50         unsigned long           lost_iaa;
  51
  52         /* termination of urbs from core */
  53         unsigned long           complete;
  54         unsigned long           unlink;
  55 };
  56
  57 /* ehci_hcd->lock guards shared data against other CPUs:
  58  *   ehci_hcd:  async, unlink, periodic (and shadow), ...
  59  *   usb_host_endpoint: hcpriv
  60  *   ehci_qh:   qh_next, qtd_list
  61  *   ehci_qtd:  qtd_list
  62  *
  63  * Also, hold this lock when talking to HC registers or
  64  * when updating hw_* fields in shared qh/qtd/... structures.
  65  */
  66
  67 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  68
  69 /*
  70  * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
  71  * controller may be doing DMA.  Lower values mean there's no DMA.
  72  */
  73 enum ehci_rh_state {
  74         EHCI_RH_HALTED,
  75         EHCI_RH_SUSPENDED,
  76         EHCI_RH_RUNNING,
  77         EHCI_RH_STOPPING
  78 };
  79
  80 /*
  81  * Timer events, ordered by increasing delay length.
  82  * Always update event_delays_ns[] and event_handlers[] (defined in
  83  * ehci-timer.c) in parallel with this list.
  84  */
  85 enum ehci_hrtimer_event {
  86         EHCI_HRTIMER_POLL_ASS,          /* Poll for async schedule off */
  87         EHCI_HRTIMER_POLL_PSS,          /* Poll for periodic schedule off */
  88         EHCI_HRTIMER_POLL_DEAD,         /* Wait for dead controller to stop */
  89         EHCI_HRTIMER_UNLINK_INTR,       /* Wait for interrupt QH unlink */
  90         EHCI_HRTIMER_FREE_ITDS,         /* Wait for unused iTDs and siTDs */
  91         EHCI_HRTIMER_ASYNC_UNLINKS,     /* Unlink empty async QHs */
  92         EHCI_HRTIMER_IAA_WATCHDOG,      /* Handle lost IAA interrupts */
  93         EHCI_HRTIMER_DISABLE_PERIODIC,  /* Wait to disable periodic sched */
  94         EHCI_HRTIMER_DISABLE_ASYNC,     /* Wait to disable async sched */
  95         EHCI_HRTIMER_IO_WATCHDOG,       /* Check for missing IRQs */
  96         EHCI_HRTIMER_NUM_EVENTS         /* Must come last */
  97 };
  98 #define EHCI_HRTIMER_NO_EVENT   99
  99
 100 struct ehci_hcd {                       /* one per controller */
 101         /* timing support */
 102         enum ehci_hrtimer_event next_hrtimer_event;
 103         unsigned                enabled_hrtimer_events;
 104         ktime_t                 hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
 105         struct hrtimer          hrtimer;
 106
 107         int                     PSS_poll_count;
 108         int                     ASS_poll_count;
 109         int                     died_poll_count;
 110
 111         /* glue to PCI and HCD framework */
 112         struct ehci_caps __iomem *caps;
 113         struct ehci_regs __iomem *regs;
 114         struct ehci_dbg_port __iomem *debug;
 115
 116         __u32                   hcs_params;     /* cached register copy */
 117         spinlock_t              lock;
 118         enum ehci_rh_state      rh_state;
 119
 120         /* general schedule support */
 121         bool                    scanning:1;
 122         bool                    need_rescan:1;
 123         bool                    intr_unlinking:1;
 124         bool                    iaa_in_progress:1;
 125         bool                    async_unlinking:1;
 126         bool                    shutdown:1;
 127         struct ehci_qh          *qh_scan_next;
 128
 129         /* async schedule support */
 130         struct ehci_qh          *async;
 131         struct ehci_qh          *dummy;         /* For AMD quirk use */
 132         struct list_head        async_unlink;
 133         struct list_head        async_idle;
 134         unsigned                async_unlink_cycle;
 135         unsigned                async_count;    /* async activity count */
 136
 137         /* periodic schedule support */
 138 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 139         unsigned                periodic_size;
 140         __hc32                  *periodic;      /* hw periodic table */
 141         dma_addr_t              periodic_dma;
 142         struct list_head        intr_qh_list;
 143         unsigned                i_thresh;       /* uframes HC might cache */
 144
 145         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
 146         struct list_head        intr_unlink;
 147         unsigned                intr_unlink_cycle;
 148         unsigned                now_frame;      /* frame from HC hardware */
 149         unsigned                last_iso_frame; /* last frame scanned for iso */
 150         unsigned                intr_count;     /* intr activity count */
 151         unsigned                isoc_count;     /* isoc activity count */
 152         unsigned                periodic_count; /* periodic activity count */
 153         unsigned                uframe_periodic_max; /* max periodic time per uframe */
 154
 155
 156         /* list of itds & sitds completed while now_frame was still active */
 157         struct list_head        cached_itd_list;
 158         struct ehci_itd         *last_itd_to_free;
 159         struct list_head        cached_sitd_list;
 160         struct ehci_sitd        *last_sitd_to_free;
 161
 162         /* per root hub port */
 163         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
 164
 165         /* bit vectors (one bit per port) */
 166         unsigned long           bus_suspended;          /* which ports were
 167                         already suspended at the start of a bus suspend */
 168         unsigned long           companion_ports;        /* which ports are
 169                         dedicated to the companion controller */
 170         unsigned long           owned_ports;            /* which ports are
 171                         owned by the companion during a bus suspend */
 172         unsigned long           port_c_suspend;         /* which ports have
 173                         the change-suspend feature turned on */
 174         unsigned long           suspended_ports;        /* which ports are
 175                         suspended */
 176         unsigned long           resuming_ports;         /* which ports have
 177                         started to resume */
 178
 179         /* per-HC memory pools (could be per-bus, but ...) */
 180         struct dma_pool         *qh_pool;       /* qh per active urb */
 181         struct dma_pool         *qtd_pool;      /* one or more per qh */
 182         struct dma_pool         *itd_pool;      /* itd per iso urb */
 183         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 184
 185         unsigned                random_frame;
 186         unsigned long           next_statechange;
 187         ktime_t                 last_periodic_enable;
 188         u32                     command;
 189
 190         /* SILICON QUIRKS */
 191         unsigned                no_selective_suspend:1;
 192         unsigned                has_fsl_port_bug:1; /* FreeScale */
 193         unsigned                big_endian_mmio:1;
 194         unsigned                big_endian_desc:1;
 195         unsigned                big_endian_capbase:1;
 196         unsigned                has_amcc_usb23:1;
 197         unsigned                need_io_watchdog:1;
 198         unsigned                amd_pll_fix:1;
 199         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 200         unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
 201         unsigned                frame_index_bug:1; /* MosChip (AKA NetMos) */
 202         unsigned                need_oc_pp_cycle:1; /* MPC834X port power */
 203
 204         /* required for usb32 quirk */
 205         #define OHCI_CTRL_HCFS          (3 << 6)
 206         #define OHCI_USB_OPER           (2 << 6)
 207         #define OHCI_USB_SUSPEND        (3 << 6)
 208
 209         #define OHCI_HCCTRL_OFFSET      0x4
 210         #define OHCI_HCCTRL_LEN         0x4
 211         __hc32                  *ohci_hcctrl_reg;
 212         unsigned                has_hostpc:1;
 213         unsigned                has_ppcd:1; /* support per-port change bits */
 214         u8                      sbrn;           /* packed release number */
 215
 216         /* irq statistics */
 217 #ifdef EHCI_STATS
 218         struct ehci_stats       stats;
 219 #       define COUNT(x) do { (x)++; } while (0)
 220 #else
 221 #       define COUNT(x) do {} while (0)
 222 #endif
 223
 224         /* debug files */
 225 #ifdef DEBUG
 226         struct dentry           *debug_dir;
 227 #endif
 228
 229         /* platform-specific data -- must come last */
 230         unsigned long           priv[0] __aligned(sizeof(s64));
 231 };
 232
 233 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 234 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 235 {
 236         return (struct ehci_hcd *) (hcd->hcd_priv);
 237 }
 238 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 239 {
 240         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 241 }
 242
 243 /*-------------------------------------------------------------------------*/
 244
 245 #include <linux/usb/ehci_def.h>
 246
 247 /*-------------------------------------------------------------------------*/
 248
 249 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 250
 251 /*
 252  * EHCI Specification 0.95 Section 3.5
 253  * QTD: describe data transfer components (buffer, direction, ...)
 254  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 255  *
 256  * These are associated only with "QH" (Queue Head) structures,
 257  * used with control, bulk, and interrupt transfers.
 258  */
 259 struct ehci_qtd {
 260         /* first part defined by EHCI spec */
 261         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 262         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 263         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 264 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 265 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 266 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 267 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 268 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 269 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 270 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 271 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 272 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 273 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 274 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 275 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 276 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 277
 278 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 279 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 280 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 281
 282         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 283         __hc32                  hw_buf_hi [5];        /* Appendix B */
 284
 285         /* the rest is HCD-private */
 286         dma_addr_t              qtd_dma;                /* qtd address */
 287         struct list_head        qtd_list;               /* sw qtd list */
 288         struct urb              *urb;                   /* qtd's urb */
 289         size_t                  length;                 /* length of buffer */
 290 } __attribute__ ((aligned (32)));
 291
 292 /* mask NakCnt+T in qh->hw_alt_next */
 293 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 294
 295 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 296
 297 /*-------------------------------------------------------------------------*/
 298
 299 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 300 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 301
 302 /*
 303  * Now the following defines are not converted using the
 304  * cpu_to_le32() macro anymore, since we have to support
 305  * "dynamic" switching between be and le support, so that the driver
 306  * can be used on one system with SoC EHCI controller using big-endian
 307  * descriptors as well as a normal little-endian PCI EHCI controller.
 308  */
 309 /* values for that type tag */
 310 #define Q_TYPE_ITD      (0 << 1)
 311 #define Q_TYPE_QH       (1 << 1)
 312 #define Q_TYPE_SITD     (2 << 1)
 313 #define Q_TYPE_FSTN     (3 << 1)
 314
 315 /* next async queue entry, or pointer to interrupt/periodic QH */
 316 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 317
 318 /* for periodic/async schedules and qtd lists, mark end of list */
 319 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 320
 321 /*
 322  * Entries in periodic shadow table are pointers to one of four kinds
 323  * of data structure.  That's dictated by the hardware; a type tag is
 324  * encoded in the low bits of the hardware's periodic schedule.  Use
 325  * Q_NEXT_TYPE to get the tag.
 326  *
 327  * For entries in the async schedule, the type tag always says "qh".
 328  */
 329 union ehci_shadow {
 330         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 331         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 332         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 333         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 334         __hc32                  *hw_next;       /* (all types) */
 335         void                    *ptr;
 336 };
 337
 338 /*-------------------------------------------------------------------------*/
 339
 340 /*
 341  * EHCI Specification 0.95 Section 3.6
 342  * QH: describes control/bulk/interrupt endpoints
 343  * See Fig 3-7 "Queue Head Structure Layout".
 344  *
 345  * These appear in both the async and (for interrupt) periodic schedules.
 346  */
 347
 348 /* first part defined by EHCI spec */
 349 struct ehci_qh_hw {
 350         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 351         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 352 #define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 353 #define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 354 #define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 355 #define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 356 #define QH_LOW_SPEED    (1 << 12)
 357 #define QH_FULL_SPEED   (0 << 12)
 358 #define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 359         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 360 #define QH_SMASK        0x000000ff
 361 #define QH_CMASK        0x0000ff00
 362 #define QH_HUBADDR      0x007f0000
 363 #define QH_HUBPORT      0x3f800000
 364 #define QH_MULT         0xc0000000
 365         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 366
 367         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 368         __hc32                  hw_qtd_next;
 369         __hc32                  hw_alt_next;
 370         __hc32                  hw_token;
 371         __hc32                  hw_buf [5];
 372         __hc32                  hw_buf_hi [5];
 373 } __attribute__ ((aligned(32)));
 374
 375 struct ehci_qh {
 376         struct ehci_qh_hw       *hw;            /* Must come first */
 377         /* the rest is HCD-private */
 378         dma_addr_t              qh_dma;         /* address of qh */
 379         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 380         struct list_head        qtd_list;       /* sw qtd list */
 381         struct list_head        intr_node;      /* list of intr QHs */
 382         struct ehci_qtd         *dummy;
 383         struct list_head        unlink_node;
 384
 385         unsigned                unlink_cycle;
 386
 387         u8                      qh_state;
 388 #define QH_STATE_LINKED         1               /* HC sees this */
 389 #define QH_STATE_UNLINK         2               /* HC may still see this */
 390 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 391 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 392 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 393
 394         u8                      xacterrs;       /* XactErr retry counter */
 395 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 396
 397         /* periodic schedule info */
 398         u8                      usecs;          /* intr bandwidth */
 399         u8                      gap_uf;         /* uframes split/csplit gap */
 400         u8                      c_usecs;        /* ... split completion bw */
 401         u16                     tt_usecs;       /* tt downstream bandwidth */
 402         unsigned short          period;         /* polling interval */
 403         unsigned short          start;          /* where polling starts */
 404 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 405
 406         struct usb_device       *dev;           /* access to TT */
 407         unsigned                is_out:1;       /* bulk or intr OUT */
 408         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 409         unsigned                dequeue_during_giveback:1;
 410         unsigned                exception:1;    /* got a fault, or an unlink
 411                                                    was requested */
 412 };
 413
 414 /*-------------------------------------------------------------------------*/
 415
 416 /* description of one iso transaction (up to 3 KB data if highspeed) */
 417 struct ehci_iso_packet {
 418         /* These will be copied to iTD when scheduling */
 419         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 420         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 421         u8                      cross;          /* buf crosses pages */
 422         /* for full speed OUT splits */
 423         u32                     buf1;
 424 };
 425
 426 /* temporary schedule data for packets from iso urbs (both speeds)
 427  * each packet is one logical usb transaction to the device (not TT),
 428  * beginning at stream->next_uframe
 429  */
 430 struct ehci_iso_sched {
 431         struct list_head        td_list;
 432         unsigned                span;
 433         struct ehci_iso_packet  packet [0];
 434 };
 435
 436 /*
 437  * ehci_iso_stream - groups all (s)itds for this endpoint.
 438  * acts like a qh would, if EHCI had them for ISO.
 439  */
 440 struct ehci_iso_stream {
 441         /* first field matches ehci_hq, but is NULL */
 442         struct ehci_qh_hw       *hw;
 443
 444         u8                      bEndpointAddress;
 445         u8                      highspeed;
 446         struct list_head        td_list;        /* queued itds/sitds */
 447         struct list_head        free_list;      /* list of unused itds/sitds */
 448         struct usb_device       *udev;
 449         struct usb_host_endpoint *ep;
 450
 451         /* output of (re)scheduling */
 452         int                     next_uframe;
 453         __hc32                  splits;
 454
 455         /* the rest is derived from the endpoint descriptor,
 456          * trusting urb->interval == f(epdesc->bInterval) and
 457          * including the extra info for hw_bufp[0..2]
 458          */
 459         u8                      usecs, c_usecs;
 460         u16                     interval;
 461         u16                     tt_usecs;
 462         u16                     maxp;
 463         u16                     raw_mask;
 464         unsigned                bandwidth;
 465
 466         /* This is used to initialize iTD's hw_bufp fields */
 467         __hc32                  buf0;
 468         __hc32                  buf1;
 469         __hc32                  buf2;
 470
 471         /* this is used to initialize sITD's tt info */
 472         __hc32                  address;
 473 };
 474
 475 /*-------------------------------------------------------------------------*/
 476
 477 /*
 478  * EHCI Specification 0.95 Section 3.3
 479  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 480  *
 481  * Schedule records for high speed iso xfers
 482  */
 483 struct ehci_itd {
 484         /* first part defined by EHCI spec */
 485         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 486         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 487 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 488 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 489 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 490 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 491 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 492 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 493
 494 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 495
 496         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 497         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 498
 499         /* the rest is HCD-private */
 500         dma_addr_t              itd_dma;        /* for this itd */
 501         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 502
 503         struct urb              *urb;
 504         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 505         struct list_head        itd_list;       /* list of stream's itds */
 506
 507         /* any/all hw_transactions here may be used by that urb */
 508         unsigned                frame;          /* where scheduled */
 509         unsigned                pg;
 510         unsigned                index[8];       /* in urb->iso_frame_desc */
 511 } __attribute__ ((aligned (32)));
 512
 513 /*-------------------------------------------------------------------------*/
 514
 515 /*
 516  * EHCI Specification 0.95 Section 3.4
 517  * siTD, aka split-transaction isochronous Transfer Descriptor
 518  *       ... describe full speed iso xfers through TT in hubs
 519  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 520  */
 521 struct ehci_sitd {
 522         /* first part defined by EHCI spec */
 523         __hc32                  hw_next;
 524 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 525         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 526         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 527         __hc32                  hw_results;             /* EHCI table 3-11 */
 528 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 529 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 530 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 531 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 532 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 533 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 534 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 535 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 536 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 537 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 538
 539 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 540
 541         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 542         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 543         __hc32                  hw_buf_hi [2];          /* Appendix B */
 544
 545         /* the rest is HCD-private */
 546         dma_addr_t              sitd_dma;
 547         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 548
 549         struct urb              *urb;
 550         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 551         struct list_head        sitd_list;      /* list of stream's sitds */
 552         unsigned                frame;
 553         unsigned                index;
 554 } __attribute__ ((aligned (32)));
 555
 556 /*-------------------------------------------------------------------------*/
 557
 558 /*
 559  * EHCI Specification 0.96 Section 3.7
 560  * Periodic Frame Span Traversal Node (FSTN)
 561  *
 562  * Manages split interrupt transactions (using TT) that span frame boundaries
 563  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 564  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 565  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 566  */
 567 struct ehci_fstn {
 568         __hc32                  hw_next;        /* any periodic q entry */
 569         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 570
 571         /* the rest is HCD-private */
 572         dma_addr_t              fstn_dma;
 573         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 574 } __attribute__ ((aligned (32)));
 575
 576 /*-------------------------------------------------------------------------*/
 577
 578 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 579
 580 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)      \
 581                 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
 582
 583 #define ehci_prepare_ports_for_controller_resume(ehci)                  \
 584                 ehci_adjust_port_wakeup_flags(ehci, false, false);
 585
 586 /*-------------------------------------------------------------------------*/
 587
 588 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 589
 590 /*
 591  * Some EHCI controllers have a Transaction Translator built into the
 592  * root hub. This is a non-standard feature.  Each controller will need
 593  * to add code to the following inline functions, and call them as
 594  * needed (mostly in root hub code).
 595  */
 596
 597 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 598
 599 /* Returns the speed of a device attached to a port on the root hub. */
 600 static inline unsigned int
 601 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 602 {
 603         if (ehci_is_TDI(ehci)) {
 604                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 605                 case 0:
 606                         return 0;
 607                 case 1:
 608                         return USB_PORT_STAT_LOW_SPEED;
 609                 case 2:
 610                 default:
 611                         return USB_PORT_STAT_HIGH_SPEED;
 612                 }
 613         }
 614         return USB_PORT_STAT_HIGH_SPEED;
 615 }
 616
 617 #else
 618
 619 #define ehci_is_TDI(e)                  (0)
 620
 621 #define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
 622 #endif
 623
 624 /*-------------------------------------------------------------------------*/
 625
 626 #ifdef CONFIG_PPC_83xx
 627 /* Some Freescale processors have an erratum in which the TT
 628  * port number in the queue head was 0..N-1 instead of 1..N.
 629  */
 630 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 631 #else
 632 #define ehci_has_fsl_portno_bug(e)              (0)
 633 #endif
 634
 635 /*
 636  * While most USB host controllers implement their registers in
 637  * little-endian format, a minority (celleb companion chip) implement
 638  * them in big endian format.
 639  *
 640  * This attempts to support either format at compile time without a
 641  * runtime penalty, or both formats with the additional overhead
 642  * of checking a flag bit.
 643  *
 644  * ehci_big_endian_capbase is a special quirk for controllers that
 645  * implement the HC capability registers as separate registers and not
 646  * as fields of a 32-bit register.
 647  */
 648
 649 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 650 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 651 #define ehci_big_endian_capbase(e)      ((e)->big_endian_capbase)
 652 #else
 653 #define ehci_big_endian_mmio(e)         0
 654 #define ehci_big_endian_capbase(e)      0
 655 #endif
 656
 657 /*
 658  * Big-endian read/write functions are arch-specific.
 659  * Other arches can be added if/when they're needed.
 660  */
 661 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 662 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 663 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 664 #endif
 665
 666 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 667                 __u32 __iomem * regs)
 668 {
 669 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 670         return ehci_big_endian_mmio(ehci) ?
 671                 readl_be(regs) :
 672                 readl(regs);
 673 #else
 674         return readl(regs);
 675 #endif
 676 }
 677
 678 static inline void ehci_writel(const struct ehci_hcd *ehci,
 679                 const unsigned int val, __u32 __iomem *regs)
 680 {
 681 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 682         ehci_big_endian_mmio(ehci) ?
 683                 writel_be(val, regs) :
 684                 writel(val, regs);
 685 #else
 686         writel(val, regs);
 687 #endif
 688 }
 689
 690 /*
 691  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 692  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 693  * Other common bits are dependent on has_amcc_usb23 quirk flag.
 694  */
 695 #ifdef CONFIG_44x
 696 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 697 {
 698         u32 hc_control;
 699
 700         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 701         if (operational)
 702                 hc_control |= OHCI_USB_OPER;
 703         else
 704                 hc_control |= OHCI_USB_SUSPEND;
 705
 706         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 707         (void) readl_be(ehci->ohci_hcctrl_reg);
 708 }
 709 #else
 710 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 711 { }
 712 #endif
 713
 714 /*-------------------------------------------------------------------------*/
 715
 716 /*
 717  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 718  * format, but also its DMA data structures (descriptors).
 719  *
 720  * EHCI controllers accessed through PCI work normally (little-endian
 721  * everywhere), so we won't bother supporting a BE-only mode for now.
 722  */
 723 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 724 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 725
 726 /* cpu to ehci */
 727 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 728 {
 729         return ehci_big_endian_desc(ehci)
 730                 ? (__force __hc32)cpu_to_be32(x)
 731                 : (__force __hc32)cpu_to_le32(x);
 732 }
 733
 734 /* ehci to cpu */
 735 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 736 {
 737         return ehci_big_endian_desc(ehci)
 738                 ? be32_to_cpu((__force __be32)x)
 739                 : le32_to_cpu((__force __le32)x);
 740 }
 741
 742 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 743 {
 744         return ehci_big_endian_desc(ehci)
 745                 ? be32_to_cpup((__force __be32 *)x)
 746                 : le32_to_cpup((__force __le32 *)x);
 747 }
 748
 749 #else
 750
 751 /* cpu to ehci */
 752 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 753 {
 754         return cpu_to_le32(x);
 755 }
 756
 757 /* ehci to cpu */
 758 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 759 {
 760         return le32_to_cpu(x);
 761 }
 762
 763 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 764 {
 765         return le32_to_cpup(x);
 766 }
 767
 768 #endif
 769
 770 /*-------------------------------------------------------------------------*/
 771
 772 #define ehci_dbg(ehci, fmt, args...) \
 773         dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 774 #define ehci_err(ehci, fmt, args...) \
 775         dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 776 #define ehci_info(ehci, fmt, args...) \
 777         dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 778 #define ehci_warn(ehci, fmt, args...) \
 779         dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 780
 781 #ifdef VERBOSE_DEBUG
 782 #       define ehci_vdbg ehci_dbg
 783 #else
 784         static inline void ehci_vdbg(struct ehci_hcd *ehci, ...) {}
 785 #endif
 786
 787 #ifndef DEBUG
 788 #define STUB_DEBUG_FILES
 789 #endif  /* DEBUG */
 790
 791 /*-------------------------------------------------------------------------*/
 792
 793 /* Declarations of things exported for use by ehci platform drivers */
 794
 795 struct ehci_driver_overrides {
 796         size_t          extra_priv_size;
 797         int             (*reset)(struct usb_hcd *hcd);
 798 };
 799
 800 extern void     ehci_init_driver(struct hc_driver *drv,
 801                                 const struct ehci_driver_overrides *over);
 802 extern int      ehci_setup(struct usb_hcd *hcd);
 803
 804 #ifdef CONFIG_PM
 805 extern int      ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
 806 extern int      ehci_resume(struct usb_hcd *hcd, bool hibernated);
 807 #endif  /* CONFIG_PM */
 808
 809 #endif /* __LINUX_EHCI_HCD_H */