2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/gfp.h>
24 #include <asm/unaligned.h>
28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
32 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
33 static u8 usb_bos_descriptor
[] = {
34 USB_DT_BOS_SIZE
, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS
, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE
, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
41 USB_SS_CAP_TYPE
, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION
, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
51 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
52 struct usb_hub_descriptor
*desc
, int ports
)
56 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
57 desc
->bHubContrCurrent
= 0;
59 desc
->bNbrPorts
= ports
;
61 /* Bits 1:0 - support per-port power switching, or power always on */
62 if (HCC_PPC(xhci
->hcc_params
))
63 temp
|= HUB_CHAR_INDV_PORT_LPSM
;
65 temp
|= HUB_CHAR_NO_LPSM
;
66 /* Bit 2 - root hubs are not part of a compound device */
67 /* Bits 4:3 - individual port over current protection */
68 temp
|= HUB_CHAR_INDV_PORT_OCPM
;
69 /* Bits 6:5 - no TTs in root ports */
70 /* Bit 7 - no port indicators */
71 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
74 /* Fill in the USB 2.0 roothub descriptor */
75 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
76 struct usb_hub_descriptor
*desc
)
80 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
84 ports
= xhci
->num_usb2_ports
;
86 xhci_common_hub_descriptor(xhci
, desc
, ports
);
87 desc
->bDescriptorType
= USB_DT_HUB
;
88 temp
= 1 + (ports
/ 8);
89 desc
->bDescLength
= USB_DT_HUB_NONVAR_SIZE
+ 2 * temp
;
91 /* The Device Removable bits are reported on a byte granularity.
92 * If the port doesn't exist within that byte, the bit is set to 0.
94 memset(port_removable
, 0, sizeof(port_removable
));
95 for (i
= 0; i
< ports
; i
++) {
96 portsc
= xhci_readl(xhci
, xhci
->usb2_ports
[i
]);
97 /* If a device is removable, PORTSC reports a 0, same as in the
98 * hub descriptor DeviceRemovable bits.
100 if (portsc
& PORT_DEV_REMOVE
)
101 /* This math is hairy because bit 0 of DeviceRemovable
102 * is reserved, and bit 1 is for port 1, etc.
104 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
108 * ports on it. The USB 2.0 specification says that there are two
109 * variable length fields at the end of the hub descriptor:
110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
113 * 0xFF, so we initialize the both arrays (DeviceRemovable and
114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
115 * set of ports that actually exist.
117 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
118 sizeof(desc
->u
.hs
.DeviceRemovable
));
119 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
120 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
122 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
123 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
127 /* Fill in the USB 3.0 roothub descriptor */
128 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
129 struct usb_hub_descriptor
*desc
)
136 ports
= xhci
->num_usb3_ports
;
137 xhci_common_hub_descriptor(xhci
, desc
, ports
);
138 desc
->bDescriptorType
= USB_DT_SS_HUB
;
139 desc
->bDescLength
= USB_DT_SS_HUB_SIZE
;
141 /* header decode latency should be zero for roothubs,
142 * see section 4.23.5.2.
144 desc
->u
.ss
.bHubHdrDecLat
= 0;
145 desc
->u
.ss
.wHubDelay
= 0;
148 /* bit 0 is reserved, bit 1 is for port 1, etc. */
149 for (i
= 0; i
< ports
; i
++) {
150 portsc
= xhci_readl(xhci
, xhci
->usb3_ports
[i
]);
151 if (portsc
& PORT_DEV_REMOVE
)
152 port_removable
|= 1 << (i
+ 1);
155 desc
->u
.ss
.DeviceRemovable
= cpu_to_le16(port_removable
);
158 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
159 struct usb_hub_descriptor
*desc
)
162 if (hcd
->speed
== HCD_USB3
)
163 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
165 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
169 static unsigned int xhci_port_speed(unsigned int port_status
)
171 if (DEV_LOWSPEED(port_status
))
172 return USB_PORT_STAT_LOW_SPEED
;
173 if (DEV_HIGHSPEED(port_status
))
174 return USB_PORT_STAT_HIGH_SPEED
;
176 * FIXME: Yes, we should check for full speed, but the core uses that as
177 * a default in portspeed() in usb/core/hub.c (which is the only place
178 * USB_PORT_STAT_*_SPEED is used).
184 * These bits are Read Only (RO) and should be saved and written to the
185 * registers: 0, 3, 10:13, 30
186 * connect status, over-current status, port speed, and device removable.
187 * connect status and port speed are also sticky - meaning they're in
188 * the AUX well and they aren't changed by a hot, warm, or cold reset.
190 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
192 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
193 * bits 5:8, 9, 14:15, 25:27
194 * link state, port power, port indicator state, "wake on" enable state
196 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
198 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
201 #define XHCI_PORT_RW1S ((1<<4))
203 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
204 * bits 1, 17, 18, 19, 20, 21, 22, 23
205 * port enable/disable, and
206 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
207 * over-current, reset, link state, and L1 change
209 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
211 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
214 #define XHCI_PORT_RW ((1<<16))
216 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
219 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
222 * Given a port state, this function returns a value that would result in the
223 * port being in the same state, if the value was written to the port status
225 * Save Read Only (RO) bits and save read/write bits where
226 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
227 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
229 u32
xhci_port_state_to_neutral(u32 state
)
231 /* Save read-only status and port state */
232 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
236 * find slot id based on port number.
237 * @port: The one-based port number from one of the two split roothubs.
239 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
244 enum usb_device_speed speed
;
247 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
250 speed
= xhci
->devs
[i
]->udev
->speed
;
251 if (((speed
== USB_SPEED_SUPER
) == (hcd
->speed
== HCD_USB3
))
252 && xhci
->devs
[i
]->fake_port
== port
) {
263 * It issues stop endpoint command for EP 0 to 30. And wait the last command
265 * suspend will set to 1, if suspend bit need to set in command.
267 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
269 struct xhci_virt_device
*virt_dev
;
270 struct xhci_command
*cmd
;
277 virt_dev
= xhci
->devs
[slot_id
];
278 cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
280 xhci_dbg(xhci
, "Couldn't allocate command structure.\n");
284 spin_lock_irqsave(&xhci
->lock
, flags
);
285 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
286 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
)
287 xhci_queue_stop_endpoint(xhci
, slot_id
, i
, suspend
);
289 cmd
->command_trb
= xhci
->cmd_ring
->enqueue
;
290 list_add_tail(&cmd
->cmd_list
, &virt_dev
->cmd_list
);
291 xhci_queue_stop_endpoint(xhci
, slot_id
, 0, suspend
);
292 xhci_ring_cmd_db(xhci
);
293 spin_unlock_irqrestore(&xhci
->lock
, flags
);
295 /* Wait for last stop endpoint command to finish */
296 timeleft
= wait_for_completion_interruptible_timeout(
298 USB_CTRL_SET_TIMEOUT
);
300 xhci_warn(xhci
, "%s while waiting for stop endpoint command\n",
301 timeleft
== 0 ? "Timeout" : "Signal");
302 spin_lock_irqsave(&xhci
->lock
, flags
);
303 /* The timeout might have raced with the event ring handler, so
304 * only delete from the list if the item isn't poisoned.
306 if (cmd
->cmd_list
.next
!= LIST_POISON1
)
307 list_del(&cmd
->cmd_list
);
308 spin_unlock_irqrestore(&xhci
->lock
, flags
);
310 goto command_cleanup
;
314 xhci_free_command(xhci
, cmd
);
319 * Ring device, it rings the all doorbells unconditionally.
321 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
325 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++)
326 if (xhci
->devs
[slot_id
]->eps
[i
].ring
&&
327 xhci
->devs
[slot_id
]->eps
[i
].ring
->dequeue
)
328 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
333 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
334 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
336 /* Don't allow the USB core to disable SuperSpeed ports. */
337 if (hcd
->speed
== HCD_USB3
) {
338 xhci_dbg(xhci
, "Ignoring request to disable "
339 "SuperSpeed port.\n");
343 /* Write 1 to disable the port */
344 xhci_writel(xhci
, port_status
| PORT_PE
, addr
);
345 port_status
= xhci_readl(xhci
, addr
);
346 xhci_dbg(xhci
, "disable port, actual port %d status = 0x%x\n",
347 wIndex
, port_status
);
350 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
351 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
353 char *port_change_bit
;
357 case USB_PORT_FEAT_C_RESET
:
359 port_change_bit
= "reset";
361 case USB_PORT_FEAT_C_BH_PORT_RESET
:
363 port_change_bit
= "warm(BH) reset";
365 case USB_PORT_FEAT_C_CONNECTION
:
367 port_change_bit
= "connect";
369 case USB_PORT_FEAT_C_OVER_CURRENT
:
371 port_change_bit
= "over-current";
373 case USB_PORT_FEAT_C_ENABLE
:
375 port_change_bit
= "enable/disable";
377 case USB_PORT_FEAT_C_SUSPEND
:
379 port_change_bit
= "suspend/resume";
381 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
383 port_change_bit
= "link state";
386 /* Should never happen */
389 /* Change bits are all write 1 to clear */
390 xhci_writel(xhci
, port_status
| status
, addr
);
391 port_status
= xhci_readl(xhci
, addr
);
392 xhci_dbg(xhci
, "clear port %s change, actual port %d status = 0x%x\n",
393 port_change_bit
, wIndex
, port_status
);
396 static int xhci_get_ports(struct usb_hcd
*hcd
, __le32 __iomem
***port_array
)
399 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
401 if (hcd
->speed
== HCD_USB3
) {
402 max_ports
= xhci
->num_usb3_ports
;
403 *port_array
= xhci
->usb3_ports
;
405 max_ports
= xhci
->num_usb2_ports
;
406 *port_array
= xhci
->usb2_ports
;
412 void xhci_set_link_state(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
413 int port_id
, u32 link_state
)
417 temp
= xhci_readl(xhci
, port_array
[port_id
]);
418 temp
= xhci_port_state_to_neutral(temp
);
419 temp
&= ~PORT_PLS_MASK
;
420 temp
|= PORT_LINK_STROBE
| link_state
;
421 xhci_writel(xhci
, temp
, port_array
[port_id
]);
424 static void xhci_set_remote_wake_mask(struct xhci_hcd
*xhci
,
425 __le32 __iomem
**port_array
, int port_id
, u16 wake_mask
)
429 temp
= xhci_readl(xhci
, port_array
[port_id
]);
430 temp
= xhci_port_state_to_neutral(temp
);
432 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_CONNECT
)
433 temp
|= PORT_WKCONN_E
;
435 temp
&= ~PORT_WKCONN_E
;
437 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
)
438 temp
|= PORT_WKDISC_E
;
440 temp
&= ~PORT_WKDISC_E
;
442 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
)
445 temp
&= ~PORT_WKOC_E
;
447 xhci_writel(xhci
, temp
, port_array
[port_id
]);
450 /* Test and clear port RWC bit */
451 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
452 int port_id
, u32 port_bit
)
456 temp
= xhci_readl(xhci
, port_array
[port_id
]);
457 if (temp
& port_bit
) {
458 temp
= xhci_port_state_to_neutral(temp
);
460 xhci_writel(xhci
, temp
, port_array
[port_id
]);
464 /* Updates Link Status for super Speed port */
465 static void xhci_hub_report_link_state(u32
*status
, u32 status_reg
)
467 u32 pls
= status_reg
& PORT_PLS_MASK
;
469 /* resume state is a xHCI internal state.
470 * Do not report it to usb core.
472 if (pls
== XDEV_RESUME
)
475 /* When the CAS bit is set then warm reset
476 * should be performed on port
478 if (status_reg
& PORT_CAS
) {
479 /* The CAS bit can be set while the port is
481 * Only roothubs have CAS bit, so we
482 * pretend to be in compliance mode
483 * unless we're already in compliance
484 * or the inactive state.
486 if (pls
!= USB_SS_PORT_LS_COMP_MOD
&&
487 pls
!= USB_SS_PORT_LS_SS_INACTIVE
) {
488 pls
= USB_SS_PORT_LS_COMP_MOD
;
490 /* Return also connection bit -
491 * hub state machine resets port
492 * when this bit is set.
494 pls
|= USB_PORT_STAT_CONNECTION
;
497 * If CAS bit isn't set but the Port is already at
498 * Compliance Mode, fake a connection so the USB core
499 * notices the Compliance state and resets the port.
500 * This resolves an issue generated by the SN65LVPE502CP
501 * in which sometimes the port enters compliance mode
502 * caused by a delay on the host-device negotiation.
504 if (pls
== USB_SS_PORT_LS_COMP_MOD
)
505 pls
|= USB_PORT_STAT_CONNECTION
;
508 /* update status field */
513 * Function for Compliance Mode Quirk.
515 * This Function verifies if all xhc USB3 ports have entered U0, if so,
516 * the compliance mode timer is deleted. A port won't enter
517 * compliance mode if it has previously entered U0.
519 void xhci_del_comp_mod_timer(struct xhci_hcd
*xhci
, u32 status
, u16 wIndex
)
521 u32 all_ports_seen_u0
= ((1 << xhci
->num_usb3_ports
)-1);
522 bool port_in_u0
= ((status
& PORT_PLS_MASK
) == XDEV_U0
);
524 if (!(xhci
->quirks
& XHCI_COMP_MODE_QUIRK
))
527 if ((xhci
->port_status_u0
!= all_ports_seen_u0
) && port_in_u0
) {
528 xhci
->port_status_u0
|= 1 << wIndex
;
529 if (xhci
->port_status_u0
== all_ports_seen_u0
) {
530 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
531 xhci_dbg(xhci
, "All USB3 ports have entered U0 already!\n");
532 xhci_dbg(xhci
, "Compliance Mode Recovery Timer Deleted.\n");
537 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
538 u16 wIndex
, char *buf
, u16 wLength
)
540 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
545 __le32 __iomem
**port_array
;
547 struct xhci_bus_state
*bus_state
;
552 max_ports
= xhci_get_ports(hcd
, &port_array
);
553 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
555 spin_lock_irqsave(&xhci
->lock
, flags
);
558 /* No power source, over-current reported per port */
561 case GetHubDescriptor
:
562 /* Check to make sure userspace is asking for the USB 3.0 hub
563 * descriptor for the USB 3.0 roothub. If not, we stall the
564 * endpoint, like external hubs do.
566 if (hcd
->speed
== HCD_USB3
&&
567 (wLength
< USB_DT_SS_HUB_SIZE
||
568 wValue
!= (USB_DT_SS_HUB
<< 8))) {
569 xhci_dbg(xhci
, "Wrong hub descriptor type for "
570 "USB 3.0 roothub.\n");
573 xhci_hub_descriptor(hcd
, xhci
,
574 (struct usb_hub_descriptor
*) buf
);
576 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
577 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
580 if (hcd
->speed
!= HCD_USB3
)
583 /* Set the U1 and U2 exit latencies. */
584 memcpy(buf
, &usb_bos_descriptor
,
585 USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
);
586 temp
= xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params3
);
587 buf
[12] = HCS_U1_LATENCY(temp
);
588 put_unaligned_le16(HCS_U2_LATENCY(temp
), &buf
[13]);
590 /* Indicate whether the host has LTM support. */
591 temp
= xhci_readl(xhci
, &xhci
->cap_regs
->hcc_params
);
593 buf
[8] |= USB_LTM_SUPPORT
;
595 spin_unlock_irqrestore(&xhci
->lock
, flags
);
596 return USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
598 if (!wIndex
|| wIndex
> max_ports
)
602 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
603 if (temp
== 0xffffffff) {
607 xhci_dbg(xhci
, "get port status, actual port %d status = 0x%x\n", wIndex
, temp
);
609 /* wPortChange bits */
611 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
613 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
614 if ((temp
& PORT_OCC
))
615 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
616 if ((temp
& PORT_RC
))
617 status
|= USB_PORT_STAT_C_RESET
<< 16;
619 if (hcd
->speed
== HCD_USB3
) {
620 if ((temp
& PORT_PLC
))
621 status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
622 if ((temp
& PORT_WRC
))
623 status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
626 if (hcd
->speed
!= HCD_USB3
) {
627 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
628 && (temp
& PORT_POWER
))
629 status
|= USB_PORT_STAT_SUSPEND
;
631 if ((temp
& PORT_PLS_MASK
) == XDEV_RESUME
&&
632 !DEV_SUPERSPEED(temp
)) {
633 if ((temp
& PORT_RESET
) || !(temp
& PORT_PE
))
635 if (time_after_eq(jiffies
,
636 bus_state
->resume_done
[wIndex
])) {
637 xhci_dbg(xhci
, "Resume USB2 port %d\n",
639 bus_state
->resume_done
[wIndex
] = 0;
640 clear_bit(wIndex
, &bus_state
->resuming_ports
);
641 xhci_set_link_state(xhci
, port_array
, wIndex
,
643 xhci_dbg(xhci
, "set port %d resume\n",
645 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
648 xhci_dbg(xhci
, "slot_id is zero\n");
651 xhci_ring_device(xhci
, slot_id
);
652 bus_state
->port_c_suspend
|= 1 << wIndex
;
653 bus_state
->suspended_ports
&= ~(1 << wIndex
);
656 * The resume has been signaling for less than
657 * 20ms. Report the port status as SUSPEND,
658 * let the usbcore check port status again
659 * and clear resume signaling later.
661 status
|= USB_PORT_STAT_SUSPEND
;
664 if ((temp
& PORT_PLS_MASK
) == XDEV_U0
665 && (temp
& PORT_POWER
)
666 && (bus_state
->suspended_ports
& (1 << wIndex
))) {
667 bus_state
->suspended_ports
&= ~(1 << wIndex
);
668 if (hcd
->speed
!= HCD_USB3
)
669 bus_state
->port_c_suspend
|= 1 << wIndex
;
671 if (temp
& PORT_CONNECT
) {
672 status
|= USB_PORT_STAT_CONNECTION
;
673 status
|= xhci_port_speed(temp
);
676 status
|= USB_PORT_STAT_ENABLE
;
678 status
|= USB_PORT_STAT_OVERCURRENT
;
679 if (temp
& PORT_RESET
)
680 status
|= USB_PORT_STAT_RESET
;
681 if (temp
& PORT_POWER
) {
682 if (hcd
->speed
== HCD_USB3
)
683 status
|= USB_SS_PORT_STAT_POWER
;
685 status
|= USB_PORT_STAT_POWER
;
687 /* Update Port Link State for super speed ports*/
688 if (hcd
->speed
== HCD_USB3
) {
689 xhci_hub_report_link_state(&status
, temp
);
691 * Verify if all USB3 Ports Have entered U0 already.
692 * Delete Compliance Mode Timer if so.
694 xhci_del_comp_mod_timer(xhci
, temp
, wIndex
);
696 if (bus_state
->port_c_suspend
& (1 << wIndex
))
697 status
|= 1 << USB_PORT_FEAT_C_SUSPEND
;
698 xhci_dbg(xhci
, "Get port status returned 0x%x\n", status
);
699 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
702 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
703 link_state
= (wIndex
& 0xff00) >> 3;
704 if (wValue
== USB_PORT_FEAT_REMOTE_WAKE_MASK
)
705 wake_mask
= wIndex
& 0xff00;
706 /* The MSB of wIndex is the U1/U2 timeout */
707 timeout
= (wIndex
& 0xff00) >> 8;
709 if (!wIndex
|| wIndex
> max_ports
)
712 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
713 if (temp
== 0xffffffff) {
717 temp
= xhci_port_state_to_neutral(temp
);
718 /* FIXME: What new port features do we need to support? */
720 case USB_PORT_FEAT_SUSPEND
:
721 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
722 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
723 /* Resume the port to U0 first */
724 xhci_set_link_state(xhci
, port_array
, wIndex
,
726 spin_unlock_irqrestore(&xhci
->lock
, flags
);
728 spin_lock_irqsave(&xhci
->lock
, flags
);
730 /* In spec software should not attempt to suspend
731 * a port unless the port reports that it is in the
732 * enabled (PED = ‘1’,PLS < ‘3’) state.
734 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
735 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
736 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
737 xhci_warn(xhci
, "USB core suspending device "
738 "not in U0/U1/U2.\n");
742 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
745 xhci_warn(xhci
, "slot_id is zero\n");
748 /* unlock to execute stop endpoint commands */
749 spin_unlock_irqrestore(&xhci
->lock
, flags
);
750 xhci_stop_device(xhci
, slot_id
, 1);
751 spin_lock_irqsave(&xhci
->lock
, flags
);
753 xhci_set_link_state(xhci
, port_array
, wIndex
, XDEV_U3
);
755 spin_unlock_irqrestore(&xhci
->lock
, flags
);
756 msleep(10); /* wait device to enter */
757 spin_lock_irqsave(&xhci
->lock
, flags
);
759 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
760 bus_state
->suspended_ports
|= 1 << wIndex
;
762 case USB_PORT_FEAT_LINK_STATE
:
763 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
766 if (link_state
== USB_SS_PORT_LS_SS_DISABLED
) {
767 xhci_dbg(xhci
, "Disable port %d\n", wIndex
);
768 temp
= xhci_port_state_to_neutral(temp
);
770 * Clear all change bits, so that we get a new
773 temp
|= PORT_CSC
| PORT_PEC
| PORT_WRC
|
774 PORT_OCC
| PORT_RC
| PORT_PLC
|
776 xhci_writel(xhci
, temp
| PORT_PE
,
778 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
782 /* Put link in RxDetect (enable port) */
783 if (link_state
== USB_SS_PORT_LS_RX_DETECT
) {
784 xhci_dbg(xhci
, "Enable port %d\n", wIndex
);
785 xhci_set_link_state(xhci
, port_array
, wIndex
,
787 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
791 /* Software should not attempt to set
792 * port link state above '3' (U3) and the port
795 if ((temp
& PORT_PE
) == 0 ||
796 (link_state
> USB_SS_PORT_LS_U3
)) {
797 xhci_warn(xhci
, "Cannot set link state.\n");
801 if (link_state
== USB_SS_PORT_LS_U3
) {
802 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
805 /* unlock to execute stop endpoint
807 spin_unlock_irqrestore(&xhci
->lock
,
809 xhci_stop_device(xhci
, slot_id
, 1);
810 spin_lock_irqsave(&xhci
->lock
, flags
);
814 xhci_set_link_state(xhci
, port_array
, wIndex
,
817 spin_unlock_irqrestore(&xhci
->lock
, flags
);
818 msleep(20); /* wait device to enter */
819 spin_lock_irqsave(&xhci
->lock
, flags
);
821 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
822 if (link_state
== USB_SS_PORT_LS_U3
)
823 bus_state
->suspended_ports
|= 1 << wIndex
;
825 case USB_PORT_FEAT_POWER
:
827 * Turn on ports, even if there isn't per-port switching.
828 * HC will report connect events even before this is set.
829 * However, khubd will ignore the roothub events until
830 * the roothub is registered.
832 xhci_writel(xhci
, temp
| PORT_POWER
,
835 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
836 xhci_dbg(xhci
, "set port power, actual port %d status = 0x%x\n", wIndex
, temp
);
838 spin_unlock_irqrestore(&xhci
->lock
, flags
);
839 temp
= usb_acpi_power_manageable(hcd
->self
.root_hub
,
842 usb_acpi_set_power_state(hcd
->self
.root_hub
,
844 spin_lock_irqsave(&xhci
->lock
, flags
);
846 case USB_PORT_FEAT_RESET
:
847 temp
= (temp
| PORT_RESET
);
848 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
850 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
851 xhci_dbg(xhci
, "set port reset, actual port %d status = 0x%x\n", wIndex
, temp
);
853 case USB_PORT_FEAT_REMOTE_WAKE_MASK
:
854 xhci_set_remote_wake_mask(xhci
, port_array
,
856 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
857 xhci_dbg(xhci
, "set port remote wake mask, "
858 "actual port %d status = 0x%x\n",
861 case USB_PORT_FEAT_BH_PORT_RESET
:
863 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
865 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
867 case USB_PORT_FEAT_U1_TIMEOUT
:
868 if (hcd
->speed
!= HCD_USB3
)
870 temp
= xhci_readl(xhci
, port_array
[wIndex
] + 1);
871 temp
&= ~PORT_U1_TIMEOUT_MASK
;
872 temp
|= PORT_U1_TIMEOUT(timeout
);
873 xhci_writel(xhci
, temp
, port_array
[wIndex
] + 1);
875 case USB_PORT_FEAT_U2_TIMEOUT
:
876 if (hcd
->speed
!= HCD_USB3
)
878 temp
= xhci_readl(xhci
, port_array
[wIndex
] + 1);
879 temp
&= ~PORT_U2_TIMEOUT_MASK
;
880 temp
|= PORT_U2_TIMEOUT(timeout
);
881 xhci_writel(xhci
, temp
, port_array
[wIndex
] + 1);
886 /* unblock any posted writes */
887 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
889 case ClearPortFeature
:
890 if (!wIndex
|| wIndex
> max_ports
)
893 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
894 if (temp
== 0xffffffff) {
898 /* FIXME: What new port features do we need to support? */
899 temp
= xhci_port_state_to_neutral(temp
);
901 case USB_PORT_FEAT_SUSPEND
:
902 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
903 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
904 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
905 if (temp
& PORT_RESET
)
907 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
908 if ((temp
& PORT_PE
) == 0)
911 xhci_set_link_state(xhci
, port_array
, wIndex
,
913 spin_unlock_irqrestore(&xhci
->lock
, flags
);
915 spin_lock_irqsave(&xhci
->lock
, flags
);
916 xhci_set_link_state(xhci
, port_array
, wIndex
,
919 bus_state
->port_c_suspend
|= 1 << wIndex
;
921 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
924 xhci_dbg(xhci
, "slot_id is zero\n");
927 xhci_ring_device(xhci
, slot_id
);
929 case USB_PORT_FEAT_C_SUSPEND
:
930 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
931 case USB_PORT_FEAT_C_RESET
:
932 case USB_PORT_FEAT_C_BH_PORT_RESET
:
933 case USB_PORT_FEAT_C_CONNECTION
:
934 case USB_PORT_FEAT_C_OVER_CURRENT
:
935 case USB_PORT_FEAT_C_ENABLE
:
936 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
937 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
938 port_array
[wIndex
], temp
);
940 case USB_PORT_FEAT_ENABLE
:
941 xhci_disable_port(hcd
, xhci
, wIndex
,
942 port_array
[wIndex
], temp
);
944 case USB_PORT_FEAT_POWER
:
945 xhci_writel(xhci
, temp
& ~PORT_POWER
,
948 spin_unlock_irqrestore(&xhci
->lock
, flags
);
949 temp
= usb_acpi_power_manageable(hcd
->self
.root_hub
,
952 usb_acpi_set_power_state(hcd
->self
.root_hub
,
954 spin_lock_irqsave(&xhci
->lock
, flags
);
962 /* "stall" on error */
965 spin_unlock_irqrestore(&xhci
->lock
, flags
);
970 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
971 * Ports are 0-indexed from the HCD point of view,
972 * and 1-indexed from the USB core pointer of view.
974 * Note that the status change bits will be cleared as soon as a port status
975 * change event is generated, so we use the saved status from that event.
977 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
983 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
985 __le32 __iomem
**port_array
;
986 struct xhci_bus_state
*bus_state
;
987 bool reset_change
= false;
989 max_ports
= xhci_get_ports(hcd
, &port_array
);
990 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
992 /* Initial status is no changes */
993 retval
= (max_ports
+ 8) / 8;
994 memset(buf
, 0, retval
);
997 * Inform the usbcore about resume-in-progress by returning
998 * a non-zero value even if there are no status changes.
1000 status
= bus_state
->resuming_ports
;
1002 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
;
1004 spin_lock_irqsave(&xhci
->lock
, flags
);
1005 /* For each port, did anything change? If so, set that bit in buf. */
1006 for (i
= 0; i
< max_ports
; i
++) {
1007 temp
= xhci_readl(xhci
, port_array
[i
]);
1008 if (temp
== 0xffffffff) {
1012 if ((temp
& mask
) != 0 ||
1013 (bus_state
->port_c_suspend
& 1 << i
) ||
1014 (bus_state
->resume_done
[i
] && time_after_eq(
1015 jiffies
, bus_state
->resume_done
[i
]))) {
1016 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
1019 if ((temp
& PORT_RC
))
1020 reset_change
= true;
1022 if (!status
&& !reset_change
) {
1023 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
1024 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1026 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1027 return status
? retval
: 0;
1032 int xhci_bus_suspend(struct usb_hcd
*hcd
)
1034 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1035 int max_ports
, port_index
;
1036 __le32 __iomem
**port_array
;
1037 struct xhci_bus_state
*bus_state
;
1038 unsigned long flags
;
1040 max_ports
= xhci_get_ports(hcd
, &port_array
);
1041 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1043 spin_lock_irqsave(&xhci
->lock
, flags
);
1045 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
1046 if (bus_state
->resuming_ports
) {
1047 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1048 xhci_dbg(xhci
, "suspend failed because "
1049 "a port is resuming\n");
1054 port_index
= max_ports
;
1055 bus_state
->bus_suspended
= 0;
1056 while (port_index
--) {
1057 /* suspend the port if the port is not suspended */
1061 t1
= xhci_readl(xhci
, port_array
[port_index
]);
1062 t2
= xhci_port_state_to_neutral(t1
);
1064 if ((t1
& PORT_PE
) && !(t1
& PORT_PLS_MASK
)) {
1065 xhci_dbg(xhci
, "port %d not suspended\n", port_index
);
1066 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1069 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1070 xhci_stop_device(xhci
, slot_id
, 1);
1071 spin_lock_irqsave(&xhci
->lock
, flags
);
1073 t2
&= ~PORT_PLS_MASK
;
1074 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
1075 set_bit(port_index
, &bus_state
->bus_suspended
);
1077 /* USB core sets remote wake mask for USB 3.0 hubs,
1078 * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
1079 * is enabled, so also enable remote wake here.
1081 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
1082 if (t1
& PORT_CONNECT
) {
1083 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
1084 t2
&= ~PORT_WKCONN_E
;
1086 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
1087 t2
&= ~PORT_WKDISC_E
;
1090 t2
&= ~PORT_WAKE_BITS
;
1092 t1
= xhci_port_state_to_neutral(t1
);
1094 xhci_writel(xhci
, t2
, port_array
[port_index
]);
1096 if (hcd
->speed
!= HCD_USB3
) {
1097 /* enable remote wake up for USB 2.0 */
1098 __le32 __iomem
*addr
;
1101 /* Add one to the port status register address to get
1102 * the port power control register address.
1104 addr
= port_array
[port_index
] + 1;
1105 tmp
= xhci_readl(xhci
, addr
);
1107 xhci_writel(xhci
, tmp
, addr
);
1110 hcd
->state
= HC_STATE_SUSPENDED
;
1111 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
1112 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1116 int xhci_bus_resume(struct usb_hcd
*hcd
)
1118 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1119 int max_ports
, port_index
;
1120 __le32 __iomem
**port_array
;
1121 struct xhci_bus_state
*bus_state
;
1123 unsigned long flags
;
1125 max_ports
= xhci_get_ports(hcd
, &port_array
);
1126 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1128 if (time_before(jiffies
, bus_state
->next_statechange
))
1131 spin_lock_irqsave(&xhci
->lock
, flags
);
1132 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1133 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1137 /* delay the irqs */
1138 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1140 xhci_writel(xhci
, temp
, &xhci
->op_regs
->command
);
1142 port_index
= max_ports
;
1143 while (port_index
--) {
1144 /* Check whether need resume ports. If needed
1145 resume port and disable remote wakeup */
1149 temp
= xhci_readl(xhci
, port_array
[port_index
]);
1150 if (DEV_SUPERSPEED(temp
))
1151 temp
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1153 temp
&= ~(PORT_RWC_BITS
| PORT_WAKE_BITS
);
1154 if (test_bit(port_index
, &bus_state
->bus_suspended
) &&
1155 (temp
& PORT_PLS_MASK
)) {
1156 if (DEV_SUPERSPEED(temp
)) {
1157 xhci_set_link_state(xhci
, port_array
,
1158 port_index
, XDEV_U0
);
1160 xhci_set_link_state(xhci
, port_array
,
1161 port_index
, XDEV_RESUME
);
1163 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1165 spin_lock_irqsave(&xhci
->lock
, flags
);
1167 xhci_set_link_state(xhci
, port_array
,
1168 port_index
, XDEV_U0
);
1170 /* wait for the port to enter U0 and report port link
1173 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1175 spin_lock_irqsave(&xhci
->lock
, flags
);
1178 xhci_test_and_clear_bit(xhci
, port_array
, port_index
,
1181 slot_id
= xhci_find_slot_id_by_port(hcd
,
1182 xhci
, port_index
+ 1);
1184 xhci_ring_device(xhci
, slot_id
);
1186 xhci_writel(xhci
, temp
, port_array
[port_index
]);
1188 if (hcd
->speed
!= HCD_USB3
) {
1189 /* disable remote wake up for USB 2.0 */
1190 __le32 __iomem
*addr
;
1193 /* Add one to the port status register address to get
1194 * the port power control register address.
1196 addr
= port_array
[port_index
] + 1;
1197 tmp
= xhci_readl(xhci
, addr
);
1199 xhci_writel(xhci
, tmp
, addr
);
1203 (void) xhci_readl(xhci
, &xhci
->op_regs
->command
);
1205 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1206 /* re-enable irqs */
1207 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1209 xhci_writel(xhci
, temp
, &xhci
->op_regs
->command
);
1210 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1212 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1216 #endif /* CONFIG_PM */