arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/config.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kdev_t.h>
  40 #include <linux/types.h>
  41 #include <linux/sched.h>
  42 #include <linux/pci.h>
  43 #include <linux/ide.h>
  44 #include <linux/ioport.h>
  45 #include <linux/param.h>        /* for HZ */
  46 #include <linux/delay.h>
  47
  48 #include <asm/addrspace.h>
  49 #include <asm/time.h>
  50 #include <asm/bcache.h>
  51 #include <asm/irq.h>
  52 #include <asm/reboot.h>
  53 #include <asm/gdb-stub.h>
  54 #include <asm/jmr3927/jmr3927.h>
  55 #include <asm/mipsregs.h>
  56 #include <asm/traps.h>
  57
  58 /* Tick Timer divider */
  59 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  60 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  61
  62 unsigned char led_state = 0xf;
  63
  64 struct {
  65     struct resource ram0;
  66     struct resource ram1;
  67     struct resource pcimem;
  68     struct resource iob;
  69     struct resource ioc;
  70     struct resource pciio;
  71     struct resource jmy1394;
  72     struct resource rom1;
  73     struct resource rom0;
  74     struct resource sio0;
  75     struct resource sio1;
  76 } jmr3927_resources = {
  77     { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
  78     { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
  79     { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
  80     { "IOB",           0x10000000, 0x13FFFFFF                  },
  81     { "IOC",           0x14000000, 0x14FFFFFF                  },
  82     { "PCIIO",         0x15000000, 0x15FFFFFF                  },
  83     { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
  84     { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
  85     { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
  86     { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
  87     { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
  88 };
  89
  90 /* don't enable - see errata */
  91 int jmr3927_ccfg_toeon = 0;
  92
  93 static inline void do_reset(void)
  94 {
  95 #ifdef CONFIG_TC35815
  96         extern void tc35815_killall(void);
  97         tc35815_killall();
  98 #endif
  99 #if 1   /* Resetting PCI bus */
 100         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 101         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
 102         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
 103         mdelay(1);
 104         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 105 #endif
 106         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
 107 }
 108
 109 static void jmr3927_machine_restart(char *command)
 110 {
 111         local_irq_disable();
 112         puts("Rebooting...");
 113         do_reset();
 114 }
 115
 116 static void jmr3927_machine_halt(void)
 117 {
 118         puts("JMR-TX3927 halted.\n");
 119         while (1);
 120 }
 121
 122 static void jmr3927_machine_power_off(void)
 123 {
 124         puts("JMR-TX3927 halted. Please turn off the power.\n");
 125         while (1);
 126 }
 127
 128 #define USE_RTC_DS1742
 129 #ifdef USE_RTC_DS1742
 130 extern void rtc_ds1742_init(unsigned long base);
 131 #endif
 132 static void __init jmr3927_time_init(void)
 133 {
 134 #ifdef USE_RTC_DS1742
 135         if (jmr3927_have_nvram()) {
 136                 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
 137         }
 138 #endif
 139 }
 140
 141 unsigned long jmr3927_do_gettimeoffset(void);
 142 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 143
 144 static void __init jmr3927_timer_setup(struct irqaction *irq)
 145 {
 146         do_gettimeoffset = jmr3927_do_gettimeoffset;
 147
 148         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 149         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 150         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 151         jmr3927_tmrptr->tcr =
 152                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 153
 154         setup_irq(JMR3927_IRQ_TICK, irq);
 155 }
 156
 157 #define USECS_PER_JIFFY (1000000/HZ)
 158
 159 unsigned long jmr3927_do_gettimeoffset(void)
 160 {
 161        unsigned long count;
 162        unsigned long res = 0;
 163
 164        /* MUST read TRR before TISR. */
 165        count = jmr3927_tmrptr->trr;
 166
 167        if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
 168                /* timer interrupt is pending.  use Max value. */
 169                res = USECS_PER_JIFFY - 1;
 170        } else {
 171                /* convert to usec */
 172                /* res = count / (JMR3927_TIMER_CLK / 1000000); */
 173                res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
 174
 175                /*
 176                 * Due to possible jiffies inconsistencies, we need to check
 177                 * the result so that we'll get a timer that is monotonic.
 178                 */
 179                if (res >= USECS_PER_JIFFY)
 180                        res = USECS_PER_JIFFY-1;
 181        }
 182
 183        return res;
 184 }
 185
 186
 187 //#undef DO_WRITE_THROUGH
 188 #define DO_WRITE_THROUGH
 189 #define DO_ENABLE_CACHE
 190
 191 extern char * __init prom_getcmdline(void);
 192 static void jmr3927_board_init(void);
 193 extern struct resource pci_io_resource;
 194 extern struct resource pci_mem_resource;
 195
 196 static void __init jmr3927_setup(void)
 197 {
 198         char *argptr;
 199
 200         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 201
 202         board_time_init = jmr3927_time_init;
 203         board_timer_setup = jmr3927_timer_setup;
 204
 205         _machine_restart = jmr3927_machine_restart;
 206         _machine_halt = jmr3927_machine_halt;
 207         _machine_power_off = jmr3927_machine_power_off;
 208
 209         /*
 210          * IO/MEM resources.
 211          */
 212         ioport_resource.start = pci_io_resource.start;
 213         ioport_resource.end = pci_io_resource.end;
 214         iomem_resource.start = pci_mem_resource.start;
 215         iomem_resource.end = pci_mem_resource.end;
 216
 217         /* Reboot on panic */
 218         panic_timeout = 180;
 219
 220         {
 221                 unsigned int conf;
 222                 conf = read_c0_conf();
 223         }
 224
 225 #if 1
 226         /* cache setup */
 227         {
 228                 unsigned int conf;
 229 #ifdef DO_ENABLE_CACHE
 230                 int mips_ic_disable = 0, mips_dc_disable = 0;
 231 #else
 232                 int mips_ic_disable = 1, mips_dc_disable = 1;
 233 #endif
 234 #ifdef DO_WRITE_THROUGH
 235                 int mips_config_cwfon = 0;
 236                 int mips_config_wbon = 0;
 237 #else
 238                 int mips_config_cwfon = 1;
 239                 int mips_config_wbon = 1;
 240 #endif
 241
 242                 conf = read_c0_conf();
 243                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 244                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 245                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 246                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 247                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 248
 249                 write_c0_conf(conf);
 250                 write_c0_cache(0);
 251         }
 252 #endif
 253
 254         /* initialize board */
 255         jmr3927_board_init();
 256
 257         argptr = prom_getcmdline();
 258
 259         if ((argptr = strstr(argptr, "toeon")) != NULL) {
 260                         jmr3927_ccfg_toeon = 1;
 261         }
 262         argptr = prom_getcmdline();
 263         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 264                 argptr = prom_getcmdline();
 265                 strcat(argptr, " ip=bootp");
 266         }
 267
 268 #ifdef CONFIG_TXX927_SERIAL_CONSOLE
 269         argptr = prom_getcmdline();
 270         if ((argptr = strstr(argptr, "console=")) == NULL) {
 271                 argptr = prom_getcmdline();
 272                 strcat(argptr, " console=ttyS1,115200");
 273         }
 274 #endif
 275 }
 276
 277 early_initcall(jmr3927_setup);
 278
 279
 280 static void tx3927_setup(void);
 281
 282 #ifdef CONFIG_PCI
 283 unsigned long mips_pci_io_base;
 284 unsigned long mips_pci_io_size;
 285 unsigned long mips_pci_mem_base;
 286 unsigned long mips_pci_mem_size;
 287 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 288 unsigned long mips_pci_io_pciaddr = 0;
 289 #endif
 290
 291 static void __init jmr3927_board_init(void)
 292 {
 293         char *argptr;
 294
 295 #ifdef CONFIG_PCI
 296         mips_pci_io_base = JMR3927_PCIIO;
 297         mips_pci_io_size = JMR3927_PCIIO_SIZE;
 298         mips_pci_mem_base = JMR3927_PCIMEM;
 299         mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 300 #endif
 301
 302         tx3927_setup();
 303
 304         if (jmr3927_have_isac()) {
 305
 306 #ifdef CONFIG_FB_E1355
 307                 argptr = prom_getcmdline();
 308                 if ((argptr = strstr(argptr, "video=")) == NULL) {
 309                         argptr = prom_getcmdline();
 310                         strcat(argptr, " video=e1355fb:crt16h");
 311                 }
 312 #endif
 313
 314 #ifdef CONFIG_BLK_DEV_IDE
 315                 /* overrides PCI-IDE */
 316 #endif
 317         }
 318
 319         /* SIO0 DTR on */
 320         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 321
 322         jmr3927_led_set(0);
 323
 324
 325         if (jmr3927_have_isac())
 326                 jmr3927_io_led_set(0);
 327         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 328                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 329                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 330                jmr3927_dipsw1(), jmr3927_dipsw2(),
 331                jmr3927_dipsw3(), jmr3927_dipsw4());
 332         if (jmr3927_have_isac())
 333                 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
 334                        jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
 335                        jmr3927_io_dipsw());
 336 }
 337
 338 static void __init tx3927_setup(void)
 339 {
 340         int i;
 341
 342         /* SDRAMC are configured by PROM */
 343
 344         /* ROMC */
 345         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 346         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 347         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 348         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 349
 350         /* CCFG */
 351         /* enable Timeout BusError */
 352         if (jmr3927_ccfg_toeon)
 353                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 354
 355         /* clear BusErrorOnWrite flag */
 356         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 357         /* Disable PCI snoop */
 358         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 359
 360 #ifdef DO_WRITE_THROUGH
 361         /* Enable PCI SNOOP - with write through only */
 362         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 363 #endif
 364
 365         /* Pin selection */
 366         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 367         tx3927_ccfgptr->pcfg |=
 368                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 369                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 370
 371         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 372                tx3927_ccfgptr->crir,
 373                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 374
 375         /* IRC */
 376         /* disable interrupt control */
 377         tx3927_ircptr->cer = 0;
 378         /* mask all IRC interrupts */
 379         tx3927_ircptr->imr = 0;
 380         for (i = 0; i < TX3927_NUM_IR / 2; i++) {
 381                 tx3927_ircptr->ilr[i] = 0;
 382         }
 383         /* setup IRC interrupt mode (Low Active) */
 384         for (i = 0; i < TX3927_NUM_IR / 8; i++) {
 385                 tx3927_ircptr->cr[i] = 0;
 386         }
 387
 388         /* TMR */
 389         /* disable all timers */
 390         for (i = 0; i < TX3927_NR_TMR; i++) {
 391                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 392                 tx3927_tmrptr(i)->tisr = 0;
 393                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 394                 tx3927_tmrptr(i)->itmr = 0;
 395                 tx3927_tmrptr(i)->ccdr = 0;
 396                 tx3927_tmrptr(i)->pgmr = 0;
 397         }
 398
 399         /* DMA */
 400         tx3927_dmaptr->mcr = 0;
 401         for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
 402                 /* reset channel */
 403                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 404                 tx3927_dmaptr->ch[i].ccr = 0;
 405         }
 406         /* enable DMA */
 407 #ifdef __BIG_ENDIAN
 408         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 409 #else
 410         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 411 #endif
 412
 413 #ifdef CONFIG_PCI
 414         /* PCIC */
 415         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 416                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 417                tx3927_pcicptr->rid);
 418         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 419                 printk("External\n");
 420                 /* XXX */
 421         } else {
 422                 printk("Internal\n");
 423
 424                 /* Reset PCI Bus */
 425                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 426                 udelay(100);
 427                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 428                                     JMR3927_IOC_RESET_ADDR);
 429                 udelay(100);
 430                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 431
 432
 433                 /* Disable External PCI Config. Access */
 434                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 435 #ifdef __BIG_ENDIAN
 436                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 437                         TX3927_PCIC_LBC_TIBSE |
 438                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 439 #endif
 440                 /* LB->PCI mappings */
 441                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 442                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 443                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 444                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 445                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 446                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 447                 /* PCI->LB mappings */
 448                 tx3927_pcicptr->iobas = 0xffffffff;
 449                 tx3927_pcicptr->ioba = 0;
 450                 tx3927_pcicptr->tlbioma = 0;
 451                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 452                 tx3927_pcicptr->mba = 0;
 453                 tx3927_pcicptr->tlbmma = 0;
 454 #ifndef JMR3927_INIT_INDIRECT_PCI
 455                 /* Enable Direct mapping Address Space Decoder */
 456                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 457 #endif
 458
 459                 /* Clear All Local Bus Status */
 460                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 461                 /* Enable All Local Bus Interrupts */
 462                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 463                 /* Clear All PCI Status Error */
 464                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 465                 /* Enable All PCI Status Error Interrupts */
 466                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 467
 468                 /* PCIC Int => IRC IRQ10 */
 469                 tx3927_pcicptr->il = TX3927_IR_PCI;
 470 #if 1
 471                 /* Target Control (per errata) */
 472                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 473 #endif
 474
 475                 /* Enable Bus Arbiter */
 476 #if 0
 477                 tx3927_pcicptr->req_trace = 0x73737373;
 478 #endif
 479                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 480
 481                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 482                         PCI_COMMAND_MEMORY |
 483 #if 1
 484                         PCI_COMMAND_IO |
 485 #endif
 486                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 487         }
 488 #endif /* CONFIG_PCI */
 489
 490         /* PIO */
 491         /* PIO[15:12] connected to LEDs */
 492         tx3927_pioptr->dir = 0x0000f000;
 493         tx3927_pioptr->maskcpu = 0;
 494         tx3927_pioptr->maskext = 0;
 495         {
 496                 unsigned int conf;
 497
 498         conf = read_c0_conf();
 499                if (!(conf & TX39_CONF_ICE))
 500                        printk("TX3927 I-Cache disabled.\n");
 501                if (!(conf & TX39_CONF_DCE))
 502                        printk("TX3927 D-Cache disabled.\n");
 503                else if (!(conf & TX39_CONF_WBON))
 504                        printk("TX3927 D-Cache WriteThrough.\n");
 505                else if (!(conf & TX39_CONF_CWFON))
 506                        printk("TX3927 D-Cache WriteBack.\n");
 507                else
 508                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 509         }
 510 }