arch/mips/mips-boards/generic/pci.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
   6  *
   7  *  This program is free software; you can distribute it and/or modify it
   8  *  under the terms of the GNU General Public License (Version 2) as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, write to the Free Software Foundation, Inc.,
  18  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19  *
  20  * MIPS boards specific PCI support.
  21  */
  22 #include <linux/config.h>
  23 #include <linux/types.h>
  24 #include <linux/pci.h>
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27
  28 #include <asm/mips-boards/generic.h>
  29 #include <asm/gt64120.h>
  30 #include <asm/mips-boards/bonito64.h>
  31 #include <asm/mips-boards/msc01_pci.h>
  32 #ifdef CONFIG_MIPS_MALTA
  33 #include <asm/mips-boards/malta.h>
  34 #endif
  35
  36 static struct resource bonito64_mem_resource = {
  37         .name   = "Bonito PCI MEM",
  38         .start  = 0x10000000UL,
  39         .end    = 0x1bffffffUL,
  40         .flags  = IORESOURCE_MEM,
  41 };
  42
  43 static struct resource bonito64_io_resource = {
  44         .name   = "Bonito IO MEM",
  45         .start  = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */
  46         .end    = 0x000fffffUL,
  47         .flags  = IORESOURCE_IO,
  48 };
  49
  50 static struct resource gt64120_mem_resource = {
  51         .name   = "GT64120 PCI MEM",
  52         .start  = 0x10000000UL,
  53         .end    = 0x1bdfffffUL,
  54         .flags  = IORESOURCE_MEM,
  55 };
  56
  57 static struct resource gt64120_io_resource = {
  58         .name   = "GT64120 IO MEM",
  59 #ifdef CONFIG_MIPS_ATLAS
  60         .start  = 0x18000000UL,
  61         .end    = 0x181fffffUL,
  62 #endif
  63 #ifdef CONFIG_MIPS_MALTA
  64         .start  = 0x00002000UL,
  65         .end    = 0x001fffffUL,
  66 #endif
  67         .flags  = IORESOURCE_IO,
  68 };
  69
  70 static struct resource msc_mem_resource = {
  71         .name   = "MSC PCI MEM",
  72         .start  = 0x10000000UL,
  73         .end    = 0x1fffffffUL,
  74         .flags  = IORESOURCE_MEM,
  75 };
  76
  77 static struct resource msc_io_resource = {
  78         .name   = "MSC IO MEM",
  79         .start  = 0x00002000UL,
  80         .end    = 0x007fffffUL,
  81         .flags  = IORESOURCE_IO,
  82 };
  83
  84 extern struct pci_ops bonito64_pci_ops;
  85 extern struct pci_ops gt64120_pci_ops;
  86 extern struct pci_ops msc_pci_ops;
  87
  88 static struct pci_controller bonito64_controller = {
  89         .pci_ops        = &bonito64_pci_ops,
  90         .io_resource    = &bonito64_io_resource,
  91         .mem_resource   = &bonito64_mem_resource,
  92         .mem_offset     = 0x10000000UL,
  93         .io_offset      = 0x00000000UL,
  94 };
  95
  96 static struct pci_controller gt64120_controller = {
  97         .pci_ops        = &gt64120_pci_ops,
  98         .io_resource    = &gt64120_io_resource,
  99         .mem_resource   = &gt64120_mem_resource,
 100         .mem_offset     = 0x00000000UL,
 101         .io_offset      = 0x00000000UL,
 102 };
 103
 104 static struct pci_controller  msc_controller = {
 105         .pci_ops        = &msc_pci_ops,
 106         .io_resource    = &msc_io_resource,
 107         .mem_resource   = &msc_mem_resource,
 108         .mem_offset     = 0x10000000UL,
 109         .io_offset      = 0x00000000UL,
 110 };
 111
 112 static int __init pcibios_init(void)
 113 {
 114         struct pci_controller *controller;
 115
 116         switch (mips_revision_corid) {
 117         case MIPS_REVISION_CORID_QED_RM5261:
 118         case MIPS_REVISION_CORID_CORE_LV:
 119         case MIPS_REVISION_CORID_CORE_FPGA:
 120         case MIPS_REVISION_CORID_CORE_FPGAR2:
 121                 /*
 122                  * Due to a bug in the Galileo system controller, we need
 123                  * to setup the PCI BAR for the Galileo internal registers.
 124                  * This should be done in the bios/bootprom and will be
 125                  * fixed in a later revision of YAMON (the MIPS boards
 126                  * boot prom).
 127                  */
 128                 GT_WRITE(GT_PCI0_CFGADDR_OFS,
 129                          (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
 130                          (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
 131                          (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
 132                          ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
 133                          GT_PCI0_CFGADDR_CONFIGEN_BIT );
 134
 135                 /* Perform the write */
 136                 GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
 137
 138                 controller = &gt64120_controller;
 139                 break;
 140
 141         case MIPS_REVISION_CORID_BONITO64:
 142         case MIPS_REVISION_CORID_CORE_20K:
 143         case MIPS_REVISION_CORID_CORE_EMUL_BON:
 144                 controller = &bonito64_controller;
 145                 break;
 146
 147         case MIPS_REVISION_CORID_CORE_MSC:
 148         case MIPS_REVISION_CORID_CORE_FPGA2:
 149         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 150                 controller = &msc_controller;
 151                 break;
 152         default:
 153                 return 1;
 154         }
 155
 156         ioport_resource.end = controller->io_resource->end;
 157
 158         register_pci_controller (controller);
 159
 160         return 0;
 161 }
 162
 163 early_initcall(pcibios_init);