arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/config.h>
  23 #include <linux/init.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/sched.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/time.h>
  29 #include <linux/timex.h>
  30 #include <linux/mc146818rtc.h>
  31
  32 #include <asm/mipsregs.h>
  33 #include <asm/ptrace.h>
  34 #include <asm/div64.h>
  35 #include <asm/cpu.h>
  36 #include <asm/time.h>
  37 #include <asm/mc146818-time.h>
  38
  39 #include <asm/mips-boards/generic.h>
  40 #include <asm/mips-boards/prom.h>
  41
  42 unsigned long cpu_khz;
  43
  44 #if defined(CONFIG_MIPS_SEAD)
  45 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5)
  46 #else
  47 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
  48 #endif
  49
  50 #if defined(CONFIG_MIPS_ATLAS)
  51 static char display_string[] = "        LINUX ON ATLAS       ";
  52 #endif
  53 #if defined(CONFIG_MIPS_MALTA)
  54 static char display_string[] = "        LINUX ON MALTA       ";
  55 #endif
  56 #if defined(CONFIG_MIPS_SEAD)
  57 static char display_string[] = "        LINUX ON SEAD       ";
  58 #endif
  59 static unsigned int display_count = 0;
  60 #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
  61
  62 #define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
  63
  64 static unsigned int timer_tick_count=0;
  65
  66 void mips_timer_interrupt(struct pt_regs *regs)
  67 {
  68         if ((timer_tick_count++ % HZ) == 0) {
  69                 mips_display_message(&display_string[display_count++]);
  70                 if (display_count == MAX_DISPLAY_COUNT)
  71                         display_count = 0;
  72
  73         }
  74
  75         ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs);
  76 }
  77
  78 /*
  79  * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
  80  */
  81 static unsigned int __init estimate_cpu_frequency(void)
  82 {
  83         unsigned int prid = read_c0_prid() & 0xffff00;
  84         unsigned int count;
  85
  86 #ifdef CONFIG_MIPS_SEAD
  87         /*
  88          * The SEAD board doesn't have a real time clock, so we can't
  89          * really calculate the timer frequency
  90          * For now we hardwire the SEAD board frequency to 12MHz.
  91          */
  92
  93         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
  94             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
  95                 count = 12000000;
  96         else
  97                 count = 6000000;
  98 #endif
  99 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 100         unsigned int flags;
 101
 102         local_irq_save(flags);
 103
 104         /* Start counter exactly on falling edge of update flag */
 105         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 106         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 107
 108         /* Start r4k counter. */
 109         write_c0_count(0);
 110
 111         /* Read counter exactly on falling edge of update flag */
 112         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 113         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 114
 115         count = read_c0_count();
 116
 117         /* restore interrupts */
 118         local_irq_restore(flags);
 119 #endif
 120
 121         mips_hpt_frequency = count;
 122         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 123             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 124                 count *= 2;
 125
 126         count += 5000;    /* round */
 127         count -= count%10000;
 128
 129         return count;
 130 }
 131
 132 unsigned long __init mips_rtc_get_time(void)
 133 {
 134         return mc146818_get_cmos_time();
 135 }
 136
 137 void __init mips_time_init(void)
 138 {
 139         unsigned int est_freq, flags;
 140
 141         local_irq_save(flags);
 142
 143 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 144         /* Set Data mode - binary. */
 145         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 146 #endif
 147
 148         est_freq = estimate_cpu_frequency ();
 149
 150         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 151                (est_freq%1000000)*100/1000000);
 152
 153         cpu_khz = est_freq / 1000;
 154
 155         local_irq_restore(flags);
 156 }
 157
 158 void __init mips_timer_setup(struct irqaction *irq)
 159 {
 160         /* we are using the cpu counter for timer interrupts */
 161         irq->handler = no_action;     /* we use our own handler */
 162         setup_irq(MIPS_CPU_TIMER_IRQ, irq);
 163
 164         /* to generate the first timer interrupt */
 165         write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
 166         set_c0_status(ALLINTS);
 167 }