2 * r2300.c: R2000 and R3000 specific mmu/cache code.
4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
6 * with a lot of changes to make this thing work for R3000s
7 * Tx39XX R4k style caches added. HK
8 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
16 #include <asm/cacheops.h>
18 #include <asm/pgtable.h>
19 #include <asm/mmu_context.h>
20 #include <asm/system.h>
21 #include <asm/isadep.h>
23 #include <asm/bootinfo.h>
26 /* For R3000 cores with R4000 style caches */
27 static unsigned long icache_size
, dcache_size
; /* Size in bytes */
29 #include <asm/r4kcache.h>
31 extern int r3k_have_wired_reg
; /* in r3k-tlb.c */
33 /* This sequence is required to ensure icache is disabled immediately */
34 #define TX39_STOP_STREAMING() \
35 __asm__ __volatile__( \
37 ".set noreorder\n\t" \
44 /* TX39H-style cache flush routines. */
45 static void tx39h_flush_icache_all(void)
47 unsigned long start
= KSEG0
;
48 unsigned long end
= (start
+ icache_size
);
49 unsigned long flags
, config
;
51 /* disable icache (set ICE#) */
52 local_irq_save(flags
);
53 config
= read_c0_conf();
54 write_c0_conf(config
& ~TX39_CONF_ICE
);
55 TX39_STOP_STREAMING();
57 /* invalidate icache */
59 cache16_unroll32(start
, Index_Invalidate_I
);
63 write_c0_conf(config
);
64 local_irq_restore(flags
);
67 static void tx39h_dma_cache_wback_inv(unsigned long addr
, unsigned long size
)
70 unsigned long dc_lsize
= current_cpu_data
.dcache
.linesz
;
72 /* Catch bad driver code */
76 a
= addr
& ~(dc_lsize
- 1);
77 end
= (addr
+ size
- 1) & ~(dc_lsize
- 1);
79 invalidate_dcache_line(a
); /* Hit_Invalidate_D */
87 static inline void tx39_blast_dcache_page(unsigned long addr
)
89 if (current_cpu_data
.cputype
!= CPU_TX3912
)
90 blast_dcache16_page(addr
);
93 static inline void tx39_blast_dcache_page_indexed(unsigned long addr
)
95 blast_dcache16_page_indexed(addr
);
98 static inline void tx39_blast_dcache(void)
103 static inline void tx39_blast_icache_page(unsigned long addr
)
105 unsigned long flags
, config
;
106 /* disable icache (set ICE#) */
107 local_irq_save(flags
);
108 config
= read_c0_conf();
109 write_c0_conf(config
& ~TX39_CONF_ICE
);
110 TX39_STOP_STREAMING();
111 blast_icache16_page(addr
);
112 write_c0_conf(config
);
113 local_irq_restore(flags
);
116 static inline void tx39_blast_icache_page_indexed(unsigned long addr
)
118 unsigned long flags
, config
;
119 /* disable icache (set ICE#) */
120 local_irq_save(flags
);
121 config
= read_c0_conf();
122 write_c0_conf(config
& ~TX39_CONF_ICE
);
123 TX39_STOP_STREAMING();
124 blast_icache16_page_indexed(addr
);
125 write_c0_conf(config
);
126 local_irq_restore(flags
);
129 static inline void tx39_blast_icache(void)
131 unsigned long flags
, config
;
132 /* disable icache (set ICE#) */
133 local_irq_save(flags
);
134 config
= read_c0_conf();
135 write_c0_conf(config
& ~TX39_CONF_ICE
);
136 TX39_STOP_STREAMING();
138 write_c0_conf(config
);
139 local_irq_restore(flags
);
142 static inline void tx39_flush_cache_all(void)
144 if (!cpu_has_dc_aliases
)
151 static inline void tx39___flush_cache_all(void)
157 static void tx39_flush_cache_mm(struct mm_struct
*mm
)
159 if (!cpu_has_dc_aliases
)
162 if (cpu_context(smp_processor_id(), mm
) != 0) {
163 tx39_flush_cache_all();
167 static void tx39_flush_cache_range(struct vm_area_struct
*vma
,
168 unsigned long start
, unsigned long end
)
170 struct mm_struct
*mm
= vma
->vm_mm
;
172 if (!cpu_has_dc_aliases
)
175 if (cpu_context(smp_processor_id(), mm
) != 0) {
181 static void tx39_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
, unsigned long pfn
)
183 int exec
= vma
->vm_flags
& VM_EXEC
;
184 struct mm_struct
*mm
= vma
->vm_mm
;
190 * If ownes no valid ASID yet, cannot possibly have gotten
191 * this page into the cache.
193 if (cpu_context(smp_processor_id(), mm
) == 0)
197 pgdp
= pgd_offset(mm
, page
);
198 pmdp
= pmd_offset(pgdp
, page
);
199 ptep
= pte_offset(pmdp
, page
);
202 * If the page isn't marked valid, the page cannot possibly be
205 if (!(pte_val(*ptep
) & _PAGE_PRESENT
))
209 * Doing flushes for another ASID than the current one is
210 * too difficult since stupid R4k caches do a TLB translation
211 * for every cache flush operation. So we do indexed flushes
212 * in that case, which doesn't overly flush the cache too much.
214 if ((mm
== current
->active_mm
) && (pte_val(*ptep
) & _PAGE_VALID
)) {
215 if (cpu_has_dc_aliases
|| exec
)
216 tx39_blast_dcache_page(page
);
218 tx39_blast_icache_page(page
);
224 * Do indexed flush, too much work to get the (possible) TLB refills
227 page
= (KSEG0
+ (page
& (dcache_size
- 1)));
228 if (cpu_has_dc_aliases
|| exec
)
229 tx39_blast_dcache_page_indexed(page
);
231 tx39_blast_icache_page_indexed(page
);
234 static void tx39_flush_data_cache_page(unsigned long addr
)
236 tx39_blast_dcache_page(addr
);
239 static void tx39_flush_icache_range(unsigned long start
, unsigned long end
)
241 unsigned long dc_lsize
= current_cpu_data
.dcache
.linesz
;
242 unsigned long addr
, aend
;
244 if (end
- start
> dcache_size
)
247 addr
= start
& ~(dc_lsize
- 1);
248 aend
= (end
- 1) & ~(dc_lsize
- 1);
251 /* Hit_Writeback_Inv_D */
252 protected_writeback_dcache_line(addr
);
259 if (end
- start
> icache_size
)
262 unsigned long flags
, config
;
263 addr
= start
& ~(dc_lsize
- 1);
264 aend
= (end
- 1) & ~(dc_lsize
- 1);
265 /* disable icache (set ICE#) */
266 local_irq_save(flags
);
267 config
= read_c0_conf();
268 write_c0_conf(config
& ~TX39_CONF_ICE
);
269 TX39_STOP_STREAMING();
271 /* Hit_Invalidate_I */
272 protected_flush_icache_line(addr
);
277 write_c0_conf(config
);
278 local_irq_restore(flags
);
283 * Ok, this seriously sucks. We use them to flush a user page but don't
284 * know the virtual address, so we have to blast away the whole icache
285 * which is significantly more expensive than the real thing. Otoh we at
286 * least know the kernel address of the page so we can flush it
289 static void tx39_flush_icache_page(struct vm_area_struct
*vma
, struct page
*page
)
293 * If there's no context yet, or the page isn't executable, no icache
296 if (!(vma
->vm_flags
& VM_EXEC
))
299 addr
= (unsigned long) page_address(page
);
300 tx39_blast_dcache_page(addr
);
303 * We're not sure of the virtual address(es) involved here, so
304 * we have to flush the entire I-cache.
309 static void tx39_dma_cache_wback_inv(unsigned long addr
, unsigned long size
)
311 unsigned long end
, a
;
313 if (((size
| addr
) & (PAGE_SIZE
- 1)) == 0) {
316 tx39_blast_dcache_page(addr
);
318 } while(addr
!= end
);
319 } else if (size
> dcache_size
) {
322 unsigned long dc_lsize
= current_cpu_data
.dcache
.linesz
;
323 a
= addr
& ~(dc_lsize
- 1);
324 end
= (addr
+ size
- 1) & ~(dc_lsize
- 1);
326 flush_dcache_line(a
); /* Hit_Writeback_Inv_D */
333 static void tx39_dma_cache_inv(unsigned long addr
, unsigned long size
)
335 unsigned long end
, a
;
337 if (((size
| addr
) & (PAGE_SIZE
- 1)) == 0) {
340 tx39_blast_dcache_page(addr
);
342 } while(addr
!= end
);
343 } else if (size
> dcache_size
) {
346 unsigned long dc_lsize
= current_cpu_data
.dcache
.linesz
;
347 a
= addr
& ~(dc_lsize
- 1);
348 end
= (addr
+ size
- 1) & ~(dc_lsize
- 1);
350 invalidate_dcache_line(a
); /* Hit_Invalidate_D */
357 static void tx39_flush_cache_sigtramp(unsigned long addr
)
359 unsigned long ic_lsize
= current_cpu_data
.icache
.linesz
;
360 unsigned long dc_lsize
= current_cpu_data
.dcache
.linesz
;
361 unsigned long config
;
364 protected_writeback_dcache_line(addr
& ~(dc_lsize
- 1));
366 /* disable icache (set ICE#) */
367 local_irq_save(flags
);
368 config
= read_c0_conf();
369 write_c0_conf(config
& ~TX39_CONF_ICE
);
370 TX39_STOP_STREAMING();
371 protected_flush_icache_line(addr
& ~(ic_lsize
- 1));
372 write_c0_conf(config
);
373 local_irq_restore(flags
);
376 static __init
void tx39_probe_cache(void)
378 unsigned long config
;
380 config
= read_c0_conf();
382 icache_size
= 1 << (10 + ((config
& TX39_CONF_ICS_MASK
) >>
383 TX39_CONF_ICS_SHIFT
));
384 dcache_size
= 1 << (10 + ((config
& TX39_CONF_DCS_MASK
) >>
385 TX39_CONF_DCS_SHIFT
));
387 current_cpu_data
.icache
.linesz
= 16;
388 switch (current_cpu_data
.cputype
) {
390 current_cpu_data
.icache
.ways
= 1;
391 current_cpu_data
.dcache
.ways
= 1;
392 current_cpu_data
.dcache
.linesz
= 4;
396 current_cpu_data
.icache
.ways
= 2;
397 current_cpu_data
.dcache
.ways
= 2;
398 current_cpu_data
.dcache
.linesz
= 16;
403 current_cpu_data
.icache
.ways
= 1;
404 current_cpu_data
.dcache
.ways
= 1;
405 current_cpu_data
.dcache
.linesz
= 16;
410 void __init
ld_mmu_tx39(void)
412 extern void build_clear_page(void);
413 extern void build_copy_page(void);
414 unsigned long config
;
416 config
= read_c0_conf();
417 config
&= ~TX39_CONF_WBON
;
418 write_c0_conf(config
);
422 switch (current_cpu_data
.cputype
) {
424 /* TX39/H core (writethru direct-map cache) */
425 flush_cache_all
= tx39h_flush_icache_all
;
426 __flush_cache_all
= tx39h_flush_icache_all
;
427 flush_cache_mm
= (void *) tx39h_flush_icache_all
;
428 flush_cache_range
= (void *) tx39h_flush_icache_all
;
429 flush_cache_page
= (void *) tx39h_flush_icache_all
;
430 flush_icache_page
= (void *) tx39h_flush_icache_all
;
431 flush_icache_range
= (void *) tx39h_flush_icache_all
;
433 flush_cache_sigtramp
= (void *) tx39h_flush_icache_all
;
434 flush_data_cache_page
= (void *) tx39h_flush_icache_all
;
436 _dma_cache_wback_inv
= tx39h_dma_cache_wback_inv
;
438 shm_align_mask
= PAGE_SIZE
- 1;
445 /* TX39/H2,H3 core (writeback 2way-set-associative cache) */
446 r3k_have_wired_reg
= 1;
447 write_c0_wired(0); /* set 8 on reset... */
448 /* board-dependent init code may set WBON */
450 flush_cache_all
= tx39_flush_cache_all
;
451 __flush_cache_all
= tx39___flush_cache_all
;
452 flush_cache_mm
= tx39_flush_cache_mm
;
453 flush_cache_range
= tx39_flush_cache_range
;
454 flush_cache_page
= tx39_flush_cache_page
;
455 flush_icache_page
= tx39_flush_icache_page
;
456 flush_icache_range
= tx39_flush_icache_range
;
458 flush_cache_sigtramp
= tx39_flush_cache_sigtramp
;
459 flush_data_cache_page
= tx39_flush_data_cache_page
;
461 _dma_cache_wback_inv
= tx39_dma_cache_wback_inv
;
462 _dma_cache_wback
= tx39_dma_cache_wback_inv
;
463 _dma_cache_inv
= tx39_dma_cache_inv
;
465 shm_align_mask
= max_t(unsigned long,
466 (dcache_size
/ current_cpu_data
.dcache
.ways
) - 1,
472 current_cpu_data
.icache
.waysize
= icache_size
/ current_cpu_data
.icache
.ways
;
473 current_cpu_data
.dcache
.waysize
= dcache_size
/ current_cpu_data
.dcache
.ways
;
475 current_cpu_data
.icache
.sets
=
476 current_cpu_data
.icache
.waysize
/ current_cpu_data
.icache
.linesz
;
477 current_cpu_data
.dcache
.sets
=
478 current_cpu_data
.dcache
.waysize
/ current_cpu_data
.dcache
.linesz
;
480 if (current_cpu_data
.dcache
.waysize
> PAGE_SIZE
)
481 current_cpu_data
.dcache
.flags
|= MIPS_CACHE_ALIASES
;
483 current_cpu_data
.icache
.waybit
= 0;
484 current_cpu_data
.dcache
.waybit
= 0;
486 printk("Primary instruction cache %ldkB, linesize %d bytes\n",
487 icache_size
>> 10, current_cpu_data
.icache
.linesz
);
488 printk("Primary data cache %ldkB, linesize %d bytes\n",
489 dcache_size
>> 10, current_cpu_data
.dcache
.linesz
);