| blob | 5a7a64e91fc5eddcb2cff1d1cc14d24e9a53981d |
1 /*
2 * arch/ppc/kernel/except_8xx.S
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications by Dan Malek
12 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 *
14 * This file contains low-level support and setup for PowerPC 8xx
15 * embedded processors, including trap and interrupt dispatch.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
24 #include <linux/config.h>
25 #include <asm/processor.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/cache.h>
29 #include <asm/pgtable.h>
30 #include <asm/cputable.h>
31 #include <asm/thread_info.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/offsets.h>
35 /* Macro to make the code more readable. */
36 #ifdef CONFIG_8xx_CPU6
37 #define DO_8xx_CPU6(val, reg) \
38 li reg, val; \
39 stw reg, 12(r0); \
40 lwz reg, 12(r0);
41 #else
42 #define DO_8xx_CPU6(val, reg)
43 #endif
44 .text
45 .globl _stext
46 _stext:
47 .text
48 .globl _start
49 _start:
51 /* MPC8xx
52 * This port was done on an MBX board with an 860. Right now I only
53 * support an ELF compressed (zImage) boot from EPPC-Bug because the
54 * code there loads up some registers before calling us:
55 * r3: ptr to board info data
56 * r4: initrd_start or if no initrd then 0
57 * r5: initrd_end - unused if r4 is 0
58 * r6: Start of command line string
59 * r7: End of command line string
60 *
61 * I decided to use conditional compilation instead of checking PVR and
62 * adding more processor specific branches around code I don't need.
63 * Since this is an embedded processor, I also appreciate any memory
64 * savings I can get.
65 *
66 * The MPC8xx does not have any BATs, but it supports large page sizes.
67 * We first initialize the MMU to support 8M byte pages, then load one
68 * entry into each of the instruction and data TLBs to map the first
69 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
70 * the "internal" processor registers before MMU_init is called.
71 *
72 * The TLB code currently contains a major hack. Since I use the condition
73 * code register, I have to save and restore it. I am out of registers, so
74 * I just store it in memory location 0 (the TLB handlers are not reentrant).
75 * To avoid making any decisions, I need to use the "segment" valid bit
76 * in the first level table, but that would require many changes to the
77 * Linux page directory/table functions that I don't want to do right now.
78 *
79 * I used to use SPRG2 for a temporary register in the TLB handler, but it
80 * has since been put to other uses. I now use a hack to save a register
81 * and the CCR at memory location 0.....Someday I'll fix this.....
82 * -- Dan
83 */
84 .globl __start
85 __start:
86 mr r31,r3 /* save parameters */
87 mr r30,r4
88 mr r29,r5
89 mr r28,r6
90 mr r27,r7
92 /* We have to turn on the MMU right away so we get cache modes
93 * set correctly.
94 */
95 bl initial_mmu
97 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
98 * ready to work.
99 */
101 turn_on_mmu:
102 mfmsr r0
103 ori r0,r0,MSR_DR|MSR_IR
104 mtspr SPRN_SRR1,r0
105 lis r0,start_here@h
106 ori r0,r0,start_here@l
107 mtspr SPRN_SRR0,r0
108 SYNC
109 rfi /* enables MMU */
111 /*
112 * Exception entry code. This code runs with address translation
113 * turned off, i.e. using physical addresses.
114 * We assume sprg3 has the physical address of the current
115 * task's thread_struct.
116 */
117 #define EXCEPTION_PROLOG \
118 mtspr SPRN_SPRG0,r10; \
119 mtspr SPRN_SPRG1,r11; \
120 mfcr r10; \
121 EXCEPTION_PROLOG_1; \
122 EXCEPTION_PROLOG_2
124 #define EXCEPTION_PROLOG_1 \
125 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
126 andi. r11,r11,MSR_PR; \
127 tophys(r11,r1); /* use tophys(r1) if kernel */ \
128 beq 1f; \
129 mfspr r11,SPRN_SPRG3; \
130 lwz r11,THREAD_INFO-THREAD(r11); \
131 addi r11,r11,THREAD_SIZE; \
132 tophys(r11,r11); \
133 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
136 #define EXCEPTION_PROLOG_2 \
137 CLR_TOP32(r11); \
138 stw r10,_CCR(r11); /* save registers */ \
139 stw r12,GPR12(r11); \
140 stw r9,GPR9(r11); \
141 mfspr r10,SPRN_SPRG0; \
142 stw r10,GPR10(r11); \
143 mfspr r12,SPRN_SPRG1; \
144 stw r12,GPR11(r11); \
145 mflr r10; \
146 stw r10,_LINK(r11); \
147 mfspr r12,SPRN_SRR0; \
148 mfspr r9,SPRN_SRR1; \
149 stw r1,GPR1(r11); \
150 stw r1,0(r11); \
151 tovirt(r1,r11); /* set new kernel sp */ \
152 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
153 MTMSRD(r10); /* (except for mach check in rtas) */ \
154 stw r0,GPR0(r11); \
155 SAVE_4GPRS(3, r11); \
156 SAVE_2GPRS(7, r11)
158 /*
159 * Note: code which follows this uses cr0.eq (set if from kernel),
160 * r11, r12 (SRR0), and r9 (SRR1).
161 *
162 * Note2: once we have set r1 we are in a position to take exceptions
163 * again, and we could thus set MSR:RI at that point.
164 */
166 /*
167 * Exception vectors.
168 */
169 #define EXCEPTION(n, label, hdlr, xfer) \
170 . = n; \
171 label: \
172 EXCEPTION_PROLOG; \
173 addi r3,r1,STACK_FRAME_OVERHEAD; \
174 xfer(n, hdlr)
176 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
177 li r10,trap; \
178 stw r10,TRAP(r11); \
179 li r10,MSR_KERNEL; \
180 copyee(r10, r9); \
181 bl tfer; \
182 i##n: \
183 .long hdlr; \
184 .long ret
186 #define COPY_EE(d, s) rlwimi d,s,0,16,16
187 #define NOCOPY(d, s)
189 #define EXC_XFER_STD(n, hdlr) \
190 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
191 ret_from_except_full)
193 #define EXC_XFER_LITE(n, hdlr) \
194 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
195 ret_from_except)
197 #define EXC_XFER_EE(n, hdlr) \
198 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
199 ret_from_except_full)
201 #define EXC_XFER_EE_LITE(n, hdlr) \
202 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
203 ret_from_except)
205 /* System reset */
206 EXCEPTION(0x100, Reset, UnknownException, EXC_XFER_STD)
208 /* Machine check */
209 . = 0x200
210 MachineCheck:
211 EXCEPTION_PROLOG
212 mfspr r4,SPRN_DAR
213 stw r4,_DAR(r11)
214 mfspr r5,SPRN_DSISR
215 stw r5,_DSISR(r11)
216 addi r3,r1,STACK_FRAME_OVERHEAD
217 EXC_XFER_STD(0x200, MachineCheckException)
219 /* Data access exception.
220 * This is "never generated" by the MPC8xx. We jump to it for other
221 * translation errors.
222 */
223 . = 0x300
224 DataAccess:
225 EXCEPTION_PROLOG
226 mfspr r10,SPRN_DSISR
227 stw r10,_DSISR(r11)
228 mr r5,r10
229 mfspr r4,SPRN_DAR
230 EXC_XFER_EE_LITE(0x300, handle_page_fault)
232 /* Instruction access exception.
233 * This is "never generated" by the MPC8xx. We jump to it for other
234 * translation errors.
235 */
236 . = 0x400
237 InstructionAccess:
238 EXCEPTION_PROLOG
239 mr r4,r12
240 mr r5,r9
241 EXC_XFER_EE_LITE(0x400, handle_page_fault)
243 /* External interrupt */
244 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
246 /* Alignment exception */
247 . = 0x600
248 Alignment:
249 EXCEPTION_PROLOG
250 mfspr r4,SPRN_DAR
251 stw r4,_DAR(r11)
252 mfspr r5,SPRN_DSISR
253 stw r5,_DSISR(r11)
254 addi r3,r1,STACK_FRAME_OVERHEAD
255 EXC_XFER_EE(0x600, AlignmentException)
257 /* Program check exception */
258 EXCEPTION(0x700, ProgramCheck, ProgramCheckException, EXC_XFER_STD)
260 /* No FPU on MPC8xx. This exception is not supposed to happen.
261 */
262 EXCEPTION(0x800, FPUnavailable, UnknownException, EXC_XFER_STD)
264 /* Decrementer */
265 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
267 EXCEPTION(0xa00, Trap_0a, UnknownException, EXC_XFER_EE)
268 EXCEPTION(0xb00, Trap_0b, UnknownException, EXC_XFER_EE)
270 /* System call */
271 . = 0xc00
272 SystemCall:
273 EXCEPTION_PROLOG
274 EXC_XFER_EE_LITE(0xc00, DoSyscall)
276 /* Single step - not used on 601 */
277 EXCEPTION(0xd00, SingleStep, SingleStepException, EXC_XFER_STD)
278 EXCEPTION(0xe00, Trap_0e, UnknownException, EXC_XFER_EE)
279 EXCEPTION(0xf00, Trap_0f, UnknownException, EXC_XFER_EE)
281 /* On the MPC8xx, this is a software emulation interrupt. It occurs
282 * for all unimplemented and illegal instructions.
283 */
284 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
286 . = 0x1100
287 /*
288 * For the MPC8xx, this is a software tablewalk to load the instruction
289 * TLB. It is modelled after the example in the Motorola manual. The task
290 * switch loads the M_TWB register with the pointer to the first level table.
291 * If we discover there is no second level table (the value is zero), the
292 * plan was to load that into the TLB, which causes another fault into the
293 * TLB Error interrupt where we can handle such problems. However, that did
294 * not work, so if we discover there is no second level table, we restore
295 * registers and branch to the error exception. We have to use the MD_xxx
296 * registers for the tablewalk because the equivalent MI_xxx registers
297 * only perform the attribute functions.
298 */
299 InstructionTLBMiss:
300 #ifdef CONFIG_8xx_CPU6
301 stw r3, 8(r0)
302 #endif
303 DO_8xx_CPU6(0x3f80, r3)
304 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
305 mfcr r10
306 stw r10, 0(r0)
307 stw r11, 4(r0)
308 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
309 DO_8xx_CPU6(0x3780, r3)
310 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
311 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
313 /* If we are faulting a kernel address, we have to use the
314 * kernel page tables.
315 */
316 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
317 beq 3f
318 lis r11, swapper_pg_dir@h
319 ori r11, r11, swapper_pg_dir@l
320 rlwimi r10, r11, 0, 2, 19
321 3:
322 lwz r11, 0(r10) /* Get the level 1 entry */
323 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
324 beq 2f /* If zero, don't try to find a pte */
326 /* We have a pte table, so load the MI_TWC with the attributes
327 * for this "segment."
328 */
329 ori r11,r11,1 /* Set valid bit */
330 DO_8xx_CPU6(0x2b80, r3)
331 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
332 DO_8xx_CPU6(0x3b80, r3)
333 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
334 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
335 lwz r10, 0(r11) /* Get the pte */
337 ori r10, r10, _PAGE_ACCESSED
338 stw r10, 0(r11)
340 /* The Linux PTE won't go exactly into the MMU TLB.
341 * Software indicator bits 21, 22 and 28 must be clear.
342 * Software indicator bits 24, 25, 26, and 27 must be
343 * set. All other Linux PTE bits control the behavior
344 * of the MMU.
345 */
346 2: li r11, 0x00f0
347 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
348 DO_8xx_CPU6(0x2d80, r3)
349 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
351 mfspr r10, SPRN_M_TW /* Restore registers */
352 lwz r11, 0(r0)
353 mtcr r11
354 lwz r11, 4(r0)
355 #ifdef CONFIG_8xx_CPU6
356 lwz r3, 8(r0)
357 #endif
358 rfi
360 . = 0x1200
361 DataStoreTLBMiss:
362 #ifdef CONFIG_8xx_CPU6
363 stw r3, 8(r0)
364 #endif
365 DO_8xx_CPU6(0x3f80, r3)
366 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
367 mfcr r10
368 stw r10, 0(r0)
369 stw r11, 4(r0)
370 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
372 /* If we are faulting a kernel address, we have to use the
373 * kernel page tables.
374 */
375 andi. r11, r10, 0x0800
376 beq 3f
377 lis r11, swapper_pg_dir@h
378 ori r11, r11, swapper_pg_dir@l
379 rlwimi r10, r11, 0, 2, 19
380 3:
381 lwz r11, 0(r10) /* Get the level 1 entry */
382 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
383 beq 2f /* If zero, don't try to find a pte */
385 /* We have a pte table, so load fetch the pte from the table.
386 */
387 ori r11, r11, 1 /* Set valid bit in physical L2 page */
388 DO_8xx_CPU6(0x3b80, r3)
389 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
390 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
391 lwz r10, 0(r10) /* Get the pte */
393 /* Insert the Guarded flag into the TWC from the Linux PTE.
394 * It is bit 27 of both the Linux PTE and the TWC (at least
395 * I got that right :-). It will be better when we can put
396 * this into the Linux pgd/pmd and load it in the operation
397 * above.
398 */
399 rlwimi r11, r10, 0, 27, 27
400 DO_8xx_CPU6(0x3b80, r3)
401 mtspr SPRN_MD_TWC, r11
403 mfspr r11, SPRN_MD_TWC /* get the pte address again */
404 ori r10, r10, _PAGE_ACCESSED
405 stw r10, 0(r11)
407 /* The Linux PTE won't go exactly into the MMU TLB.
408 * Software indicator bits 21, 22 and 28 must be clear.
409 * Software indicator bits 24, 25, 26, and 27 must be
410 * set. All other Linux PTE bits control the behavior
411 * of the MMU.
412 */
413 2: li r11, 0x00f0
414 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
415 DO_8xx_CPU6(0x3d80, r3)
416 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
418 mfspr r10, SPRN_M_TW /* Restore registers */
419 lwz r11, 0(r0)
420 mtcr r11
421 lwz r11, 4(r0)
422 #ifdef CONFIG_8xx_CPU6
423 lwz r3, 8(r0)
424 #endif
425 rfi
427 /* This is an instruction TLB error on the MPC8xx. This could be due
428 * to many reasons, such as executing guarded memory or illegal instruction
429 * addresses. There is nothing to do but handle a big time error fault.
430 */
431 . = 0x1300
432 InstructionTLBError:
433 b InstructionAccess
435 /* This is the data TLB error on the MPC8xx. This could be due to
436 * many reasons, including a dirty update to a pte. We can catch that
437 * one here, but anything else is an error. First, we track down the
438 * Linux pte. If it is valid, write access is allowed, but the
439 * page dirty bit is not set, we will set it and reload the TLB. For
440 * any other case, we bail out to a higher level function that can
441 * handle it.
442 */
443 . = 0x1400
444 DataTLBError:
445 #ifdef CONFIG_8xx_CPU6
446 stw r3, 8(r0)
447 #endif
448 DO_8xx_CPU6(0x3f80, r3)
449 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
450 mfcr r10
451 stw r10, 0(r0)
452 stw r11, 4(r0)
454 /* First, make sure this was a store operation.
455 */
456 mfspr r10, SPRN_DSISR
457 andis. r11, r10, 0x0200 /* If set, indicates store op */
458 beq 2f
460 /* The EA of a data TLB miss is automatically stored in the MD_EPN
461 * register. The EA of a data TLB error is automatically stored in
462 * the DAR, but not the MD_EPN register. We must copy the 20 most
463 * significant bits of the EA from the DAR to MD_EPN before we
464 * start walking the page tables. We also need to copy the CASID
465 * value from the M_CASID register.
466 * Addendum: The EA of a data TLB error is _supposed_ to be stored
467 * in DAR, but it seems that this doesn't happen in some cases, such
468 * as when the error is due to a dcbi instruction to a page with a
469 * TLB that doesn't have the changed bit set. In such cases, there
470 * does not appear to be any way to recover the EA of the error
471 * since it is neither in DAR nor MD_EPN. As a workaround, the
472 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
473 * are initialized in mapin_ram(). This will avoid the problem,
474 * assuming we only use the dcbi instruction on kernel addresses.
475 */
476 mfspr r10, SPRN_DAR
477 rlwinm r11, r10, 0, 0, 19
478 ori r11, r11, MD_EVALID
479 mfspr r10, SPRN_M_CASID
480 rlwimi r11, r10, 0, 28, 31
481 DO_8xx_CPU6(0x3780, r3)
482 mtspr SPRN_MD_EPN, r11
484 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
486 /* If we are faulting a kernel address, we have to use the
487 * kernel page tables.
488 */
489 andi. r11, r10, 0x0800
490 beq 3f
491 lis r11, swapper_pg_dir@h
492 ori r11, r11, swapper_pg_dir@l
493 rlwimi r10, r11, 0, 2, 19
494 3:
495 lwz r11, 0(r10) /* Get the level 1 entry */
496 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
497 beq 2f /* If zero, bail */
499 /* We have a pte table, so fetch the pte from the table.
500 */
501 ori r11, r11, 1 /* Set valid bit in physical L2 page */
502 DO_8xx_CPU6(0x3b80, r3)
503 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
504 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
505 lwz r10, 0(r11) /* Get the pte */
507 andi. r11, r10, _PAGE_RW /* Is it writeable? */
508 beq 2f /* Bail out if not */
510 /* Update 'changed', among others.
511 */
512 ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
513 mfspr r11, SPRN_MD_TWC /* Get pte address again */
514 stw r10, 0(r11) /* and update pte in table */
516 /* The Linux PTE won't go exactly into the MMU TLB.
517 * Software indicator bits 21, 22 and 28 must be clear.
518 * Software indicator bits 24, 25, 26, and 27 must be
519 * set. All other Linux PTE bits control the behavior
520 * of the MMU.
521 */
522 li r11, 0x00f0
523 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
524 DO_8xx_CPU6(0x3d80, r3)
525 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
527 mfspr r10, SPRN_M_TW /* Restore registers */
528 lwz r11, 0(r0)
529 mtcr r11
530 lwz r11, 4(r0)
531 #ifdef CONFIG_8xx_CPU6
532 lwz r3, 8(r0)
533 #endif
534 rfi
535 2:
536 mfspr r10, SPRN_M_TW /* Restore registers */
537 lwz r11, 0(r0)
538 mtcr r11
539 lwz r11, 4(r0)
540 #ifdef CONFIG_8xx_CPU6
541 lwz r3, 8(r0)
542 #endif
543 b DataAccess
545 EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE)
546 EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE)
547 EXCEPTION(0x1700, Trap_17, UnknownException, EXC_XFER_EE)
548 EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE)
549 EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE)
550 EXCEPTION(0x1a00, Trap_1a, UnknownException, EXC_XFER_EE)
551 EXCEPTION(0x1b00, Trap_1b, UnknownException, EXC_XFER_EE)
553 /* On the MPC8xx, these next four traps are used for development
554 * support of breakpoints and such. Someday I will get around to
555 * using them.
556 */
557 EXCEPTION(0x1c00, Trap_1c, UnknownException, EXC_XFER_EE)
558 EXCEPTION(0x1d00, Trap_1d, UnknownException, EXC_XFER_EE)
559 EXCEPTION(0x1e00, Trap_1e, UnknownException, EXC_XFER_EE)
560 EXCEPTION(0x1f00, Trap_1f, UnknownException, EXC_XFER_EE)
562 . = 0x2000
564 .globl giveup_fpu
565 giveup_fpu:
566 blr
568 /*
569 * This is where the main kernel code starts.
570 */
571 start_here:
572 /* ptr to current */
573 lis r2,init_task@h
574 ori r2,r2,init_task@l
576 /* ptr to phys current thread */
577 tophys(r4,r2)
578 addi r4,r4,THREAD /* init task's THREAD */
579 mtspr SPRN_SPRG3,r4
580 li r3,0
581 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
583 /* stack */
584 lis r1,init_thread_union@ha
585 addi r1,r1,init_thread_union@l
586 li r0,0
587 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
589 bl early_init /* We have to do this with MMU on */
591 /*
592 * Decide what sort of machine this is and initialize the MMU.
593 */
594 mr r3,r31
595 mr r4,r30
596 mr r5,r29
597 mr r6,r28
598 mr r7,r27
599 bl machine_init
600 bl MMU_init
602 /*
603 * Go back to running unmapped so we can load up new values
604 * and change to using our exception vectors.
605 * On the 8xx, all we have to do is invalidate the TLB to clear
606 * the old 8M byte TLB mappings and load the page table base register.
607 */
608 /* The right way to do this would be to track it down through
609 * init's THREAD like the context switch code does, but this is
610 * easier......until someone changes init's static structures.
611 */
612 lis r6, swapper_pg_dir@h
613 ori r6, r6, swapper_pg_dir@l
614 tophys(r6,r6)
615 #ifdef CONFIG_8xx_CPU6
616 lis r4, cpu6_errata_word@h
617 ori r4, r4, cpu6_errata_word@l
618 li r3, 0x3980
619 stw r3, 12(r4)
620 lwz r3, 12(r4)
621 #endif
622 mtspr SPRN_M_TWB, r6
623 lis r4,2f@h
624 ori r4,r4,2f@l
625 tophys(r4,r4)
626 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
627 mtspr SPRN_SRR0,r4
628 mtspr SPRN_SRR1,r3
629 rfi
630 /* Load up the kernel context */
631 2:
632 SYNC /* Force all PTE updates to finish */
633 tlbia /* Clear all TLB entries */
634 sync /* wait for tlbia/tlbie to finish */
635 TLBSYNC /* ... on all CPUs */
637 /* set up the PTE pointers for the Abatron bdiGDB.
638 */
639 tovirt(r6,r6)
640 lis r5, abatron_pteptrs@h
641 ori r5, r5, abatron_pteptrs@l
642 stw r5, 0xf0(r0) /* Must match your Abatron config file */
643 tophys(r5,r5)
644 stw r6, 0(r5)
646 /* Now turn on the MMU for real! */
647 li r4,MSR_KERNEL
648 lis r3,start_kernel@h
649 ori r3,r3,start_kernel@l
650 mtspr SPRN_SRR0,r3
651 mtspr SPRN_SRR1,r4
652 rfi /* enable MMU and jump to start_kernel */
654 /* Set up the initial MMU state so we can do the first level of
655 * kernel initialization. This maps the first 8 MBytes of memory 1:1
656 * virtual to physical. Also, set the cache mode since that is defined
657 * by TLB entries and perform any additional mapping (like of the IMMR).
658 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
659 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
660 * these mappings is mapped by page tables.
661 */
662 initial_mmu:
663 tlbia /* Invalidate all TLB entries */
664 #ifdef CONFIG_PIN_TLB
665 lis r8, MI_RSV4I@h
666 ori r8, r8, 0x1c00
667 #else
668 li r8, 0
669 #endif
670 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
672 #ifdef CONFIG_PIN_TLB
673 lis r10, (MD_RSV4I | MD_RESETVAL)@h
674 ori r10, r10, 0x1c00
675 mr r8, r10
676 #else
677 lis r10, MD_RESETVAL@h
678 #endif
679 #ifndef CONFIG_8xx_COPYBACK
680 oris r10, r10, MD_WTDEF@h
681 #endif
682 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
684 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
685 * we can load the instruction and data TLB registers with the
686 * same values.
687 */
688 lis r8, KERNELBASE@h /* Create vaddr for TLB */
689 ori r8, r8, MI_EVALID /* Mark it valid */
690 mtspr SPRN_MI_EPN, r8
691 mtspr SPRN_MD_EPN, r8
692 li r8, MI_PS8MEG /* Set 8M byte page */
693 ori r8, r8, MI_SVALID /* Make it valid */
694 mtspr SPRN_MI_TWC, r8
695 mtspr SPRN_MD_TWC, r8
696 li r8, MI_BOOTINIT /* Create RPN for address 0 */
697 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
698 mtspr SPRN_MD_RPN, r8
699 lis r8, MI_Kp@h /* Set the protection mode */
700 mtspr SPRN_MI_AP, r8
701 mtspr SPRN_MD_AP, r8
703 /* Map another 8 MByte at the IMMR to get the processor
704 * internal registers (among other things).
705 */
706 #ifdef CONFIG_PIN_TLB
707 addi r10, r10, 0x0100
708 mtspr SPRN_MD_CTR, r10
709 #endif
710 mfspr r9, 638 /* Get current IMMR */
711 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
713 mr r8, r9 /* Create vaddr for TLB */
714 ori r8, r8, MD_EVALID /* Mark it valid */
715 mtspr SPRN_MD_EPN, r8
716 li r8, MD_PS8MEG /* Set 8M byte page */
717 ori r8, r8, MD_SVALID /* Make it valid */
718 mtspr SPRN_MD_TWC, r8
719 mr r8, r9 /* Create paddr for TLB */
720 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
721 mtspr SPRN_MD_RPN, r8
723 #ifdef CONFIG_PIN_TLB
724 /* Map two more 8M kernel data pages.
725 */
726 addi r10, r10, 0x0100
727 mtspr SPRN_MD_CTR, r10
729 lis r8, KERNELBASE@h /* Create vaddr for TLB */
730 addis r8, r8, 0x0080 /* Add 8M */
731 ori r8, r8, MI_EVALID /* Mark it valid */
732 mtspr SPRN_MD_EPN, r8
733 li r9, MI_PS8MEG /* Set 8M byte page */
734 ori r9, r9, MI_SVALID /* Make it valid */
735 mtspr SPRN_MD_TWC, r9
736 li r11, MI_BOOTINIT /* Create RPN for address 0 */
737 addis r11, r11, 0x0080 /* Add 8M */
738 mtspr SPRN_MD_RPN, r8
740 addis r8, r8, 0x0080 /* Add 8M */
741 mtspr SPRN_MD_EPN, r8
742 mtspr SPRN_MD_TWC, r9
743 addis r11, r11, 0x0080 /* Add 8M */
744 mtspr SPRN_MD_RPN, r8
745 #endif
747 /* Since the cache is enabled according to the information we
748 * just loaded into the TLB, invalidate and enable the caches here.
749 * We should probably check/set other modes....later.
750 */
751 lis r8, IDC_INVALL@h
752 mtspr SPRN_IC_CST, r8
753 mtspr SPRN_DC_CST, r8
754 lis r8, IDC_ENABLE@h
755 mtspr SPRN_IC_CST, r8
756 #ifdef CONFIG_8xx_COPYBACK
757 mtspr SPRN_DC_CST, r8
758 #else
759 /* For a debug option, I left this here to easily enable
760 * the write through cache mode
761 */
762 lis r8, DC_SFWT@h
763 mtspr SPRN_DC_CST, r8
764 lis r8, IDC_ENABLE@h
765 mtspr SPRN_DC_CST, r8
766 #endif
767 blr
770 /*
771 * Set up to use a given MMU context.
772 * r3 is context number, r4 is PGD pointer.
773 *
774 * We place the physical address of the new task page directory loaded
775 * into the MMU base register, and set the ASID compare register with
776 * the new "context."
777 */
778 _GLOBAL(set_context)
780 #ifdef CONFIG_BDI_SWITCH
781 /* Context switch the PTE pointer for the Abatron BDI2000.
782 * The PGDIR is passed as second argument.
783 */
784 lis r5, KERNELBASE@h
785 lwz r5, 0xf0(r5)
786 stw r4, 0x4(r5)
787 #endif
789 #ifdef CONFIG_8xx_CPU6
790 lis r6, cpu6_errata_word@h
791 ori r6, r6, cpu6_errata_word@l
792 tophys (r4, r4)
793 li r7, 0x3980
794 stw r7, 12(r6)
795 lwz r7, 12(r6)
796 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
797 li r7, 0x3380
798 stw r7, 12(r6)
799 lwz r7, 12(r6)
800 mtspr SPRN_M_CASID, r3 /* Update context */
801 #else
802 mtspr SPRN_M_CASID,r3 /* Update context */
803 tophys (r4, r4)
804 mtspr SPRN_M_TWB, r4 /* and pgd */
805 #endif
806 SYNC
807 blr
809 #ifdef CONFIG_8xx_CPU6
810 /* It's here because it is unique to the 8xx.
811 * It is important we get called with interrupts disabled. I used to
812 * do that, but it appears that all code that calls this already had
813 * interrupt disabled.
814 */
815 .globl set_dec_cpu6
816 set_dec_cpu6:
817 lis r7, cpu6_errata_word@h
818 ori r7, r7, cpu6_errata_word@l
819 li r4, 0x2c00
820 stw r4, 8(r7)
821 lwz r4, 8(r7)
822 mtspr 22, r3 /* Update Decrementer */
823 SYNC
824 blr
825 #endif
827 /*
828 * We put a few things here that have to be page-aligned.
829 * This stuff goes at the beginning of the data segment,
830 * which is page-aligned.
831 */
832 .data
833 .globl sdata
834 sdata:
835 .globl empty_zero_page
836 empty_zero_page:
837 .space 4096
839 .globl swapper_pg_dir
840 swapper_pg_dir:
841 .space 4096
843 /*
844 * This space gets a copy of optional info passed to us by the bootstrap
845 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
846 */
847 .globl cmd_line
848 cmd_line:
849 .space 512
851 /* Room for two PTE table poiners, usually the kernel and current user
852 * pointer to their respective root page table (pgdir).
853 */
854 abatron_pteptrs:
855 .space 8
857 #ifdef CONFIG_8xx_CPU6
858 .globl cpu6_errata_word
859 cpu6_errata_word:
860 .space 16
861 #endif