arch/ppc/platforms/4xx/ocotea.c

   1 /*
   2  * arch/ppc/platforms/4xx/ocotea.c
   3  *
   4  * Ocotea board specific routines
   5  *
   6  * Matt Porter <mporter@kernel.crashing.org>
   7  *
   8  * Copyright 2003-2005 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/types.h>
  25 #include <linux/major.h>
  26 #include <linux/blkdev.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/ide.h>
  30 #include <linux/initrd.h>
  31 #include <linux/irq.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/root_dev.h>
  34 #include <linux/tty.h>
  35 #include <linux/serial.h>
  36 #include <linux/serial_core.h>
  37
  38 #include <asm/system.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/page.h>
  41 #include <asm/dma.h>
  42 #include <asm/io.h>
  43 #include <asm/machdep.h>
  44 #include <asm/ocp.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/time.h>
  47 #include <asm/todc.h>
  48 #include <asm/bootinfo.h>
  49 #include <asm/ppc4xx_pic.h>
  50 #include <asm/ppcboot.h>
  51
  52 #include <syslib/gen550.h>
  53 #include <syslib/ibm440gx_common.h>
  54
  55 /*
  56  * This is a horrible kludge, we eventually need to abstract this
  57  * generic PHY stuff, so the  standard phy mode defines can be
  58  * easily used from arch code.
  59  */
  60 #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
  61
  62 bd_t __res;
  63
  64 static struct ibm44x_clocks clocks __initdata;
  65
  66 static void __init
  67 ocotea_calibrate_decr(void)
  68 {
  69         unsigned int freq;
  70
  71         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  72                 freq = OCOTEA_TMR_CLK;
  73         else
  74                 freq = clocks.cpu;
  75
  76         ibm44x_calibrate_decr(freq);
  77 }
  78
  79 static int
  80 ocotea_show_cpuinfo(struct seq_file *m)
  81 {
  82         seq_printf(m, "vendor\t\t: IBM\n");
  83         seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
  84         ibm440gx_show_cpuinfo(m);
  85         return 0;
  86 }
  87
  88 static inline int
  89 ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  90 {
  91         static char pci_irq_table[][4] =
  92         /*
  93          *      PCI IDSEL/INTPIN->INTLINE
  94          *         A   B   C   D
  95          */
  96         {
  97                 { 23, 23, 23, 23 },     /* IDSEL 1 - PCI Slot 0 */
  98                 { 24, 24, 24, 24 },     /* IDSEL 2 - PCI Slot 1 */
  99                 { 25, 25, 25, 25 },     /* IDSEL 3 - PCI Slot 2 */
 100                 { 26, 26, 26, 26 },     /* IDSEL 4 - PCI Slot 3 */
 101         };
 102
 103         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 104         return PCI_IRQ_TABLE_LOOKUP;
 105 }
 106
 107 static void __init ocotea_set_emacdata(void)
 108 {
 109         struct ocp_def *def;
 110         struct ocp_func_emac_data *emacdata;
 111         int i;
 112
 113         /*
 114          * Note: Current rev. board only operates in Group 4a
 115          * mode, so we always set EMAC0-1 for SMII and EMAC2-3
 116          * for RGMII (though these could run in RTBI just the same).
 117          *
 118          * The FPGA reg 3 information isn't even suitable for
 119          * determining the phy_mode, so if the board becomes
 120          * usable in !4a, it will be necessary to parse an environment
 121          * variable from the firmware or similar to properly configure
 122          * the phy_map/phy_mode.
 123          */
 124         /* Set phy_map, phy_mode, and mac_addr for each EMAC */
 125         for (i=0; i<4; i++) {
 126                 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
 127                 emacdata = def->additions;
 128                 if (i < 2) {
 129                         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 130                         emacdata->phy_mode = PHY_MODE_SMII;
 131                 }
 132                 else {
 133                         emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
 134                         emacdata->phy_mode = PHY_MODE_RGMII;
 135                 }
 136                 if (i == 0)
 137                         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 138                 else if (i == 1)
 139                         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 140                 else if (i == 2)
 141                         memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
 142                 else if (i == 3)
 143                         memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
 144         }
 145 }
 146
 147 #define PCIX_READW(offset) \
 148         (readw(pcix_reg_base+offset))
 149
 150 #define PCIX_WRITEW(value, offset) \
 151         (writew(value, pcix_reg_base+offset))
 152
 153 #define PCIX_WRITEL(value, offset) \
 154         (writel(value, pcix_reg_base+offset))
 155
 156 /*
 157  * FIXME: This is only here to "make it work".  This will move
 158  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 159  * configuration library. -Matt
 160  */
 161 static void __init
 162 ocotea_setup_pcix(void)
 163 {
 164         void *pcix_reg_base;
 165
 166         pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 167
 168         /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 169         PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 170
 171         /* Disable all windows */
 172         PCIX_WRITEL(0, PCIX0_POM0SA);
 173         PCIX_WRITEL(0, PCIX0_POM1SA);
 174         PCIX_WRITEL(0, PCIX0_POM2SA);
 175         PCIX_WRITEL(0, PCIX0_PIM0SA);
 176         PCIX_WRITEL(0, PCIX0_PIM0SAH);
 177         PCIX_WRITEL(0, PCIX0_PIM1SA);
 178         PCIX_WRITEL(0, PCIX0_PIM2SA);
 179         PCIX_WRITEL(0, PCIX0_PIM2SAH);
 180
 181         /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 182         PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 183         PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 184         PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 185         PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 186         PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 187
 188         /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 189         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 190         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 191         PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
 192
 193         eieio();
 194 }
 195
 196 static void __init
 197 ocotea_setup_hose(void)
 198 {
 199         struct pci_controller *hose;
 200
 201         /* Configure windows on the PCI-X host bridge */
 202         ocotea_setup_pcix();
 203
 204         hose = pcibios_alloc_controller();
 205
 206         if (!hose)
 207                 return;
 208
 209         hose->first_busno = 0;
 210         hose->last_busno = 0xff;
 211
 212         hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
 213
 214         pci_init_resource(&hose->io_resource,
 215                         OCOTEA_PCI_LOWER_IO,
 216                         OCOTEA_PCI_UPPER_IO,
 217                         IORESOURCE_IO,
 218                         "PCI host bridge");
 219
 220         pci_init_resource(&hose->mem_resources[0],
 221                         OCOTEA_PCI_LOWER_MEM,
 222                         OCOTEA_PCI_UPPER_MEM,
 223                         IORESOURCE_MEM,
 224                         "PCI host bridge");
 225
 226         hose->io_space.start = OCOTEA_PCI_LOWER_IO;
 227         hose->io_space.end = OCOTEA_PCI_UPPER_IO;
 228         hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
 229         hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
 230         hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
 231         isa_io_base = (unsigned long) hose->io_base_virt;
 232
 233         setup_indirect_pci(hose,
 234                         OCOTEA_PCI_CFGA_PLB32,
 235                         OCOTEA_PCI_CFGD_PLB32);
 236         hose->set_cfg_type = 1;
 237
 238         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 239
 240         ppc_md.pci_swizzle = common_swizzle;
 241         ppc_md.pci_map_irq = ocotea_map_irq;
 242 }
 243
 244
 245 TODC_ALLOC();
 246
 247 static void __init
 248 ocotea_early_serial_map(void)
 249 {
 250         struct uart_port port;
 251
 252         /* Setup ioremapped serial port access */
 253         memset(&port, 0, sizeof(port));
 254         port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
 255         port.irq = UART0_INT;
 256         port.uartclk = clocks.uart0;
 257         port.regshift = 0;
 258         port.iotype = SERIAL_IO_MEM;
 259         port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
 260         port.line = 0;
 261
 262         if (early_serial_setup(&port) != 0) {
 263                 printk("Early serial init of port 0 failed\n");
 264         }
 265
 266 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 267         /* Configure debug serial access */
 268         gen550_init(0, &port);
 269 #endif
 270
 271         port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
 272         port.irq = UART1_INT;
 273         port.uartclk = clocks.uart1;
 274         port.line = 1;
 275
 276         if (early_serial_setup(&port) != 0) {
 277                 printk("Early serial init of port 1 failed\n");
 278         }
 279
 280 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 281         /* Configure debug serial access */
 282         gen550_init(1, &port);
 283 #endif
 284 }
 285
 286 static void __init
 287 ocotea_setup_arch(void)
 288 {
 289         ocotea_set_emacdata();
 290
 291         ibm440gx_tah_enable();
 292
 293         /* Setup TODC access */
 294         TODC_INIT(TODC_TYPE_DS1743,
 295                         0,
 296                         0,
 297                         ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
 298                         8);
 299
 300         /* init to some ~sane value until calibrate_delay() runs */
 301         loops_per_jiffy = 50000000/HZ;
 302
 303         /* Setup PCI host bridge */
 304         ocotea_setup_hose();
 305
 306 #ifdef CONFIG_BLK_DEV_INITRD
 307         if (initrd_start)
 308                 ROOT_DEV = Root_RAM0;
 309         else
 310 #endif
 311 #ifdef CONFIG_ROOT_NFS
 312                 ROOT_DEV = Root_NFS;
 313 #else
 314                 ROOT_DEV = Root_HDA1;
 315 #endif
 316
 317         ocotea_early_serial_map();
 318
 319         /* Identify the system */
 320         printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
 321 }
 322
 323 static void __init ocotea_init(void)
 324 {
 325         ibm440gx_l2c_setup(&clocks);
 326 }
 327
 328 void __init platform_init(unsigned long r3, unsigned long r4,
 329                 unsigned long r5, unsigned long r6, unsigned long r7)
 330 {
 331         parse_bootinfo(find_bootinfo());
 332
 333         /*
 334          * If we were passed in a board information, copy it into the
 335          * residual data area.
 336          */
 337         if (r3)
 338                 __res = *(bd_t *)(r3 + KERNELBASE);
 339
 340         /*
 341          * Determine various clocks.
 342          * To be completely correct we should get SysClk
 343          * from FPGA, because it can be changed by on-board switches
 344          * --ebs
 345          */
 346         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 347         ocp_sys_info.opb_bus_freq = clocks.opb;
 348
 349         ibm44x_platform_init();
 350
 351         ppc_md.setup_arch = ocotea_setup_arch;
 352         ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
 353         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 354
 355         ppc_md.calibrate_decr = ocotea_calibrate_decr;
 356         ppc_md.time_init = todc_time_init;
 357         ppc_md.set_rtc_time = todc_set_rtc_time;
 358         ppc_md.get_rtc_time = todc_get_rtc_time;
 359
 360         ppc_md.nvram_read_val = todc_direct_read_val;
 361         ppc_md.nvram_write_val = todc_direct_write_val;
 362 #ifdef CONFIG_KGDB
 363         ppc_md.early_serial_map = ocotea_early_serial_map;
 364 #endif
 365         ppc_md.init = ocotea_init;
 366 }