2 * arch/ppc/platform/85xx/sbc85xx.c
4 * WindRiver PowerQUICC III SBC85xx board common routines
6 * Copyright 2002, 2003 Motorola Inc.
7 * Copyright 2004 Red Hat, Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/config.h>
16 #include <linux/stddef.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/irq.h>
27 #include <linux/seq_file.h>
28 #include <linux/serial.h>
29 #include <linux/module.h>
31 #include <asm/system.h>
32 #include <asm/pgtable.h>
34 #include <asm/atomic.h>
37 #include <asm/machdep.h>
39 #include <asm/open_pic.h>
40 #include <asm/bootinfo.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/mpc85xx.h>
44 #include <asm/immap_85xx.h>
45 #include <asm/ppc_sys.h>
47 #include <mm/mmu_decl.h>
49 #include <platforms/85xx/sbc85xx.h>
51 unsigned char __res
[sizeof (bd_t
)];
54 unsigned long isa_io_base
= 0;
55 unsigned long isa_mem_base
= 0;
56 unsigned long pci_dram_offset
= 0;
59 extern unsigned long total_memory
; /* in mm/init */
61 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
63 static u_char sbc8560_openpic_initsenses
[] __initdata
= {
64 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 0: L2 Cache */
65 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 1: ECM */
66 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 2: DDR DRAM */
67 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 3: LBIU */
68 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 4: DMA 0 */
69 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 5: DMA 1 */
70 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 6: DMA 2 */
71 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 7: DMA 3 */
72 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 8: PCI/PCI-X */
73 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 9: RIO Inbound Port Write Error */
74 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 10: RIO Doorbell Inbound */
75 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 11: RIO Outbound Message */
76 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 12: RIO Inbound Message */
77 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 13: TSEC 0 Transmit */
78 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 14: TSEC 0 Receive */
79 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 15: Unused */
80 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 16: Unused */
81 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 17: Unused */
82 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 18: TSEC 0 Receive/Transmit Error */
83 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 19: TSEC 1 Transmit */
84 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 20: TSEC 1 Receive */
85 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 21: Unused */
86 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 22: Unused */
87 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 23: Unused */
88 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 24: TSEC 1 Receive/Transmit Error */
89 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 25: Fast Ethernet */
90 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 26: DUART */
91 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 27: I2C */
92 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 28: Performance Monitor */
93 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 29: Unused */
94 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 30: CPM */
95 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* Internal 31: Unused */
96 0x0, /* External 0: */
97 0x0, /* External 1: */
98 #if defined(CONFIG_PCI)
99 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 2: PCI slot 0 */
100 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 3: PCI slot 1 */
101 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 4: PCI slot 2 */
102 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 5: PCI slot 3 */
104 0x0, /* External 2: */
105 0x0, /* External 3: */
106 0x0, /* External 4: */
107 0x0, /* External 5: */
109 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 6: PHY */
110 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 7: PHY */
111 0x0, /* External 8: */
112 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* External 9: PHY */
113 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* External 10: PHY */
114 0x0, /* External 11: */
117 /* ************************************************************************ */
119 sbc8560_show_cpuinfo(struct seq_file
*m
)
121 uint pvid
, svid
, phid1
;
122 uint memsize
= total_memory
;
123 bd_t
*binfo
= (bd_t
*) __res
;
126 /* get the core frequency */
127 freq
= binfo
->bi_intfreq
;
129 pvid
= mfspr(SPRN_PVR
);
130 svid
= mfspr(SPRN_SVR
);
132 seq_printf(m
, "Vendor\t\t: Wind River\n");
133 seq_printf(m
, "Machine\t\t: SBC%s\n", cur_ppc_sys_spec
->ppc_sys_name
);
134 seq_printf(m
, "clock\t\t: %dMHz\n", freq
/ 1000000);
135 seq_printf(m
, "PVR\t\t: 0x%x\n", pvid
);
136 seq_printf(m
, "SVR\t\t: 0x%x\n", svid
);
138 /* Display cpu Pll setting */
139 phid1
= mfspr(SPRN_HID1
);
140 seq_printf(m
, "PLL setting\t: 0x%x\n", ((phid1
>> 24) & 0x3f));
142 /* Display the amount of memory */
143 seq_printf(m
, "Memory\t\t: %d MB\n", memsize
/ (1024 * 1024));
149 sbc8560_init_IRQ(void)
151 bd_t
*binfo
= (bd_t
*) __res
;
152 /* Determine the Physical Address of the OpenPIC regs */
153 phys_addr_t OpenPIC_PAddr
=
154 binfo
->bi_immr_base
+ MPC85xx_OPENPIC_OFFSET
;
155 OpenPIC_Addr
= ioremap(OpenPIC_PAddr
, MPC85xx_OPENPIC_SIZE
);
156 OpenPIC_InitSenses
= sbc8560_openpic_initsenses
;
157 OpenPIC_NumInitSenses
= sizeof (sbc8560_openpic_initsenses
);
159 /* Skip reserved space and internal sources */
160 openpic_set_sources(0, 32, OpenPIC_Addr
+ 0x10200);
161 /* Map PIC IRQs 0-11 */
162 openpic_set_sources(32, 12, OpenPIC_Addr
+ 0x10000);
164 /* we let openpic interrupts starting from an offset, to
165 * leave space for cascading interrupts underneath.
167 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET
);
177 int mpc85xx_map_irq(struct pci_dev
*dev
, unsigned char idsel
,
180 static char pci_irq_table
[][4] =
182 * PCI IDSEL/INTPIN->INTLINE
186 {PIRQA
, PIRQB
, PIRQC
, PIRQD
},
187 {PIRQD
, PIRQA
, PIRQB
, PIRQC
},
188 {PIRQC
, PIRQD
, PIRQA
, PIRQB
},
189 {PIRQB
, PIRQC
, PIRQD
, PIRQA
},
192 const long min_idsel
= 12, max_idsel
= 15, irqs_per_slot
= 4;
193 return PCI_IRQ_TABLE_LOOKUP
;
196 int mpc85xx_exclude_device(u_char bus
, u_char devfn
)
198 if (bus
== 0 && PCI_SLOT(devfn
) == 0)
199 return PCIBIOS_DEVICE_NOT_FOUND
;
201 return PCIBIOS_SUCCESSFUL
;
203 #endif /* CONFIG_PCI */