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Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/gregkh/driver...
[linux-2.6/verdex.git] / arch / ppc / syslib / mv64x60.c
blob7b241e7876bda9ca46ac5ffe7444bc5b90a7eb8b
1 /*
2 * arch/ppc/syslib/mv64x60.c
3 *
4 * Common routines for the Marvell/Galileo Discovery line of host bridges
5 * (gt64260, mv64360, mv64460, ...).
6 *
7 * Author: Mark A. Greer <mgreer@mvista.com>
8 *
9 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/bootmem.h>
21 #include <linux/spinlock.h>
22 #include <linux/mv643xx.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26 #include <asm/irq.h>
27 #include <asm/uaccess.h>
28 #include <asm/machdep.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/delay.h>
31 #include <asm/mv64x60.h>
32
33
34 u8 mv64x60_pci_exclude_bridge = 1;
35 spinlock_t mv64x60_lock = SPIN_LOCK_UNLOCKED;
36
37 static phys_addr_t mv64x60_bridge_pbase = 0;
38 static void *mv64x60_bridge_vbase = 0;
39 static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID;
40 static u32 mv64x60_bridge_rev = 0;
41
42 static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
43 static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
44 static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus,
45 u32 window, u32 base);
46 static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
47 struct pci_controller *hose, u32 bus, u32 base);
48 static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
49 static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
50 static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
51 static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
52 static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
53 static void gt64260_disable_all_windows(struct mv64x60_handle *bh,
54 struct mv64x60_setup_info *si);
55 static void gt64260a_chip_specific_init(struct mv64x60_handle *bh,
56 struct mv64x60_setup_info *si);
57 static void gt64260b_chip_specific_init(struct mv64x60_handle *bh,
58 struct mv64x60_setup_info *si);
59
60 static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits);
61 static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits);
62 static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus,
63 u32 window, u32 base);
64 static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
65 struct pci_controller *hose, u32 bus, u32 base);
66 static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
67 static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
68 static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
69 static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
70 static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
71 static void mv64360_disable_all_windows(struct mv64x60_handle *bh,
72 struct mv64x60_setup_info *si);
73 static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
74 struct mv64x60_setup_info *si,
75 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
76 static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base);
77 static void mv64360_chip_specific_init(struct mv64x60_handle *bh,
78 struct mv64x60_setup_info *si);
79 static void mv64460_chip_specific_init(struct mv64x60_handle *bh,
80 struct mv64x60_setup_info *si);
81
82
83 /*
84 * Define tables that have the chip-specific info for each type of
85 * Marvell bridge chip.
86 */
87 static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */
88 .translate_size = gt64260_translate_size,
89 .untranslate_size = gt64260_untranslate_size,
90 .set_pci2mem_window = gt64260_set_pci2mem_window,
91 .set_pci2regs_window = gt64260_set_pci2regs_window,
92 .is_enabled_32bit = gt64260_is_enabled_32bit,
93 .enable_window_32bit = gt64260_enable_window_32bit,
94 .disable_window_32bit = gt64260_disable_window_32bit,
95 .enable_window_64bit = gt64260_enable_window_64bit,
96 .disable_window_64bit = gt64260_disable_window_64bit,
97 .disable_all_windows = gt64260_disable_all_windows,
98 .chip_specific_init = gt64260a_chip_specific_init,
99 .window_tab_32bit = gt64260_32bit_windows,
100 .window_tab_64bit = gt64260_64bit_windows,
101 };
102
103 static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */
104 .translate_size = gt64260_translate_size,
105 .untranslate_size = gt64260_untranslate_size,
106 .set_pci2mem_window = gt64260_set_pci2mem_window,
107 .set_pci2regs_window = gt64260_set_pci2regs_window,
108 .is_enabled_32bit = gt64260_is_enabled_32bit,
109 .enable_window_32bit = gt64260_enable_window_32bit,
110 .disable_window_32bit = gt64260_disable_window_32bit,
111 .enable_window_64bit = gt64260_enable_window_64bit,
112 .disable_window_64bit = gt64260_disable_window_64bit,
113 .disable_all_windows = gt64260_disable_all_windows,
114 .chip_specific_init = gt64260b_chip_specific_init,
115 .window_tab_32bit = gt64260_32bit_windows,
116 .window_tab_64bit = gt64260_64bit_windows,
117 };
118
119 static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */
120 .translate_size = mv64360_translate_size,
121 .untranslate_size = mv64360_untranslate_size,
122 .set_pci2mem_window = mv64360_set_pci2mem_window,
123 .set_pci2regs_window = mv64360_set_pci2regs_window,
124 .is_enabled_32bit = mv64360_is_enabled_32bit,
125 .enable_window_32bit = mv64360_enable_window_32bit,
126 .disable_window_32bit = mv64360_disable_window_32bit,
127 .enable_window_64bit = mv64360_enable_window_64bit,
128 .disable_window_64bit = mv64360_disable_window_64bit,
129 .disable_all_windows = mv64360_disable_all_windows,
130 .config_io2mem_windows = mv64360_config_io2mem_windows,
131 .set_mpsc2regs_window = mv64360_set_mpsc2regs_window,
132 .chip_specific_init = mv64360_chip_specific_init,
133 .window_tab_32bit = mv64360_32bit_windows,
134 .window_tab_64bit = mv64360_64bit_windows,
135 };
136
137 static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */
138 .translate_size = mv64360_translate_size,
139 .untranslate_size = mv64360_untranslate_size,
140 .set_pci2mem_window = mv64360_set_pci2mem_window,
141 .set_pci2regs_window = mv64360_set_pci2regs_window,
142 .is_enabled_32bit = mv64360_is_enabled_32bit,
143 .enable_window_32bit = mv64360_enable_window_32bit,
144 .disable_window_32bit = mv64360_disable_window_32bit,
145 .enable_window_64bit = mv64360_enable_window_64bit,
146 .disable_window_64bit = mv64360_disable_window_64bit,
147 .disable_all_windows = mv64360_disable_all_windows,
148 .config_io2mem_windows = mv64360_config_io2mem_windows,
149 .set_mpsc2regs_window = mv64360_set_mpsc2regs_window,
150 .chip_specific_init = mv64460_chip_specific_init,
151 .window_tab_32bit = mv64360_32bit_windows,
152 .window_tab_64bit = mv64360_64bit_windows,
153 };
154
155 /*
156 *****************************************************************************
157 *
158 * Platform Device Definitions
159 *
160 *****************************************************************************
161 */
162 #ifdef CONFIG_SERIAL_MPSC
163 static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
164 .mrr_val = 0x3ffffe38,
165 .rcrr_val = 0,
166 .tcrr_val = 0,
167 .intr_cause_val = 0,
168 .intr_mask_val = 0,
169 };
170
171 static struct resource mv64x60_mpsc_shared_resources[] = {
172 /* Do not change the order of the IORESOURCE_MEM resources */
173 [0] = {
174 .name = "mpsc routing base",
175 .start = MV64x60_MPSC_ROUTING_OFFSET,
176 .end = MV64x60_MPSC_ROUTING_OFFSET +
177 MPSC_ROUTING_REG_BLOCK_SIZE - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .name = "sdma intr base",
182 .start = MV64x60_SDMA_INTR_OFFSET,
183 .end = MV64x60_SDMA_INTR_OFFSET +
184 MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1,
185 .flags = IORESOURCE_MEM,
186 },
187 };
188
189 static struct platform_device mpsc_shared_device = { /* Shared device */
190 .name = MPSC_SHARED_NAME,
191 .id = 0,
192 .num_resources = ARRAY_SIZE(mv64x60_mpsc_shared_resources),
193 .resource = mv64x60_mpsc_shared_resources,
194 .dev = {
195 .platform_data = &mv64x60_mpsc_shared_pdata,
196 },
197 };
198
199 static struct mpsc_pdata mv64x60_mpsc0_pdata = {
200 .mirror_regs = 0,
201 .cache_mgmt = 0,
202 .max_idle = 0,
203 .default_baud = 9600,
204 .default_bits = 8,
205 .default_parity = 'n',
206 .default_flow = 'n',
207 .chr_1_val = 0x00000000,
208 .chr_2_val = 0x00000000,
209 .chr_10_val = 0x00000003,
210 .mpcr_val = 0,
211 .bcr_val = 0,
212 .brg_can_tune = 0,
213 .brg_clk_src = 8, /* Default to TCLK */
214 .brg_clk_freq = 100000000, /* Default to 100 MHz */
215 };
216
217 static struct resource mv64x60_mpsc0_resources[] = {
218 /* Do not change the order of the IORESOURCE_MEM resources */
219 [0] = {
220 .name = "mpsc 0 base",
221 .start = MV64x60_MPSC_0_OFFSET,
222 .end = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
223 .flags = IORESOURCE_MEM,
224 },
225 [1] = {
226 .name = "sdma 0 base",
227 .start = MV64x60_SDMA_0_OFFSET,
228 .end = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
229 .flags = IORESOURCE_MEM,
230 },
231 [2] = {
232 .name = "brg 0 base",
233 .start = MV64x60_BRG_0_OFFSET,
234 .end = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
235 .flags = IORESOURCE_MEM,
236 },
237 [3] = {
238 .name = "sdma 0 irq",
239 .start = MV64x60_IRQ_SDMA_0,
240 .end = MV64x60_IRQ_SDMA_0,
241 .flags = IORESOURCE_IRQ,
242 },
243 };
244
245 static struct platform_device mpsc0_device = {
246 .name = MPSC_CTLR_NAME,
247 .id = 0,
248 .num_resources = ARRAY_SIZE(mv64x60_mpsc0_resources),
249 .resource = mv64x60_mpsc0_resources,
250 .dev = {
251 .platform_data = &mv64x60_mpsc0_pdata,
252 },
253 };
254
255 static struct mpsc_pdata mv64x60_mpsc1_pdata = {
256 .mirror_regs = 0,
257 .cache_mgmt = 0,
258 .max_idle = 0,
259 .default_baud = 9600,
260 .default_bits = 8,
261 .default_parity = 'n',
262 .default_flow = 'n',
263 .chr_1_val = 0x00000000,
264 .chr_1_val = 0x00000000,
265 .chr_2_val = 0x00000000,
266 .chr_10_val = 0x00000003,
267 .mpcr_val = 0,
268 .bcr_val = 0,
269 .brg_can_tune = 0,
270 .brg_clk_src = 8, /* Default to TCLK */
271 .brg_clk_freq = 100000000, /* Default to 100 MHz */
272 };
273
274 static struct resource mv64x60_mpsc1_resources[] = {
275 /* Do not change the order of the IORESOURCE_MEM resources */
276 [0] = {
277 .name = "mpsc 1 base",
278 .start = MV64x60_MPSC_1_OFFSET,
279 .end = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
280 .flags = IORESOURCE_MEM,
281 },
282 [1] = {
283 .name = "sdma 1 base",
284 .start = MV64x60_SDMA_1_OFFSET,
285 .end = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
286 .flags = IORESOURCE_MEM,
287 },
288 [2] = {
289 .name = "brg 1 base",
290 .start = MV64x60_BRG_1_OFFSET,
291 .end = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
292 .flags = IORESOURCE_MEM,
293 },
294 [3] = {
295 .name = "sdma 1 irq",
296 .start = MV64360_IRQ_SDMA_1,
297 .end = MV64360_IRQ_SDMA_1,
298 .flags = IORESOURCE_IRQ,
299 },
300 };
301
302 static struct platform_device mpsc1_device = {
303 .name = MPSC_CTLR_NAME,
304 .id = 1,
305 .num_resources = ARRAY_SIZE(mv64x60_mpsc1_resources),
306 .resource = mv64x60_mpsc1_resources,
307 .dev = {
308 .platform_data = &mv64x60_mpsc1_pdata,
309 },
310 };
311 #endif
312
313 #ifdef CONFIG_MV643XX_ETH
314 static struct resource mv64x60_eth_shared_resources[] = {
315 [0] = {
316 .name = "ethernet shared base",
317 .start = MV643XX_ETH_SHARED_REGS,
318 .end = MV643XX_ETH_SHARED_REGS +
319 MV643XX_ETH_SHARED_REGS_SIZE - 1,
320 .flags = IORESOURCE_MEM,
321 },
322 };
323
324 static struct platform_device mv64x60_eth_shared_device = {
325 .name = MV643XX_ETH_SHARED_NAME,
326 .id = 0,
327 .num_resources = ARRAY_SIZE(mv64x60_eth_shared_resources),
328 .resource = mv64x60_eth_shared_resources,
329 };
330
331 #ifdef CONFIG_MV643XX_ETH_0
332 static struct resource mv64x60_eth0_resources[] = {
333 [0] = {
334 .name = "eth0 irq",
335 .start = MV64x60_IRQ_ETH_0,
336 .end = MV64x60_IRQ_ETH_0,
337 .flags = IORESOURCE_IRQ,
338 },
339 };
340
341 static struct mv643xx_eth_platform_data eth0_pd;
342
343 static struct platform_device eth0_device = {
344 .name = MV643XX_ETH_NAME,
345 .id = 0,
346 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
347 .resource = mv64x60_eth0_resources,
348 .dev = {
349 .platform_data = &eth0_pd,
350 },
351 };
352 #endif
353
354 #ifdef CONFIG_MV643XX_ETH_1
355 static struct resource mv64x60_eth1_resources[] = {
356 [0] = {
357 .name = "eth1 irq",
358 .start = MV64x60_IRQ_ETH_1,
359 .end = MV64x60_IRQ_ETH_1,
360 .flags = IORESOURCE_IRQ,
361 },
362 };
363
364 static struct mv643xx_eth_platform_data eth1_pd;
365
366 static struct platform_device eth1_device = {
367 .name = MV643XX_ETH_NAME,
368 .id = 1,
369 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
370 .resource = mv64x60_eth1_resources,
371 .dev = {
372 .platform_data = &eth1_pd,
373 },
374 };
375 #endif
376
377 #ifdef CONFIG_MV643XX_ETH_2
378 static struct resource mv64x60_eth2_resources[] = {
379 [0] = {
380 .name = "eth2 irq",
381 .start = MV64x60_IRQ_ETH_2,
382 .end = MV64x60_IRQ_ETH_2,
383 .flags = IORESOURCE_IRQ,
384 },
385 };
386
387 static struct mv643xx_eth_platform_data eth2_pd;
388
389 static struct platform_device eth2_device = {
390 .name = MV643XX_ETH_NAME,
391 .id = 2,
392 .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
393 .resource = mv64x60_eth2_resources,
394 .dev = {
395 .platform_data = &eth2_pd,
396 },
397 };
398 #endif
399 #endif
400
401 #ifdef CONFIG_I2C_MV64XXX
402 static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
403 .freq_m = 8,
404 .freq_n = 3,
405 .timeout = 1000, /* Default timeout of 1 second */
406 .retries = 1,
407 };
408
409 static struct resource mv64xxx_i2c_resources[] = {
410 /* Do not change the order of the IORESOURCE_MEM resources */
411 [0] = {
412 .name = "mv64xxx i2c base",
413 .start = MV64XXX_I2C_OFFSET,
414 .end = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
415 .flags = IORESOURCE_MEM,
416 },
417 [1] = {
418 .name = "mv64xxx i2c irq",
419 .start = MV64x60_IRQ_I2C,
420 .end = MV64x60_IRQ_I2C,
421 .flags = IORESOURCE_IRQ,
422 },
423 };
424
425 static struct platform_device i2c_device = {
426 .name = MV64XXX_I2C_CTLR_NAME,
427 .id = 0,
428 .num_resources = ARRAY_SIZE(mv64xxx_i2c_resources),
429 .resource = mv64xxx_i2c_resources,
430 .dev = {
431 .platform_data = &mv64xxx_i2c_pdata,
432 },
433 };
434 #endif
435
436 static struct platform_device *mv64x60_pd_devs[] __initdata = {
437 #ifdef CONFIG_SERIAL_MPSC
438 &mpsc_shared_device,
439 &mpsc0_device,
440 &mpsc1_device,
441 #endif
442 #ifdef CONFIG_MV643XX_ETH
443 &mv64x60_eth_shared_device,
444 #endif
445 #ifdef CONFIG_MV643XX_ETH_0
446 &eth0_device,
447 #endif
448 #ifdef CONFIG_MV643XX_ETH_1
449 &eth1_device,
450 #endif
451 #ifdef CONFIG_MV643XX_ETH_2
452 &eth2_device,
453 #endif
454 #ifdef CONFIG_I2C_MV64XXX
455 &i2c_device,
456 #endif
457 };
458
459 /*
460 *****************************************************************************
461 *
462 * Bridge Initialization Routines
463 *
464 *****************************************************************************
465 */
466 /*
467 * mv64x60_init()
468 *
469 * Initialze the bridge based on setting passed in via 'si'. The bridge
470 * handle, 'bh', will be set so that it can be used to make subsequent
471 * calls to routines in this file.
472 */
473 int __init
474 mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
475 {
476 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
477
478 if (ppc_md.progress)
479 ppc_md.progress("mv64x60 initialization", 0x0);
480
481 spin_lock_init(&mv64x60_lock);
482 mv64x60_early_init(bh, si);
483
484 if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
485 iounmap(bh->v_base);
486 bh->v_base = 0;
487 if (ppc_md.progress)
488 ppc_md.progress("mv64x60_init: Can't determine chip",0);
489 return -1;
490 }
491
492 bh->ci->disable_all_windows(bh, si);
493 mv64x60_get_mem_windows(bh, mem_windows);
494 mv64x60_config_cpu2mem_windows(bh, si, mem_windows);
495
496 if (bh->ci->config_io2mem_windows)
497 bh->ci->config_io2mem_windows(bh, si, mem_windows);
498 if (bh->ci->set_mpsc2regs_window)
499 bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base);
500
501 if (si->pci_1.enable_bus) {
502 bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base,
503 si->pci_1.pci_io.size);
504 isa_io_base = bh->io_base_b;
505 }
506
507 if (si->pci_0.enable_bus) {
508 bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base,
509 si->pci_0.pci_io.size);
510 isa_io_base = bh->io_base_a;
511
512 mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR,
513 MV64x60_PCI0_CONFIG_DATA, &bh->hose_a);
514 mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a);
515 mv64x60_config_pci_params(bh->hose_a, &si->pci_0);
516
517 mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0);
518 mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0,
519 mem_windows);
520 bh->ci->set_pci2regs_window(bh, bh->hose_a, 0,
521 si->phys_reg_base);
522 }
523
524 if (si->pci_1.enable_bus) {
525 mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR,
526 MV64x60_PCI1_CONFIG_DATA, &bh->hose_b);
527 mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b);
528 mv64x60_config_pci_params(bh->hose_b, &si->pci_1);
529
530 mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1);
531 mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1,
532 mem_windows);
533 bh->ci->set_pci2regs_window(bh, bh->hose_b, 1,
534 si->phys_reg_base);
535 }
536
537 bh->ci->chip_specific_init(bh, si);
538 mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs));
539
540 return 0;
541 }
542
543 /*
544 * mv64x60_early_init()
545 *
546 * Do some bridge work that must take place before we start messing with
547 * the bridge for real.
548 */
549 void __init
550 mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
551 {
552 struct pci_controller hose_a, hose_b;
553
554 memset(bh, 0, sizeof(*bh));
555
556 bh->p_base = si->phys_reg_base;
557 bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
558
559 mv64x60_bridge_pbase = bh->p_base;
560 mv64x60_bridge_vbase = bh->v_base;
561
562 /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
563 bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) &
564 MV64x60_PCIMODE_MASK;
565 bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) &
566 MV64x60_PCIMODE_MASK;
567
568 /* Need temporary hose structs to call mv64x60_set_bus() */
569 memset(&hose_a, 0, sizeof(hose_a));
570 memset(&hose_b, 0, sizeof(hose_b));
571 setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
572 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
573 setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR,
574 bh->v_base + MV64x60_PCI1_CONFIG_DATA);
575 bh->hose_a = &hose_a;
576 bh->hose_b = &hose_b;
577
578 mv64x60_set_bus(bh, 0, 0);
579 mv64x60_set_bus(bh, 1, 0);
580
581 bh->hose_a = NULL;
582 bh->hose_b = NULL;
583
584 /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
585 mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001);
586 mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001);
587
588 /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
589 mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12));
590 mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27));
591
592 mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff);
593 mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff);
594
595 return;
596 }
597
598 /*
599 *****************************************************************************
600 *
601 * Window Config Routines
602 *
603 *****************************************************************************
604 */
605 /*
606 * mv64x60_get_32bit_window()
607 *
608 * Determine the base address and size of a 32-bit window on the bridge.
609 */
610 void __init
611 mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
612 u32 *base, u32 *size)
613 {
614 u32 val, base_reg, size_reg, base_bits, size_bits;
615 u32 (*get_from_field)(u32 val, u32 num_bits);
616
617 base_reg = bh->ci->window_tab_32bit[window].base_reg;
618
619 if (base_reg != 0) {
620 size_reg = bh->ci->window_tab_32bit[window].size_reg;
621 base_bits = bh->ci->window_tab_32bit[window].base_bits;
622 size_bits = bh->ci->window_tab_32bit[window].size_bits;
623 get_from_field= bh->ci->window_tab_32bit[window].get_from_field;
624
625 val = mv64x60_read(bh, base_reg);
626 *base = get_from_field(val, base_bits);
627
628 if (size_reg != 0) {
629 val = mv64x60_read(bh, size_reg);
630 val = get_from_field(val, size_bits);
631 *size = bh->ci->untranslate_size(*base, val, size_bits);
632 }
633 else
634 *size = 0;
635 }
636 else {
637 *base = 0;
638 *size = 0;
639 }
640
641 pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
642 window, *base, *size);
643
644 return;
645 }
646
647 /*
648 * mv64x60_set_32bit_window()
649 *
650 * Set the base address and size of a 32-bit window on the bridge.
651 */
652 void __init
653 mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window,
654 u32 base, u32 size, u32 other_bits)
655 {
656 u32 val, base_reg, size_reg, base_bits, size_bits;
657 u32 (*map_to_field)(u32 val, u32 num_bits);
658
659 pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
660 window, base, size, other_bits);
661
662 base_reg = bh->ci->window_tab_32bit[window].base_reg;
663
664 if (base_reg != 0) {
665 size_reg = bh->ci->window_tab_32bit[window].size_reg;
666 base_bits = bh->ci->window_tab_32bit[window].base_bits;
667 size_bits = bh->ci->window_tab_32bit[window].size_bits;
668 map_to_field = bh->ci->window_tab_32bit[window].map_to_field;
669
670 val = map_to_field(base, base_bits) | other_bits;
671 mv64x60_write(bh, base_reg, val);
672
673 if (size_reg != 0) {
674 val = bh->ci->translate_size(base, size, size_bits);
675 val = map_to_field(val, size_bits);
676 mv64x60_write(bh, size_reg, val);
677 }
678
679 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
680 }
681
682 return;
683 }
684
685 /*
686 * mv64x60_get_64bit_window()
687 *
688 * Determine the base address and size of a 64-bit window on the bridge.
689 */
690 void __init
691 mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
692 u32 *base_hi, u32 *base_lo, u32 *size)
693 {
694 u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
695 u32 (*get_from_field)(u32 val, u32 num_bits);
696
697 base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
698
699 if (base_lo_reg != 0) {
700 size_reg = bh->ci->window_tab_64bit[window].size_reg;
701 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
702 size_bits = bh->ci->window_tab_64bit[window].size_bits;
703 get_from_field= bh->ci->window_tab_64bit[window].get_from_field;
704
705 *base_hi = mv64x60_read(bh,
706 bh->ci->window_tab_64bit[window].base_hi_reg);
707
708 val = mv64x60_read(bh, base_lo_reg);
709 *base_lo = get_from_field(val, base_lo_bits);
710
711 if (size_reg != 0) {
712 val = mv64x60_read(bh, size_reg);
713 val = get_from_field(val, size_bits);
714 *size = bh->ci->untranslate_size(*base_lo, val,
715 size_bits);
716 }
717 else
718 *size = 0;
719 }
720 else {
721 *base_hi = 0;
722 *base_lo = 0;
723 *size = 0;
724 }
725
726 pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
727 "size: 0x%x\n", window, *base_hi, *base_lo, *size);
728
729 return;
730 }
731
732 /*
733 * mv64x60_set_64bit_window()
734 *
735 * Set the base address and size of a 64-bit window on the bridge.
736 */
737 void __init
738 mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
739 u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
740 {
741 u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
742 u32 (*map_to_field)(u32 val, u32 num_bits);
743
744 pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
745 "size: 0x%x, other: 0x%x\n",
746 window, base_hi, base_lo, size, other_bits);
747
748 base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
749
750 if (base_lo_reg != 0) {
751 size_reg = bh->ci->window_tab_64bit[window].size_reg;
752 base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
753 size_bits = bh->ci->window_tab_64bit[window].size_bits;
754 map_to_field = bh->ci->window_tab_64bit[window].map_to_field;
755
756 mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg,
757 base_hi);
758
759 val = map_to_field(base_lo, base_lo_bits) | other_bits;
760 mv64x60_write(bh, base_lo_reg, val);
761
762 if (size_reg != 0) {
763 val = bh->ci->translate_size(base_lo, size, size_bits);
764 val = map_to_field(val, size_bits);
765 mv64x60_write(bh, size_reg, val);
766 }
767
768 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
769 }
770
771 return;
772 }
773
774 /*
775 * mv64x60_mask()
776 *
777 * Take the high-order 'num_bits' of 'val' & mask off low bits.
778 */
779 u32 __init
780 mv64x60_mask(u32 val, u32 num_bits)
781 {
782 return val & (0xffffffff << (32 - num_bits));
783 }
784
785 /*
786 * mv64x60_shift_left()
787 *
788 * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
789 */
790 u32 __init
791 mv64x60_shift_left(u32 val, u32 num_bits)
792 {
793 return val << (32 - num_bits);
794 }
795
796 /*
797 * mv64x60_shift_right()
798 *
799 * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
800 */
801 u32 __init
802 mv64x60_shift_right(u32 val, u32 num_bits)
803 {
804 return val >> (32 - num_bits);
805 }
806
807 /*
808 *****************************************************************************
809 *
810 * Chip Identification Routines
811 *
812 *****************************************************************************
813 */
814 /*
815 * mv64x60_get_type()
816 *
817 * Determine the type of bridge chip we have.
818 */
819 int __init
820 mv64x60_get_type(struct mv64x60_handle *bh)
821 {
822 struct pci_controller hose;
823 u16 val;
824 u8 save_exclude;
825
826 memset(&hose, 0, sizeof(hose));
827 setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
828 bh->v_base + MV64x60_PCI0_CONFIG_DATA);
829
830 save_exclude = mv64x60_pci_exclude_bridge;
831 mv64x60_pci_exclude_bridge = 0;
832 /* Sanity check of bridge's Vendor ID */
833 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
834
835 if (val != PCI_VENDOR_ID_MARVELL) {
836 mv64x60_pci_exclude_bridge = save_exclude;
837 return -1;
838 }
839
840 /* Get the revision of the chip */
841 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION,
842 &val);
843 bh->rev = (u32)(val & 0xff);
844
845 /* Figure out the type of Marvell bridge it is */
846 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val);
847 mv64x60_pci_exclude_bridge = save_exclude;
848
849 switch (val) {
850 case PCI_DEVICE_ID_MARVELL_GT64260:
851 switch (bh->rev) {
852 case GT64260_REV_A:
853 bh->type = MV64x60_TYPE_GT64260A;
854 break;
855
856 default:
857 printk(KERN_WARNING "Unsupported GT64260 rev %04x\n",
858 bh->rev);
859 /* Assume its similar to a 'B' rev and fallthru */
860 case GT64260_REV_B:
861 bh->type = MV64x60_TYPE_GT64260B;
862 break;
863 }
864 break;
865
866 case PCI_DEVICE_ID_MARVELL_MV64360:
867 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
868 bh->type = MV64x60_TYPE_MV64360;
869 break;
870
871 case PCI_DEVICE_ID_MARVELL_MV64460:
872 bh->type = MV64x60_TYPE_MV64460;
873 break;
874
875 default:
876 printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val);
877 return -1;
878 }
879
880 /* Hang onto bridge type & rev for PIC code */
881 mv64x60_bridge_type = bh->type;
882 mv64x60_bridge_rev = bh->rev;
883
884 return 0;
885 }
886
887 /*
888 * mv64x60_setup_for_chip()
889 *
890 * Set 'bh' to use the proper set of routine for the bridge chip that we have.
891 */
892 int __init
893 mv64x60_setup_for_chip(struct mv64x60_handle *bh)
894 {
895 int rc = 0;
896
897 /* Set up chip-specific info based on the chip/bridge type */
898 switch(bh->type) {
899 case MV64x60_TYPE_GT64260A:
900 bh->ci = &gt64260a_ci;
901 break;
902
903 case MV64x60_TYPE_GT64260B:
904 bh->ci = &gt64260b_ci;
905 break;
906
907 case MV64x60_TYPE_MV64360:
908 bh->ci = &mv64360_ci;
909 break;
910
911 case MV64x60_TYPE_MV64460:
912 bh->ci = &mv64460_ci;
913 break;
914
915 case MV64x60_TYPE_INVALID:
916 default:
917 if (ppc_md.progress)
918 ppc_md.progress("mv64x60: Unsupported bridge", 0x0);
919 printk(KERN_ERR "mv64x60: Unsupported bridge\n");
920 rc = -1;
921 }
922
923 return rc;
924 }
925
926 /*
927 * mv64x60_get_bridge_vbase()
928 *
929 * Return the virtual address of the bridge's registers.
930 */
931 void *
932 mv64x60_get_bridge_vbase(void)
933 {
934 return mv64x60_bridge_vbase;
935 }
936
937 /*
938 * mv64x60_get_bridge_type()
939 *
940 * Return the type of bridge on the platform.
941 */
942 u32
943 mv64x60_get_bridge_type(void)
944 {
945 return mv64x60_bridge_type;
946 }
947
948 /*
949 * mv64x60_get_bridge_rev()
950 *
951 * Return the revision of the bridge on the platform.
952 */
953 u32
954 mv64x60_get_bridge_rev(void)
955 {
956 return mv64x60_bridge_rev;
957 }
958
959 /*
960 *****************************************************************************
961 *
962 * System Memory Window Related Routines
963 *
964 *****************************************************************************
965 */
966 /*
967 * mv64x60_get_mem_size()
968 *
969 * Calculate the amount of memory that the memory controller is set up for.
970 * This should only be used by board-specific code if there is no other
971 * way to determine the amount of memory in the system.
972 */
973 u32 __init
974 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
975 {
976 struct mv64x60_handle bh;
977 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
978 u32 rc = 0;
979
980 memset(&bh, 0, sizeof(bh));
981
982 bh.type = chip_type;
983 bh.v_base = (void *)bridge_base;
984
985 if (!mv64x60_setup_for_chip(&bh)) {
986 mv64x60_get_mem_windows(&bh, mem_windows);
987 rc = mv64x60_calc_mem_size(&bh, mem_windows);
988 }
989
990 return rc;
991 }
992
993 /*
994 * mv64x60_get_mem_windows()
995 *
996 * Get the values in the memory controller & return in the 'mem_windows' array.
997 */
998 void __init
999 mv64x60_get_mem_windows(struct mv64x60_handle *bh,
1000 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1001 {
1002 u32 i, win;
1003
1004 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1005 if (bh->ci->is_enabled_32bit(bh, win))
1006 mv64x60_get_32bit_window(bh, win,
1007 &mem_windows[i][0], &mem_windows[i][1]);
1008 else {
1009 mem_windows[i][0] = 0;
1010 mem_windows[i][1] = 0;
1011 }
1012
1013 return;
1014 }
1015
1016 /*
1017 * mv64x60_calc_mem_size()
1018 *
1019 * Using the memory controller register values in 'mem_windows', determine
1020 * how much memory it is set up for.
1021 */
1022 u32 __init
1023 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
1024 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1025 {
1026 u32 i, total = 0;
1027
1028 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
1029 total += mem_windows[i][1];
1030
1031 return total;
1032 }
1033
1034 /*
1035 *****************************************************************************
1036 *
1037 * CPU->System MEM, PCI Config Routines
1038 *
1039 *****************************************************************************
1040 */
1041 /*
1042 * mv64x60_config_cpu2mem_windows()
1043 *
1044 * Configure CPU->Memory windows on the bridge.
1045 */
1046 static u32 prot_tab[] __initdata = {
1047 MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN,
1048 MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN
1049 };
1050
1051 static u32 cpu_snoop_tab[] __initdata = {
1052 MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN,
1053 MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN
1054 };
1055
1056 void __init
1057 mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
1058 struct mv64x60_setup_info *si,
1059 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1060 {
1061 u32 i, win;
1062
1063 /* Set CPU protection & snoop windows */
1064 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1065 if (bh->ci->is_enabled_32bit(bh, win)) {
1066 mv64x60_set_32bit_window(bh, prot_tab[i],
1067 mem_windows[i][0], mem_windows[i][1],
1068 si->cpu_prot_options[i]);
1069 bh->ci->enable_window_32bit(bh, prot_tab[i]);
1070
1071 if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]].
1072 base_reg != 0) {
1073 mv64x60_set_32bit_window(bh, cpu_snoop_tab[i],
1074 mem_windows[i][0], mem_windows[i][1],
1075 si->cpu_snoop_options[i]);
1076 bh->ci->enable_window_32bit(bh,
1077 cpu_snoop_tab[i]);
1078 }
1079
1080 }
1081
1082 return;
1083 }
1084
1085 /*
1086 * mv64x60_config_cpu2pci_windows()
1087 *
1088 * Configure the CPU->PCI windows for one of the PCI buses.
1089 */
1090 static u32 win_tab[2][4] __initdata = {
1091 { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN,
1092 MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN },
1093 { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN,
1094 MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN },
1095 };
1096
1097 static u32 remap_tab[2][4] __initdata = {
1098 { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN,
1099 MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN },
1100 { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN,
1101 MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN }
1102 };
1103
1104 void __init
1105 mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
1106 struct mv64x60_pci_info *pi, u32 bus)
1107 {
1108 int i;
1109
1110 if (pi->pci_io.size > 0) {
1111 mv64x60_set_32bit_window(bh, win_tab[bus][0],
1112 pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap);
1113 mv64x60_set_32bit_window(bh, remap_tab[bus][0],
1114 pi->pci_io.pci_base_lo, 0, 0);
1115 bh->ci->enable_window_32bit(bh, win_tab[bus][0]);
1116 }
1117 else /* Actually, the window should already be disabled */
1118 bh->ci->disable_window_32bit(bh, win_tab[bus][0]);
1119
1120 for (i=0; i<3; i++)
1121 if (pi->pci_mem[i].size > 0) {
1122 mv64x60_set_32bit_window(bh, win_tab[bus][i+1],
1123 pi->pci_mem[i].cpu_base, pi->pci_mem[i].size,
1124 pi->pci_mem[i].swap);
1125 mv64x60_set_64bit_window(bh, remap_tab[bus][i+1],
1126 pi->pci_mem[i].pci_base_hi,
1127 pi->pci_mem[i].pci_base_lo, 0, 0);
1128 bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]);
1129 }
1130 else /* Actually, the window should already be disabled */
1131 bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]);
1132
1133 return;
1134 }
1135
1136 /*
1137 *****************************************************************************
1138 *
1139 * PCI->System MEM Config Routines
1140 *
1141 *****************************************************************************
1142 */
1143 /*
1144 * mv64x60_config_pci2mem_windows()
1145 *
1146 * Configure the PCI->Memory windows on the bridge.
1147 */
1148 static u32 pci_acc_tab[2][4] __initdata = {
1149 { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN,
1150 MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN },
1151 { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN,
1152 MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN }
1153 };
1154
1155 static u32 pci_snoop_tab[2][4] __initdata = {
1156 { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN,
1157 MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN },
1158 { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN,
1159 MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN }
1160 };
1161
1162 static u32 pci_size_tab[2][4] __initdata = {
1163 { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE,
1164 MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE },
1165 { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE,
1166 MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE }
1167 };
1168
1169 void __init
1170 mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
1171 struct pci_controller *hose, struct mv64x60_pci_info *pi,
1172 u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
1173 {
1174 u32 i, win;
1175
1176 /*
1177 * Set the access control, snoop, BAR size, and window base addresses.
1178 * PCI->MEM windows base addresses will match exactly what the
1179 * CPU->MEM windows are.
1180 */
1181 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
1182 if (bh->ci->is_enabled_32bit(bh, win)) {
1183 mv64x60_set_64bit_window(bh,
1184 pci_acc_tab[bus][i], 0,
1185 mem_windows[i][0], mem_windows[i][1],
1186 pi->acc_cntl_options[i]);
1187 bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]);
1188
1189 if (bh->ci->window_tab_64bit[
1190 pci_snoop_tab[bus][i]].base_lo_reg != 0) {
1191
1192 mv64x60_set_64bit_window(bh,
1193 pci_snoop_tab[bus][i], 0,
1194 mem_windows[i][0], mem_windows[i][1],
1195 pi->snoop_options[i]);
1196 bh->ci->enable_window_64bit(bh,
1197 pci_snoop_tab[bus][i]);
1198 }
1199
1200 bh->ci->set_pci2mem_window(hose, bus, i,
1201 mem_windows[i][0]);
1202 mv64x60_write(bh, pci_size_tab[bus][i],
1203 mv64x60_mask(mem_windows[i][1] - 1, 20));
1204
1205 /* Enable the window */
1206 mv64x60_clr_bits(bh, ((bus == 0) ?
1207 MV64x60_PCI0_BAR_ENABLE :
1208 MV64x60_PCI1_BAR_ENABLE), (1 << i));
1209 }
1210
1211 return;
1212 }
1213
1214 /*
1215 *****************************************************************************
1216 *
1217 * Hose & Resource Alloc/Init Routines
1218 *
1219 *****************************************************************************
1220 */
1221 /*
1222 * mv64x60_alloc_hoses()
1223 *
1224 * Allocate the PCI hose structures for the bridge's PCI buses.
1225 */
1226 void __init
1227 mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
1228 struct pci_controller **hose)
1229 {
1230 *hose = pcibios_alloc_controller();
1231 setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr,
1232 bh->v_base + cfg_data);
1233 return;
1234 }
1235
1236 /*
1237 * mv64x60_config_resources()
1238 *
1239 * Calculate the offsets, etc. for the hose structures to reflect all of
1240 * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1241 */
1242 void __init
1243 mv64x60_config_resources(struct pci_controller *hose,
1244 struct mv64x60_pci_info *pi, u32 io_base)
1245 {
1246 int i;
1247 /* 2 hoses; 4 resources/hose; string <= 64 bytes */
1248 static char s[2][4][64];
1249
1250 if (pi->pci_io.size != 0) {
1251 sprintf(s[hose->index][0], "PCI hose %d I/O Space",
1252 hose->index);
1253 pci_init_resource(&hose->io_resource, io_base - isa_io_base,
1254 io_base - isa_io_base + pi->pci_io.size - 1,
1255 IORESOURCE_IO, s[hose->index][0]);
1256 hose->io_space.start = pi->pci_io.pci_base_lo;
1257 hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
1258 hose->io_base_phys = pi->pci_io.cpu_base;
1259 hose->io_base_virt = (void *)isa_io_base;
1260 }
1261
1262 for (i=0; i<3; i++)
1263 if (pi->pci_mem[i].size != 0) {
1264 sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d",
1265 hose->index, i);
1266 pci_init_resource(&hose->mem_resources[i],
1267 pi->pci_mem[i].cpu_base,
1268 pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1,
1269 IORESOURCE_MEM, s[hose->index][i+1]);
1270 }
1271
1272 hose->mem_space.end = pi->pci_mem[0].pci_base_lo +
1273 pi->pci_mem[0].size - 1;
1274 hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
1275 pi->pci_mem[0].pci_base_lo;
1276 return;
1277 }
1278
1279 /*
1280 * mv64x60_config_pci_params()
1281 *
1282 * Configure a hose's PCI config space parameters.
1283 */
1284 void __init
1285 mv64x60_config_pci_params(struct pci_controller *hose,
1286 struct mv64x60_pci_info *pi)
1287 {
1288 u32 devfn;
1289 u16 u16_val;
1290 u8 save_exclude;
1291
1292 devfn = PCI_DEVFN(0,0);
1293
1294 save_exclude = mv64x60_pci_exclude_bridge;
1295 mv64x60_pci_exclude_bridge = 0;
1296
1297 /* Set class code to indicate host bridge */
1298 u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */
1299 early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val);
1300
1301 /* Enable bridge to be PCI master & respond to PCI MEM cycles */
1302 early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val);
1303 u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE |
1304 PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
1305 u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1306 early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
1307
1308 /* Set latency timer, cache line size, clear BIST */
1309 u16_val = (pi->latency_timer << 8) | (L1_CACHE_LINE_SIZE >> 2);
1310 early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
1311
1312 mv64x60_pci_exclude_bridge = save_exclude;
1313 return;
1314 }
1315
1316 /*
1317 *****************************************************************************
1318 *
1319 * PCI Related Routine
1320 *
1321 *****************************************************************************
1322 */
1323 /*
1324 * mv64x60_set_bus()
1325 *
1326 * Set the bus number for the hose directly under the bridge.
1327 */
1328 void __init
1329 mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1330 {
1331 struct pci_controller *hose;
1332 u32 pci_mode, p2p_cfg, pci_cfg_offset, val;
1333 u8 save_exclude;
1334
1335 if (bus == 0) {
1336 pci_mode = bh->pci_mode_a;
1337 p2p_cfg = MV64x60_PCI0_P2P_CONFIG;
1338 pci_cfg_offset = 0x64;
1339 hose = bh->hose_a;
1340 }
1341 else {
1342 pci_mode = bh->pci_mode_b;
1343 p2p_cfg = MV64x60_PCI1_P2P_CONFIG;
1344 pci_cfg_offset = 0xe4;
1345 hose = bh->hose_b;
1346 }
1347
1348 child_bus &= 0xff;
1349 val = mv64x60_read(bh, p2p_cfg);
1350
1351 if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) {
1352 val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
1353 val |= (child_bus << 16) | 0xff;
1354 mv64x60_write(bh, p2p_cfg, val);
1355 (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */
1356 }
1357 else { /* PCI-X */
1358 /*
1359 * Need to use the current bus/dev number (that's in the
1360 * P2P CONFIG reg) to access the bridge's pci config space.
1361 */
1362 save_exclude = mv64x60_pci_exclude_bridge;
1363 mv64x60_pci_exclude_bridge = 0;
1364 early_write_config_dword(hose, (val & 0x00ff0000) >> 16,
1365 PCI_DEVFN(((val & 0x1f000000) >> 24), 0),
1366 pci_cfg_offset, child_bus << 8);
1367 mv64x60_pci_exclude_bridge = save_exclude;
1368 }
1369
1370 return;
1371 }
1372
1373 /*
1374 * mv64x60_pci_exclude_device()
1375 *
1376 * This routine is used to make the bridge not appear when the
1377 * PCI subsystem is accessing PCI devices (in PCI config space).
1378 */
1379 int
1380 mv64x60_pci_exclude_device(u8 bus, u8 devfn)
1381 {
1382 struct pci_controller *hose;
1383
1384 hose = pci_bus_to_hose(bus);
1385
1386 /* Skip slot 0 on both hoses */
1387 if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) &&
1388 (hose->first_busno == bus))
1389
1390 return PCIBIOS_DEVICE_NOT_FOUND;
1391 else
1392 return PCIBIOS_SUCCESSFUL;
1393 } /* mv64x60_pci_exclude_device() */
1394
1395 /*
1396 *****************************************************************************
1397 *
1398 * Platform Device Routines
1399 *
1400 *****************************************************************************
1401 */
1402
1403 /*
1404 * mv64x60_pd_fixup()
1405 *
1406 * Need to add the base addr of where the bridge's regs are mapped in the
1407 * physical addr space so drivers can ioremap() them.
1408 */
1409 void __init
1410 mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[],
1411 u32 entries)
1412 {
1413 struct resource *r;
1414 u32 i, j;
1415
1416 for (i=0; i<entries; i++) {
1417 j = 0;
1418
1419 while ((r = platform_get_resource(pd_devs[i],IORESOURCE_MEM,j))
1420 != NULL) {
1421
1422 r->start += bh->p_base;
1423 r->end += bh->p_base;
1424 j++;
1425 }
1426 }
1427
1428 return;
1429 }
1430
1431 /*
1432 * mv64x60_add_pds()
1433 *
1434 * Add the mv64x60 platform devices to the list of platform devices.
1435 */
1436 static int __init
1437 mv64x60_add_pds(void)
1438 {
1439 return platform_add_devices(mv64x60_pd_devs,
1440 ARRAY_SIZE(mv64x60_pd_devs));
1441 }
1442 arch_initcall(mv64x60_add_pds);
1443
1444 /*
1445 *****************************************************************************
1446 *
1447 * GT64260-Specific Routines
1448 *
1449 *****************************************************************************
1450 */
1451 /*
1452 * gt64260_translate_size()
1453 *
1454 * On the GT64260, the size register is really the "top" address of the window.
1455 */
1456 static u32 __init
1457 gt64260_translate_size(u32 base, u32 size, u32 num_bits)
1458 {
1459 return base + mv64x60_mask(size - 1, num_bits);
1460 }
1461
1462 /*
1463 * gt64260_untranslate_size()
1464 *
1465 * Translate the top address of a window into a window size.
1466 */
1467 static u32 __init
1468 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits)
1469 {
1470 if (size >= base)
1471 size = size - base + (1 << (32 - num_bits));
1472 else
1473 size = 0;
1474
1475 return size;
1476 }
1477
1478 /*
1479 * gt64260_set_pci2mem_window()
1480 *
1481 * The PCI->MEM window registers are actually in PCI config space so need
1482 * to set them by setting the correct config space BARs.
1483 */
1484 static u32 gt64260_reg_addrs[2][4] __initdata = {
1485 { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
1486 };
1487
1488 static void __init
1489 gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1490 u32 base)
1491 {
1492 u8 save_exclude;
1493
1494 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1495 hose->index, base);
1496
1497 save_exclude = mv64x60_pci_exclude_bridge;
1498 mv64x60_pci_exclude_bridge = 0;
1499 early_write_config_dword(hose, 0, PCI_DEVFN(0, 0),
1500 gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8);
1501 mv64x60_pci_exclude_bridge = save_exclude;
1502
1503 return;
1504 }
1505
1506 /*
1507 * gt64260_set_pci2regs_window()
1508 *
1509 * Set where the bridge's registers appear in PCI MEM space.
1510 */
1511 static u32 gt64260_offset[2] __initdata = {0x20, 0xa0};
1512
1513 static void __init
1514 gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
1515 struct pci_controller *hose, u32 bus, u32 base)
1516 {
1517 u8 save_exclude;
1518
1519 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1520 base);
1521
1522 save_exclude = mv64x60_pci_exclude_bridge;
1523 mv64x60_pci_exclude_bridge = 0;
1524 early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus],
1525 (base << 16));
1526 mv64x60_pci_exclude_bridge = save_exclude;
1527
1528 return;
1529 }
1530
1531 /*
1532 * gt64260_is_enabled_32bit()
1533 *
1534 * On a GT64260, a window is enabled iff its top address is >= to its base
1535 * address.
1536 */
1537 static u32 __init
1538 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1539 {
1540 u32 rc = 0;
1541
1542 if ((gt64260_32bit_windows[window].base_reg != 0) &&
1543 (gt64260_32bit_windows[window].size_reg != 0) &&
1544 ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) &
1545 ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >=
1546 (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) &
1547 ((1 << gt64260_32bit_windows[window].base_bits) - 1))))
1548
1549 rc = 1;
1550
1551 return rc;
1552 }
1553
1554 /*
1555 * gt64260_enable_window_32bit()
1556 *
1557 * On the GT64260, a window is enabled iff the top address is >= to the base
1558 * address of the window. Since the window has already been configured by
1559 * the time this routine is called, we have nothing to do here.
1560 */
1561 static void __init
1562 gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
1563 {
1564 pr_debug("enable 32bit window: %d\n", window);
1565 return;
1566 }
1567
1568 /*
1569 * gt64260_disable_window_32bit()
1570 *
1571 * On a GT64260, you disable a window by setting its top address to be less
1572 * than its base address.
1573 */
1574 static void __init
1575 gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
1576 {
1577 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1578 window, gt64260_32bit_windows[window].base_reg,
1579 gt64260_32bit_windows[window].size_reg);
1580
1581 if ((gt64260_32bit_windows[window].base_reg != 0) &&
1582 (gt64260_32bit_windows[window].size_reg != 0)) {
1583
1584 /* To disable, make bottom reg higher than top reg */
1585 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
1586 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
1587 }
1588
1589 return;
1590 }
1591
1592 /*
1593 * gt64260_enable_window_64bit()
1594 *
1595 * On the GT64260, a window is enabled iff the top address is >= to the base
1596 * address of the window. Since the window has already been configured by
1597 * the time this routine is called, we have nothing to do here.
1598 */
1599 static void __init
1600 gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
1601 {
1602 pr_debug("enable 64bit window: %d\n", window);
1603 return; /* Enabled when window configured (i.e., when top >= base) */
1604 }
1605
1606 /*
1607 * gt64260_disable_window_64bit()
1608 *
1609 * On a GT64260, you disable a window by setting its top address to be less
1610 * than its base address.
1611 */
1612 static void __init
1613 gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
1614 {
1615 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1616 window, gt64260_64bit_windows[window].base_lo_reg,
1617 gt64260_64bit_windows[window].size_reg);
1618
1619 if ((gt64260_64bit_windows[window].base_lo_reg != 0) &&
1620 (gt64260_64bit_windows[window].size_reg != 0)) {
1621
1622 /* To disable, make bottom reg higher than top reg */
1623 mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg,
1624 0xfff);
1625 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
1626 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
1627 }
1628
1629 return;
1630 }
1631
1632 /*
1633 * gt64260_disable_all_windows()
1634 *
1635 * The GT64260 has several windows that aren't represented in the table of
1636 * windows at the top of this file. This routine turns all of them off
1637 * except for the memory controller windows, of course.
1638 */
1639 static void __init
1640 gt64260_disable_all_windows(struct mv64x60_handle *bh,
1641 struct mv64x60_setup_info *si)
1642 {
1643 u32 i, preserve;
1644
1645 /* Disable 32bit windows (don't disable cpu->mem windows) */
1646 for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
1647 if (i < 32)
1648 preserve = si->window_preserve_mask_32_lo & (1 << i);
1649 else
1650 preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
1651
1652 if (!preserve)
1653 gt64260_disable_window_32bit(bh, i);
1654 }
1655
1656 /* Disable 64bit windows */
1657 for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
1658 if (!(si->window_preserve_mask_64 & (1<<i)))
1659 gt64260_disable_window_64bit(bh, i);
1660
1661 /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
1662 mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff);
1663 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0);
1664 mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff);
1665 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0);
1666 mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff);
1667 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0);
1668 mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff);
1669 mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0);
1670
1671 /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
1672 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff);
1673 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0);
1674 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0);
1675 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff);
1676 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0);
1677 mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0);
1678 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff);
1679 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0);
1680 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0);
1681 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff);
1682 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0);
1683 mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0);
1684
1685 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff);
1686 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0);
1687 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0);
1688 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff);
1689 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0);
1690 mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0);
1691 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff);
1692 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0);
1693 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0);
1694 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff);
1695 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0);
1696 mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0);
1697
1698 /* Disable all PCI-><whatever> windows */
1699 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff);
1700 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff);
1701
1702 /*
1703 * Some firmwares enable a bunch of intr sources
1704 * for the PCI INT output pins.
1705 */
1706 mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0);
1707 mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0);
1708 mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0);
1709 mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0);
1710 mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0);
1711 mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0);
1712 mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0);
1713 mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0);
1714 mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0);
1715 mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0);
1716
1717 return;
1718 }
1719
1720 /*
1721 * gt64260a_chip_specific_init()
1722 *
1723 * Implement errata work arounds for the GT64260A.
1724 */
1725 static void __init
1726 gt64260a_chip_specific_init(struct mv64x60_handle *bh,
1727 struct mv64x60_setup_info *si)
1728 {
1729 #ifdef CONFIG_SERIAL_MPSC
1730 struct resource *r;
1731 #endif
1732 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1733 u32 val;
1734 u8 save_exclude;
1735 #endif
1736
1737 if (si->pci_0.enable_bus)
1738 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1739 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1740
1741 if (si->pci_1.enable_bus)
1742 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1743 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1744
1745 /*
1746 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1747 * be set if you are using cache coherency.
1748 */
1749 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1750 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1751 if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1752 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1753
1754 save_exclude = mv64x60_pci_exclude_bridge;
1755 mv64x60_pci_exclude_bridge = 0;
1756 if (si->pci_0.enable_bus) {
1757 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1758 PCI_COMMAND, &val);
1759 val |= PCI_COMMAND_INVALIDATE;
1760 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1761 PCI_COMMAND, val);
1762 }
1763
1764 if (si->pci_1.enable_bus) {
1765 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1766 PCI_COMMAND, &val);
1767 val |= PCI_COMMAND_INVALIDATE;
1768 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1769 PCI_COMMAND, val);
1770 }
1771 mv64x60_pci_exclude_bridge = save_exclude;
1772 #endif
1773
1774 /* Disable buffer/descriptor snooping */
1775 mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1776 mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1777
1778 #ifdef CONFIG_SERIAL_MPSC
1779 mv64x60_mpsc0_pdata.mirror_regs = 1;
1780 mv64x60_mpsc0_pdata.cache_mgmt = 1;
1781 mv64x60_mpsc1_pdata.mirror_regs = 1;
1782 mv64x60_mpsc1_pdata.cache_mgmt = 1;
1783
1784 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1785 != NULL) {
1786
1787 r->start = MV64x60_IRQ_SDMA_0;
1788 r->end = MV64x60_IRQ_SDMA_0;
1789 }
1790 #endif
1791
1792 return;
1793 }
1794
1795 /*
1796 * gt64260b_chip_specific_init()
1797 *
1798 * Implement errata work arounds for the GT64260B.
1799 */
1800 static void __init
1801 gt64260b_chip_specific_init(struct mv64x60_handle *bh,
1802 struct mv64x60_setup_info *si)
1803 {
1804 #ifdef CONFIG_SERIAL_MPSC
1805 struct resource *r;
1806 #endif
1807 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1808 u32 val;
1809 u8 save_exclude;
1810 #endif
1811
1812 if (si->pci_0.enable_bus)
1813 mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
1814 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1815
1816 if (si->pci_1.enable_bus)
1817 mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
1818 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1819
1820 /*
1821 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1822 * be set if you are using cache coherency.
1823 */
1824 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1825 mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf);
1826
1827 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1828 if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
1829 mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
1830
1831 save_exclude = mv64x60_pci_exclude_bridge;
1832 mv64x60_pci_exclude_bridge = 0;
1833 if (si->pci_0.enable_bus) {
1834 early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1835 PCI_COMMAND, &val);
1836 val |= PCI_COMMAND_INVALIDATE;
1837 early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
1838 PCI_COMMAND, val);
1839 }
1840
1841 if (si->pci_1.enable_bus) {
1842 early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1843 PCI_COMMAND, &val);
1844 val |= PCI_COMMAND_INVALIDATE;
1845 early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
1846 PCI_COMMAND, val);
1847 }
1848 mv64x60_pci_exclude_bridge = save_exclude;
1849 #endif
1850
1851 /* Disable buffer/descriptor snooping */
1852 mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1853 mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1854
1855 #ifdef CONFIG_SERIAL_MPSC
1856 /*
1857 * The 64260B is not supposed to have the bug where the MPSC & ENET
1858 * can't access cache coherent regions. However, testing has shown
1859 * that the MPSC, at least, still has this bug.
1860 */
1861 mv64x60_mpsc0_pdata.cache_mgmt = 1;
1862 mv64x60_mpsc1_pdata.cache_mgmt = 1;
1863
1864 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1865 != NULL) {
1866
1867 r->start = MV64x60_IRQ_SDMA_0;
1868 r->end = MV64x60_IRQ_SDMA_0;
1869 }
1870 #endif
1871
1872 return;
1873 }
1874
1875 /*
1876 *****************************************************************************
1877 *
1878 * MV64360-Specific Routines
1879 *
1880 *****************************************************************************
1881 */
1882 /*
1883 * mv64360_translate_size()
1884 *
1885 * On the MV64360, the size register is set similar to the size you get
1886 * from a pci config space BAR register. That is, programmed from LSB to MSB
1887 * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
1888 * assumption that the size is a power of 2.
1889 */
1890 static u32 __init
1891 mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits)
1892 {
1893 return mv64x60_mask(size - 1, num_bits);
1894 }
1895
1896 /*
1897 * mv64360_untranslate_size()
1898 *
1899 * Translate the size register value of a window into a window size.
1900 */
1901 static u32 __init
1902 mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits)
1903 {
1904 if (size > 0) {
1905 size >>= (32 - num_bits);
1906 size++;
1907 size <<= (32 - num_bits);
1908 }
1909
1910 return size;
1911 }
1912
1913 /*
1914 * mv64360_set_pci2mem_window()
1915 *
1916 * The PCI->MEM window registers are actually in PCI config space so need
1917 * to set them by setting the correct config space BARs.
1918 */
1919 struct {
1920 u32 fcn;
1921 u32 base_hi_bar;
1922 u32 base_lo_bar;
1923 } static mv64360_reg_addrs[2][4] __initdata = {
1924 {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
1925 { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
1926 {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
1927 { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
1928 };
1929
1930 static void __init
1931 mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1932 u32 base)
1933 {
1934 u8 save_exclude;
1935
1936 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
1937 hose->index, base);
1938
1939 save_exclude = mv64x60_pci_exclude_bridge;
1940 mv64x60_pci_exclude_bridge = 0;
1941 early_write_config_dword(hose, 0,
1942 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1943 mv64360_reg_addrs[bus][window].base_hi_bar, 0);
1944 early_write_config_dword(hose, 0,
1945 PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
1946 mv64360_reg_addrs[bus][window].base_lo_bar,
1947 mv64x60_mask(base,20) | 0xc);
1948 mv64x60_pci_exclude_bridge = save_exclude;
1949
1950 return;
1951 }
1952
1953 /*
1954 * mv64360_set_pci2regs_window()
1955 *
1956 * Set where the bridge's registers appear in PCI MEM space.
1957 */
1958 static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}};
1959
1960 static void __init
1961 mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
1962 struct pci_controller *hose, u32 bus, u32 base)
1963 {
1964 u8 save_exclude;
1965
1966 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
1967 base);
1968
1969 save_exclude = mv64x60_pci_exclude_bridge;
1970 mv64x60_pci_exclude_bridge = 0;
1971 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1972 mv64360_offset[bus][0], (base << 16));
1973 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1974 mv64360_offset[bus][1], 0);
1975 mv64x60_pci_exclude_bridge = save_exclude;
1976
1977 return;
1978 }
1979
1980 /*
1981 * mv64360_is_enabled_32bit()
1982 *
1983 * On a MV64360, a window is enabled by either clearing a bit in the
1984 * CPU BAR Enable reg or setting a bit in the window's base reg.
1985 * Note that this doesn't work for windows on the PCI slave side but we don't
1986 * check those so its okay.
1987 */
1988 static u32 __init
1989 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
1990 {
1991 u32 extra, rc = 0;
1992
1993 if (((mv64360_32bit_windows[window].base_reg != 0) &&
1994 (mv64360_32bit_windows[window].size_reg != 0)) ||
1995 (window == MV64x60_CPU2SRAM_WIN)) {
1996
1997 extra = mv64360_32bit_windows[window].extra;
1998
1999 switch (extra & MV64x60_EXTRA_MASK) {
2000 case MV64x60_EXTRA_CPUWIN_ENAB:
2001 rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) &
2002 (1 << (extra & 0x1f))) == 0;
2003 break;
2004
2005 case MV64x60_EXTRA_CPUPROT_ENAB:
2006 rc = (mv64x60_read(bh,
2007 mv64360_32bit_windows[window].base_reg) &
2008 (1 << (extra & 0x1f))) != 0;
2009 break;
2010
2011 case MV64x60_EXTRA_ENET_ENAB:
2012 rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) &
2013 (1 << (extra & 0x7))) == 0;
2014 break;
2015
2016 case MV64x60_EXTRA_MPSC_ENAB:
2017 rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) &
2018 (1 << (extra & 0x3))) == 0;
2019 break;
2020
2021 case MV64x60_EXTRA_IDMA_ENAB:
2022 rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) &
2023 (1 << (extra & 0x7))) == 0;
2024 break;
2025
2026 default:
2027 printk(KERN_ERR "mv64360_is_enabled: %s\n",
2028 "32bit table corrupted");
2029 }
2030 }
2031
2032 return rc;
2033 }
2034
2035 /*
2036 * mv64360_enable_window_32bit()
2037 *
2038 * On a MV64360, a window is enabled by either clearing a bit in the
2039 * CPU BAR Enable reg or setting a bit in the window's base reg.
2040 */
2041 static void __init
2042 mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
2043 {
2044 u32 extra;
2045
2046 pr_debug("enable 32bit window: %d\n", window);
2047
2048 if (((mv64360_32bit_windows[window].base_reg != 0) &&
2049 (mv64360_32bit_windows[window].size_reg != 0)) ||
2050 (window == MV64x60_CPU2SRAM_WIN)) {
2051
2052 extra = mv64360_32bit_windows[window].extra;
2053
2054 switch (extra & MV64x60_EXTRA_MASK) {
2055 case MV64x60_EXTRA_CPUWIN_ENAB:
2056 mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE,
2057 (1 << (extra & 0x1f)));
2058 break;
2059
2060 case MV64x60_EXTRA_CPUPROT_ENAB:
2061 mv64x60_set_bits(bh,
2062 mv64360_32bit_windows[window].base_reg,
2063 (1 << (extra & 0x1f)));
2064 break;
2065
2066 case MV64x60_EXTRA_ENET_ENAB:
2067 mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2068 (1 << (extra & 0x7)));
2069 break;
2070
2071 case MV64x60_EXTRA_MPSC_ENAB:
2072 mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2073 (1 << (extra & 0x3)));
2074 break;
2075
2076 case MV64x60_EXTRA_IDMA_ENAB:
2077 mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2078 (1 << (extra & 0x7)));
2079 break;
2080
2081 default:
2082 printk(KERN_ERR "mv64360_enable: %s\n",
2083 "32bit table corrupted");
2084 }
2085 }
2086
2087 return;
2088 }
2089
2090 /*
2091 * mv64360_disable_window_32bit()
2092 *
2093 * On a MV64360, a window is disabled by either setting a bit in the
2094 * CPU BAR Enable reg or clearing a bit in the window's base reg.
2095 */
2096 static void __init
2097 mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
2098 {
2099 u32 extra;
2100
2101 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2102 window, mv64360_32bit_windows[window].base_reg,
2103 mv64360_32bit_windows[window].size_reg);
2104
2105 if (((mv64360_32bit_windows[window].base_reg != 0) &&
2106 (mv64360_32bit_windows[window].size_reg != 0)) ||
2107 (window == MV64x60_CPU2SRAM_WIN)) {
2108
2109 extra = mv64360_32bit_windows[window].extra;
2110
2111 switch (extra & MV64x60_EXTRA_MASK) {
2112 case MV64x60_EXTRA_CPUWIN_ENAB:
2113 mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE,
2114 (1 << (extra & 0x1f)));
2115 break;
2116
2117 case MV64x60_EXTRA_CPUPROT_ENAB:
2118 mv64x60_clr_bits(bh,
2119 mv64360_32bit_windows[window].base_reg,
2120 (1 << (extra & 0x1f)));
2121 break;
2122
2123 case MV64x60_EXTRA_ENET_ENAB:
2124 mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
2125 (1 << (extra & 0x7)));
2126 break;
2127
2128 case MV64x60_EXTRA_MPSC_ENAB:
2129 mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
2130 (1 << (extra & 0x3)));
2131 break;
2132
2133 case MV64x60_EXTRA_IDMA_ENAB:
2134 mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
2135 (1 << (extra & 0x7)));
2136 break;
2137
2138 default:
2139 printk(KERN_ERR "mv64360_disable: %s\n",
2140 "32bit table corrupted");
2141 }
2142 }
2143
2144 return;
2145 }
2146
2147 /*
2148 * mv64360_enable_window_64bit()
2149 *
2150 * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2151 * base reg.
2152 */
2153 static void __init
2154 mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
2155 {
2156 pr_debug("enable 64bit window: %d\n", window);
2157
2158 if ((mv64360_64bit_windows[window].base_lo_reg!= 0) &&
2159 (mv64360_64bit_windows[window].size_reg != 0)) {
2160
2161 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2162 == MV64x60_EXTRA_PCIACC_ENAB)
2163
2164 mv64x60_set_bits(bh,
2165 mv64360_64bit_windows[window].base_lo_reg,
2166 (1 << (mv64360_64bit_windows[window].extra &
2167 0x1f)));
2168 else
2169 printk(KERN_ERR "mv64360_enable: %s\n",
2170 "64bit table corrupted");
2171 }
2172
2173 return;
2174 }
2175
2176 /*
2177 * mv64360_disable_window_64bit()
2178 *
2179 * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2180 * base reg.
2181 */
2182 static void __init
2183 mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
2184 {
2185 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2186 window, mv64360_64bit_windows[window].base_lo_reg,
2187 mv64360_64bit_windows[window].size_reg);
2188
2189 if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
2190 (mv64360_64bit_windows[window].size_reg != 0)) {
2191
2192 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2193 == MV64x60_EXTRA_PCIACC_ENAB)
2194
2195 mv64x60_clr_bits(bh,
2196 mv64360_64bit_windows[window].base_lo_reg,
2197 (1 << (mv64360_64bit_windows[window].extra &
2198 0x1f)));
2199 else
2200 printk(KERN_ERR "mv64360_disable: %s\n",
2201 "64bit table corrupted");
2202 }
2203
2204 return;
2205 }
2206
2207 /*
2208 * mv64360_disable_all_windows()
2209 *
2210 * The MV64360 has a few windows that aren't represented in the table of
2211 * windows at the top of this file. This routine turns all of them off
2212 * except for the memory controller windows, of course.
2213 */
2214 static void __init
2215 mv64360_disable_all_windows(struct mv64x60_handle *bh,
2216 struct mv64x60_setup_info *si)
2217 {
2218 u32 preserve, i;
2219
2220 /* Disable 32bit windows (don't disable cpu->mem windows) */
2221 for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
2222 if (i < 32)
2223 preserve = si->window_preserve_mask_32_lo & (1 << i);
2224 else
2225 preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
2226
2227 if (!preserve)
2228 mv64360_disable_window_32bit(bh, i);
2229 }
2230
2231 /* Disable 64bit windows */
2232 for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
2233 if (!(si->window_preserve_mask_64 & (1<<i)))
2234 mv64360_disable_window_64bit(bh, i);
2235
2236 /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2237 mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0);
2238 mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0);
2239 mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0);
2240 mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0);
2241
2242 /* Disable all PCI-><whatever> windows */
2243 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
2244 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
2245
2246 return;
2247 }
2248
2249 /*
2250 * mv64360_config_io2mem_windows()
2251 *
2252 * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
2253 * must be set up so that the respective ctlr can access system memory.
2254 */
2255 static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2256 MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN,
2257 MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN,
2258 };
2259
2260 static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2261 MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN,
2262 MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN,
2263 };
2264
2265 static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
2266 MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN,
2267 MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN,
2268 };
2269
2270 static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata =
2271 { 0xe, 0xd, 0xb, 0x7 };
2272
2273 static void __init
2274 mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
2275 struct mv64x60_setup_info *si,
2276 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
2277 {
2278 u32 i, win;
2279
2280 pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
2281
2282 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0);
2283 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0);
2284 mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0);
2285
2286 mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0);
2287 mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0);
2288
2289 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0);
2290 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0);
2291 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0);
2292 mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0);
2293
2294 /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
2295 for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
2296 if (bh->ci->is_enabled_32bit(bh, win)) {
2297 mv64x60_set_32bit_window(bh, enet_tab[i],
2298 mem_windows[i][0], mem_windows[i][1],
2299 (dram_selects[i] << 8) |
2300 (si->enet_options[i] & 0x3000));
2301 bh->ci->enable_window_32bit(bh, enet_tab[i]);
2302
2303 /* Give enet r/w access to memory region */
2304 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0,
2305 (0x3 << (i << 1)));
2306 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1,
2307 (0x3 << (i << 1)));
2308 mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2,
2309 (0x3 << (i << 1)));
2310
2311 mv64x60_set_32bit_window(bh, mpsc_tab[i],
2312 mem_windows[i][0], mem_windows[i][1],
2313 (dram_selects[i] << 8) |
2314 (si->mpsc_options[i] & 0x3000));
2315 bh->ci->enable_window_32bit(bh, mpsc_tab[i]);
2316
2317 /* Give mpsc r/w access to memory region */
2318 mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0,
2319 (0x3 << (i << 1)));
2320 mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1,
2321 (0x3 << (i << 1)));
2322
2323 mv64x60_set_32bit_window(bh, idma_tab[i],
2324 mem_windows[i][0], mem_windows[i][1],
2325 (dram_selects[i] << 8) |
2326 (si->idma_options[i] & 0x3000));
2327 bh->ci->enable_window_32bit(bh, idma_tab[i]);
2328
2329 /* Give idma r/w access to memory region */
2330 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0,
2331 (0x3 << (i << 1)));
2332 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1,
2333 (0x3 << (i << 1)));
2334 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2,
2335 (0x3 << (i << 1)));
2336 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3,
2337 (0x3 << (i << 1)));
2338 }
2339
2340 return;
2341 }
2342
2343 /*
2344 * mv64360_set_mpsc2regs_window()
2345 *
2346 * MPSC has a window to the bridge's internal registers. Call this routine
2347 * to change that window so it doesn't conflict with the windows mapping the
2348 * mpsc to system memory.
2349 */
2350 static void __init
2351 mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base)
2352 {
2353 pr_debug("set mpsc->internal regs, base: 0x%x\n", base);
2354
2355 mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000);
2356 return;
2357 }
2358
2359 /*
2360 * mv64360_chip_specific_init()
2361 *
2362 * No errata work arounds for the MV64360 implemented at this point.
2363 */
2364 static void __init
2365 mv64360_chip_specific_init(struct mv64x60_handle *bh,
2366 struct mv64x60_setup_info *si)
2367 {
2368 #ifdef CONFIG_SERIAL_MPSC
2369 mv64x60_mpsc0_pdata.brg_can_tune = 1;
2370 mv64x60_mpsc0_pdata.cache_mgmt = 1;
2371 mv64x60_mpsc1_pdata.brg_can_tune = 1;
2372 mv64x60_mpsc1_pdata.cache_mgmt = 1;
2373 #endif
2374
2375 return;
2376 }
2377
2378 /*
2379 * mv64460_chip_specific_init()
2380 *
2381 * No errata work arounds for the MV64460 implemented at this point.
2382 */
2383 static void __init
2384 mv64460_chip_specific_init(struct mv64x60_handle *bh,
2385 struct mv64x60_setup_info *si)
2386 {
2387 #ifdef CONFIG_SERIAL_MPSC
2388 mv64x60_mpsc0_pdata.brg_can_tune = 1;
2389 mv64x60_mpsc1_pdata.brg_can_tune = 1;
2390 #endif
2391 return;
2392 }
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