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Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/gregkh/driver...
[linux-2.6/verdex.git] / arch / sparc64 / kernel / pci_sabre.c
blob5525d1ec4af883884404d13b17ddc6deda8379f5
1 /* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
2 * pci_sabre.c: Sabre specific PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/interrupt.h>
15
16 #include <asm/apb.h>
17 #include <asm/pbm.h>
18 #include <asm/iommu.h>
19 #include <asm/irq.h>
20 #include <asm/smp.h>
21 #include <asm/oplib.h>
22
23 #include "pci_impl.h"
24 #include "iommu_common.h"
25
26 /* All SABRE registers are 64-bits. The following accessor
27 * routines are how they are accessed. The REG parameter
28 * is a physical address.
29 */
30 #define sabre_read(__reg) \
31 ({ u64 __ret; \
32 __asm__ __volatile__("ldxa [%1] %2, %0" \
33 : "=r" (__ret) \
34 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
35 : "memory"); \
36 __ret; \
37 })
38 #define sabre_write(__reg, __val) \
39 __asm__ __volatile__("stxa %0, [%1] %2" \
40 : /* no outputs */ \
41 : "r" (__val), "r" (__reg), \
42 "i" (ASI_PHYS_BYPASS_EC_E) \
43 : "memory")
44
45 /* SABRE PCI controller register offsets and definitions. */
46 #define SABRE_UE_AFSR 0x0030UL
47 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
48 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
49 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
50 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
51 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
52 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
53 #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
54 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
55 #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
56 #define SABRE_UECE_AFAR 0x0038UL
57 #define SABRE_CE_AFSR 0x0040UL
58 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
59 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
60 #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
61 #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
62 #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */
63 #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
64 #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */
65 #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */
66 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
67 #define SABRE_IOMMU_CONTROL 0x0200UL
68 #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */
69 #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */
70 #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */
71 #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */
72 #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
73 #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000
74 #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000
75 #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000
76 #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000
77 #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000
78 #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000
79 #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000
80 #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
81 #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */
82 #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
83 #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
84 #define SABRE_IOMMU_TSBBASE 0x0208UL
85 #define SABRE_IOMMU_FLUSH 0x0210UL
86 #define SABRE_IMAP_A_SLOT0 0x0c00UL
87 #define SABRE_IMAP_B_SLOT0 0x0c20UL
88 #define SABRE_IMAP_SCSI 0x1000UL
89 #define SABRE_IMAP_ETH 0x1008UL
90 #define SABRE_IMAP_BPP 0x1010UL
91 #define SABRE_IMAP_AU_REC 0x1018UL
92 #define SABRE_IMAP_AU_PLAY 0x1020UL
93 #define SABRE_IMAP_PFAIL 0x1028UL
94 #define SABRE_IMAP_KMS 0x1030UL
95 #define SABRE_IMAP_FLPY 0x1038UL
96 #define SABRE_IMAP_SHW 0x1040UL
97 #define SABRE_IMAP_KBD 0x1048UL
98 #define SABRE_IMAP_MS 0x1050UL
99 #define SABRE_IMAP_SER 0x1058UL
100 #define SABRE_IMAP_UE 0x1070UL
101 #define SABRE_IMAP_CE 0x1078UL
102 #define SABRE_IMAP_PCIERR 0x1080UL
103 #define SABRE_IMAP_GFX 0x1098UL
104 #define SABRE_IMAP_EUPA 0x10a0UL
105 #define SABRE_ICLR_A_SLOT0 0x1400UL
106 #define SABRE_ICLR_B_SLOT0 0x1480UL
107 #define SABRE_ICLR_SCSI 0x1800UL
108 #define SABRE_ICLR_ETH 0x1808UL
109 #define SABRE_ICLR_BPP 0x1810UL
110 #define SABRE_ICLR_AU_REC 0x1818UL
111 #define SABRE_ICLR_AU_PLAY 0x1820UL
112 #define SABRE_ICLR_PFAIL 0x1828UL
113 #define SABRE_ICLR_KMS 0x1830UL
114 #define SABRE_ICLR_FLPY 0x1838UL
115 #define SABRE_ICLR_SHW 0x1840UL
116 #define SABRE_ICLR_KBD 0x1848UL
117 #define SABRE_ICLR_MS 0x1850UL
118 #define SABRE_ICLR_SER 0x1858UL
119 #define SABRE_ICLR_UE 0x1870UL
120 #define SABRE_ICLR_CE 0x1878UL
121 #define SABRE_ICLR_PCIERR 0x1880UL
122 #define SABRE_WRSYNC 0x1c20UL
123 #define SABRE_PCICTRL 0x2000UL
124 #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */
125 #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */
126 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
127 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
128 #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */
129 #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */
130 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */
131 #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */
132 #define SABRE_PIOAFSR 0x2010UL
133 #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */
134 #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */
135 #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
136 #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
137 #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
138 #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
139 #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
140 #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
141 #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */
142 #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */
143 #define SABRE_PIOAFAR 0x2018UL
144 #define SABRE_PCIDIAG 0x2020UL
145 #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */
146 #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */
147 #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */
148 #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */
149 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
150 #define SABRE_PCITASR 0x2028UL
151 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
152 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
153 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
154 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
155 #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
156 #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */
157 #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */
158 #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */
159 #define SABRE_PIOBUF_DIAG 0x5000UL
160 #define SABRE_DMABUF_DIAGLO 0x5100UL
161 #define SABRE_DMABUF_DIAGHI 0x51c0UL
162 #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */
163 #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */
164 #define SABRE_IOMMU_VADIAG 0xa400UL
165 #define SABRE_IOMMU_TCDIAG 0xa408UL
166 #define SABRE_IOMMU_TAG 0xa580UL
167 #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */
168 #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */
169 #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */
170 #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */
171 #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */
172 #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */
173 #define SABRE_IOMMU_DATA 0xa600UL
174 #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */
175 #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */
176 #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */
177 #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */
178 #define SABRE_PCI_IRQSTATE 0xa800UL
179 #define SABRE_OBIO_IRQSTATE 0xa808UL
180 #define SABRE_FFBCFG 0xf000UL
181 #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */
182 #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */
183 #define SABRE_MCCTRL0 0xf010UL
184 #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */
185 #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */
186 #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */
187 #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */
188 #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */
189 #define SABRE_MCCTRL1 0xf018UL
190 #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */
191 #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */
192 #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
193 #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */
194 #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */
195 #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */
196 #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */
197 #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */
198 #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */
199 #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */
200 #define SABRE_RESETCTRL 0xf020UL
201
202 #define SABRE_CONFIGSPACE 0x001000000UL
203 #define SABRE_IOSPACE 0x002000000UL
204 #define SABRE_IOSPACE_SIZE 0x000ffffffUL
205 #define SABRE_MEMSPACE 0x100000000UL
206 #define SABRE_MEMSPACE_SIZE 0x07fffffffUL
207
208 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
209 * configuration space address format:
210 *
211 * 32 24 23 16 15 11 10 8 7 2 1 0
212 * ---------------------------------------------------------
213 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
214 * ---------------------------------------------------------
215 */
216 #define SABRE_CONFIG_BASE(PBM) \
217 ((PBM)->config_space | (1UL << 24))
218 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
219 (((unsigned long)(BUS) << 16) | \
220 ((unsigned long)(DEVFN) << 8) | \
221 ((unsigned long)(REG)))
222
223 static int hummingbird_p;
224 static struct pci_bus *sabre_root_bus;
225
226 static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
227 unsigned char bus,
228 unsigned int devfn,
229 int where)
230 {
231 if (!pbm)
232 return NULL;
233 return (void *)
234 (SABRE_CONFIG_BASE(pbm) |
235 SABRE_CONFIG_ENCODE(bus, devfn, where));
236 }
237
238 static int sabre_out_of_range(unsigned char devfn)
239 {
240 if (hummingbird_p)
241 return 0;
242
243 return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
244 ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
245 (PCI_SLOT(devfn) > 1));
246 }
247
248 static int __sabre_out_of_range(struct pci_pbm_info *pbm,
249 unsigned char bus,
250 unsigned char devfn)
251 {
252 if (hummingbird_p)
253 return 0;
254
255 return ((pbm->parent == 0) ||
256 ((pbm == &pbm->parent->pbm_B) &&
257 (bus == pbm->pci_first_busno) &&
258 PCI_SLOT(devfn) > 8) ||
259 ((pbm == &pbm->parent->pbm_A) &&
260 (bus == pbm->pci_first_busno) &&
261 PCI_SLOT(devfn) > 8));
262 }
263
264 static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
265 int where, int size, u32 *value)
266 {
267 struct pci_pbm_info *pbm = bus_dev->sysdata;
268 unsigned char bus = bus_dev->number;
269 u32 *addr;
270 u16 tmp16;
271 u8 tmp8;
272
273 switch (size) {
274 case 1:
275 *value = 0xff;
276 break;
277 case 2:
278 *value = 0xffff;
279 break;
280 case 4:
281 *value = 0xffffffff;
282 break;
283 }
284
285 addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
286 if (!addr)
287 return PCIBIOS_SUCCESSFUL;
288
289 if (__sabre_out_of_range(pbm, bus, devfn))
290 return PCIBIOS_SUCCESSFUL;
291
292 switch (size) {
293 case 1:
294 pci_config_read8((u8 *) addr, &tmp8);
295 *value = tmp8;
296 break;
297
298 case 2:
299 if (where & 0x01) {
300 printk("pci_read_config_word: misaligned reg [%x]\n",
301 where);
302 return PCIBIOS_SUCCESSFUL;
303 }
304 pci_config_read16((u16 *) addr, &tmp16);
305 *value = tmp16;
306 break;
307
308 case 4:
309 if (where & 0x03) {
310 printk("pci_read_config_dword: misaligned reg [%x]\n",
311 where);
312 return PCIBIOS_SUCCESSFUL;
313 }
314 pci_config_read32(addr, value);
315 break;
316 }
317
318 return PCIBIOS_SUCCESSFUL;
319 }
320
321 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
322 int where, int size, u32 *value)
323 {
324 if (!bus->number && sabre_out_of_range(devfn)) {
325 switch (size) {
326 case 1:
327 *value = 0xff;
328 break;
329 case 2:
330 *value = 0xffff;
331 break;
332 case 4:
333 *value = 0xffffffff;
334 break;
335 }
336 return PCIBIOS_SUCCESSFUL;
337 }
338
339 if (bus->number || PCI_SLOT(devfn))
340 return __sabre_read_pci_cfg(bus, devfn, where, size, value);
341
342 /* When accessing PCI config space of the PCI controller itself (bus
343 * 0, device slot 0, function 0) there are restrictions. Each
344 * register must be accessed as it's natural size. Thus, for example
345 * the Vendor ID must be accessed as a 16-bit quantity.
346 */
347
348 switch (size) {
349 case 1:
350 if (where < 8) {
351 u32 tmp32;
352 u16 tmp16;
353
354 __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
355 tmp16 = (u16) tmp32;
356 if (where & 1)
357 *value = tmp16 >> 8;
358 else
359 *value = tmp16 & 0xff;
360 } else
361 return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
362 break;
363
364 case 2:
365 if (where < 8)
366 return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
367 else {
368 u32 tmp32;
369 u8 tmp8;
370
371 __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
372 tmp8 = (u8) tmp32;
373 *value = tmp8;
374 __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
375 tmp8 = (u8) tmp32;
376 *value |= tmp8 << 8;
377 }
378 break;
379
380 case 4: {
381 u32 tmp32;
382 u16 tmp16;
383
384 sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
385 tmp16 = (u16) tmp32;
386 *value = tmp16;
387 sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
388 tmp16 = (u16) tmp32;
389 *value |= tmp16 << 16;
390 break;
391 }
392 }
393 return PCIBIOS_SUCCESSFUL;
394 }
395
396 static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
397 int where, int size, u32 value)
398 {
399 struct pci_pbm_info *pbm = bus_dev->sysdata;
400 unsigned char bus = bus_dev->number;
401 u32 *addr;
402
403 addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
404 if (!addr)
405 return PCIBIOS_SUCCESSFUL;
406
407 if (__sabre_out_of_range(pbm, bus, devfn))
408 return PCIBIOS_SUCCESSFUL;
409
410 switch (size) {
411 case 1:
412 pci_config_write8((u8 *) addr, value);
413 break;
414
415 case 2:
416 if (where & 0x01) {
417 printk("pci_write_config_word: misaligned reg [%x]\n",
418 where);
419 return PCIBIOS_SUCCESSFUL;
420 }
421 pci_config_write16((u16 *) addr, value);
422 break;
423
424 case 4:
425 if (where & 0x03) {
426 printk("pci_write_config_dword: misaligned reg [%x]\n",
427 where);
428 return PCIBIOS_SUCCESSFUL;
429 }
430 pci_config_write32(addr, value);
431 break;
432 }
433
434 return PCIBIOS_SUCCESSFUL;
435 }
436
437 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
438 int where, int size, u32 value)
439 {
440 if (bus->number)
441 return __sabre_write_pci_cfg(bus, devfn, where, size, value);
442
443 if (sabre_out_of_range(devfn))
444 return PCIBIOS_SUCCESSFUL;
445
446 switch (size) {
447 case 1:
448 if (where < 8) {
449 u32 tmp32;
450 u16 tmp16;
451
452 __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
453 tmp16 = (u16) tmp32;
454 if (where & 1) {
455 value &= 0x00ff;
456 value |= tmp16 << 8;
457 } else {
458 value &= 0xff00;
459 value |= tmp16;
460 }
461 tmp32 = (u32) tmp16;
462 return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
463 } else
464 return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
465 break;
466 case 2:
467 if (where < 8)
468 return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
469 else {
470 __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
471 __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
472 }
473 break;
474 case 4:
475 sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
476 sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
477 break;
478 }
479 return PCIBIOS_SUCCESSFUL;
480 }
481
482 static struct pci_ops sabre_ops = {
483 .read = sabre_read_pci_cfg,
484 .write = sabre_write_pci_cfg,
485 };
486
487 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
488 {
489 unsigned int bus = (ino & 0x10) >> 4;
490 unsigned int slot = (ino & 0x0c) >> 2;
491
492 if (bus == 0)
493 return SABRE_IMAP_A_SLOT0 + (slot * 8);
494 else
495 return SABRE_IMAP_B_SLOT0 + (slot * 8);
496 }
497
498 static unsigned long __onboard_imap_off[] = {
499 /*0x20*/ SABRE_IMAP_SCSI,
500 /*0x21*/ SABRE_IMAP_ETH,
501 /*0x22*/ SABRE_IMAP_BPP,
502 /*0x23*/ SABRE_IMAP_AU_REC,
503 /*0x24*/ SABRE_IMAP_AU_PLAY,
504 /*0x25*/ SABRE_IMAP_PFAIL,
505 /*0x26*/ SABRE_IMAP_KMS,
506 /*0x27*/ SABRE_IMAP_FLPY,
507 /*0x28*/ SABRE_IMAP_SHW,
508 /*0x29*/ SABRE_IMAP_KBD,
509 /*0x2a*/ SABRE_IMAP_MS,
510 /*0x2b*/ SABRE_IMAP_SER,
511 /*0x2c*/ 0 /* reserved */,
512 /*0x2d*/ 0 /* reserved */,
513 /*0x2e*/ SABRE_IMAP_UE,
514 /*0x2f*/ SABRE_IMAP_CE,
515 /*0x30*/ SABRE_IMAP_PCIERR,
516 };
517 #define SABRE_ONBOARD_IRQ_BASE 0x20
518 #define SABRE_ONBOARD_IRQ_LAST 0x30
519 #define sabre_onboard_imap_offset(__ino) \
520 __onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
521
522 #define sabre_iclr_offset(ino) \
523 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
524 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
525
526 /* PCI SABRE INO number to Sparc PIL level. */
527 static unsigned char sabre_pil_table[] = {
528 /*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
529 /*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
530 /*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
531 /*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
532 /*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
533 /*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
534 /*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
535 /*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
536 /*0x20*/4, /* SCSI */
537 /*0x21*/5, /* Ethernet */
538 /*0x22*/8, /* Parallel Port */
539 /*0x23*/13, /* Audio Record */
540 /*0x24*/14, /* Audio Playback */
541 /*0x25*/15, /* PowerFail */
542 /*0x26*/4, /* second SCSI */
543 /*0x27*/11, /* Floppy */
544 /*0x28*/4, /* Spare Hardware */
545 /*0x29*/9, /* Keyboard */
546 /*0x2a*/4, /* Mouse */
547 /*0x2b*/12, /* Serial */
548 /*0x2c*/10, /* Timer 0 */
549 /*0x2d*/11, /* Timer 1 */
550 /*0x2e*/15, /* Uncorrectable ECC */
551 /*0x2f*/15, /* Correctable ECC */
552 /*0x30*/15, /* PCI Bus A Error */
553 /*0x31*/15, /* PCI Bus B Error */
554 /*0x32*/15, /* Power Management */
555 };
556
557 static int __init sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
558 {
559 int ret;
560
561 if (pdev &&
562 pdev->vendor == PCI_VENDOR_ID_SUN &&
563 pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
564 return 9;
565
566 ret = sabre_pil_table[ino];
567 if (ret == 0 && pdev == NULL) {
568 ret = 4;
569 } else if (ret == 0) {
570 switch ((pdev->class >> 16) & 0xff) {
571 case PCI_BASE_CLASS_STORAGE:
572 ret = 4;
573 break;
574
575 case PCI_BASE_CLASS_NETWORK:
576 ret = 6;
577 break;
578
579 case PCI_BASE_CLASS_DISPLAY:
580 ret = 9;
581 break;
582
583 case PCI_BASE_CLASS_MULTIMEDIA:
584 case PCI_BASE_CLASS_MEMORY:
585 case PCI_BASE_CLASS_BRIDGE:
586 case PCI_BASE_CLASS_SERIAL:
587 ret = 10;
588 break;
589
590 default:
591 ret = 4;
592 break;
593 };
594 }
595 return ret;
596 }
597
598 static unsigned int __init sabre_irq_build(struct pci_pbm_info *pbm,
599 struct pci_dev *pdev,
600 unsigned int ino)
601 {
602 struct ino_bucket *bucket;
603 unsigned long imap, iclr;
604 unsigned long imap_off, iclr_off;
605 int pil, inofixup = 0;
606
607 ino &= PCI_IRQ_INO;
608 if (ino < SABRE_ONBOARD_IRQ_BASE) {
609 /* PCI slot */
610 imap_off = sabre_pcislot_imap_offset(ino);
611 } else {
612 /* onboard device */
613 if (ino > SABRE_ONBOARD_IRQ_LAST) {
614 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
615 prom_halt();
616 }
617 imap_off = sabre_onboard_imap_offset(ino);
618 }
619
620 /* Now build the IRQ bucket. */
621 pil = sabre_ino_to_pil(pdev, ino);
622
623 if (PIL_RESERVED(pil))
624 BUG();
625
626 imap = pbm->controller_regs + imap_off;
627 imap += 4;
628
629 iclr_off = sabre_iclr_offset(ino);
630 iclr = pbm->controller_regs + iclr_off;
631 iclr += 4;
632
633 if ((ino & 0x20) == 0)
634 inofixup = ino & 0x03;
635
636 bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
637 bucket->flags |= IBF_PCI;
638
639 if (pdev) {
640 struct pcidev_cookie *pcp = pdev->sysdata;
641
642 /* When a device lives behind a bridge deeper in the
643 * PCI bus topology than APB, a special sequence must
644 * run to make sure all pending DMA transfers at the
645 * time of IRQ delivery are visible in the coherency
646 * domain by the cpu. This sequence is to perform
647 * a read on the far side of the non-APB bridge, then
648 * perform a read of Sabre's DMA write-sync register.
649 *
650 * Currently, the PCI_CONFIG register for the device
651 * is used for this read from the far side of the bridge.
652 */
653 if (pdev->bus->number != pcp->pbm->pci_first_busno) {
654 bucket->flags |= IBF_DMA_SYNC;
655 bucket->synctab_ent = dma_sync_reg_table_entry++;
656 dma_sync_reg_table[bucket->synctab_ent] =
657 (unsigned long) sabre_pci_config_mkaddr(
658 pcp->pbm,
659 pdev->bus->number, pdev->devfn, PCI_COMMAND);
660 }
661 }
662 return __irq(bucket);
663 }
664
665 /* SABRE error handling support. */
666 static void sabre_check_iommu_error(struct pci_controller_info *p,
667 unsigned long afsr,
668 unsigned long afar)
669 {
670 struct pci_iommu *iommu = p->pbm_A.iommu;
671 unsigned long iommu_tag[16];
672 unsigned long iommu_data[16];
673 unsigned long flags;
674 u64 control;
675 int i;
676
677 spin_lock_irqsave(&iommu->lock, flags);
678 control = sabre_read(iommu->iommu_control);
679 if (control & SABRE_IOMMUCTRL_ERR) {
680 char *type_string;
681
682 /* Clear the error encountered bit.
683 * NOTE: On Sabre this is write 1 to clear,
684 * which is different from Psycho.
685 */
686 sabre_write(iommu->iommu_control, control);
687 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
688 case 1:
689 type_string = "Invalid Error";
690 break;
691 case 3:
692 type_string = "ECC Error";
693 break;
694 default:
695 type_string = "Unknown";
696 break;
697 };
698 printk("SABRE%d: IOMMU Error, type[%s]\n",
699 p->index, type_string);
700
701 /* Enter diagnostic mode and probe for error'd
702 * entries in the IOTLB.
703 */
704 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
705 sabre_write(iommu->iommu_control,
706 (control | SABRE_IOMMUCTRL_DENAB));
707 for (i = 0; i < 16; i++) {
708 unsigned long base = p->pbm_A.controller_regs;
709
710 iommu_tag[i] =
711 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
712 iommu_data[i] =
713 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
714 sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
715 sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
716 }
717 sabre_write(iommu->iommu_control, control);
718
719 for (i = 0; i < 16; i++) {
720 unsigned long tag, data;
721
722 tag = iommu_tag[i];
723 if (!(tag & SABRE_IOMMUTAG_ERR))
724 continue;
725
726 data = iommu_data[i];
727 switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
728 case 1:
729 type_string = "Invalid Error";
730 break;
731 case 3:
732 type_string = "ECC Error";
733 break;
734 default:
735 type_string = "Unknown";
736 break;
737 };
738 printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
739 p->index, i, tag, type_string,
740 ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
741 ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
742 ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
743 printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
744 p->index, i, data,
745 ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
746 ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
747 ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
748 ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
749 }
750 }
751 spin_unlock_irqrestore(&iommu->lock, flags);
752 }
753
754 static irqreturn_t sabre_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
755 {
756 struct pci_controller_info *p = dev_id;
757 unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
758 unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
759 unsigned long afsr, afar, error_bits;
760 int reported;
761
762 /* Latch uncorrectable error status. */
763 afar = sabre_read(afar_reg);
764 afsr = sabre_read(afsr_reg);
765
766 /* Clear the primary/secondary error status bits. */
767 error_bits = afsr &
768 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
769 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
770 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
771 if (!error_bits)
772 return IRQ_NONE;
773 sabre_write(afsr_reg, error_bits);
774
775 /* Log the error. */
776 printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
777 p->index,
778 ((error_bits & SABRE_UEAFSR_PDRD) ?
779 "DMA Read" :
780 ((error_bits & SABRE_UEAFSR_PDWR) ?
781 "DMA Write" : "???")),
782 ((error_bits & SABRE_UEAFSR_PDTE) ?
783 ":Translation Error" : ""));
784 printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
785 p->index,
786 (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
787 (afsr & SABRE_UEAFSR_OFF) >> 29UL,
788 ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
789 printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
790 printk("SABRE%d: UE Secondary errors [", p->index);
791 reported = 0;
792 if (afsr & SABRE_UEAFSR_SDRD) {
793 reported++;
794 printk("(DMA Read)");
795 }
796 if (afsr & SABRE_UEAFSR_SDWR) {
797 reported++;
798 printk("(DMA Write)");
799 }
800 if (afsr & SABRE_UEAFSR_SDTE) {
801 reported++;
802 printk("(Translation Error)");
803 }
804 if (!reported)
805 printk("(none)");
806 printk("]\n");
807
808 /* Interrogate IOMMU for error status. */
809 sabre_check_iommu_error(p, afsr, afar);
810
811 return IRQ_HANDLED;
812 }
813
814 static irqreturn_t sabre_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
815 {
816 struct pci_controller_info *p = dev_id;
817 unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
818 unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
819 unsigned long afsr, afar, error_bits;
820 int reported;
821
822 /* Latch error status. */
823 afar = sabre_read(afar_reg);
824 afsr = sabre_read(afsr_reg);
825
826 /* Clear primary/secondary error status bits. */
827 error_bits = afsr &
828 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
829 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
830 if (!error_bits)
831 return IRQ_NONE;
832 sabre_write(afsr_reg, error_bits);
833
834 /* Log the error. */
835 printk("SABRE%d: Correctable Error, primary error type[%s]\n",
836 p->index,
837 ((error_bits & SABRE_CEAFSR_PDRD) ?
838 "DMA Read" :
839 ((error_bits & SABRE_CEAFSR_PDWR) ?
840 "DMA Write" : "???")));
841
842 /* XXX Use syndrome and afar to print out module string just like
843 * XXX UDB CE trap handler does... -DaveM
844 */
845 printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
846 "was_block(%d)\n",
847 p->index,
848 (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
849 (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
850 (afsr & SABRE_CEAFSR_OFF) >> 29UL,
851 ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
852 printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
853 printk("SABRE%d: CE Secondary errors [", p->index);
854 reported = 0;
855 if (afsr & SABRE_CEAFSR_SDRD) {
856 reported++;
857 printk("(DMA Read)");
858 }
859 if (afsr & SABRE_CEAFSR_SDWR) {
860 reported++;
861 printk("(DMA Write)");
862 }
863 if (!reported)
864 printk("(none)");
865 printk("]\n");
866
867 return IRQ_HANDLED;
868 }
869
870 static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
871 {
872 unsigned long csr_reg, csr, csr_error_bits;
873 irqreturn_t ret = IRQ_NONE;
874 u16 stat;
875
876 csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
877 csr = sabre_read(csr_reg);
878 csr_error_bits =
879 csr & SABRE_PCICTRL_SERR;
880 if (csr_error_bits) {
881 /* Clear the errors. */
882 sabre_write(csr_reg, csr);
883
884 /* Log 'em. */
885 if (csr_error_bits & SABRE_PCICTRL_SERR)
886 printk("SABRE%d: PCI SERR signal asserted.\n",
887 p->index);
888 ret = IRQ_HANDLED;
889 }
890 pci_read_config_word(sabre_root_bus->self,
891 PCI_STATUS, &stat);
892 if (stat & (PCI_STATUS_PARITY |
893 PCI_STATUS_SIG_TARGET_ABORT |
894 PCI_STATUS_REC_TARGET_ABORT |
895 PCI_STATUS_REC_MASTER_ABORT |
896 PCI_STATUS_SIG_SYSTEM_ERROR)) {
897 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
898 p->index, stat);
899 pci_write_config_word(sabre_root_bus->self,
900 PCI_STATUS, 0xffff);
901 ret = IRQ_HANDLED;
902 }
903 return ret;
904 }
905
906 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
907 {
908 struct pci_controller_info *p = dev_id;
909 unsigned long afsr_reg, afar_reg;
910 unsigned long afsr, afar, error_bits;
911 int reported;
912
913 afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
914 afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
915
916 /* Latch error status. */
917 afar = sabre_read(afar_reg);
918 afsr = sabre_read(afsr_reg);
919
920 /* Clear primary/secondary error status bits. */
921 error_bits = afsr &
922 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
923 SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
924 SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
925 SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
926 if (!error_bits)
927 return sabre_pcierr_intr_other(p);
928 sabre_write(afsr_reg, error_bits);
929
930 /* Log the error. */
931 printk("SABRE%d: PCI Error, primary error type[%s]\n",
932 p->index,
933 (((error_bits & SABRE_PIOAFSR_PMA) ?
934 "Master Abort" :
935 ((error_bits & SABRE_PIOAFSR_PTA) ?
936 "Target Abort" :
937 ((error_bits & SABRE_PIOAFSR_PRTRY) ?
938 "Excessive Retries" :
939 ((error_bits & SABRE_PIOAFSR_PPERR) ?
940 "Parity Error" : "???"))))));
941 printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
942 p->index,
943 (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
944 (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
945 printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
946 printk("SABRE%d: PCI Secondary errors [", p->index);
947 reported = 0;
948 if (afsr & SABRE_PIOAFSR_SMA) {
949 reported++;
950 printk("(Master Abort)");
951 }
952 if (afsr & SABRE_PIOAFSR_STA) {
953 reported++;
954 printk("(Target Abort)");
955 }
956 if (afsr & SABRE_PIOAFSR_SRTRY) {
957 reported++;
958 printk("(Excessive Retries)");
959 }
960 if (afsr & SABRE_PIOAFSR_SPERR) {
961 reported++;
962 printk("(Parity Error)");
963 }
964 if (!reported)
965 printk("(none)");
966 printk("]\n");
967
968 /* For the error types shown, scan both PCI buses for devices
969 * which have logged that error type.
970 */
971
972 /* If we see a Target Abort, this could be the result of an
973 * IOMMU translation error of some sort. It is extremely
974 * useful to log this information as usually it indicates
975 * a bug in the IOMMU support code or a PCI device driver.
976 */
977 if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
978 sabre_check_iommu_error(p, afsr, afar);
979 pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
980 pci_scan_for_target_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
981 }
982 if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) {
983 pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
984 pci_scan_for_master_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
985 }
986 /* For excessive retries, SABRE/PBM will abort the device
987 * and there is no way to specifically check for excessive
988 * retries in the config space status registers. So what
989 * we hope is that we'll catch it via the master/target
990 * abort events.
991 */
992
993 if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) {
994 pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
995 pci_scan_for_parity_error(p, &p->pbm_B, p->pbm_B.pci_bus);
996 }
997
998 return IRQ_HANDLED;
999 }
1000
1001 /* XXX What about PowerFail/PowerManagement??? -DaveM */
1002 #define SABRE_UE_INO 0x2e
1003 #define SABRE_CE_INO 0x2f
1004 #define SABRE_PCIERR_INO 0x30
1005 static void __init sabre_register_error_handlers(struct pci_controller_info *p)
1006 {
1007 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
1008 unsigned long base = pbm->controller_regs;
1009 unsigned long irq, portid = pbm->portid;
1010 u64 tmp;
1011
1012 /* We clear the error bits in the appropriate AFSR before
1013 * registering the handler so that we don't get spurious
1014 * interrupts.
1015 */
1016 sabre_write(base + SABRE_UE_AFSR,
1017 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
1018 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
1019 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
1020 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_UE_INO);
1021 if (request_irq(irq, sabre_ue_intr,
1022 SA_SHIRQ, "SABRE UE", p) < 0) {
1023 prom_printf("SABRE%d: Cannot register UE interrupt.\n",
1024 p->index);
1025 prom_halt();
1026 }
1027
1028 sabre_write(base + SABRE_CE_AFSR,
1029 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
1030 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
1031 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_CE_INO);
1032 if (request_irq(irq, sabre_ce_intr,
1033 SA_SHIRQ, "SABRE CE", p) < 0) {
1034 prom_printf("SABRE%d: Cannot register CE interrupt.\n",
1035 p->index);
1036 prom_halt();
1037 }
1038
1039 irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_PCIERR_INO);
1040 if (request_irq(irq, sabre_pcierr_intr,
1041 SA_SHIRQ, "SABRE PCIERR", p) < 0) {
1042 prom_printf("SABRE%d: Cannot register PciERR interrupt.\n",
1043 p->index);
1044 prom_halt();
1045 }
1046
1047 tmp = sabre_read(base + SABRE_PCICTRL);
1048 tmp |= SABRE_PCICTRL_ERREN;
1049 sabre_write(base + SABRE_PCICTRL, tmp);
1050 }
1051
1052 static void __init sabre_resource_adjust(struct pci_dev *pdev,
1053 struct resource *res,
1054 struct resource *root)
1055 {
1056 struct pci_pbm_info *pbm = pdev->bus->sysdata;
1057 unsigned long base;
1058
1059 if (res->flags & IORESOURCE_IO)
1060 base = pbm->controller_regs + SABRE_IOSPACE;
1061 else
1062 base = pbm->controller_regs + SABRE_MEMSPACE;
1063
1064 res->start += base;
1065 res->end += base;
1066 }
1067
1068 static void __init sabre_base_address_update(struct pci_dev *pdev, int resource)
1069 {
1070 struct pcidev_cookie *pcp = pdev->sysdata;
1071 struct pci_pbm_info *pbm = pcp->pbm;
1072 struct resource *res;
1073 unsigned long base;
1074 u32 reg;
1075 int where, size, is_64bit;
1076
1077 res = &pdev->resource[resource];
1078 if (resource < 6) {
1079 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1080 } else if (resource == PCI_ROM_RESOURCE) {
1081 where = pdev->rom_base_reg;
1082 } else {
1083 /* Somebody might have asked allocation of a non-standard resource */
1084 return;
1085 }
1086
1087 is_64bit = 0;
1088 if (res->flags & IORESOURCE_IO)
1089 base = pbm->controller_regs + SABRE_IOSPACE;
1090 else {
1091 base = pbm->controller_regs + SABRE_MEMSPACE;
1092 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1093 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1094 is_64bit = 1;
1095 }
1096
1097 size = res->end - res->start;
1098 pci_read_config_dword(pdev, where, &reg);
1099 reg = ((reg & size) |
1100 (((u32)(res->start - base)) & ~size));
1101 if (resource == PCI_ROM_RESOURCE) {
1102 reg |= PCI_ROM_ADDRESS_ENABLE;
1103 res->flags |= IORESOURCE_ROM_ENABLE;
1104 }
1105 pci_write_config_dword(pdev, where, reg);
1106
1107 /* This knows that the upper 32-bits of the address
1108 * must be zero. Our PCI common layer enforces this.
1109 */
1110 if (is_64bit)
1111 pci_write_config_dword(pdev, where + 4, 0);
1112 }
1113
1114 static void __init apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
1115 {
1116 struct pci_dev *pdev;
1117
1118 list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
1119
1120 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1121 pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
1122 u32 word32;
1123 u16 word16;
1124
1125 sabre_read_pci_cfg(pdev->bus, pdev->devfn,
1126 PCI_COMMAND, 2, &word32);
1127 word16 = (u16) word32;
1128 word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
1129 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
1130 PCI_COMMAND_IO;
1131 word32 = (u32) word16;
1132 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1133 PCI_COMMAND, 2, word32);
1134
1135 /* Status register bits are "write 1 to clear". */
1136 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1137 PCI_STATUS, 2, 0xffff);
1138 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1139 PCI_SEC_STATUS, 2, 0xffff);
1140
1141 /* Use a primary/seconday latency timer value
1142 * of 64.
1143 */
1144 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1145 PCI_LATENCY_TIMER, 1, 64);
1146 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1147 PCI_SEC_LATENCY_TIMER, 1, 64);
1148
1149 /* Enable reporting/forwarding of master aborts,
1150 * parity, and SERR.
1151 */
1152 sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1153 PCI_BRIDGE_CONTROL, 1,
1154 (PCI_BRIDGE_CTL_PARITY |
1155 PCI_BRIDGE_CTL_SERR |
1156 PCI_BRIDGE_CTL_MASTER_ABORT));
1157 }
1158 }
1159 }
1160
1161 static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
1162 {
1163 struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
1164
1165 if (!cookie) {
1166 prom_printf("SABRE: Critical allocation failure.\n");
1167 prom_halt();
1168 }
1169
1170 /* All we care about is the PBM. */
1171 memset(cookie, 0, sizeof(*cookie));
1172 cookie->pbm = pbm;
1173
1174 return cookie;
1175 }
1176
1177 static void __init sabre_scan_bus(struct pci_controller_info *p)
1178 {
1179 static int once;
1180 struct pci_bus *sabre_bus, *pbus;
1181 struct pci_pbm_info *pbm;
1182 struct pcidev_cookie *cookie;
1183 int sabres_scanned;
1184
1185 /* The APB bridge speaks to the Sabre host PCI bridge
1186 * at 66Mhz, but the front side of APB runs at 33Mhz
1187 * for both segments.
1188 */
1189 p->pbm_A.is_66mhz_capable = 0;
1190 p->pbm_B.is_66mhz_capable = 0;
1191
1192 /* This driver has not been verified to handle
1193 * multiple SABREs yet, so trap this.
1194 *
1195 * Also note that the SABRE host bridge is hardwired
1196 * to live at bus 0.
1197 */
1198 if (once != 0) {
1199 prom_printf("SABRE: Multiple controllers unsupported.\n");
1200 prom_halt();
1201 }
1202 once++;
1203
1204 cookie = alloc_bridge_cookie(&p->pbm_A);
1205
1206 sabre_bus = pci_scan_bus(p->pci_first_busno,
1207 p->pci_ops,
1208 &p->pbm_A);
1209 pci_fixup_host_bridge_self(sabre_bus);
1210 sabre_bus->self->sysdata = cookie;
1211
1212 sabre_root_bus = sabre_bus;
1213
1214 apb_init(p, sabre_bus);
1215
1216 sabres_scanned = 0;
1217
1218 list_for_each_entry(pbus, &sabre_bus->children, node) {
1219
1220 if (pbus->number == p->pbm_A.pci_first_busno) {
1221 pbm = &p->pbm_A;
1222 } else if (pbus->number == p->pbm_B.pci_first_busno) {
1223 pbm = &p->pbm_B;
1224 } else
1225 continue;
1226
1227 cookie = alloc_bridge_cookie(pbm);
1228 pbus->self->sysdata = cookie;
1229
1230 sabres_scanned++;
1231
1232 pbus->sysdata = pbm;
1233 pbm->pci_bus = pbus;
1234 pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
1235 pci_record_assignments(pbm, pbus);
1236 pci_assign_unassigned(pbm, pbus);
1237 pci_fixup_irq(pbm, pbus);
1238 pci_determine_66mhz_disposition(pbm, pbus);
1239 pci_setup_busmastering(pbm, pbus);
1240 }
1241
1242 if (!sabres_scanned) {
1243 /* Hummingbird, no APBs. */
1244 pbm = &p->pbm_A;
1245 sabre_bus->sysdata = pbm;
1246 pbm->pci_bus = sabre_bus;
1247 pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
1248 pci_record_assignments(pbm, sabre_bus);
1249 pci_assign_unassigned(pbm, sabre_bus);
1250 pci_fixup_irq(pbm, sabre_bus);
1251 pci_determine_66mhz_disposition(pbm, sabre_bus);
1252 pci_setup_busmastering(pbm, sabre_bus);
1253 }
1254
1255 sabre_register_error_handlers(p);
1256 }
1257
1258 static void __init sabre_iommu_init(struct pci_controller_info *p,
1259 int tsbsize, unsigned long dvma_offset,
1260 u32 dma_mask)
1261 {
1262 struct pci_iommu *iommu = p->pbm_A.iommu;
1263 unsigned long tsbbase, i, order;
1264 u64 control;
1265
1266 /* Setup initial software IOMMU state. */
1267 spin_lock_init(&iommu->lock);
1268 iommu->iommu_cur_ctx = 0;
1269
1270 /* Register addresses. */
1271 iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
1272 iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
1273 iommu->iommu_flush = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
1274 iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
1275 /* Sabre's IOMMU lacks ctx flushing. */
1276 iommu->iommu_ctxflush = 0;
1277
1278 /* Invalidate TLB Entries. */
1279 control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1280 control |= SABRE_IOMMUCTRL_DENAB;
1281 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1282
1283 for(i = 0; i < 16; i++) {
1284 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
1285 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
1286 }
1287
1288 /* Leave diag mode enabled for full-flushing done
1289 * in pci_iommu.c
1290 */
1291
1292 iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
1293 if (!iommu->dummy_page) {
1294 prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
1295 prom_halt();
1296 }
1297 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
1298 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
1299
1300 tsbbase = __get_free_pages(GFP_KERNEL, order = get_order(tsbsize * 1024 * 8));
1301 if (!tsbbase) {
1302 prom_printf("SABRE_IOMMU: Error, gfp(tsb) failed.\n");
1303 prom_halt();
1304 }
1305 iommu->page_table = (iopte_t *)tsbbase;
1306 iommu->page_table_map_base = dvma_offset;
1307 iommu->dma_addr_mask = dma_mask;
1308 pci_iommu_table_init(iommu, PAGE_SIZE << order);
1309
1310 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE, __pa(tsbbase));
1311
1312 control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1313 control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
1314 control |= SABRE_IOMMUCTRL_ENAB;
1315 switch(tsbsize) {
1316 case 64:
1317 control |= SABRE_IOMMU_TSBSZ_64K;
1318 iommu->page_table_sz_bits = 16;
1319 break;
1320 case 128:
1321 control |= SABRE_IOMMU_TSBSZ_128K;
1322 iommu->page_table_sz_bits = 17;
1323 break;
1324 default:
1325 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1326 prom_halt();
1327 break;
1328 }
1329 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1330
1331 /* We start with no consistent mappings. */
1332 iommu->lowest_consistent_map =
1333 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
1334
1335 for (i = 0; i < PBM_NCLUSTERS; i++) {
1336 iommu->alloc_info[i].flush = 0;
1337 iommu->alloc_info[i].next = 0;
1338 }
1339 }
1340
1341 static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
1342 struct pci_pbm_info *pbm)
1343 {
1344 char *name = pbm->name;
1345 unsigned long ibase = p->pbm_A.controller_regs + SABRE_IOSPACE;
1346 unsigned long mbase = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1347 unsigned int devfn;
1348 unsigned long first, last, i;
1349 u8 *addr, map;
1350
1351 sprintf(name, "SABRE%d PBM%c",
1352 p->index,
1353 (pbm == &p->pbm_A ? 'A' : 'B'));
1354 pbm->io_space.name = pbm->mem_space.name = name;
1355
1356 devfn = PCI_DEVFN(1, (pbm == &p->pbm_A) ? 0 : 1);
1357 addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_IO_ADDRESS_MAP);
1358 map = 0;
1359 pci_config_read8(addr, &map);
1360
1361 first = 8;
1362 last = 0;
1363 for (i = 0; i < 8; i++) {
1364 if ((map & (1 << i)) != 0) {
1365 if (first > i)
1366 first = i;
1367 if (last < i)
1368 last = i;
1369 }
1370 }
1371 pbm->io_space.start = ibase + (first << 21UL);
1372 pbm->io_space.end = ibase + (last << 21UL) + ((1 << 21UL) - 1);
1373 pbm->io_space.flags = IORESOURCE_IO;
1374
1375 addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_MEM_ADDRESS_MAP);
1376 map = 0;
1377 pci_config_read8(addr, &map);
1378
1379 first = 8;
1380 last = 0;
1381 for (i = 0; i < 8; i++) {
1382 if ((map & (1 << i)) != 0) {
1383 if (first > i)
1384 first = i;
1385 if (last < i)
1386 last = i;
1387 }
1388 }
1389 pbm->mem_space.start = mbase + (first << 29UL);
1390 pbm->mem_space.end = mbase + (last << 29UL) + ((1 << 29UL) - 1);
1391 pbm->mem_space.flags = IORESOURCE_MEM;
1392
1393 if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1394 prom_printf("Cannot register PBM-%c's IO space.\n",
1395 (pbm == &p->pbm_A ? 'A' : 'B'));
1396 prom_halt();
1397 }
1398 if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1399 prom_printf("Cannot register PBM-%c's MEM space.\n",
1400 (pbm == &p->pbm_A ? 'A' : 'B'));
1401 prom_halt();
1402 }
1403
1404 /* Register legacy regions if this PBM covers that area. */
1405 if (pbm->io_space.start == ibase &&
1406 pbm->mem_space.start == mbase)
1407 pci_register_legacy_regions(&pbm->io_space,
1408 &pbm->mem_space);
1409 }
1410
1411 static void __init sabre_pbm_init(struct pci_controller_info *p, int sabre_node, u32 dma_begin)
1412 {
1413 struct pci_pbm_info *pbm;
1414 char namebuf[128];
1415 u32 busrange[2];
1416 int node, simbas_found;
1417
1418 simbas_found = 0;
1419 node = prom_getchild(sabre_node);
1420 while ((node = prom_searchsiblings(node, "pci")) != 0) {
1421 int err;
1422
1423 err = prom_getproperty(node, "model", namebuf, sizeof(namebuf));
1424 if ((err <= 0) || strncmp(namebuf, "SUNW,simba", err))
1425 goto next_pci;
1426
1427 err = prom_getproperty(node, "bus-range",
1428 (char *)&busrange[0], sizeof(busrange));
1429 if (err == 0 || err == -1) {
1430 prom_printf("APB: Error, cannot get PCI bus-range.\n");
1431 prom_halt();
1432 }
1433
1434 simbas_found++;
1435 if (busrange[0] == 1)
1436 pbm = &p->pbm_B;
1437 else
1438 pbm = &p->pbm_A;
1439 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
1440 pbm->parent = p;
1441 pbm->prom_node = node;
1442 pbm->pci_first_slot = 1;
1443 pbm->pci_first_busno = busrange[0];
1444 pbm->pci_last_busno = busrange[1];
1445
1446 prom_getstring(node, "name", pbm->prom_name, sizeof(pbm->prom_name));
1447 err = prom_getproperty(node, "ranges",
1448 (char *)pbm->pbm_ranges,
1449 sizeof(pbm->pbm_ranges));
1450 if (err != -1)
1451 pbm->num_pbm_ranges =
1452 (err / sizeof(struct linux_prom_pci_ranges));
1453 else
1454 pbm->num_pbm_ranges = 0;
1455
1456 err = prom_getproperty(node, "interrupt-map",
1457 (char *)pbm->pbm_intmap,
1458 sizeof(pbm->pbm_intmap));
1459 if (err != -1) {
1460 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1461 err = prom_getproperty(node, "interrupt-map-mask",
1462 (char *)&pbm->pbm_intmask,
1463 sizeof(pbm->pbm_intmask));
1464 if (err == -1) {
1465 prom_printf("APB: Fatal error, no interrupt-map-mask.\n");
1466 prom_halt();
1467 }
1468 } else {
1469 pbm->num_pbm_intmap = 0;
1470 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1471 }
1472
1473 pbm_register_toplevel_resources(p, pbm);
1474
1475 next_pci:
1476 node = prom_getsibling(node);
1477 if (!node)
1478 break;
1479 }
1480 if (simbas_found == 0) {
1481 int err;
1482
1483 /* No APBs underneath, probably this is a hummingbird
1484 * system.
1485 */
1486 pbm = &p->pbm_A;
1487 pbm->parent = p;
1488 pbm->prom_node = sabre_node;
1489 pbm->pci_first_busno = p->pci_first_busno;
1490 pbm->pci_last_busno = p->pci_last_busno;
1491
1492 prom_getstring(sabre_node, "name", pbm->prom_name, sizeof(pbm->prom_name));
1493 err = prom_getproperty(sabre_node, "ranges",
1494 (char *) pbm->pbm_ranges,
1495 sizeof(pbm->pbm_ranges));
1496 if (err != -1)
1497 pbm->num_pbm_ranges =
1498 (err / sizeof(struct linux_prom_pci_ranges));
1499 else
1500 pbm->num_pbm_ranges = 0;
1501
1502 err = prom_getproperty(sabre_node, "interrupt-map",
1503 (char *) pbm->pbm_intmap,
1504 sizeof(pbm->pbm_intmap));
1505
1506 if (err != -1) {
1507 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1508 err = prom_getproperty(sabre_node, "interrupt-map-mask",
1509 (char *)&pbm->pbm_intmask,
1510 sizeof(pbm->pbm_intmask));
1511 if (err == -1) {
1512 prom_printf("Hummingbird: Fatal error, no interrupt-map-mask.\n");
1513 prom_halt();
1514 }
1515 } else {
1516 pbm->num_pbm_intmap = 0;
1517 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1518 }
1519
1520
1521 sprintf(pbm->name, "SABRE%d PBM%c", p->index,
1522 (pbm == &p->pbm_A ? 'A' : 'B'));
1523 pbm->io_space.name = pbm->mem_space.name = pbm->name;
1524
1525 /* Hack up top-level resources. */
1526 pbm->io_space.start = p->pbm_A.controller_regs + SABRE_IOSPACE;
1527 pbm->io_space.end = pbm->io_space.start + (1UL << 24) - 1UL;
1528 pbm->io_space.flags = IORESOURCE_IO;
1529
1530 pbm->mem_space.start = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1531 pbm->mem_space.end = pbm->mem_space.start + (unsigned long)dma_begin - 1UL;
1532 pbm->mem_space.flags = IORESOURCE_MEM;
1533
1534 if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1535 prom_printf("Cannot register Hummingbird's IO space.\n");
1536 prom_halt();
1537 }
1538 if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1539 prom_printf("Cannot register Hummingbird's MEM space.\n");
1540 prom_halt();
1541 }
1542
1543 pci_register_legacy_regions(&pbm->io_space,
1544 &pbm->mem_space);
1545 }
1546 }
1547
1548 void __init sabre_init(int pnode, char *model_name)
1549 {
1550 struct linux_prom64_registers pr_regs[2];
1551 struct pci_controller_info *p;
1552 struct pci_iommu *iommu;
1553 int tsbsize, err;
1554 u32 busrange[2];
1555 u32 vdma[2];
1556 u32 upa_portid, dma_mask;
1557 u64 clear_irq;
1558
1559 hummingbird_p = 0;
1560 if (!strcmp(model_name, "pci108e,a001"))
1561 hummingbird_p = 1;
1562 else if (!strcmp(model_name, "SUNW,sabre")) {
1563 char compat[64];
1564
1565 if (prom_getproperty(pnode, "compatible",
1566 compat, sizeof(compat)) > 0 &&
1567 !strcmp(compat, "pci108e,a001")) {
1568 hummingbird_p = 1;
1569 } else {
1570 int cpu_node;
1571
1572 /* Of course, Sun has to encode things a thousand
1573 * different ways, inconsistently.
1574 */
1575 cpu_find_by_instance(0, &cpu_node, NULL);
1576 if (prom_getproperty(cpu_node, "name",
1577 compat, sizeof(compat)) > 0 &&
1578 !strcmp(compat, "SUNW,UltraSPARC-IIe"))
1579 hummingbird_p = 1;
1580 }
1581 }
1582
1583 p = kmalloc(sizeof(*p), GFP_ATOMIC);
1584 if (!p) {
1585 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1586 prom_halt();
1587 }
1588 memset(p, 0, sizeof(*p));
1589
1590 iommu = kmalloc(sizeof(*iommu), GFP_ATOMIC);
1591 if (!iommu) {
1592 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
1593 prom_halt();
1594 }
1595 memset(iommu, 0, sizeof(*iommu));
1596 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1597
1598 upa_portid = prom_getintdefault(pnode, "upa-portid", 0xff);
1599
1600 p->next = pci_controller_root;
1601 pci_controller_root = p;
1602
1603 p->pbm_A.portid = upa_portid;
1604 p->pbm_B.portid = upa_portid;
1605 p->index = pci_num_controllers++;
1606 p->pbms_same_domain = 1;
1607 p->scan_bus = sabre_scan_bus;
1608 p->irq_build = sabre_irq_build;
1609 p->base_address_update = sabre_base_address_update;
1610 p->resource_adjust = sabre_resource_adjust;
1611 p->pci_ops = &sabre_ops;
1612
1613 /*
1614 * Map in SABRE register set and report the presence of this SABRE.
1615 */
1616 err = prom_getproperty(pnode, "reg",
1617 (char *)&pr_regs[0], sizeof(pr_regs));
1618 if(err == 0 || err == -1) {
1619 prom_printf("SABRE: Error, cannot get U2P registers "
1620 "from PROM.\n");
1621 prom_halt();
1622 }
1623
1624 /*
1625 * First REG in property is base of entire SABRE register space.
1626 */
1627 p->pbm_A.controller_regs = pr_regs[0].phys_addr;
1628 p->pbm_B.controller_regs = pr_regs[0].phys_addr;
1629 pci_dma_wsync = p->pbm_A.controller_regs + SABRE_WRSYNC;
1630
1631 printk("PCI: Found SABRE, main regs at %016lx, wsync at %016lx\n",
1632 p->pbm_A.controller_regs, pci_dma_wsync);
1633
1634 /* Clear interrupts */
1635
1636 /* PCI first */
1637 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
1638 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1639
1640 /* Then OBIO */
1641 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
1642 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1643
1644 /* Error interrupts are enabled later after the bus scan. */
1645 sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
1646 (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
1647 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
1648
1649 /* Now map in PCI config space for entire SABRE. */
1650 p->pbm_A.config_space = p->pbm_B.config_space =
1651 (p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
1652 printk("SABRE: Shared PCI config space at %016lx\n",
1653 p->pbm_A.config_space);
1654
1655 err = prom_getproperty(pnode, "virtual-dma",
1656 (char *)&vdma[0], sizeof(vdma));
1657 if(err == 0 || err == -1) {
1658 prom_printf("SABRE: Error, cannot get virtual-dma property "
1659 "from PROM.\n");
1660 prom_halt();
1661 }
1662
1663 dma_mask = vdma[0];
1664 switch(vdma[1]) {
1665 case 0x20000000:
1666 dma_mask |= 0x1fffffff;
1667 tsbsize = 64;
1668 break;
1669 case 0x40000000:
1670 dma_mask |= 0x3fffffff;
1671 tsbsize = 128;
1672 break;
1673
1674 case 0x80000000:
1675 dma_mask |= 0x7fffffff;
1676 tsbsize = 128;
1677 break;
1678 default:
1679 prom_printf("SABRE: strange virtual-dma size.\n");
1680 prom_halt();
1681 }
1682
1683 sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
1684
1685 printk("SABRE: DVMA at %08x [%08x]\n", vdma[0], vdma[1]);
1686
1687 err = prom_getproperty(pnode, "bus-range",
1688 (char *)&busrange[0], sizeof(busrange));
1689 if(err == 0 || err == -1) {
1690 prom_printf("SABRE: Error, cannot get PCI bus-range "
1691 " from PROM.\n");
1692 prom_halt();
1693 }
1694
1695 p->pci_first_busno = busrange[0];
1696 p->pci_last_busno = busrange[1];
1697
1698 /*
1699 * Look for APB underneath.
1700 */
1701 sabre_pbm_init(p, pnode, vdma[0]);
1702 }
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