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Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/gregkh/driver...
[linux-2.6/verdex.git] / drivers / char / drm / mga_state.c
blob3c7a8f5ba50133e3289971b05e52402418935a82
1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 * Rewritten by:
32 * Gareth Hughes <gareth@valinux.com>
33 */
34
35 #include "drmP.h"
36 #include "drm.h"
37 #include "mga_drm.h"
38 #include "mga_drv.h"
39
40 /* ================================================================
41 * DMA hardware state programming functions
42 */
43
44 static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
45 drm_clip_rect_t *box )
46 {
47 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
48 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
49 unsigned int pitch = dev_priv->front_pitch;
50 DMA_LOCALS;
51
52 BEGIN_DMA( 2 );
53
54 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
55 */
56 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
57 DMA_BLOCK( MGA_DWGCTL, ctx->dwgctl,
58 MGA_LEN + MGA_EXEC, 0x80000000,
59 MGA_DWGCTL, ctx->dwgctl,
60 MGA_LEN + MGA_EXEC, 0x80000000 );
61 }
62 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
63 MGA_CXBNDRY, (box->x2 << 16) | box->x1,
64 MGA_YTOP, box->y1 * pitch,
65 MGA_YBOT, box->y2 * pitch );
66
67 ADVANCE_DMA();
68 }
69
70 static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv )
71 {
72 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
73 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
74 DMA_LOCALS;
75
76 BEGIN_DMA( 3 );
77
78 DMA_BLOCK( MGA_DSTORG, ctx->dstorg,
79 MGA_MACCESS, ctx->maccess,
80 MGA_PLNWT, ctx->plnwt,
81 MGA_DWGCTL, ctx->dwgctl );
82
83 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl,
84 MGA_FOGCOL, ctx->fogcolor,
85 MGA_WFLAG, ctx->wflag,
86 MGA_ZORG, dev_priv->depth_offset );
87
88 DMA_BLOCK( MGA_FCOL, ctx->fcol,
89 MGA_DMAPAD, 0x00000000,
90 MGA_DMAPAD, 0x00000000,
91 MGA_DMAPAD, 0x00000000 );
92
93 ADVANCE_DMA();
94 }
95
96 static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv )
97 {
98 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
99 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
100 DMA_LOCALS;
101
102 BEGIN_DMA( 4 );
103
104 DMA_BLOCK( MGA_DSTORG, ctx->dstorg,
105 MGA_MACCESS, ctx->maccess,
106 MGA_PLNWT, ctx->plnwt,
107 MGA_DWGCTL, ctx->dwgctl );
108
109 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl,
110 MGA_FOGCOL, ctx->fogcolor,
111 MGA_WFLAG, ctx->wflag,
112 MGA_ZORG, dev_priv->depth_offset );
113
114 DMA_BLOCK( MGA_WFLAG1, ctx->wflag,
115 MGA_TDUALSTAGE0, ctx->tdualstage0,
116 MGA_TDUALSTAGE1, ctx->tdualstage1,
117 MGA_FCOL, ctx->fcol );
118
119 DMA_BLOCK( MGA_STENCIL, ctx->stencil,
120 MGA_STENCILCTL, ctx->stencilctl,
121 MGA_DMAPAD, 0x00000000,
122 MGA_DMAPAD, 0x00000000 );
123
124 ADVANCE_DMA();
125 }
126
127 static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
128 {
129 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
130 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
131 DMA_LOCALS;
132
133 BEGIN_DMA( 4 );
134
135 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2,
136 MGA_TEXCTL, tex->texctl,
137 MGA_TEXFILTER, tex->texfilter,
138 MGA_TEXBORDERCOL, tex->texbordercol );
139
140 DMA_BLOCK( MGA_TEXORG, tex->texorg,
141 MGA_TEXORG1, tex->texorg1,
142 MGA_TEXORG2, tex->texorg2,
143 MGA_TEXORG3, tex->texorg3 );
144
145 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
146 MGA_TEXWIDTH, tex->texwidth,
147 MGA_TEXHEIGHT, tex->texheight,
148 MGA_WR24, tex->texwidth );
149
150 DMA_BLOCK( MGA_WR34, tex->texheight,
151 MGA_TEXTRANS, 0x0000ffff,
152 MGA_TEXTRANSHIGH, 0x0000ffff,
153 MGA_DMAPAD, 0x00000000 );
154
155 ADVANCE_DMA();
156 }
157
158 static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
159 {
160 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
161 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
162 DMA_LOCALS;
163
164 /* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
165 /* tex->texctl, tex->texctl2); */
166
167 BEGIN_DMA( 6 );
168
169 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
170 MGA_TEXCTL, tex->texctl,
171 MGA_TEXFILTER, tex->texfilter,
172 MGA_TEXBORDERCOL, tex->texbordercol );
173
174 DMA_BLOCK( MGA_TEXORG, tex->texorg,
175 MGA_TEXORG1, tex->texorg1,
176 MGA_TEXORG2, tex->texorg2,
177 MGA_TEXORG3, tex->texorg3 );
178
179 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
180 MGA_TEXWIDTH, tex->texwidth,
181 MGA_TEXHEIGHT, tex->texheight,
182 MGA_WR49, 0x00000000 );
183
184 DMA_BLOCK( MGA_WR57, 0x00000000,
185 MGA_WR53, 0x00000000,
186 MGA_WR61, 0x00000000,
187 MGA_WR52, MGA_G400_WR_MAGIC );
188
189 DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC,
190 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
191 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
192 MGA_DMAPAD, 0x00000000 );
193
194 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
195 MGA_DMAPAD, 0x00000000,
196 MGA_TEXTRANS, 0x0000ffff,
197 MGA_TEXTRANSHIGH, 0x0000ffff );
198
199 ADVANCE_DMA();
200 }
201
202 static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
203 {
204 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
205 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
206 DMA_LOCALS;
207
208 /* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
209 /* tex->texctl, tex->texctl2); */
210
211 BEGIN_DMA( 5 );
212
213 DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 |
214 MGA_MAP1_ENABLE |
215 MGA_G400_TC2_MAGIC),
216 MGA_TEXCTL, tex->texctl,
217 MGA_TEXFILTER, tex->texfilter,
218 MGA_TEXBORDERCOL, tex->texbordercol );
219
220 DMA_BLOCK( MGA_TEXORG, tex->texorg,
221 MGA_TEXORG1, tex->texorg1,
222 MGA_TEXORG2, tex->texorg2,
223 MGA_TEXORG3, tex->texorg3 );
224
225 DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
226 MGA_TEXWIDTH, tex->texwidth,
227 MGA_TEXHEIGHT, tex->texheight,
228 MGA_WR49, 0x00000000 );
229
230 DMA_BLOCK( MGA_WR57, 0x00000000,
231 MGA_WR53, 0x00000000,
232 MGA_WR61, 0x00000000,
233 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC );
234
235 DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
236 MGA_TEXTRANS, 0x0000ffff,
237 MGA_TEXTRANSHIGH, 0x0000ffff,
238 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC );
239
240 ADVANCE_DMA();
241 }
242
243 static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
244 {
245 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
246 unsigned int pipe = sarea_priv->warp_pipe;
247 DMA_LOCALS;
248
249 BEGIN_DMA( 3 );
250
251 DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND,
252 MGA_WVRTXSZ, 0x00000007,
253 MGA_WFLAG, 0x00000000,
254 MGA_WR24, 0x00000000 );
255
256 DMA_BLOCK( MGA_WR25, 0x00000100,
257 MGA_WR34, 0x00000000,
258 MGA_WR42, 0x0000ffff,
259 MGA_WR60, 0x0000ffff );
260
261 /* Padding required to to hardware bug.
262 */
263 DMA_BLOCK( MGA_DMAPAD, 0xffffffff,
264 MGA_DMAPAD, 0xffffffff,
265 MGA_DMAPAD, 0xffffffff,
266 MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
267 MGA_WMODE_START |
268 MGA_WAGP_ENABLE) );
269
270 ADVANCE_DMA();
271 }
272
273 static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
274 {
275 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
276 unsigned int pipe = sarea_priv->warp_pipe;
277 DMA_LOCALS;
278
279 /* printk("mga_g400_emit_pipe %x\n", pipe); */
280
281 BEGIN_DMA( 10 );
282
283 DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND,
284 MGA_DMAPAD, 0x00000000,
285 MGA_DMAPAD, 0x00000000,
286 MGA_DMAPAD, 0x00000000 );
287
288 if ( pipe & MGA_T2 ) {
289 DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09,
290 MGA_DMAPAD, 0x00000000,
291 MGA_DMAPAD, 0x00000000,
292 MGA_DMAPAD, 0x00000000 );
293
294 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000,
295 MGA_WACCEPTSEQ, 0x00000000,
296 MGA_WACCEPTSEQ, 0x00000000,
297 MGA_WACCEPTSEQ, 0x1e000000 );
298 } else {
299 if ( dev_priv->warp_pipe & MGA_T2 ) {
300 /* Flush the WARP pipe */
301 DMA_BLOCK( MGA_YDST, 0x00000000,
302 MGA_FXLEFT, 0x00000000,
303 MGA_FXRIGHT, 0x00000001,
304 MGA_DWGCTL, MGA_DWGCTL_FLUSH );
305
306 DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001,
307 MGA_DWGSYNC, 0x00007000,
308 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
309 MGA_LEN + MGA_EXEC, 0x00000000 );
310
311 DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX |
312 MGA_G400_TC2_MAGIC),
313 MGA_LEN + MGA_EXEC, 0x00000000,
314 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
315 MGA_DMAPAD, 0x00000000 );
316 }
317
318 DMA_BLOCK( MGA_WVRTXSZ, 0x00001807,
319 MGA_DMAPAD, 0x00000000,
320 MGA_DMAPAD, 0x00000000,
321 MGA_DMAPAD, 0x00000000 );
322
323 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000,
324 MGA_WACCEPTSEQ, 0x00000000,
325 MGA_WACCEPTSEQ, 0x00000000,
326 MGA_WACCEPTSEQ, 0x18000000 );
327 }
328
329 DMA_BLOCK( MGA_WFLAG, 0x00000000,
330 MGA_WFLAG1, 0x00000000,
331 MGA_WR56, MGA_G400_WR56_MAGIC,
332 MGA_DMAPAD, 0x00000000 );
333
334 DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */
335 MGA_WR57, 0x00000000, /* tex0 */
336 MGA_WR53, 0x00000000, /* tex1 */
337 MGA_WR61, 0x00000000 ); /* tex1 */
338
339 DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
340 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
341 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
342 MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */
343
344 /* Padding required to to hardware bug */
345 DMA_BLOCK( MGA_DMAPAD, 0xffffffff,
346 MGA_DMAPAD, 0xffffffff,
347 MGA_DMAPAD, 0xffffffff,
348 MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
349 MGA_WMODE_START |
350 MGA_WAGP_ENABLE) );
351
352 ADVANCE_DMA();
353 }
354
355 static void mga_g200_emit_state( drm_mga_private_t *dev_priv )
356 {
357 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
358 unsigned int dirty = sarea_priv->dirty;
359
360 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
361 mga_g200_emit_pipe( dev_priv );
362 dev_priv->warp_pipe = sarea_priv->warp_pipe;
363 }
364
365 if ( dirty & MGA_UPLOAD_CONTEXT ) {
366 mga_g200_emit_context( dev_priv );
367 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
368 }
369
370 if ( dirty & MGA_UPLOAD_TEX0 ) {
371 mga_g200_emit_tex0( dev_priv );
372 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
373 }
374 }
375
376 static void mga_g400_emit_state( drm_mga_private_t *dev_priv )
377 {
378 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
379 unsigned int dirty = sarea_priv->dirty;
380 int multitex = sarea_priv->warp_pipe & MGA_T2;
381
382 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
383 mga_g400_emit_pipe( dev_priv );
384 dev_priv->warp_pipe = sarea_priv->warp_pipe;
385 }
386
387 if ( dirty & MGA_UPLOAD_CONTEXT ) {
388 mga_g400_emit_context( dev_priv );
389 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
390 }
391
392 if ( dirty & MGA_UPLOAD_TEX0 ) {
393 mga_g400_emit_tex0( dev_priv );
394 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
395 }
396
397 if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) {
398 mga_g400_emit_tex1( dev_priv );
399 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
400 }
401 }
402
403
404 /* ================================================================
405 * SAREA state verification
406 */
407
408 /* Disallow all write destinations except the front and backbuffer.
409 */
410 static int mga_verify_context( drm_mga_private_t *dev_priv )
411 {
412 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
413 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
414
415 if ( ctx->dstorg != dev_priv->front_offset &&
416 ctx->dstorg != dev_priv->back_offset ) {
417 DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n",
418 ctx->dstorg, dev_priv->front_offset,
419 dev_priv->back_offset );
420 ctx->dstorg = 0;
421 return DRM_ERR(EINVAL);
422 }
423
424 return 0;
425 }
426
427 /* Disallow texture reads from PCI space.
428 */
429 static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
430 {
431 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
432 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
433 unsigned int org;
434
435 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
436
437 if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) {
438 DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n",
439 tex->texorg, unit );
440 tex->texorg = 0;
441 return DRM_ERR(EINVAL);
442 }
443
444 return 0;
445 }
446
447 static int mga_verify_state( drm_mga_private_t *dev_priv )
448 {
449 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
450 unsigned int dirty = sarea_priv->dirty;
451 int ret = 0;
452
453 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
454 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
455
456 if ( dirty & MGA_UPLOAD_CONTEXT )
457 ret |= mga_verify_context( dev_priv );
458
459 if ( dirty & MGA_UPLOAD_TEX0 )
460 ret |= mga_verify_tex( dev_priv, 0 );
461
462 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
463 if ( dirty & MGA_UPLOAD_TEX1 )
464 ret |= mga_verify_tex( dev_priv, 1 );
465
466 if ( dirty & MGA_UPLOAD_PIPE )
467 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES );
468 } else {
469 if ( dirty & MGA_UPLOAD_PIPE )
470 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES );
471 }
472
473 return ( ret == 0 );
474 }
475
476 static int mga_verify_iload( drm_mga_private_t *dev_priv,
477 unsigned int dstorg, unsigned int length )
478 {
479 if ( dstorg < dev_priv->texture_offset ||
480 dstorg + length > (dev_priv->texture_offset +
481 dev_priv->texture_size) ) {
482 DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg );
483 return DRM_ERR(EINVAL);
484 }
485
486 if ( length & MGA_ILOAD_MASK ) {
487 DRM_ERROR( "*** bad iload length: 0x%x\n",
488 length & MGA_ILOAD_MASK );
489 return DRM_ERR(EINVAL);
490 }
491
492 return 0;
493 }
494
495 static int mga_verify_blit( drm_mga_private_t *dev_priv,
496 unsigned int srcorg, unsigned int dstorg )
497 {
498 if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
499 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) {
500 DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n",
501 srcorg, dstorg );
502 return DRM_ERR(EINVAL);
503 }
504 return 0;
505 }
506
507
508 /* ================================================================
509 *
510 */
511
512 static void mga_dma_dispatch_clear( drm_device_t *dev,
513 drm_mga_clear_t *clear )
514 {
515 drm_mga_private_t *dev_priv = dev->dev_private;
516 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
517 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
518 drm_clip_rect_t *pbox = sarea_priv->boxes;
519 int nbox = sarea_priv->nbox;
520 int i;
521 DMA_LOCALS;
522 DRM_DEBUG( "\n" );
523
524 BEGIN_DMA( 1 );
525
526 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
527 MGA_DMAPAD, 0x00000000,
528 MGA_DWGSYNC, 0x00007100,
529 MGA_DWGSYNC, 0x00007000 );
530
531 ADVANCE_DMA();
532
533 for ( i = 0 ; i < nbox ; i++ ) {
534 drm_clip_rect_t *box = &pbox[i];
535 u32 height = box->y2 - box->y1;
536
537 DRM_DEBUG( " from=%d,%d to=%d,%d\n",
538 box->x1, box->y1, box->x2, box->y2 );
539
540 if ( clear->flags & MGA_FRONT ) {
541 BEGIN_DMA( 2 );
542
543 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
544 MGA_PLNWT, clear->color_mask,
545 MGA_YDSTLEN, (box->y1 << 16) | height,
546 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
547
548 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
549 MGA_FCOL, clear->clear_color,
550 MGA_DSTORG, dev_priv->front_offset,
551 MGA_DWGCTL + MGA_EXEC,
552 dev_priv->clear_cmd );
553
554 ADVANCE_DMA();
555 }
556
557
558 if ( clear->flags & MGA_BACK ) {
559 BEGIN_DMA( 2 );
560
561 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
562 MGA_PLNWT, clear->color_mask,
563 MGA_YDSTLEN, (box->y1 << 16) | height,
564 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
565
566 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
567 MGA_FCOL, clear->clear_color,
568 MGA_DSTORG, dev_priv->back_offset,
569 MGA_DWGCTL + MGA_EXEC,
570 dev_priv->clear_cmd );
571
572 ADVANCE_DMA();
573 }
574
575 if ( clear->flags & MGA_DEPTH ) {
576 BEGIN_DMA( 2 );
577
578 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
579 MGA_PLNWT, clear->depth_mask,
580 MGA_YDSTLEN, (box->y1 << 16) | height,
581 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
582
583 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
584 MGA_FCOL, clear->clear_depth,
585 MGA_DSTORG, dev_priv->depth_offset,
586 MGA_DWGCTL + MGA_EXEC,
587 dev_priv->clear_cmd );
588
589 ADVANCE_DMA();
590 }
591
592 }
593
594 BEGIN_DMA( 1 );
595
596 /* Force reset of DWGCTL */
597 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
598 MGA_DMAPAD, 0x00000000,
599 MGA_PLNWT, ctx->plnwt,
600 MGA_DWGCTL, ctx->dwgctl );
601
602 ADVANCE_DMA();
603
604 FLUSH_DMA();
605 }
606
607 static void mga_dma_dispatch_swap( drm_device_t *dev )
608 {
609 drm_mga_private_t *dev_priv = dev->dev_private;
610 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
611 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
612 drm_clip_rect_t *pbox = sarea_priv->boxes;
613 int nbox = sarea_priv->nbox;
614 int i;
615 DMA_LOCALS;
616 DRM_DEBUG( "\n" );
617
618 sarea_priv->last_frame.head = dev_priv->prim.tail;
619 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
620
621 BEGIN_DMA( 4 + nbox );
622
623 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
624 MGA_DMAPAD, 0x00000000,
625 MGA_DWGSYNC, 0x00007100,
626 MGA_DWGSYNC, 0x00007000 );
627
628 DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset,
629 MGA_MACCESS, dev_priv->maccess,
630 MGA_SRCORG, dev_priv->back_offset,
631 MGA_AR5, dev_priv->front_pitch );
632
633 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
634 MGA_DMAPAD, 0x00000000,
635 MGA_PLNWT, 0xffffffff,
636 MGA_DWGCTL, MGA_DWGCTL_COPY );
637
638 for ( i = 0 ; i < nbox ; i++ ) {
639 drm_clip_rect_t *box = &pbox[i];
640 u32 height = box->y2 - box->y1;
641 u32 start = box->y1 * dev_priv->front_pitch;
642
643 DRM_DEBUG( " from=%d,%d to=%d,%d\n",
644 box->x1, box->y1, box->x2, box->y2 );
645
646 DMA_BLOCK( MGA_AR0, start + box->x2 - 1,
647 MGA_AR3, start + box->x1,
648 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
649 MGA_YDSTLEN + MGA_EXEC,
650 (box->y1 << 16) | height );
651 }
652
653 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
654 MGA_PLNWT, ctx->plnwt,
655 MGA_SRCORG, dev_priv->front_offset,
656 MGA_DWGCTL, ctx->dwgctl );
657
658 ADVANCE_DMA();
659
660 FLUSH_DMA();
661
662 DRM_DEBUG( "%s... done.\n", __FUNCTION__ );
663 }
664
665 static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
666 {
667 drm_mga_private_t *dev_priv = dev->dev_private;
668 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
669 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
670 u32 address = (u32) buf->bus_address;
671 u32 length = (u32) buf->used;
672 int i = 0;
673 DMA_LOCALS;
674 DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used );
675
676 if ( buf->used ) {
677 buf_priv->dispatched = 1;
678
679 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
680
681 do {
682 if ( i < sarea_priv->nbox ) {
683 mga_emit_clip_rect( dev_priv,
684 &sarea_priv->boxes[i] );
685 }
686
687 BEGIN_DMA( 1 );
688
689 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
690 MGA_DMAPAD, 0x00000000,
691 MGA_SECADDRESS, (address |
692 MGA_DMA_VERTEX),
693 MGA_SECEND, ((address + length) |
694 MGA_PAGPXFER) );
695
696 ADVANCE_DMA();
697 } while ( ++i < sarea_priv->nbox );
698 }
699
700 if ( buf_priv->discard ) {
701 AGE_BUFFER( buf_priv );
702 buf->pending = 0;
703 buf->used = 0;
704 buf_priv->dispatched = 0;
705
706 mga_freelist_put( dev, buf );
707 }
708
709 FLUSH_DMA();
710 }
711
712 static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
713 unsigned int start, unsigned int end )
714 {
715 drm_mga_private_t *dev_priv = dev->dev_private;
716 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
717 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
718 u32 address = (u32) buf->bus_address;
719 int i = 0;
720 DMA_LOCALS;
721 DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end );
722
723 if ( start != end ) {
724 buf_priv->dispatched = 1;
725
726 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
727
728 do {
729 if ( i < sarea_priv->nbox ) {
730 mga_emit_clip_rect( dev_priv,
731 &sarea_priv->boxes[i] );
732 }
733
734 BEGIN_DMA( 1 );
735
736 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
737 MGA_DMAPAD, 0x00000000,
738 MGA_SETUPADDRESS, address + start,
739 MGA_SETUPEND, ((address + end) |
740 MGA_PAGPXFER) );
741
742 ADVANCE_DMA();
743 } while ( ++i < sarea_priv->nbox );
744 }
745
746 if ( buf_priv->discard ) {
747 AGE_BUFFER( buf_priv );
748 buf->pending = 0;
749 buf->used = 0;
750 buf_priv->dispatched = 0;
751
752 mga_freelist_put( dev, buf );
753 }
754
755 FLUSH_DMA();
756 }
757
758 /* This copies a 64 byte aligned agp region to the frambuffer with a
759 * standard blit, the ioctl needs to do checking.
760 */
761 static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
762 unsigned int dstorg, unsigned int length )
763 {
764 drm_mga_private_t *dev_priv = dev->dev_private;
765 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
766 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
767 u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
768 u32 y2;
769 DMA_LOCALS;
770 DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used );
771
772 y2 = length / 64;
773
774 BEGIN_DMA( 5 );
775
776 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
777 MGA_DMAPAD, 0x00000000,
778 MGA_DWGSYNC, 0x00007100,
779 MGA_DWGSYNC, 0x00007000 );
780
781 DMA_BLOCK( MGA_DSTORG, dstorg,
782 MGA_MACCESS, 0x00000000,
783 MGA_SRCORG, srcorg,
784 MGA_AR5, 64 );
785
786 DMA_BLOCK( MGA_PITCH, 64,
787 MGA_PLNWT, 0xffffffff,
788 MGA_DMAPAD, 0x00000000,
789 MGA_DWGCTL, MGA_DWGCTL_COPY );
790
791 DMA_BLOCK( MGA_AR0, 63,
792 MGA_AR3, 0,
793 MGA_FXBNDRY, (63 << 16) | 0,
794 MGA_YDSTLEN + MGA_EXEC, y2 );
795
796 DMA_BLOCK( MGA_PLNWT, ctx->plnwt,
797 MGA_SRCORG, dev_priv->front_offset,
798 MGA_PITCH, dev_priv->front_pitch,
799 MGA_DWGSYNC, 0x00007000 );
800
801 ADVANCE_DMA();
802
803 AGE_BUFFER( buf_priv );
804
805 buf->pending = 0;
806 buf->used = 0;
807 buf_priv->dispatched = 0;
808
809 mga_freelist_put( dev, buf );
810
811 FLUSH_DMA();
812 }
813
814 static void mga_dma_dispatch_blit( drm_device_t *dev,
815 drm_mga_blit_t *blit )
816 {
817 drm_mga_private_t *dev_priv = dev->dev_private;
818 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
819 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
820 drm_clip_rect_t *pbox = sarea_priv->boxes;
821 int nbox = sarea_priv->nbox;
822 u32 scandir = 0, i;
823 DMA_LOCALS;
824 DRM_DEBUG( "\n" );
825
826 BEGIN_DMA( 4 + nbox );
827
828 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
829 MGA_DMAPAD, 0x00000000,
830 MGA_DWGSYNC, 0x00007100,
831 MGA_DWGSYNC, 0x00007000 );
832
833 DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY,
834 MGA_PLNWT, blit->planemask,
835 MGA_SRCORG, blit->srcorg,
836 MGA_DSTORG, blit->dstorg );
837
838 DMA_BLOCK( MGA_SGN, scandir,
839 MGA_MACCESS, dev_priv->maccess,
840 MGA_AR5, blit->ydir * blit->src_pitch,
841 MGA_PITCH, blit->dst_pitch );
842
843 for ( i = 0 ; i < nbox ; i++ ) {
844 int srcx = pbox[i].x1 + blit->delta_sx;
845 int srcy = pbox[i].y1 + blit->delta_sy;
846 int dstx = pbox[i].x1 + blit->delta_dx;
847 int dsty = pbox[i].y1 + blit->delta_dy;
848 int h = pbox[i].y2 - pbox[i].y1;
849 int w = pbox[i].x2 - pbox[i].x1 - 1;
850 int start;
851
852 if ( blit->ydir == -1 ) {
853 srcy = blit->height - srcy - 1;
854 }
855
856 start = srcy * blit->src_pitch + srcx;
857
858 DMA_BLOCK( MGA_AR0, start + w,
859 MGA_AR3, start,
860 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
861 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h );
862 }
863
864 /* Do something to flush AGP?
865 */
866
867 /* Force reset of DWGCTL */
868 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
869 MGA_PLNWT, ctx->plnwt,
870 MGA_PITCH, dev_priv->front_pitch,
871 MGA_DWGCTL, ctx->dwgctl );
872
873 ADVANCE_DMA();
874 }
875
876
877 /* ================================================================
878 *
879 */
880
881 static int mga_dma_clear( DRM_IOCTL_ARGS )
882 {
883 DRM_DEVICE;
884 drm_mga_private_t *dev_priv = dev->dev_private;
885 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
886 drm_mga_clear_t clear;
887
888 LOCK_TEST_WITH_RETURN( dev, filp );
889
890 DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) );
891
892 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
893 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
894
895 WRAP_TEST_WITH_RETURN( dev_priv );
896
897 mga_dma_dispatch_clear( dev, &clear );
898
899 /* Make sure we restore the 3D state next time.
900 */
901 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
902
903 return 0;
904 }
905
906 static int mga_dma_swap( DRM_IOCTL_ARGS )
907 {
908 DRM_DEVICE;
909 drm_mga_private_t *dev_priv = dev->dev_private;
910 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
911
912 LOCK_TEST_WITH_RETURN( dev, filp );
913
914 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
915 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
916
917 WRAP_TEST_WITH_RETURN( dev_priv );
918
919 mga_dma_dispatch_swap( dev );
920
921 /* Make sure we restore the 3D state next time.
922 */
923 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
924
925 return 0;
926 }
927
928 static int mga_dma_vertex( DRM_IOCTL_ARGS )
929 {
930 DRM_DEVICE;
931 drm_mga_private_t *dev_priv = dev->dev_private;
932 drm_device_dma_t *dma = dev->dma;
933 drm_buf_t *buf;
934 drm_mga_buf_priv_t *buf_priv;
935 drm_mga_vertex_t vertex;
936
937 LOCK_TEST_WITH_RETURN( dev, filp );
938
939 DRM_COPY_FROM_USER_IOCTL( vertex,
940 (drm_mga_vertex_t __user *)data,
941 sizeof(vertex) );
942
943 if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL);
944 buf = dma->buflist[vertex.idx];
945 buf_priv = buf->dev_private;
946
947 buf->used = vertex.used;
948 buf_priv->discard = vertex.discard;
949
950 if ( !mga_verify_state( dev_priv ) ) {
951 if ( vertex.discard ) {
952 if ( buf_priv->dispatched == 1 )
953 AGE_BUFFER( buf_priv );
954 buf_priv->dispatched = 0;
955 mga_freelist_put( dev, buf );
956 }
957 return DRM_ERR(EINVAL);
958 }
959
960 WRAP_TEST_WITH_RETURN( dev_priv );
961
962 mga_dma_dispatch_vertex( dev, buf );
963
964 return 0;
965 }
966
967 static int mga_dma_indices( DRM_IOCTL_ARGS )
968 {
969 DRM_DEVICE;
970 drm_mga_private_t *dev_priv = dev->dev_private;
971 drm_device_dma_t *dma = dev->dma;
972 drm_buf_t *buf;
973 drm_mga_buf_priv_t *buf_priv;
974 drm_mga_indices_t indices;
975
976 LOCK_TEST_WITH_RETURN( dev, filp );
977
978 DRM_COPY_FROM_USER_IOCTL( indices,
979 (drm_mga_indices_t __user *)data,
980 sizeof(indices) );
981
982 if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL);
983
984 buf = dma->buflist[indices.idx];
985 buf_priv = buf->dev_private;
986
987 buf_priv->discard = indices.discard;
988
989 if ( !mga_verify_state( dev_priv ) ) {
990 if ( indices.discard ) {
991 if ( buf_priv->dispatched == 1 )
992 AGE_BUFFER( buf_priv );
993 buf_priv->dispatched = 0;
994 mga_freelist_put( dev, buf );
995 }
996 return DRM_ERR(EINVAL);
997 }
998
999 WRAP_TEST_WITH_RETURN( dev_priv );
1000
1001 mga_dma_dispatch_indices( dev, buf, indices.start, indices.end );
1002
1003 return 0;
1004 }
1005
1006 static int mga_dma_iload( DRM_IOCTL_ARGS )
1007 {
1008 DRM_DEVICE;
1009 drm_device_dma_t *dma = dev->dma;
1010 drm_mga_private_t *dev_priv = dev->dev_private;
1011 drm_buf_t *buf;
1012 drm_mga_buf_priv_t *buf_priv;
1013 drm_mga_iload_t iload;
1014 DRM_DEBUG( "\n" );
1015
1016 LOCK_TEST_WITH_RETURN( dev, filp );
1017
1018 DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) );
1019
1020 #if 0
1021 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {
1022 if ( MGA_DMA_DEBUG )
1023 DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ );
1024 return DRM_ERR(EBUSY);
1025 }
1026 #endif
1027 if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL);
1028
1029 buf = dma->buflist[iload.idx];
1030 buf_priv = buf->dev_private;
1031
1032 if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) {
1033 mga_freelist_put( dev, buf );
1034 return DRM_ERR(EINVAL);
1035 }
1036
1037 WRAP_TEST_WITH_RETURN( dev_priv );
1038
1039 mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length );
1040
1041 /* Make sure we restore the 3D state next time.
1042 */
1043 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1044
1045 return 0;
1046 }
1047
1048 static int mga_dma_blit( DRM_IOCTL_ARGS )
1049 {
1050 DRM_DEVICE;
1051 drm_mga_private_t *dev_priv = dev->dev_private;
1052 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1053 drm_mga_blit_t blit;
1054 DRM_DEBUG( "\n" );
1055
1056 LOCK_TEST_WITH_RETURN( dev, filp );
1057
1058 DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) );
1059
1060 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
1061 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1062
1063 if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) )
1064 return DRM_ERR(EINVAL);
1065
1066 WRAP_TEST_WITH_RETURN( dev_priv );
1067
1068 mga_dma_dispatch_blit( dev, &blit );
1069
1070 /* Make sure we restore the 3D state next time.
1071 */
1072 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1073
1074 return 0;
1075 }
1076
1077 static int mga_getparam( DRM_IOCTL_ARGS )
1078 {
1079 DRM_DEVICE;
1080 drm_mga_private_t *dev_priv = dev->dev_private;
1081 drm_mga_getparam_t param;
1082 int value;
1083
1084 if ( !dev_priv ) {
1085 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1086 return DRM_ERR(EINVAL);
1087 }
1088
1089 DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data,
1090 sizeof(param) );
1091
1092 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
1093
1094 switch( param.param ) {
1095 case MGA_PARAM_IRQ_NR:
1096 value = dev->irq;
1097 break;
1098 default:
1099 return DRM_ERR(EINVAL);
1100 }
1101
1102 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
1103 DRM_ERROR( "copy_to_user\n" );
1104 return DRM_ERR(EFAULT);
1105 }
1106
1107 return 0;
1108 }
1109
1110 drm_ioctl_desc_t mga_ioctls[] = {
1111 [DRM_IOCTL_NR(DRM_MGA_INIT)] = { mga_dma_init, 1, 1 },
1112 [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = { mga_dma_flush, 1, 0 },
1113 [DRM_IOCTL_NR(DRM_MGA_RESET)] = { mga_dma_reset, 1, 0 },
1114 [DRM_IOCTL_NR(DRM_MGA_SWAP)] = { mga_dma_swap, 1, 0 },
1115 [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = { mga_dma_clear, 1, 0 },
1116 [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 },
1117 [DRM_IOCTL_NR(DRM_MGA_INDICES)] = { mga_dma_indices, 1, 0 },
1118 [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = { mga_dma_iload, 1, 0 },
1119 [DRM_IOCTL_NR(DRM_MGA_BLIT)] = { mga_dma_blit, 1, 0 },
1120 [DRM_IOCTL_NR(DRM_MGA_GETPARAM)]= { mga_getparam, 1, 0 },
1121 };
1122
1123 int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);
Verdex Pro support