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Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/gregkh/driver...
[linux-2.6/verdex.git] / drivers / char / drm / radeon_cp.c
blob20bcf872b348859fec8ca7ccab6270d2d400a192
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "radeon_drm.h"
34 #include "radeon_drv.h"
35
36 #define RADEON_FIFO_DEBUG 0
37
38 static int radeon_do_cleanup_cp( drm_device_t *dev );
39
40 /* CP microcode (from ATI) */
41 static u32 R200_cp_microcode[][2] = {
42 { 0x21007000, 0000000000 },
43 { 0x20007000, 0000000000 },
44 { 0x000000ab, 0x00000004 },
45 { 0x000000af, 0x00000004 },
46 { 0x66544a49, 0000000000 },
47 { 0x49494174, 0000000000 },
48 { 0x54517d83, 0000000000 },
49 { 0x498d8b64, 0000000000 },
50 { 0x49494949, 0000000000 },
51 { 0x49da493c, 0000000000 },
52 { 0x49989898, 0000000000 },
53 { 0xd34949d5, 0000000000 },
54 { 0x9dc90e11, 0000000000 },
55 { 0xce9b9b9b, 0000000000 },
56 { 0x000f0000, 0x00000016 },
57 { 0x352e232c, 0000000000 },
58 { 0x00000013, 0x00000004 },
59 { 0x000f0000, 0x00000016 },
60 { 0x352e272c, 0000000000 },
61 { 0x000f0001, 0x00000016 },
62 { 0x3239362f, 0000000000 },
63 { 0x000077ef, 0x00000002 },
64 { 0x00061000, 0x00000002 },
65 { 0x00000020, 0x0000001a },
66 { 0x00004000, 0x0000001e },
67 { 0x00061000, 0x00000002 },
68 { 0x00000020, 0x0000001a },
69 { 0x00004000, 0x0000001e },
70 { 0x00061000, 0x00000002 },
71 { 0x00000020, 0x0000001a },
72 { 0x00004000, 0x0000001e },
73 { 0x00000016, 0x00000004 },
74 { 0x0003802a, 0x00000002 },
75 { 0x040067e0, 0x00000002 },
76 { 0x00000016, 0x00000004 },
77 { 0x000077e0, 0x00000002 },
78 { 0x00065000, 0x00000002 },
79 { 0x000037e1, 0x00000002 },
80 { 0x040067e1, 0x00000006 },
81 { 0x000077e0, 0x00000002 },
82 { 0x000077e1, 0x00000002 },
83 { 0x000077e1, 0x00000006 },
84 { 0xffffffff, 0000000000 },
85 { 0x10000000, 0000000000 },
86 { 0x0003802a, 0x00000002 },
87 { 0x040067e0, 0x00000006 },
88 { 0x00007675, 0x00000002 },
89 { 0x00007676, 0x00000002 },
90 { 0x00007677, 0x00000002 },
91 { 0x00007678, 0x00000006 },
92 { 0x0003802b, 0x00000002 },
93 { 0x04002676, 0x00000002 },
94 { 0x00007677, 0x00000002 },
95 { 0x00007678, 0x00000006 },
96 { 0x0000002e, 0x00000018 },
97 { 0x0000002e, 0x00000018 },
98 { 0000000000, 0x00000006 },
99 { 0x0000002f, 0x00000018 },
100 { 0x0000002f, 0x00000018 },
101 { 0000000000, 0x00000006 },
102 { 0x01605000, 0x00000002 },
103 { 0x00065000, 0x00000002 },
104 { 0x00098000, 0x00000002 },
105 { 0x00061000, 0x00000002 },
106 { 0x64c0603d, 0x00000004 },
107 { 0x00080000, 0x00000016 },
108 { 0000000000, 0000000000 },
109 { 0x0400251d, 0x00000002 },
110 { 0x00007580, 0x00000002 },
111 { 0x00067581, 0x00000002 },
112 { 0x04002580, 0x00000002 },
113 { 0x00067581, 0x00000002 },
114 { 0x00000046, 0x00000004 },
115 { 0x00005000, 0000000000 },
116 { 0x00061000, 0x00000002 },
117 { 0x0000750e, 0x00000002 },
118 { 0x00019000, 0x00000002 },
119 { 0x00011055, 0x00000014 },
120 { 0x00000055, 0x00000012 },
121 { 0x0400250f, 0x00000002 },
122 { 0x0000504a, 0x00000004 },
123 { 0x00007565, 0x00000002 },
124 { 0x00007566, 0x00000002 },
125 { 0x00000051, 0x00000004 },
126 { 0x01e655b4, 0x00000002 },
127 { 0x4401b0dc, 0x00000002 },
128 { 0x01c110dc, 0x00000002 },
129 { 0x2666705d, 0x00000018 },
130 { 0x040c2565, 0x00000002 },
131 { 0x0000005d, 0x00000018 },
132 { 0x04002564, 0x00000002 },
133 { 0x00007566, 0x00000002 },
134 { 0x00000054, 0x00000004 },
135 { 0x00401060, 0x00000008 },
136 { 0x00101000, 0x00000002 },
137 { 0x000d80ff, 0x00000002 },
138 { 0x00800063, 0x00000008 },
139 { 0x000f9000, 0x00000002 },
140 { 0x000e00ff, 0x00000002 },
141 { 0000000000, 0x00000006 },
142 { 0x00000080, 0x00000018 },
143 { 0x00000054, 0x00000004 },
144 { 0x00007576, 0x00000002 },
145 { 0x00065000, 0x00000002 },
146 { 0x00009000, 0x00000002 },
147 { 0x00041000, 0x00000002 },
148 { 0x0c00350e, 0x00000002 },
149 { 0x00049000, 0x00000002 },
150 { 0x00051000, 0x00000002 },
151 { 0x01e785f8, 0x00000002 },
152 { 0x00200000, 0x00000002 },
153 { 0x00600073, 0x0000000c },
154 { 0x00007563, 0x00000002 },
155 { 0x006075f0, 0x00000021 },
156 { 0x20007068, 0x00000004 },
157 { 0x00005068, 0x00000004 },
158 { 0x00007576, 0x00000002 },
159 { 0x00007577, 0x00000002 },
160 { 0x0000750e, 0x00000002 },
161 { 0x0000750f, 0x00000002 },
162 { 0x00a05000, 0x00000002 },
163 { 0x00600076, 0x0000000c },
164 { 0x006075f0, 0x00000021 },
165 { 0x000075f8, 0x00000002 },
166 { 0x00000076, 0x00000004 },
167 { 0x000a750e, 0x00000002 },
168 { 0x0020750f, 0x00000002 },
169 { 0x00600079, 0x00000004 },
170 { 0x00007570, 0x00000002 },
171 { 0x00007571, 0x00000002 },
172 { 0x00007572, 0x00000006 },
173 { 0x00005000, 0x00000002 },
174 { 0x00a05000, 0x00000002 },
175 { 0x00007568, 0x00000002 },
176 { 0x00061000, 0x00000002 },
177 { 0x00000084, 0x0000000c },
178 { 0x00058000, 0x00000002 },
179 { 0x0c607562, 0x00000002 },
180 { 0x00000086, 0x00000004 },
181 { 0x00600085, 0x00000004 },
182 { 0x400070dd, 0000000000 },
183 { 0x000380dd, 0x00000002 },
184 { 0x00000093, 0x0000001c },
185 { 0x00065095, 0x00000018 },
186 { 0x040025bb, 0x00000002 },
187 { 0x00061096, 0x00000018 },
188 { 0x040075bc, 0000000000 },
189 { 0x000075bb, 0x00000002 },
190 { 0x000075bc, 0000000000 },
191 { 0x00090000, 0x00000006 },
192 { 0x00090000, 0x00000002 },
193 { 0x000d8002, 0x00000006 },
194 { 0x00005000, 0x00000002 },
195 { 0x00007821, 0x00000002 },
196 { 0x00007800, 0000000000 },
197 { 0x00007821, 0x00000002 },
198 { 0x00007800, 0000000000 },
199 { 0x01665000, 0x00000002 },
200 { 0x000a0000, 0x00000002 },
201 { 0x000671cc, 0x00000002 },
202 { 0x0286f1cd, 0x00000002 },
203 { 0x000000a3, 0x00000010 },
204 { 0x21007000, 0000000000 },
205 { 0x000000aa, 0x0000001c },
206 { 0x00065000, 0x00000002 },
207 { 0x000a0000, 0x00000002 },
208 { 0x00061000, 0x00000002 },
209 { 0x000b0000, 0x00000002 },
210 { 0x38067000, 0x00000002 },
211 { 0x000a00a6, 0x00000004 },
212 { 0x20007000, 0000000000 },
213 { 0x01200000, 0x00000002 },
214 { 0x20077000, 0x00000002 },
215 { 0x01200000, 0x00000002 },
216 { 0x20007000, 0000000000 },
217 { 0x00061000, 0x00000002 },
218 { 0x0120751b, 0x00000002 },
219 { 0x8040750a, 0x00000002 },
220 { 0x8040750b, 0x00000002 },
221 { 0x00110000, 0x00000002 },
222 { 0x000380dd, 0x00000002 },
223 { 0x000000bd, 0x0000001c },
224 { 0x00061096, 0x00000018 },
225 { 0x844075bd, 0x00000002 },
226 { 0x00061095, 0x00000018 },
227 { 0x840075bb, 0x00000002 },
228 { 0x00061096, 0x00000018 },
229 { 0x844075bc, 0x00000002 },
230 { 0x000000c0, 0x00000004 },
231 { 0x804075bd, 0x00000002 },
232 { 0x800075bb, 0x00000002 },
233 { 0x804075bc, 0x00000002 },
234 { 0x00108000, 0x00000002 },
235 { 0x01400000, 0x00000002 },
236 { 0x006000c4, 0x0000000c },
237 { 0x20c07000, 0x00000020 },
238 { 0x000000c6, 0x00000012 },
239 { 0x00800000, 0x00000006 },
240 { 0x0080751d, 0x00000006 },
241 { 0x000025bb, 0x00000002 },
242 { 0x000040c0, 0x00000004 },
243 { 0x0000775c, 0x00000002 },
244 { 0x00a05000, 0x00000002 },
245 { 0x00661000, 0x00000002 },
246 { 0x0460275d, 0x00000020 },
247 { 0x00004000, 0000000000 },
248 { 0x00007999, 0x00000002 },
249 { 0x00a05000, 0x00000002 },
250 { 0x00661000, 0x00000002 },
251 { 0x0460299b, 0x00000020 },
252 { 0x00004000, 0000000000 },
253 { 0x01e00830, 0x00000002 },
254 { 0x21007000, 0000000000 },
255 { 0x00005000, 0x00000002 },
256 { 0x00038042, 0x00000002 },
257 { 0x040025e0, 0x00000002 },
258 { 0x000075e1, 0000000000 },
259 { 0x00000001, 0000000000 },
260 { 0x000380d9, 0x00000002 },
261 { 0x04007394, 0000000000 },
262 { 0000000000, 0000000000 },
263 { 0000000000, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
297 { 0000000000, 0000000000 },
298 };
299
300
301 static u32 radeon_cp_microcode[][2] = {
302 { 0x21007000, 0000000000 },
303 { 0x20007000, 0000000000 },
304 { 0x000000b4, 0x00000004 },
305 { 0x000000b8, 0x00000004 },
306 { 0x6f5b4d4c, 0000000000 },
307 { 0x4c4c427f, 0000000000 },
308 { 0x5b568a92, 0000000000 },
309 { 0x4ca09c6d, 0000000000 },
310 { 0xad4c4c4c, 0000000000 },
311 { 0x4ce1af3d, 0000000000 },
312 { 0xd8afafaf, 0000000000 },
313 { 0xd64c4cdc, 0000000000 },
314 { 0x4cd10d10, 0000000000 },
315 { 0x000f0000, 0x00000016 },
316 { 0x362f242d, 0000000000 },
317 { 0x00000012, 0x00000004 },
318 { 0x000f0000, 0x00000016 },
319 { 0x362f282d, 0000000000 },
320 { 0x000380e7, 0x00000002 },
321 { 0x04002c97, 0x00000002 },
322 { 0x000f0001, 0x00000016 },
323 { 0x333a3730, 0000000000 },
324 { 0x000077ef, 0x00000002 },
325 { 0x00061000, 0x00000002 },
326 { 0x00000021, 0x0000001a },
327 { 0x00004000, 0x0000001e },
328 { 0x00061000, 0x00000002 },
329 { 0x00000021, 0x0000001a },
330 { 0x00004000, 0x0000001e },
331 { 0x00061000, 0x00000002 },
332 { 0x00000021, 0x0000001a },
333 { 0x00004000, 0x0000001e },
334 { 0x00000017, 0x00000004 },
335 { 0x0003802b, 0x00000002 },
336 { 0x040067e0, 0x00000002 },
337 { 0x00000017, 0x00000004 },
338 { 0x000077e0, 0x00000002 },
339 { 0x00065000, 0x00000002 },
340 { 0x000037e1, 0x00000002 },
341 { 0x040067e1, 0x00000006 },
342 { 0x000077e0, 0x00000002 },
343 { 0x000077e1, 0x00000002 },
344 { 0x000077e1, 0x00000006 },
345 { 0xffffffff, 0000000000 },
346 { 0x10000000, 0000000000 },
347 { 0x0003802b, 0x00000002 },
348 { 0x040067e0, 0x00000006 },
349 { 0x00007675, 0x00000002 },
350 { 0x00007676, 0x00000002 },
351 { 0x00007677, 0x00000002 },
352 { 0x00007678, 0x00000006 },
353 { 0x0003802c, 0x00000002 },
354 { 0x04002676, 0x00000002 },
355 { 0x00007677, 0x00000002 },
356 { 0x00007678, 0x00000006 },
357 { 0x0000002f, 0x00000018 },
358 { 0x0000002f, 0x00000018 },
359 { 0000000000, 0x00000006 },
360 { 0x00000030, 0x00000018 },
361 { 0x00000030, 0x00000018 },
362 { 0000000000, 0x00000006 },
363 { 0x01605000, 0x00000002 },
364 { 0x00065000, 0x00000002 },
365 { 0x00098000, 0x00000002 },
366 { 0x00061000, 0x00000002 },
367 { 0x64c0603e, 0x00000004 },
368 { 0x000380e6, 0x00000002 },
369 { 0x040025c5, 0x00000002 },
370 { 0x00080000, 0x00000016 },
371 { 0000000000, 0000000000 },
372 { 0x0400251d, 0x00000002 },
373 { 0x00007580, 0x00000002 },
374 { 0x00067581, 0x00000002 },
375 { 0x04002580, 0x00000002 },
376 { 0x00067581, 0x00000002 },
377 { 0x00000049, 0x00000004 },
378 { 0x00005000, 0000000000 },
379 { 0x000380e6, 0x00000002 },
380 { 0x040025c5, 0x00000002 },
381 { 0x00061000, 0x00000002 },
382 { 0x0000750e, 0x00000002 },
383 { 0x00019000, 0x00000002 },
384 { 0x00011055, 0x00000014 },
385 { 0x00000055, 0x00000012 },
386 { 0x0400250f, 0x00000002 },
387 { 0x0000504f, 0x00000004 },
388 { 0x000380e6, 0x00000002 },
389 { 0x040025c5, 0x00000002 },
390 { 0x00007565, 0x00000002 },
391 { 0x00007566, 0x00000002 },
392 { 0x00000058, 0x00000004 },
393 { 0x000380e6, 0x00000002 },
394 { 0x040025c5, 0x00000002 },
395 { 0x01e655b4, 0x00000002 },
396 { 0x4401b0e4, 0x00000002 },
397 { 0x01c110e4, 0x00000002 },
398 { 0x26667066, 0x00000018 },
399 { 0x040c2565, 0x00000002 },
400 { 0x00000066, 0x00000018 },
401 { 0x04002564, 0x00000002 },
402 { 0x00007566, 0x00000002 },
403 { 0x0000005d, 0x00000004 },
404 { 0x00401069, 0x00000008 },
405 { 0x00101000, 0x00000002 },
406 { 0x000d80ff, 0x00000002 },
407 { 0x0080006c, 0x00000008 },
408 { 0x000f9000, 0x00000002 },
409 { 0x000e00ff, 0x00000002 },
410 { 0000000000, 0x00000006 },
411 { 0x0000008f, 0x00000018 },
412 { 0x0000005b, 0x00000004 },
413 { 0x000380e6, 0x00000002 },
414 { 0x040025c5, 0x00000002 },
415 { 0x00007576, 0x00000002 },
416 { 0x00065000, 0x00000002 },
417 { 0x00009000, 0x00000002 },
418 { 0x00041000, 0x00000002 },
419 { 0x0c00350e, 0x00000002 },
420 { 0x00049000, 0x00000002 },
421 { 0x00051000, 0x00000002 },
422 { 0x01e785f8, 0x00000002 },
423 { 0x00200000, 0x00000002 },
424 { 0x0060007e, 0x0000000c },
425 { 0x00007563, 0x00000002 },
426 { 0x006075f0, 0x00000021 },
427 { 0x20007073, 0x00000004 },
428 { 0x00005073, 0x00000004 },
429 { 0x000380e6, 0x00000002 },
430 { 0x040025c5, 0x00000002 },
431 { 0x00007576, 0x00000002 },
432 { 0x00007577, 0x00000002 },
433 { 0x0000750e, 0x00000002 },
434 { 0x0000750f, 0x00000002 },
435 { 0x00a05000, 0x00000002 },
436 { 0x00600083, 0x0000000c },
437 { 0x006075f0, 0x00000021 },
438 { 0x000075f8, 0x00000002 },
439 { 0x00000083, 0x00000004 },
440 { 0x000a750e, 0x00000002 },
441 { 0x000380e6, 0x00000002 },
442 { 0x040025c5, 0x00000002 },
443 { 0x0020750f, 0x00000002 },
444 { 0x00600086, 0x00000004 },
445 { 0x00007570, 0x00000002 },
446 { 0x00007571, 0x00000002 },
447 { 0x00007572, 0x00000006 },
448 { 0x000380e6, 0x00000002 },
449 { 0x040025c5, 0x00000002 },
450 { 0x00005000, 0x00000002 },
451 { 0x00a05000, 0x00000002 },
452 { 0x00007568, 0x00000002 },
453 { 0x00061000, 0x00000002 },
454 { 0x00000095, 0x0000000c },
455 { 0x00058000, 0x00000002 },
456 { 0x0c607562, 0x00000002 },
457 { 0x00000097, 0x00000004 },
458 { 0x000380e6, 0x00000002 },
459 { 0x040025c5, 0x00000002 },
460 { 0x00600096, 0x00000004 },
461 { 0x400070e5, 0000000000 },
462 { 0x000380e6, 0x00000002 },
463 { 0x040025c5, 0x00000002 },
464 { 0x000380e5, 0x00000002 },
465 { 0x000000a8, 0x0000001c },
466 { 0x000650aa, 0x00000018 },
467 { 0x040025bb, 0x00000002 },
468 { 0x000610ab, 0x00000018 },
469 { 0x040075bc, 0000000000 },
470 { 0x000075bb, 0x00000002 },
471 { 0x000075bc, 0000000000 },
472 { 0x00090000, 0x00000006 },
473 { 0x00090000, 0x00000002 },
474 { 0x000d8002, 0x00000006 },
475 { 0x00007832, 0x00000002 },
476 { 0x00005000, 0x00000002 },
477 { 0x000380e7, 0x00000002 },
478 { 0x04002c97, 0x00000002 },
479 { 0x00007820, 0x00000002 },
480 { 0x00007821, 0x00000002 },
481 { 0x00007800, 0000000000 },
482 { 0x01200000, 0x00000002 },
483 { 0x20077000, 0x00000002 },
484 { 0x01200000, 0x00000002 },
485 { 0x20007000, 0x00000002 },
486 { 0x00061000, 0x00000002 },
487 { 0x0120751b, 0x00000002 },
488 { 0x8040750a, 0x00000002 },
489 { 0x8040750b, 0x00000002 },
490 { 0x00110000, 0x00000002 },
491 { 0x000380e5, 0x00000002 },
492 { 0x000000c6, 0x0000001c },
493 { 0x000610ab, 0x00000018 },
494 { 0x844075bd, 0x00000002 },
495 { 0x000610aa, 0x00000018 },
496 { 0x840075bb, 0x00000002 },
497 { 0x000610ab, 0x00000018 },
498 { 0x844075bc, 0x00000002 },
499 { 0x000000c9, 0x00000004 },
500 { 0x804075bd, 0x00000002 },
501 { 0x800075bb, 0x00000002 },
502 { 0x804075bc, 0x00000002 },
503 { 0x00108000, 0x00000002 },
504 { 0x01400000, 0x00000002 },
505 { 0x006000cd, 0x0000000c },
506 { 0x20c07000, 0x00000020 },
507 { 0x000000cf, 0x00000012 },
508 { 0x00800000, 0x00000006 },
509 { 0x0080751d, 0x00000006 },
510 { 0000000000, 0000000000 },
511 { 0x0000775c, 0x00000002 },
512 { 0x00a05000, 0x00000002 },
513 { 0x00661000, 0x00000002 },
514 { 0x0460275d, 0x00000020 },
515 { 0x00004000, 0000000000 },
516 { 0x01e00830, 0x00000002 },
517 { 0x21007000, 0000000000 },
518 { 0x6464614d, 0000000000 },
519 { 0x69687420, 0000000000 },
520 { 0x00000073, 0000000000 },
521 { 0000000000, 0000000000 },
522 { 0x00005000, 0x00000002 },
523 { 0x000380d0, 0x00000002 },
524 { 0x040025e0, 0x00000002 },
525 { 0x000075e1, 0000000000 },
526 { 0x00000001, 0000000000 },
527 { 0x000380e0, 0x00000002 },
528 { 0x04002394, 0x00000002 },
529 { 0x00005000, 0000000000 },
530 { 0000000000, 0000000000 },
531 { 0000000000, 0000000000 },
532 { 0x00000008, 0000000000 },
533 { 0x00000004, 0000000000 },
534 { 0000000000, 0000000000 },
535 { 0000000000, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0000000000, 0000000000 },
539 { 0000000000, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
557 { 0000000000, 0000000000 },
558 };
559
560 static u32 R300_cp_microcode[][2] = {
561 { 0x4200e000, 0000000000 },
562 { 0x4000e000, 0000000000 },
563 { 0x000000af, 0x00000008 },
564 { 0x000000b3, 0x00000008 },
565 { 0x6c5a504f, 0000000000 },
566 { 0x4f4f497a, 0000000000 },
567 { 0x5a578288, 0000000000 },
568 { 0x4f91906a, 0000000000 },
569 { 0x4f4f4f4f, 0000000000 },
570 { 0x4fe24f44, 0000000000 },
571 { 0x4f9c9c9c, 0000000000 },
572 { 0xdc4f4fde, 0000000000 },
573 { 0xa1cd4f4f, 0000000000 },
574 { 0xd29d9d9d, 0000000000 },
575 { 0x4f0f9fd7, 0000000000 },
576 { 0x000ca000, 0x00000004 },
577 { 0x000d0012, 0x00000038 },
578 { 0x0000e8b4, 0x00000004 },
579 { 0x000d0014, 0x00000038 },
580 { 0x0000e8b6, 0x00000004 },
581 { 0x000d0016, 0x00000038 },
582 { 0x0000e854, 0x00000004 },
583 { 0x000d0018, 0x00000038 },
584 { 0x0000e855, 0x00000004 },
585 { 0x000d001a, 0x00000038 },
586 { 0x0000e856, 0x00000004 },
587 { 0x000d001c, 0x00000038 },
588 { 0x0000e857, 0x00000004 },
589 { 0x000d001e, 0x00000038 },
590 { 0x0000e824, 0x00000004 },
591 { 0x000d0020, 0x00000038 },
592 { 0x0000e825, 0x00000004 },
593 { 0x000d0022, 0x00000038 },
594 { 0x0000e830, 0x00000004 },
595 { 0x000d0024, 0x00000038 },
596 { 0x0000f0c0, 0x00000004 },
597 { 0x000d0026, 0x00000038 },
598 { 0x0000f0c1, 0x00000004 },
599 { 0x000d0028, 0x00000038 },
600 { 0x0000f041, 0x00000004 },
601 { 0x000d002a, 0x00000038 },
602 { 0x0000f184, 0x00000004 },
603 { 0x000d002c, 0x00000038 },
604 { 0x0000f185, 0x00000004 },
605 { 0x000d002e, 0x00000038 },
606 { 0x0000f186, 0x00000004 },
607 { 0x000d0030, 0x00000038 },
608 { 0x0000f187, 0x00000004 },
609 { 0x000d0032, 0x00000038 },
610 { 0x0000f180, 0x00000004 },
611 { 0x000d0034, 0x00000038 },
612 { 0x0000f393, 0x00000004 },
613 { 0x000d0036, 0x00000038 },
614 { 0x0000f38a, 0x00000004 },
615 { 0x000d0038, 0x00000038 },
616 { 0x0000f38e, 0x00000004 },
617 { 0x0000e821, 0x00000004 },
618 { 0x0140a000, 0x00000004 },
619 { 0x00000043, 0x00000018 },
620 { 0x00cce800, 0x00000004 },
621 { 0x001b0001, 0x00000004 },
622 { 0x08004800, 0x00000004 },
623 { 0x001b0001, 0x00000004 },
624 { 0x08004800, 0x00000004 },
625 { 0x001b0001, 0x00000004 },
626 { 0x08004800, 0x00000004 },
627 { 0x0000003a, 0x00000008 },
628 { 0x0000a000, 0000000000 },
629 { 0x02c0a000, 0x00000004 },
630 { 0x000ca000, 0x00000004 },
631 { 0x00130000, 0x00000004 },
632 { 0x000c2000, 0x00000004 },
633 { 0xc980c045, 0x00000008 },
634 { 0x2000451d, 0x00000004 },
635 { 0x0000e580, 0x00000004 },
636 { 0x000ce581, 0x00000004 },
637 { 0x08004580, 0x00000004 },
638 { 0x000ce581, 0x00000004 },
639 { 0x0000004c, 0x00000008 },
640 { 0x0000a000, 0000000000 },
641 { 0x000c2000, 0x00000004 },
642 { 0x0000e50e, 0x00000004 },
643 { 0x00032000, 0x00000004 },
644 { 0x00022056, 0x00000028 },
645 { 0x00000056, 0x00000024 },
646 { 0x0800450f, 0x00000004 },
647 { 0x0000a050, 0x00000008 },
648 { 0x0000e565, 0x00000004 },
649 { 0x0000e566, 0x00000004 },
650 { 0x00000057, 0x00000008 },
651 { 0x03cca5b4, 0x00000004 },
652 { 0x05432000, 0x00000004 },
653 { 0x00022000, 0x00000004 },
654 { 0x4ccce063, 0x00000030 },
655 { 0x08274565, 0x00000004 },
656 { 0x00000063, 0x00000030 },
657 { 0x08004564, 0x00000004 },
658 { 0x0000e566, 0x00000004 },
659 { 0x0000005a, 0x00000008 },
660 { 0x00802066, 0x00000010 },
661 { 0x00202000, 0x00000004 },
662 { 0x001b00ff, 0x00000004 },
663 { 0x01000069, 0x00000010 },
664 { 0x001f2000, 0x00000004 },
665 { 0x001c00ff, 0x00000004 },
666 { 0000000000, 0x0000000c },
667 { 0x00000085, 0x00000030 },
668 { 0x0000005a, 0x00000008 },
669 { 0x0000e576, 0x00000004 },
670 { 0x000ca000, 0x00000004 },
671 { 0x00012000, 0x00000004 },
672 { 0x00082000, 0x00000004 },
673 { 0x1800650e, 0x00000004 },
674 { 0x00092000, 0x00000004 },
675 { 0x000a2000, 0x00000004 },
676 { 0x000f0000, 0x00000004 },
677 { 0x00400000, 0x00000004 },
678 { 0x00000079, 0x00000018 },
679 { 0x0000e563, 0x00000004 },
680 { 0x00c0e5f9, 0x000000c2 },
681 { 0x0000006e, 0x00000008 },
682 { 0x0000a06e, 0x00000008 },
683 { 0x0000e576, 0x00000004 },
684 { 0x0000e577, 0x00000004 },
685 { 0x0000e50e, 0x00000004 },
686 { 0x0000e50f, 0x00000004 },
687 { 0x0140a000, 0x00000004 },
688 { 0x0000007c, 0x00000018 },
689 { 0x00c0e5f9, 0x000000c2 },
690 { 0x0000007c, 0x00000008 },
691 { 0x0014e50e, 0x00000004 },
692 { 0x0040e50f, 0x00000004 },
693 { 0x00c0007f, 0x00000008 },
694 { 0x0000e570, 0x00000004 },
695 { 0x0000e571, 0x00000004 },
696 { 0x0000e572, 0x0000000c },
697 { 0x0000a000, 0x00000004 },
698 { 0x0140a000, 0x00000004 },
699 { 0x0000e568, 0x00000004 },
700 { 0x000c2000, 0x00000004 },
701 { 0x00000089, 0x00000018 },
702 { 0x000b0000, 0x00000004 },
703 { 0x18c0e562, 0x00000004 },
704 { 0x0000008b, 0x00000008 },
705 { 0x00c0008a, 0x00000008 },
706 { 0x000700e4, 0x00000004 },
707 { 0x00000097, 0x00000038 },
708 { 0x000ca099, 0x00000030 },
709 { 0x080045bb, 0x00000004 },
710 { 0x000c209a, 0x00000030 },
711 { 0x0800e5bc, 0000000000 },
712 { 0x0000e5bb, 0x00000004 },
713 { 0x0000e5bc, 0000000000 },
714 { 0x00120000, 0x0000000c },
715 { 0x00120000, 0x00000004 },
716 { 0x001b0002, 0x0000000c },
717 { 0x0000a000, 0x00000004 },
718 { 0x0000e821, 0x00000004 },
719 { 0x0000e800, 0000000000 },
720 { 0x0000e821, 0x00000004 },
721 { 0x0000e82e, 0000000000 },
722 { 0x02cca000, 0x00000004 },
723 { 0x00140000, 0x00000004 },
724 { 0x000ce1cc, 0x00000004 },
725 { 0x050de1cd, 0x00000004 },
726 { 0x000000a7, 0x00000020 },
727 { 0x4200e000, 0000000000 },
728 { 0x000000ae, 0x00000038 },
729 { 0x000ca000, 0x00000004 },
730 { 0x00140000, 0x00000004 },
731 { 0x000c2000, 0x00000004 },
732 { 0x00160000, 0x00000004 },
733 { 0x700ce000, 0x00000004 },
734 { 0x001400aa, 0x00000008 },
735 { 0x4000e000, 0000000000 },
736 { 0x02400000, 0x00000004 },
737 { 0x400ee000, 0x00000004 },
738 { 0x02400000, 0x00000004 },
739 { 0x4000e000, 0000000000 },
740 { 0x000c2000, 0x00000004 },
741 { 0x0240e51b, 0x00000004 },
742 { 0x0080e50a, 0x00000005 },
743 { 0x0080e50b, 0x00000005 },
744 { 0x00220000, 0x00000004 },
745 { 0x000700e4, 0x00000004 },
746 { 0x000000c1, 0x00000038 },
747 { 0x000c209a, 0x00000030 },
748 { 0x0880e5bd, 0x00000005 },
749 { 0x000c2099, 0x00000030 },
750 { 0x0800e5bb, 0x00000005 },
751 { 0x000c209a, 0x00000030 },
752 { 0x0880e5bc, 0x00000005 },
753 { 0x000000c4, 0x00000008 },
754 { 0x0080e5bd, 0x00000005 },
755 { 0x0000e5bb, 0x00000005 },
756 { 0x0080e5bc, 0x00000005 },
757 { 0x00210000, 0x00000004 },
758 { 0x02800000, 0x00000004 },
759 { 0x00c000c8, 0x00000018 },
760 { 0x4180e000, 0x00000040 },
761 { 0x000000ca, 0x00000024 },
762 { 0x01000000, 0x0000000c },
763 { 0x0100e51d, 0x0000000c },
764 { 0x000045bb, 0x00000004 },
765 { 0x000080c4, 0x00000008 },
766 { 0x0000f3ce, 0x00000004 },
767 { 0x0140a000, 0x00000004 },
768 { 0x00cc2000, 0x00000004 },
769 { 0x08c053cf, 0x00000040 },
770 { 0x00008000, 0000000000 },
771 { 0x0000f3d2, 0x00000004 },
772 { 0x0140a000, 0x00000004 },
773 { 0x00cc2000, 0x00000004 },
774 { 0x08c053d3, 0x00000040 },
775 { 0x00008000, 0000000000 },
776 { 0x0000f39d, 0x00000004 },
777 { 0x0140a000, 0x00000004 },
778 { 0x00cc2000, 0x00000004 },
779 { 0x08c0539e, 0x00000040 },
780 { 0x00008000, 0000000000 },
781 { 0x03c00830, 0x00000004 },
782 { 0x4200e000, 0000000000 },
783 { 0x0000a000, 0x00000004 },
784 { 0x200045e0, 0x00000004 },
785 { 0x0000e5e1, 0000000000 },
786 { 0x00000001, 0000000000 },
787 { 0x000700e1, 0x00000004 },
788 { 0x0800e394, 0000000000 },
789 { 0000000000, 0000000000 },
790 { 0000000000, 0000000000 },
791 { 0000000000, 0000000000 },
792 { 0000000000, 0000000000 },
793 { 0000000000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0000000000, 0000000000 },
796 { 0000000000, 0000000000 },
797 { 0000000000, 0000000000 },
798 { 0000000000, 0000000000 },
799 { 0000000000, 0000000000 },
800 { 0000000000, 0000000000 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805 { 0000000000, 0000000000 },
806 { 0000000000, 0000000000 },
807 { 0000000000, 0000000000 },
808 { 0000000000, 0000000000 },
809 { 0000000000, 0000000000 },
810 { 0000000000, 0000000000 },
811 { 0000000000, 0000000000 },
812 { 0000000000, 0000000000 },
813 { 0000000000, 0000000000 },
814 { 0000000000, 0000000000 },
815 { 0000000000, 0000000000 },
816 { 0000000000, 0000000000 },
817 };
818
819 static int RADEON_READ_PLL(drm_device_t *dev, int addr)
820 {
821 drm_radeon_private_t *dev_priv = dev->dev_private;
822
823 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
825 }
826
827 #if RADEON_FIFO_DEBUG
828 static void radeon_status( drm_radeon_private_t *dev_priv )
829 {
830 printk( "%s:\n", __FUNCTION__ );
831 printk( "RBBM_STATUS = 0x%08x\n",
832 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
833 printk( "CP_RB_RTPR = 0x%08x\n",
834 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
835 printk( "CP_RB_WTPR = 0x%08x\n",
836 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
837 printk( "AIC_CNTL = 0x%08x\n",
838 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
839 printk( "AIC_STAT = 0x%08x\n",
840 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
841 printk( "AIC_PT_BASE = 0x%08x\n",
842 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
843 printk( "TLB_ADDR = 0x%08x\n",
844 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
845 printk( "TLB_DATA = 0x%08x\n",
846 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
847 }
848 #endif
849
850
851 /* ================================================================
852 * Engine, FIFO control
853 */
854
855 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
856 {
857 u32 tmp;
858 int i;
859
860 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
861
862 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
863 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
864 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
865
866 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
867 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
868 & RADEON_RB2D_DC_BUSY) ) {
869 return 0;
870 }
871 DRM_UDELAY( 1 );
872 }
873
874 #if RADEON_FIFO_DEBUG
875 DRM_ERROR( "failed!\n" );
876 radeon_status( dev_priv );
877 #endif
878 return DRM_ERR(EBUSY);
879 }
880
881 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
882 int entries )
883 {
884 int i;
885
886 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
887
888 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
889 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
890 & RADEON_RBBM_FIFOCNT_MASK );
891 if ( slots >= entries ) return 0;
892 DRM_UDELAY( 1 );
893 }
894
895 #if RADEON_FIFO_DEBUG
896 DRM_ERROR( "failed!\n" );
897 radeon_status( dev_priv );
898 #endif
899 return DRM_ERR(EBUSY);
900 }
901
902 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
903 {
904 int i, ret;
905
906 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
907
908 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
909 if ( ret ) return ret;
910
911 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
912 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
913 & RADEON_RBBM_ACTIVE) ) {
914 radeon_do_pixcache_flush( dev_priv );
915 return 0;
916 }
917 DRM_UDELAY( 1 );
918 }
919
920 #if RADEON_FIFO_DEBUG
921 DRM_ERROR( "failed!\n" );
922 radeon_status( dev_priv );
923 #endif
924 return DRM_ERR(EBUSY);
925 }
926
927
928 /* ================================================================
929 * CP control, initialization
930 */
931
932 /* Load the microcode for the CP */
933 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
934 {
935 int i;
936 DRM_DEBUG( "\n" );
937
938 radeon_do_wait_for_idle( dev_priv );
939
940 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
941
942 if (dev_priv->microcode_version==UCODE_R200) {
943 DRM_INFO("Loading R200 Microcode\n");
944 for ( i = 0 ; i < 256 ; i++ )
945 {
946 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
947 R200_cp_microcode[i][1] );
948 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
949 R200_cp_microcode[i][0] );
950 }
951 } else if (dev_priv->microcode_version==UCODE_R300) {
952 DRM_INFO("Loading R300 Microcode\n");
953 for ( i = 0 ; i < 256 ; i++ )
954 {
955 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
956 R300_cp_microcode[i][1] );
957 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
958 R300_cp_microcode[i][0] );
959 }
960 } else {
961 for ( i = 0 ; i < 256 ; i++ ) {
962 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
963 radeon_cp_microcode[i][1] );
964 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
965 radeon_cp_microcode[i][0] );
966 }
967 }
968 }
969
970 /* Flush any pending commands to the CP. This should only be used just
971 * prior to a wait for idle, as it informs the engine that the command
972 * stream is ending.
973 */
974 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
975 {
976 DRM_DEBUG( "\n" );
977 #if 0
978 u32 tmp;
979
980 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
981 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
982 #endif
983 }
984
985 /* Wait for the CP to go idle.
986 */
987 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
988 {
989 RING_LOCALS;
990 DRM_DEBUG( "\n" );
991
992 BEGIN_RING( 6 );
993
994 RADEON_PURGE_CACHE();
995 RADEON_PURGE_ZCACHE();
996 RADEON_WAIT_UNTIL_IDLE();
997
998 ADVANCE_RING();
999 COMMIT_RING();
1000
1001 return radeon_do_wait_for_idle( dev_priv );
1002 }
1003
1004 /* Start the Command Processor.
1005 */
1006 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
1007 {
1008 RING_LOCALS;
1009 DRM_DEBUG( "\n" );
1010
1011 radeon_do_wait_for_idle( dev_priv );
1012
1013 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
1014
1015 dev_priv->cp_running = 1;
1016
1017 BEGIN_RING( 6 );
1018
1019 RADEON_PURGE_CACHE();
1020 RADEON_PURGE_ZCACHE();
1021 RADEON_WAIT_UNTIL_IDLE();
1022
1023 ADVANCE_RING();
1024 COMMIT_RING();
1025 }
1026
1027 /* Reset the Command Processor. This will not flush any pending
1028 * commands, so you must wait for the CP command stream to complete
1029 * before calling this routine.
1030 */
1031 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
1032 {
1033 u32 cur_read_ptr;
1034 DRM_DEBUG( "\n" );
1035
1036 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1037 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1038 SET_RING_HEAD( dev_priv, cur_read_ptr );
1039 dev_priv->ring.tail = cur_read_ptr;
1040 }
1041
1042 /* Stop the Command Processor. This will not flush any pending
1043 * commands, so you must flush the command stream and wait for the CP
1044 * to go idle before calling this routine.
1045 */
1046 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
1047 {
1048 DRM_DEBUG( "\n" );
1049
1050 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
1051
1052 dev_priv->cp_running = 0;
1053 }
1054
1055 /* Reset the engine. This will stop the CP if it is running.
1056 */
1057 static int radeon_do_engine_reset( drm_device_t *dev )
1058 {
1059 drm_radeon_private_t *dev_priv = dev->dev_private;
1060 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1061 DRM_DEBUG( "\n" );
1062
1063 radeon_do_pixcache_flush( dev_priv );
1064
1065 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
1066 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
1067
1068 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
1069 RADEON_FORCEON_MCLKA |
1070 RADEON_FORCEON_MCLKB |
1071 RADEON_FORCEON_YCLKA |
1072 RADEON_FORCEON_YCLKB |
1073 RADEON_FORCEON_MC |
1074 RADEON_FORCEON_AIC ) );
1075
1076 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
1077
1078 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
1079 RADEON_SOFT_RESET_CP |
1080 RADEON_SOFT_RESET_HI |
1081 RADEON_SOFT_RESET_SE |
1082 RADEON_SOFT_RESET_RE |
1083 RADEON_SOFT_RESET_PP |
1084 RADEON_SOFT_RESET_E2 |
1085 RADEON_SOFT_RESET_RB ) );
1086 RADEON_READ( RADEON_RBBM_SOFT_RESET );
1087 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
1088 ~( RADEON_SOFT_RESET_CP |
1089 RADEON_SOFT_RESET_HI |
1090 RADEON_SOFT_RESET_SE |
1091 RADEON_SOFT_RESET_RE |
1092 RADEON_SOFT_RESET_PP |
1093 RADEON_SOFT_RESET_E2 |
1094 RADEON_SOFT_RESET_RB ) ) );
1095 RADEON_READ( RADEON_RBBM_SOFT_RESET );
1096
1097
1098 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
1099 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
1100 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
1101
1102 /* Reset the CP ring */
1103 radeon_do_cp_reset( dev_priv );
1104
1105 /* The CP is no longer running after an engine reset */
1106 dev_priv->cp_running = 0;
1107
1108 /* Reset any pending vertex, indirect buffers */
1109 radeon_freelist_reset( dev );
1110
1111 return 0;
1112 }
1113
1114 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1115 drm_radeon_private_t *dev_priv )
1116 {
1117 u32 ring_start, cur_read_ptr;
1118 u32 tmp;
1119
1120 /* Initialize the memory controller */
1121 RADEON_WRITE( RADEON_MC_FB_LOCATION,
1122 ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
1123 | ( dev_priv->fb_location >> 16 ) );
1124
1125 #if __OS_HAS_AGP
1126 if ( !dev_priv->is_pci ) {
1127 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
1128 (((dev_priv->gart_vm_start - 1 +
1129 dev_priv->gart_size) & 0xffff0000) |
1130 (dev_priv->gart_vm_start >> 16)) );
1131
1132 ring_start = (dev_priv->cp_ring->offset
1133 - dev->agp->base
1134 + dev_priv->gart_vm_start);
1135 } else
1136 #endif
1137 ring_start = (dev_priv->cp_ring->offset
1138 - dev->sg->handle
1139 + dev_priv->gart_vm_start);
1140
1141 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
1142
1143 /* Set the write pointer delay */
1144 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
1145
1146 /* Initialize the ring buffer's read and write pointers */
1147 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1148 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1149 SET_RING_HEAD( dev_priv, cur_read_ptr );
1150 dev_priv->ring.tail = cur_read_ptr;
1151
1152 #if __OS_HAS_AGP
1153 if ( !dev_priv->is_pci ) {
1154 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1155 dev_priv->ring_rptr->offset
1156 - dev->agp->base
1157 + dev_priv->gart_vm_start);
1158 } else
1159 #endif
1160 {
1161 drm_sg_mem_t *entry = dev->sg;
1162 unsigned long tmp_ofs, page_ofs;
1163
1164 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1165 page_ofs = tmp_ofs >> PAGE_SHIFT;
1166
1167 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1168 entry->busaddr[page_ofs]);
1169 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
1170 (unsigned long) entry->busaddr[page_ofs],
1171 entry->handle + tmp_ofs );
1172 }
1173
1174 /* Initialize the scratch register pointer. This will cause
1175 * the scratch register values to be written out to memory
1176 * whenever they are updated.
1177 *
1178 * We simply put this behind the ring read pointer, this works
1179 * with PCI GART as well as (whatever kind of) AGP GART
1180 */
1181 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
1182 + RADEON_SCRATCH_REG_OFFSET );
1183
1184 dev_priv->scratch = ((__volatile__ u32 *)
1185 dev_priv->ring_rptr->handle +
1186 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1187
1188 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
1189
1190 /* Writeback doesn't seem to work everywhere, test it first */
1191 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
1192 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
1193
1194 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
1195 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
1196 break;
1197 DRM_UDELAY( 1 );
1198 }
1199
1200 if ( tmp < dev_priv->usec_timeout ) {
1201 dev_priv->writeback_works = 1;
1202 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
1203 } else {
1204 dev_priv->writeback_works = 0;
1205 DRM_DEBUG( "writeback test failed\n" );
1206 }
1207
1208 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1209 RADEON_WRITE( RADEON_LAST_FRAME_REG,
1210 dev_priv->sarea_priv->last_frame );
1211
1212 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1213 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
1214 dev_priv->sarea_priv->last_dispatch );
1215
1216 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1217 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
1218 dev_priv->sarea_priv->last_clear );
1219
1220 /* Set ring buffer size */
1221 #ifdef __BIG_ENDIAN
1222 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
1223 #else
1224 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
1225 #endif
1226
1227 radeon_do_wait_for_idle( dev_priv );
1228
1229 /* Turn on bus mastering */
1230 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
1231 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
1232
1233 /* Sync everything up */
1234 RADEON_WRITE( RADEON_ISYNC_CNTL,
1235 (RADEON_ISYNC_ANY2D_IDLE3D |
1236 RADEON_ISYNC_ANY3D_IDLE2D |
1237 RADEON_ISYNC_WAIT_IDLEGUI |
1238 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
1239 }
1240
1241 /* Enable or disable PCI GART on the chip */
1242 static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
1243 {
1244 u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
1245
1246 if ( on ) {
1247 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
1248
1249 /* set PCI GART page-table base address
1250 */
1251 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1252
1253 /* set address range for PCI address translate
1254 */
1255 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
1256 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1257 + dev_priv->gart_size - 1);
1258
1259 /* Turn off AGP aperture -- is this required for PCI GART?
1260 */
1261 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1262 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1263 } else {
1264 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1265 }
1266 }
1267
1268 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1269 {
1270 drm_radeon_private_t *dev_priv = dev->dev_private;;
1271 DRM_DEBUG( "\n" );
1272
1273 dev_priv->is_pci = init->is_pci;
1274
1275 if ( dev_priv->is_pci && !dev->sg ) {
1276 DRM_ERROR( "PCI GART memory not allocated!\n" );
1277 dev->dev_private = (void *)dev_priv;
1278 radeon_do_cleanup_cp(dev);
1279 return DRM_ERR(EINVAL);
1280 }
1281
1282 dev_priv->usec_timeout = init->usec_timeout;
1283 if ( dev_priv->usec_timeout < 1 ||
1284 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1285 DRM_DEBUG( "TIMEOUT problem!\n" );
1286 dev->dev_private = (void *)dev_priv;
1287 radeon_do_cleanup_cp(dev);
1288 return DRM_ERR(EINVAL);
1289 }
1290
1291 switch(init->func) {
1292 case RADEON_INIT_R200_CP:
1293 dev_priv->microcode_version=UCODE_R200;
1294 break;
1295 case RADEON_INIT_R300_CP:
1296 dev_priv->microcode_version=UCODE_R300;
1297 break;
1298 default:
1299 dev_priv->microcode_version=UCODE_R100;
1300 }
1301
1302 dev_priv->do_boxes = 0;
1303 dev_priv->cp_mode = init->cp_mode;
1304
1305 /* We don't support anything other than bus-mastering ring mode,
1306 * but the ring can be in either AGP or PCI space for the ring
1307 * read pointer.
1308 */
1309 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1310 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1311 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1312 dev->dev_private = (void *)dev_priv;
1313 radeon_do_cleanup_cp(dev);
1314 return DRM_ERR(EINVAL);
1315 }
1316
1317 switch ( init->fb_bpp ) {
1318 case 16:
1319 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1320 break;
1321 case 32:
1322 default:
1323 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1324 break;
1325 }
1326 dev_priv->front_offset = init->front_offset;
1327 dev_priv->front_pitch = init->front_pitch;
1328 dev_priv->back_offset = init->back_offset;
1329 dev_priv->back_pitch = init->back_pitch;
1330
1331 switch ( init->depth_bpp ) {
1332 case 16:
1333 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1334 break;
1335 case 32:
1336 default:
1337 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1338 break;
1339 }
1340 dev_priv->depth_offset = init->depth_offset;
1341 dev_priv->depth_pitch = init->depth_pitch;
1342
1343 /* Hardware state for depth clears. Remove this if/when we no
1344 * longer clear the depth buffer with a 3D rectangle. Hard-code
1345 * all values to prevent unwanted 3D state from slipping through
1346 * and screwing with the clear operation.
1347 */
1348 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1349 (dev_priv->color_fmt << 10) |
1350 (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1351
1352 dev_priv->depth_clear.rb3d_zstencilcntl =
1353 (dev_priv->depth_fmt |
1354 RADEON_Z_TEST_ALWAYS |
1355 RADEON_STENCIL_TEST_ALWAYS |
1356 RADEON_STENCIL_S_FAIL_REPLACE |
1357 RADEON_STENCIL_ZPASS_REPLACE |
1358 RADEON_STENCIL_ZFAIL_REPLACE |
1359 RADEON_Z_WRITE_ENABLE);
1360
1361 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1362 RADEON_BFACE_SOLID |
1363 RADEON_FFACE_SOLID |
1364 RADEON_FLAT_SHADE_VTX_LAST |
1365 RADEON_DIFFUSE_SHADE_FLAT |
1366 RADEON_ALPHA_SHADE_FLAT |
1367 RADEON_SPECULAR_SHADE_FLAT |
1368 RADEON_FOG_SHADE_FLAT |
1369 RADEON_VTX_PIX_CENTER_OGL |
1370 RADEON_ROUND_MODE_TRUNC |
1371 RADEON_ROUND_PREC_8TH_PIX);
1372
1373 DRM_GETSAREA();
1374
1375 dev_priv->fb_offset = init->fb_offset;
1376 dev_priv->mmio_offset = init->mmio_offset;
1377 dev_priv->ring_offset = init->ring_offset;
1378 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1379 dev_priv->buffers_offset = init->buffers_offset;
1380 dev_priv->gart_textures_offset = init->gart_textures_offset;
1381
1382 if(!dev_priv->sarea) {
1383 DRM_ERROR("could not find sarea!\n");
1384 dev->dev_private = (void *)dev_priv;
1385 radeon_do_cleanup_cp(dev);
1386 return DRM_ERR(EINVAL);
1387 }
1388
1389 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1390 if(!dev_priv->mmio) {
1391 DRM_ERROR("could not find mmio region!\n");
1392 dev->dev_private = (void *)dev_priv;
1393 radeon_do_cleanup_cp(dev);
1394 return DRM_ERR(EINVAL);
1395 }
1396 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1397 if(!dev_priv->cp_ring) {
1398 DRM_ERROR("could not find cp ring region!\n");
1399 dev->dev_private = (void *)dev_priv;
1400 radeon_do_cleanup_cp(dev);
1401 return DRM_ERR(EINVAL);
1402 }
1403 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1404 if(!dev_priv->ring_rptr) {
1405 DRM_ERROR("could not find ring read pointer!\n");
1406 dev->dev_private = (void *)dev_priv;
1407 radeon_do_cleanup_cp(dev);
1408 return DRM_ERR(EINVAL);
1409 }
1410 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1411 if(!dev->agp_buffer_map) {
1412 DRM_ERROR("could not find dma buffer region!\n");
1413 dev->dev_private = (void *)dev_priv;
1414 radeon_do_cleanup_cp(dev);
1415 return DRM_ERR(EINVAL);
1416 }
1417
1418 if ( init->gart_textures_offset ) {
1419 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
1420 if ( !dev_priv->gart_textures ) {
1421 DRM_ERROR("could not find GART texture region!\n");
1422 dev->dev_private = (void *)dev_priv;
1423 radeon_do_cleanup_cp(dev);
1424 return DRM_ERR(EINVAL);
1425 }
1426 }
1427
1428 dev_priv->sarea_priv =
1429 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1430 init->sarea_priv_offset);
1431
1432 #if __OS_HAS_AGP
1433 if ( !dev_priv->is_pci ) {
1434 drm_core_ioremap( dev_priv->cp_ring, dev );
1435 drm_core_ioremap( dev_priv->ring_rptr, dev );
1436 drm_core_ioremap( dev->agp_buffer_map, dev );
1437 if(!dev_priv->cp_ring->handle ||
1438 !dev_priv->ring_rptr->handle ||
1439 !dev->agp_buffer_map->handle) {
1440 DRM_ERROR("could not find ioremap agp regions!\n");
1441 dev->dev_private = (void *)dev_priv;
1442 radeon_do_cleanup_cp(dev);
1443 return DRM_ERR(EINVAL);
1444 }
1445 } else
1446 #endif
1447 {
1448 dev_priv->cp_ring->handle =
1449 (void *)dev_priv->cp_ring->offset;
1450 dev_priv->ring_rptr->handle =
1451 (void *)dev_priv->ring_rptr->offset;
1452 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
1453
1454 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1455 dev_priv->cp_ring->handle );
1456 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1457 dev_priv->ring_rptr->handle );
1458 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
1459 dev->agp_buffer_map->handle );
1460 }
1461
1462 dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
1463 & 0xffff ) << 16;
1464
1465 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1466 ( ( dev_priv->front_offset
1467 + dev_priv->fb_location ) >> 10 ) );
1468
1469 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1470 ( ( dev_priv->back_offset
1471 + dev_priv->fb_location ) >> 10 ) );
1472
1473 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1474 ( ( dev_priv->depth_offset
1475 + dev_priv->fb_location ) >> 10 ) );
1476
1477
1478 dev_priv->gart_size = init->gart_size;
1479 dev_priv->gart_vm_start = dev_priv->fb_location
1480 + RADEON_READ( RADEON_CONFIG_APER_SIZE );
1481
1482 #if __OS_HAS_AGP
1483 if ( !dev_priv->is_pci )
1484 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1485 - dev->agp->base
1486 + dev_priv->gart_vm_start);
1487 else
1488 #endif
1489 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1490 - dev->sg->handle
1491 + dev_priv->gart_vm_start);
1492
1493 DRM_DEBUG( "dev_priv->gart_size %d\n",
1494 dev_priv->gart_size );
1495 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1496 dev_priv->gart_vm_start );
1497 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1498 dev_priv->gart_buffers_offset );
1499
1500 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1501 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1502 + init->ring_size / sizeof(u32));
1503 dev_priv->ring.size = init->ring_size;
1504 dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );
1505
1506 dev_priv->ring.tail_mask =
1507 (dev_priv->ring.size / sizeof(u32)) - 1;
1508
1509 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1510
1511 #if __OS_HAS_AGP
1512 if ( !dev_priv->is_pci ) {
1513 /* Turn off PCI GART */
1514 radeon_set_pcigart( dev_priv, 0 );
1515 } else
1516 #endif
1517 {
1518 if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart,
1519 &dev_priv->bus_pci_gart)) {
1520 DRM_ERROR( "failed to init PCI GART!\n" );
1521 dev->dev_private = (void *)dev_priv;
1522 radeon_do_cleanup_cp(dev);
1523 return DRM_ERR(ENOMEM);
1524 }
1525
1526 /* Turn on PCI GART */
1527 radeon_set_pcigart( dev_priv, 1 );
1528 }
1529
1530 radeon_cp_load_microcode( dev_priv );
1531 radeon_cp_init_ring_buffer( dev, dev_priv );
1532
1533 dev_priv->last_buf = 0;
1534
1535 dev->dev_private = (void *)dev_priv;
1536
1537 radeon_do_engine_reset( dev );
1538
1539 return 0;
1540 }
1541
1542 static int radeon_do_cleanup_cp( drm_device_t *dev )
1543 {
1544 drm_radeon_private_t *dev_priv = dev->dev_private;
1545 DRM_DEBUG( "\n" );
1546
1547 /* Make sure interrupts are disabled here because the uninstall ioctl
1548 * may not have been called from userspace and after dev_private
1549 * is freed, it's too late.
1550 */
1551 if ( dev->irq_enabled ) drm_irq_uninstall(dev);
1552
1553 #if __OS_HAS_AGP
1554 if ( !dev_priv->is_pci ) {
1555 if ( dev_priv->cp_ring != NULL )
1556 drm_core_ioremapfree( dev_priv->cp_ring, dev );
1557 if ( dev_priv->ring_rptr != NULL )
1558 drm_core_ioremapfree( dev_priv->ring_rptr, dev );
1559 if ( dev->agp_buffer_map != NULL )
1560 {
1561 drm_core_ioremapfree( dev->agp_buffer_map, dev );
1562 dev->agp_buffer_map = NULL;
1563 }
1564 } else
1565 #endif
1566 {
1567 if (!drm_ati_pcigart_cleanup( dev,
1568 dev_priv->phys_pci_gart,
1569 dev_priv->bus_pci_gart ))
1570 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1571 }
1572
1573 /* only clear to the start of flags */
1574 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1575
1576 return 0;
1577 }
1578
1579 /* This code will reinit the Radeon CP hardware after a resume from disc.
1580 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1581 * here we make sure that all Radeon hardware initialisation is re-done without
1582 * affecting running applications.
1583 *
1584 * Charl P. Botha <http://cpbotha.net>
1585 */
1586 static int radeon_do_resume_cp( drm_device_t *dev )
1587 {
1588 drm_radeon_private_t *dev_priv = dev->dev_private;
1589
1590 if ( !dev_priv ) {
1591 DRM_ERROR( "Called with no initialization\n" );
1592 return DRM_ERR( EINVAL );
1593 }
1594
1595 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1596
1597 #if __OS_HAS_AGP
1598 if ( !dev_priv->is_pci ) {
1599 /* Turn off PCI GART */
1600 radeon_set_pcigart( dev_priv, 0 );
1601 } else
1602 #endif
1603 {
1604 /* Turn on PCI GART */
1605 radeon_set_pcigart( dev_priv, 1 );
1606 }
1607
1608 radeon_cp_load_microcode( dev_priv );
1609 radeon_cp_init_ring_buffer( dev, dev_priv );
1610
1611 radeon_do_engine_reset( dev );
1612
1613 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1614
1615 return 0;
1616 }
1617
1618
1619 int radeon_cp_init( DRM_IOCTL_ARGS )
1620 {
1621 DRM_DEVICE;
1622 drm_radeon_init_t init;
1623
1624 LOCK_TEST_WITH_RETURN( dev, filp );
1625
1626 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );
1627
1628 switch ( init.func ) {
1629 case RADEON_INIT_CP:
1630 case RADEON_INIT_R200_CP:
1631 case RADEON_INIT_R300_CP:
1632 return radeon_do_init_cp( dev, &init );
1633 case RADEON_CLEANUP_CP:
1634 return radeon_do_cleanup_cp( dev );
1635 }
1636
1637 return DRM_ERR(EINVAL);
1638 }
1639
1640 int radeon_cp_start( DRM_IOCTL_ARGS )
1641 {
1642 DRM_DEVICE;
1643 drm_radeon_private_t *dev_priv = dev->dev_private;
1644 DRM_DEBUG( "\n" );
1645
1646 LOCK_TEST_WITH_RETURN( dev, filp );
1647
1648 if ( dev_priv->cp_running ) {
1649 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1650 return 0;
1651 }
1652 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1653 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1654 __FUNCTION__, dev_priv->cp_mode );
1655 return 0;
1656 }
1657
1658 radeon_do_cp_start( dev_priv );
1659
1660 return 0;
1661 }
1662
1663 /* Stop the CP. The engine must have been idled before calling this
1664 * routine.
1665 */
1666 int radeon_cp_stop( DRM_IOCTL_ARGS )
1667 {
1668 DRM_DEVICE;
1669 drm_radeon_private_t *dev_priv = dev->dev_private;
1670 drm_radeon_cp_stop_t stop;
1671 int ret;
1672 DRM_DEBUG( "\n" );
1673
1674 LOCK_TEST_WITH_RETURN( dev, filp );
1675
1676 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );
1677
1678 if (!dev_priv->cp_running)
1679 return 0;
1680
1681 /* Flush any pending CP commands. This ensures any outstanding
1682 * commands are exectuted by the engine before we turn it off.
1683 */
1684 if ( stop.flush ) {
1685 radeon_do_cp_flush( dev_priv );
1686 }
1687
1688 /* If we fail to make the engine go idle, we return an error
1689 * code so that the DRM ioctl wrapper can try again.
1690 */
1691 if ( stop.idle ) {
1692 ret = radeon_do_cp_idle( dev_priv );
1693 if ( ret ) return ret;
1694 }
1695
1696 /* Finally, we can turn off the CP. If the engine isn't idle,
1697 * we will get some dropped triangles as they won't be fully
1698 * rendered before the CP is shut down.
1699 */
1700 radeon_do_cp_stop( dev_priv );
1701
1702 /* Reset the engine */
1703 radeon_do_engine_reset( dev );
1704
1705 return 0;
1706 }
1707
1708
1709 void radeon_do_release( drm_device_t *dev )
1710 {
1711 drm_radeon_private_t *dev_priv = dev->dev_private;
1712 int i, ret;
1713
1714 if (dev_priv) {
1715 if (dev_priv->cp_running) {
1716 /* Stop the cp */
1717 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1718 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1719 #ifdef __linux__
1720 schedule();
1721 #else
1722 tsleep(&ret, PZERO, "rdnrel", 1);
1723 #endif
1724 }
1725 radeon_do_cp_stop( dev_priv );
1726 radeon_do_engine_reset( dev );
1727 }
1728
1729 /* Disable *all* interrupts */
1730 if (dev_priv->mmio) /* remove this after permanent addmaps */
1731 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1732
1733 if (dev_priv->mmio) {/* remove all surfaces */
1734 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1735 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1736 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1737 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1738 }
1739 }
1740
1741 /* Free memory heap structures */
1742 radeon_mem_takedown( &(dev_priv->gart_heap) );
1743 radeon_mem_takedown( &(dev_priv->fb_heap) );
1744
1745 /* deallocate kernel resources */
1746 radeon_do_cleanup_cp( dev );
1747 }
1748 }
1749
1750 /* Just reset the CP ring. Called as part of an X Server engine reset.
1751 */
1752 int radeon_cp_reset( DRM_IOCTL_ARGS )
1753 {
1754 DRM_DEVICE;
1755 drm_radeon_private_t *dev_priv = dev->dev_private;
1756 DRM_DEBUG( "\n" );
1757
1758 LOCK_TEST_WITH_RETURN( dev, filp );
1759
1760 if ( !dev_priv ) {
1761 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1762 return DRM_ERR(EINVAL);
1763 }
1764
1765 radeon_do_cp_reset( dev_priv );
1766
1767 /* The CP is no longer running after an engine reset */
1768 dev_priv->cp_running = 0;
1769
1770 return 0;
1771 }
1772
1773 int radeon_cp_idle( DRM_IOCTL_ARGS )
1774 {
1775 DRM_DEVICE;
1776 drm_radeon_private_t *dev_priv = dev->dev_private;
1777 DRM_DEBUG( "\n" );
1778
1779 LOCK_TEST_WITH_RETURN( dev, filp );
1780
1781 return radeon_do_cp_idle( dev_priv );
1782 }
1783
1784 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1785 */
1786 int radeon_cp_resume( DRM_IOCTL_ARGS )
1787 {
1788 DRM_DEVICE;
1789
1790 return radeon_do_resume_cp(dev);
1791 }
1792
1793
1794 int radeon_engine_reset( DRM_IOCTL_ARGS )
1795 {
1796 DRM_DEVICE;
1797 DRM_DEBUG( "\n" );
1798
1799 LOCK_TEST_WITH_RETURN( dev, filp );
1800
1801 return radeon_do_engine_reset( dev );
1802 }
1803
1804
1805 /* ================================================================
1806 * Fullscreen mode
1807 */
1808
1809 /* KW: Deprecated to say the least:
1810 */
1811 int radeon_fullscreen( DRM_IOCTL_ARGS )
1812 {
1813 return 0;
1814 }
1815
1816
1817 /* ================================================================
1818 * Freelist management
1819 */
1820
1821 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1822 * bufs until freelist code is used. Note this hides a problem with
1823 * the scratch register * (used to keep track of last buffer
1824 * completed) being written to before * the last buffer has actually
1825 * completed rendering.
1826 *
1827 * KW: It's also a good way to find free buffers quickly.
1828 *
1829 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1830 * sleep. However, bugs in older versions of radeon_accel.c mean that
1831 * we essentially have to do this, else old clients will break.
1832 *
1833 * However, it does leave open a potential deadlock where all the
1834 * buffers are held by other clients, which can't release them because
1835 * they can't get the lock.
1836 */
1837
1838 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1839 {
1840 drm_device_dma_t *dma = dev->dma;
1841 drm_radeon_private_t *dev_priv = dev->dev_private;
1842 drm_radeon_buf_priv_t *buf_priv;
1843 drm_buf_t *buf;
1844 int i, t;
1845 int start;
1846
1847 if ( ++dev_priv->last_buf >= dma->buf_count )
1848 dev_priv->last_buf = 0;
1849
1850 start = dev_priv->last_buf;
1851
1852 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1853 u32 done_age = GET_SCRATCH( 1 );
1854 DRM_DEBUG("done_age = %d\n",done_age);
1855 for ( i = start ; i < dma->buf_count ; i++ ) {
1856 buf = dma->buflist[i];
1857 buf_priv = buf->dev_private;
1858 if ( buf->filp == 0 || (buf->pending &&
1859 buf_priv->age <= done_age) ) {
1860 dev_priv->stats.requested_bufs++;
1861 buf->pending = 0;
1862 return buf;
1863 }
1864 start = 0;
1865 }
1866
1867 if (t) {
1868 DRM_UDELAY( 1 );
1869 dev_priv->stats.freelist_loops++;
1870 }
1871 }
1872
1873 DRM_DEBUG( "returning NULL!\n" );
1874 return NULL;
1875 }
1876 #if 0
1877 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1878 {
1879 drm_device_dma_t *dma = dev->dma;
1880 drm_radeon_private_t *dev_priv = dev->dev_private;
1881 drm_radeon_buf_priv_t *buf_priv;
1882 drm_buf_t *buf;
1883 int i, t;
1884 int start;
1885 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1886
1887 if ( ++dev_priv->last_buf >= dma->buf_count )
1888 dev_priv->last_buf = 0;
1889
1890 start = dev_priv->last_buf;
1891 dev_priv->stats.freelist_loops++;
1892
1893 for ( t = 0 ; t < 2 ; t++ ) {
1894 for ( i = start ; i < dma->buf_count ; i++ ) {
1895 buf = dma->buflist[i];
1896 buf_priv = buf->dev_private;
1897 if ( buf->filp == 0 || (buf->pending &&
1898 buf_priv->age <= done_age) ) {
1899 dev_priv->stats.requested_bufs++;
1900 buf->pending = 0;
1901 return buf;
1902 }
1903 }
1904 start = 0;
1905 }
1906
1907 return NULL;
1908 }
1909 #endif
1910
1911 void radeon_freelist_reset( drm_device_t *dev )
1912 {
1913 drm_device_dma_t *dma = dev->dma;
1914 drm_radeon_private_t *dev_priv = dev->dev_private;
1915 int i;
1916
1917 dev_priv->last_buf = 0;
1918 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1919 drm_buf_t *buf = dma->buflist[i];
1920 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1921 buf_priv->age = 0;
1922 }
1923 }
1924
1925
1926 /* ================================================================
1927 * CP command submission
1928 */
1929
1930 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1931 {
1932 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1933 int i;
1934 u32 last_head = GET_RING_HEAD( dev_priv );
1935
1936 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1937 u32 head = GET_RING_HEAD( dev_priv );
1938
1939 ring->space = (head - ring->tail) * sizeof(u32);
1940 if ( ring->space <= 0 )
1941 ring->space += ring->size;
1942 if ( ring->space > n )
1943 return 0;
1944
1945 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1946
1947 if (head != last_head)
1948 i = 0;
1949 last_head = head;
1950
1951 DRM_UDELAY( 1 );
1952 }
1953
1954 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1955 #if RADEON_FIFO_DEBUG
1956 radeon_status( dev_priv );
1957 DRM_ERROR( "failed!\n" );
1958 #endif
1959 return DRM_ERR(EBUSY);
1960 }
1961
1962 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1963 {
1964 int i;
1965 drm_buf_t *buf;
1966
1967 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1968 buf = radeon_freelist_get( dev );
1969 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1970
1971 buf->filp = filp;
1972
1973 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1974 sizeof(buf->idx) ) )
1975 return DRM_ERR(EFAULT);
1976 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1977 sizeof(buf->total) ) )
1978 return DRM_ERR(EFAULT);
1979
1980 d->granted_count++;
1981 }
1982 return 0;
1983 }
1984
1985 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1986 {
1987 DRM_DEVICE;
1988 drm_device_dma_t *dma = dev->dma;
1989 int ret = 0;
1990 drm_dma_t __user *argp = (void __user *)data;
1991 drm_dma_t d;
1992
1993 LOCK_TEST_WITH_RETURN( dev, filp );
1994
1995 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
1996
1997 /* Please don't send us buffers.
1998 */
1999 if ( d.send_count != 0 ) {
2000 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
2001 DRM_CURRENTPID, d.send_count );
2002 return DRM_ERR(EINVAL);
2003 }
2004
2005 /* We'll send you buffers.
2006 */
2007 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
2008 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
2009 DRM_CURRENTPID, d.request_count, dma->buf_count );
2010 return DRM_ERR(EINVAL);
2011 }
2012
2013 d.granted_count = 0;
2014
2015 if ( d.request_count ) {
2016 ret = radeon_cp_get_buffers( filp, dev, &d );
2017 }
2018
2019 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
2020
2021 return ret;
2022 }
2023
2024 int radeon_driver_preinit(struct drm_device *dev, unsigned long flags)
2025 {
2026 drm_radeon_private_t *dev_priv;
2027 int ret = 0;
2028
2029 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2030 if (dev_priv == NULL)
2031 return DRM_ERR(ENOMEM);
2032
2033 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2034 dev->dev_private = (void *)dev_priv;
2035 dev_priv->flags = flags;
2036
2037 switch (flags & CHIP_FAMILY_MASK) {
2038 case CHIP_R100:
2039 case CHIP_RV200:
2040 case CHIP_R200:
2041 case CHIP_R300:
2042 dev_priv->flags |= CHIP_HAS_HIERZ;
2043 break;
2044 default:
2045 /* all other chips have no hierarchical z buffer */
2046 break;
2047 }
2048 return ret;
2049 }
2050
2051 int radeon_driver_postcleanup(struct drm_device *dev)
2052 {
2053 drm_radeon_private_t *dev_priv = dev->dev_private;
2054
2055 DRM_DEBUG("\n");
2056
2057 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2058
2059 dev->dev_private = NULL;
2060 return 0;
2061 }
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