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Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/gregkh/driver...
[linux-2.6/verdex.git] / drivers / scsi / qla2xxx / qla_def.h
blob7d47b8d9204716ad22e7c0d2a2263e45884b3c1c
1 /********************************************************************************
2 * QLOGIC LINUX SOFTWARE
3 *
4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2004 QLogic Corporation
6 * (www.qlogic.com)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 **
18 ******************************************************************************/
19
20 #ifndef __QLA_DEF_H
21 #define __QLA_DEF_H
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/dmapool.h>
33 #include <linux/mempool.h>
34 #include <linux/spinlock.h>
35 #include <linux/completion.h>
36 #include <asm/semaphore.h>
37
38 #include <scsi/scsi.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_device.h>
41 #include <scsi/scsi_cmnd.h>
42
43 /* XXX(hch): move to pci_ids.h */
44 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2300
45 #define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300
46 #endif
47
48 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2312
49 #define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312
50 #endif
51
52 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2322
53 #define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322
54 #endif
55
56 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6312
57 #define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312
58 #endif
59
60 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6322
61 #define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322
62 #endif
63
64 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
65 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
66 #else
67 #define IS_QLA2100(ha) 0
68 #endif
69
70 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
71 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
72 #else
73 #define IS_QLA2200(ha) 0
74 #endif
75
76 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
77 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
78 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
79 #else
80 #define IS_QLA2300(ha) 0
81 #define IS_QLA2312(ha) 0
82 #endif
83
84 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
85 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
86 #else
87 #define IS_QLA2322(ha) 0
88 #endif
89
90 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
91 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
92 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
93 #else
94 #define IS_QLA6312(ha) 0
95 #define IS_QLA6322(ha) 0
96 #endif
97
98 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
99 IS_QLA6312(ha) || IS_QLA6322(ha))
100
101 /*
102 * Only non-ISP2[12]00 have extended addressing support in the firmware.
103 */
104 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
105
106 /*
107 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
108 * but that's fine as we don't look at the last 24 ones for
109 * ISP2100 HBAs.
110 */
111 #define MAILBOX_REGISTER_COUNT_2100 8
112 #define MAILBOX_REGISTER_COUNT 32
113
114 #define QLA2200A_RISC_ROM_VER 4
115 #define FPM_2300 6
116 #define FPM_2310 7
117
118 #include "qla_settings.h"
119
120 /*
121 * Data bit definitions
122 */
123 #define BIT_0 0x1
124 #define BIT_1 0x2
125 #define BIT_2 0x4
126 #define BIT_3 0x8
127 #define BIT_4 0x10
128 #define BIT_5 0x20
129 #define BIT_6 0x40
130 #define BIT_7 0x80
131 #define BIT_8 0x100
132 #define BIT_9 0x200
133 #define BIT_10 0x400
134 #define BIT_11 0x800
135 #define BIT_12 0x1000
136 #define BIT_13 0x2000
137 #define BIT_14 0x4000
138 #define BIT_15 0x8000
139 #define BIT_16 0x10000
140 #define BIT_17 0x20000
141 #define BIT_18 0x40000
142 #define BIT_19 0x80000
143 #define BIT_20 0x100000
144 #define BIT_21 0x200000
145 #define BIT_22 0x400000
146 #define BIT_23 0x800000
147 #define BIT_24 0x1000000
148 #define BIT_25 0x2000000
149 #define BIT_26 0x4000000
150 #define BIT_27 0x8000000
151 #define BIT_28 0x10000000
152 #define BIT_29 0x20000000
153 #define BIT_30 0x40000000
154 #define BIT_31 0x80000000
155
156 #define LSB(x) ((uint8_t)(x))
157 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
158
159 #define LSW(x) ((uint16_t)(x))
160 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
161
162 #define LSD(x) ((uint32_t)((uint64_t)(x)))
163 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
164
165
166 /*
167 * I/O register
168 */
169
170 #define RD_REG_BYTE(addr) readb(addr)
171 #define RD_REG_WORD(addr) readw(addr)
172 #define RD_REG_DWORD(addr) readl(addr)
173 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
174 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
175 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
176 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
177 #define WRT_REG_WORD(addr, data) writew(data,addr)
178 #define WRT_REG_DWORD(addr, data) writel(data,addr)
179
180 /*
181 * Fibre Channel device definitions.
182 */
183 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
184 #define MAX_FIBRE_DEVICES 512
185 #define MAX_FIBRE_LUNS 256
186 #define MAX_RSCN_COUNT 32
187 #define MAX_HOST_COUNT 16
188
189 /*
190 * Host adapter default definitions.
191 */
192 #define MAX_BUSES 1 /* We only have one bus today */
193 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
194 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
195 #define MAX_TARGETS MAX_FIBRE_DEVICES
196 #define MIN_LUNS 8
197 #define MAX_LUNS MAX_FIBRE_LUNS
198 #define MAX_CMDS_PER_LUN 255
199
200 /*
201 * Fibre Channel device definitions.
202 */
203 #define SNS_LAST_LOOP_ID_2100 0xfe
204 #define SNS_LAST_LOOP_ID_2300 0x7ff
205
206 #define LAST_LOCAL_LOOP_ID 0x7d
207 #define SNS_FL_PORT 0x7e
208 #define FABRIC_CONTROLLER 0x7f
209 #define SIMPLE_NAME_SERVER 0x80
210 #define SNS_FIRST_LOOP_ID 0x81
211 #define MANAGEMENT_SERVER 0xfe
212 #define BROADCAST 0xff
213
214 #define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \
215 x < SNS_FIRST_LOOP_ID) || \
216 x == MANAGEMENT_SERVER || \
217 x == BROADCAST)
218
219 /*
220 * Timeout timer counts in seconds
221 */
222 #define PORT_RETRY_TIME 1
223 #define LOOP_DOWN_TIMEOUT 60
224 #define LOOP_DOWN_TIME 255 /* 240 */
225 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
226
227 /* Maximum outstanding commands in ISP queues (1-65535) */
228 #define MAX_OUTSTANDING_COMMANDS 1024
229
230 /* ISP request and response entry counts (37-65535) */
231 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
232 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
233 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
234 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
235 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
236
237 /*
238 * SCSI Request Block
239 */
240 typedef struct srb {
241 struct list_head list;
242
243 struct scsi_qla_host *ha; /* HA the SP is queued on */
244 struct fc_port *fcport;
245
246 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
247
248 struct timer_list timer; /* Command timer */
249 atomic_t ref_count; /* Reference count for this structure */
250 uint16_t flags;
251
252 /* Request state */
253 uint16_t state;
254
255 /* Timing counts. */
256 unsigned long e_start; /* Start of extend timeout */
257 unsigned long r_start; /* Start of request */
258 unsigned long u_start; /* When sent to RISC */
259 unsigned long f_start; /* When placed in FO queue*/
260
261 /* Single transfer DMA context */
262 dma_addr_t dma_handle;
263
264 uint32_t request_sense_length;
265 uint8_t *request_sense_ptr;
266
267 int ext_history;
268
269 /* Suspend delay */
270 int delay;
271
272 /* Raw completion info for use by failover ? */
273 uint8_t fo_retry_cnt; /* Retry count this request */
274 uint8_t err_id; /* error id */
275 #define SRB_ERR_PORT 1 /* Request failed -- "port down" */
276 #define SRB_ERR_LOOP 2 /* Request failed -- "loop down" */
277 #define SRB_ERR_DEVICE 3 /* Request failed -- "device error" */
278 #define SRB_ERR_OTHER 4
279
280 /* SRB magic number */
281 uint16_t magic;
282 #define SRB_MAGIC 0x10CB
283 } srb_t;
284
285 /*
286 * SRB flag definitions
287 */
288 #define SRB_TIMEOUT BIT_0 /* Command timed out */
289 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
290 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
291 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
292
293 #define SRB_ABORTED BIT_4 /* Command aborted command already */
294 #define SRB_RETRY BIT_5 /* Command needs retrying */
295 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
296 #define SRB_FAILOVER BIT_7 /* Command in failover state */
297
298 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
299 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
300 #define SRB_IOCTL BIT_10 /* IOCTL command. */
301 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
302
303 /*
304 * SRB state definitions
305 */
306 #define SRB_FREE_STATE 0 /* returned back */
307 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
308 #define SRB_ACTIVE_STATE 2 /* in Active Array */
309 #define SRB_DONE_STATE 3 /* queued in Done Queue */
310 #define SRB_RETRY_STATE 4 /* in Retry Queue */
311 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
312 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
313 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
314 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
315 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
316
317
318 /*
319 * ISP I/O Register Set structure definitions.
320 */
321 typedef volatile struct {
322 volatile uint16_t flash_address; /* Flash BIOS address */
323 volatile uint16_t flash_data; /* Flash BIOS data */
324 uint16_t unused_1[1]; /* Gap */
325 volatile uint16_t ctrl_status; /* Control/Status */
326 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
327 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
328 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
329
330 volatile uint16_t ictrl; /* Interrupt control */
331 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
332 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
333
334 volatile uint16_t istatus; /* Interrupt status */
335 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
336
337 volatile uint16_t semaphore; /* Semaphore */
338 volatile uint16_t nvram; /* NVRAM register. */
339 #define NVR_DESELECT 0
340 #define NVR_BUSY BIT_15
341 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
342 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
343 #define NVR_DATA_IN BIT_3
344 #define NVR_DATA_OUT BIT_2
345 #define NVR_SELECT BIT_1
346 #define NVR_CLOCK BIT_0
347
348 union {
349 struct {
350 volatile uint16_t mailbox0;
351 volatile uint16_t mailbox1;
352 volatile uint16_t mailbox2;
353 volatile uint16_t mailbox3;
354 volatile uint16_t mailbox4;
355 volatile uint16_t mailbox5;
356 volatile uint16_t mailbox6;
357 volatile uint16_t mailbox7;
358 uint16_t unused_2[59]; /* Gap */
359 } __attribute__((packed)) isp2100;
360 struct {
361 /* Request Queue */
362 volatile uint16_t req_q_in; /* In-Pointer */
363 volatile uint16_t req_q_out; /* Out-Pointer */
364 /* Response Queue */
365 volatile uint16_t rsp_q_in; /* In-Pointer */
366 volatile uint16_t rsp_q_out; /* Out-Pointer */
367
368 /* RISC to Host Status */
369 volatile uint32_t host_status;
370 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
371 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
372
373 /* Host to Host Semaphore */
374 volatile uint16_t host_semaphore;
375 uint16_t unused_3[17]; /* Gap */
376 volatile uint16_t mailbox0;
377 volatile uint16_t mailbox1;
378 volatile uint16_t mailbox2;
379 volatile uint16_t mailbox3;
380 volatile uint16_t mailbox4;
381 volatile uint16_t mailbox5;
382 volatile uint16_t mailbox6;
383 volatile uint16_t mailbox7;
384 volatile uint16_t mailbox8;
385 volatile uint16_t mailbox9;
386 volatile uint16_t mailbox10;
387 volatile uint16_t mailbox11;
388 volatile uint16_t mailbox12;
389 volatile uint16_t mailbox13;
390 volatile uint16_t mailbox14;
391 volatile uint16_t mailbox15;
392 volatile uint16_t mailbox16;
393 volatile uint16_t mailbox17;
394 volatile uint16_t mailbox18;
395 volatile uint16_t mailbox19;
396 volatile uint16_t mailbox20;
397 volatile uint16_t mailbox21;
398 volatile uint16_t mailbox22;
399 volatile uint16_t mailbox23;
400 volatile uint16_t mailbox24;
401 volatile uint16_t mailbox25;
402 volatile uint16_t mailbox26;
403 volatile uint16_t mailbox27;
404 volatile uint16_t mailbox28;
405 volatile uint16_t mailbox29;
406 volatile uint16_t mailbox30;
407 volatile uint16_t mailbox31;
408 volatile uint16_t fb_cmd;
409 uint16_t unused_4[10]; /* Gap */
410 } __attribute__((packed)) isp2300;
411 } u;
412
413 volatile uint16_t fpm_diag_config;
414 uint16_t unused_5[0x6]; /* Gap */
415 volatile uint16_t pcr; /* Processor Control Register. */
416 uint16_t unused_6[0x5]; /* Gap */
417 volatile uint16_t mctr; /* Memory Configuration and Timing. */
418 uint16_t unused_7[0x3]; /* Gap */
419 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */
420 uint16_t unused_8[0x3]; /* Gap */
421 volatile uint16_t hccr; /* Host command & control register. */
422 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
423 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
424 /* HCCR commands */
425 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
426 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
427 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
428 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
429 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
430 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
431 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
432 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
433
434 uint16_t unused_9[5]; /* Gap */
435 volatile uint16_t gpiod; /* GPIO Data register. */
436 volatile uint16_t gpioe; /* GPIO Enable register. */
437 #define GPIO_LED_MASK 0x00C0
438 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
439 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
440 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
441 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
442
443 union {
444 struct {
445 uint16_t unused_10[8]; /* Gap */
446 volatile uint16_t mailbox8;
447 volatile uint16_t mailbox9;
448 volatile uint16_t mailbox10;
449 volatile uint16_t mailbox11;
450 volatile uint16_t mailbox12;
451 volatile uint16_t mailbox13;
452 volatile uint16_t mailbox14;
453 volatile uint16_t mailbox15;
454 volatile uint16_t mailbox16;
455 volatile uint16_t mailbox17;
456 volatile uint16_t mailbox18;
457 volatile uint16_t mailbox19;
458 volatile uint16_t mailbox20;
459 volatile uint16_t mailbox21;
460 volatile uint16_t mailbox22;
461 volatile uint16_t mailbox23; /* Also probe reg. */
462 } __attribute__((packed)) isp2200;
463 } u_end;
464 } device_reg_t;
465
466 #define ISP_REQ_Q_IN(ha, reg) \
467 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
468 &(reg)->u.isp2100.mailbox4 : \
469 &(reg)->u.isp2300.req_q_in)
470 #define ISP_REQ_Q_OUT(ha, reg) \
471 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
472 &(reg)->u.isp2100.mailbox4 : \
473 &(reg)->u.isp2300.req_q_out)
474 #define ISP_RSP_Q_IN(ha, reg) \
475 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
476 &(reg)->u.isp2100.mailbox5 : \
477 &(reg)->u.isp2300.rsp_q_in)
478 #define ISP_RSP_Q_OUT(ha, reg) \
479 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
480 &(reg)->u.isp2100.mailbox5 : \
481 &(reg)->u.isp2300.rsp_q_out)
482
483 #define MAILBOX_REG(ha, reg, num) \
484 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
485 (num < 8 ? \
486 &(reg)->u.isp2100.mailbox0 + (num) : \
487 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
488 &(reg)->u.isp2300.mailbox0 + (num))
489 #define RD_MAILBOX_REG(ha, reg, num) \
490 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
491 #define WRT_MAILBOX_REG(ha, reg, num, data) \
492 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
493
494 #define FB_CMD_REG(ha, reg) \
495 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
496 &(reg)->fb_cmd_2100 : \
497 &(reg)->u.isp2300.fb_cmd)
498 #define RD_FB_CMD_REG(ha, reg) \
499 RD_REG_WORD(FB_CMD_REG(ha, reg))
500 #define WRT_FB_CMD_REG(ha, reg, data) \
501 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
502
503 typedef struct {
504 uint32_t out_mb; /* outbound from driver */
505 uint32_t in_mb; /* Incoming from RISC */
506 uint16_t mb[MAILBOX_REGISTER_COUNT];
507 long buf_size;
508 void *bufp;
509 uint32_t tov;
510 uint8_t flags;
511 #define MBX_DMA_IN BIT_0
512 #define MBX_DMA_OUT BIT_1
513 #define IOCTL_CMD BIT_2
514 } mbx_cmd_t;
515
516 #define MBX_TOV_SECONDS 30
517
518 /*
519 * ISP product identification definitions in mailboxes after reset.
520 */
521 #define PROD_ID_1 0x4953
522 #define PROD_ID_2 0x0000
523 #define PROD_ID_2a 0x5020
524 #define PROD_ID_3 0x2020
525
526 /*
527 * ISP mailbox Self-Test status codes
528 */
529 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
530 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
531 #define MBS_BUSY 4 /* Busy. */
532
533 /*
534 * ISP mailbox command complete status codes
535 */
536 #define MBS_COMMAND_COMPLETE 0x4000
537 #define MBS_INVALID_COMMAND 0x4001
538 #define MBS_HOST_INTERFACE_ERROR 0x4002
539 #define MBS_TEST_FAILED 0x4003
540 #define MBS_COMMAND_ERROR 0x4005
541 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
542 #define MBS_PORT_ID_USED 0x4007
543 #define MBS_LOOP_ID_USED 0x4008
544 #define MBS_ALL_IDS_IN_USE 0x4009
545 #define MBS_NOT_LOGGED_IN 0x400A
546
547 /*
548 * ISP mailbox asynchronous event status codes
549 */
550 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
551 #define MBA_RESET 0x8001 /* Reset Detected. */
552 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
553 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
554 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
555 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
556 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
557 /* occurred. */
558 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
559 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
560 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
561 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
562 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
563 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
564 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
565 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
566 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
567 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
568 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
569 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
570 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
571 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
572 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
573 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
574 /* used. */
575 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
576 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
577 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
578 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
579 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
580 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
581 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
582 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
583 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
584 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
585 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
586 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
587 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
588
589 /*
590 * Firmware options 1, 2, 3.
591 */
592 #define FO1_AE_ON_LIPF8 BIT_0
593 #define FO1_AE_ALL_LIP_RESET BIT_1
594 #define FO1_CTIO_RETRY BIT_3
595 #define FO1_DISABLE_LIP_F7_SW BIT_4
596 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
597 #define FO1_DISABLE_GPIO6_7 BIT_6
598 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
599 #define FO1_SET_EMPHASIS_SWING BIT_8
600 #define FO1_AE_AUTO_BYPASS BIT_9
601 #define FO1_ENABLE_PURE_IOCB BIT_10
602 #define FO1_AE_PLOGI_RJT BIT_11
603 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
604 #define FO1_AE_QUEUE_FULL BIT_13
605
606 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
607 #define FO2_REV_LOOPBACK BIT_1
608
609 #define FO3_ENABLE_EMERG_IOCB BIT_0
610 #define FO3_AE_RND_ERROR BIT_1
611
612 /*
613 * ISP mailbox commands
614 */
615 #define MBC_LOAD_RAM 1 /* Load RAM. */
616 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
617 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
618 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
619 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
620 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
621 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
622 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
623 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
624 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
625 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
626 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
627 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
628 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
629 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
630 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
631 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
632 #define MBC_RESET 0x18 /* Reset. */
633 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
634 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
635 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
636 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
637 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
638 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
639 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
640 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
641 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
642 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
643 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
644 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
645 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
646 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
647 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
648 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
649 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
650 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
651 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
652 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
653 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
654 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
655 /* Initialization Procedure */
656 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
657 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
658 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
659 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
660 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
661 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
662 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
663 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
664 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
665 #define MBC_LIP_RESET 0x6c /* LIP reset. */
666 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
667 /* commandd. */
668 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
669 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
670 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
671 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
672 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
673 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
674 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
675 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
676 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
677 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
678 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
679
680 /* Firmware return data sizes */
681 #define FCAL_MAP_SIZE 128
682
683 /* Mailbox bit definitions for out_mb and in_mb */
684 #define MBX_31 BIT_31
685 #define MBX_30 BIT_30
686 #define MBX_29 BIT_29
687 #define MBX_28 BIT_28
688 #define MBX_27 BIT_27
689 #define MBX_26 BIT_26
690 #define MBX_25 BIT_25
691 #define MBX_24 BIT_24
692 #define MBX_23 BIT_23
693 #define MBX_22 BIT_22
694 #define MBX_21 BIT_21
695 #define MBX_20 BIT_20
696 #define MBX_19 BIT_19
697 #define MBX_18 BIT_18
698 #define MBX_17 BIT_17
699 #define MBX_16 BIT_16
700 #define MBX_15 BIT_15
701 #define MBX_14 BIT_14
702 #define MBX_13 BIT_13
703 #define MBX_12 BIT_12
704 #define MBX_11 BIT_11
705 #define MBX_10 BIT_10
706 #define MBX_9 BIT_9
707 #define MBX_8 BIT_8
708 #define MBX_7 BIT_7
709 #define MBX_6 BIT_6
710 #define MBX_5 BIT_5
711 #define MBX_4 BIT_4
712 #define MBX_3 BIT_3
713 #define MBX_2 BIT_2
714 #define MBX_1 BIT_1
715 #define MBX_0 BIT_0
716
717 /*
718 * Firmware state codes from get firmware state mailbox command
719 */
720 #define FSTATE_CONFIG_WAIT 0
721 #define FSTATE_WAIT_AL_PA 1
722 #define FSTATE_WAIT_LOGIN 2
723 #define FSTATE_READY 3
724 #define FSTATE_LOSS_OF_SYNC 4
725 #define FSTATE_ERROR 5
726 #define FSTATE_REINIT 6
727 #define FSTATE_NON_PART 7
728
729 #define FSTATE_CONFIG_CORRECT 0
730 #define FSTATE_P2P_RCV_LIP 1
731 #define FSTATE_P2P_CHOOSE_LOOP 2
732 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
733 #define FSTATE_FATAL_ERROR 4
734 #define FSTATE_LOOP_BACK_CONN 5
735
736 /*
737 * Port Database structure definition
738 * Little endian except where noted.
739 */
740 #define PORT_DATABASE_SIZE 128 /* bytes */
741 typedef struct {
742 uint8_t options;
743 uint8_t control;
744 uint8_t master_state;
745 uint8_t slave_state;
746 uint8_t reserved[2];
747 uint8_t hard_address;
748 uint8_t reserved_1;
749 uint8_t port_id[4];
750 uint8_t node_name[WWN_SIZE];
751 uint8_t port_name[WWN_SIZE];
752 uint16_t execution_throttle;
753 uint16_t execution_count;
754 uint8_t reset_count;
755 uint8_t reserved_2;
756 uint16_t resource_allocation;
757 uint16_t current_allocation;
758 uint16_t queue_head;
759 uint16_t queue_tail;
760 uint16_t transmit_execution_list_next;
761 uint16_t transmit_execution_list_previous;
762 uint16_t common_features;
763 uint16_t total_concurrent_sequences;
764 uint16_t RO_by_information_category;
765 uint8_t recipient;
766 uint8_t initiator;
767 uint16_t receive_data_size;
768 uint16_t concurrent_sequences;
769 uint16_t open_sequences_per_exchange;
770 uint16_t lun_abort_flags;
771 uint16_t lun_stop_flags;
772 uint16_t stop_queue_head;
773 uint16_t stop_queue_tail;
774 uint16_t port_retry_timer;
775 uint16_t next_sequence_id;
776 uint16_t frame_count;
777 uint16_t PRLI_payload_length;
778 uint8_t prli_svc_param_word_0[2]; /* Big endian */
779 /* Bits 15-0 of word 0 */
780 uint8_t prli_svc_param_word_3[2]; /* Big endian */
781 /* Bits 15-0 of word 3 */
782 uint16_t loop_id;
783 uint16_t extended_lun_info_list_pointer;
784 uint16_t extended_lun_stop_list_pointer;
785 } port_database_t;
786
787 /*
788 * Port database slave/master states
789 */
790 #define PD_STATE_DISCOVERY 0
791 #define PD_STATE_WAIT_DISCOVERY_ACK 1
792 #define PD_STATE_PORT_LOGIN 2
793 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
794 #define PD_STATE_PROCESS_LOGIN 4
795 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
796 #define PD_STATE_PORT_LOGGED_IN 6
797 #define PD_STATE_PORT_UNAVAILABLE 7
798 #define PD_STATE_PROCESS_LOGOUT 8
799 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
800 #define PD_STATE_PORT_LOGOUT 10
801 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
802
803
804 /*
805 * ISP Initialization Control Block.
806 * Little endian except where noted.
807 */
808 #define ICB_VERSION 1
809 typedef struct {
810 uint8_t version;
811 uint8_t reserved_1;
812
813 /*
814 * LSB BIT 0 = Enable Hard Loop Id
815 * LSB BIT 1 = Enable Fairness
816 * LSB BIT 2 = Enable Full-Duplex
817 * LSB BIT 3 = Enable Fast Posting
818 * LSB BIT 4 = Enable Target Mode
819 * LSB BIT 5 = Disable Initiator Mode
820 * LSB BIT 6 = Enable ADISC
821 * LSB BIT 7 = Enable Target Inquiry Data
822 *
823 * MSB BIT 0 = Enable PDBC Notify
824 * MSB BIT 1 = Non Participating LIP
825 * MSB BIT 2 = Descending Loop ID Search
826 * MSB BIT 3 = Acquire Loop ID in LIPA
827 * MSB BIT 4 = Stop PortQ on Full Status
828 * MSB BIT 5 = Full Login after LIP
829 * MSB BIT 6 = Node Name Option
830 * MSB BIT 7 = Ext IFWCB enable bit
831 */
832 uint8_t firmware_options[2];
833
834 uint16_t frame_payload_size;
835 uint16_t max_iocb_allocation;
836 uint16_t execution_throttle;
837 uint8_t retry_count;
838 uint8_t retry_delay; /* unused */
839 uint8_t port_name[WWN_SIZE]; /* Big endian. */
840 uint16_t hard_address;
841 uint8_t inquiry_data;
842 uint8_t login_timeout;
843 uint8_t node_name[WWN_SIZE]; /* Big endian. */
844
845 uint16_t request_q_outpointer;
846 uint16_t response_q_inpointer;
847 uint16_t request_q_length;
848 uint16_t response_q_length;
849 uint32_t request_q_address[2];
850 uint32_t response_q_address[2];
851
852 uint16_t lun_enables;
853 uint8_t command_resource_count;
854 uint8_t immediate_notify_resource_count;
855 uint16_t timeout;
856 uint8_t reserved_2[2];
857
858 /*
859 * LSB BIT 0 = Timer Operation mode bit 0
860 * LSB BIT 1 = Timer Operation mode bit 1
861 * LSB BIT 2 = Timer Operation mode bit 2
862 * LSB BIT 3 = Timer Operation mode bit 3
863 * LSB BIT 4 = Init Config Mode bit 0
864 * LSB BIT 5 = Init Config Mode bit 1
865 * LSB BIT 6 = Init Config Mode bit 2
866 * LSB BIT 7 = Enable Non part on LIHA failure
867 *
868 * MSB BIT 0 = Enable class 2
869 * MSB BIT 1 = Enable ACK0
870 * MSB BIT 2 =
871 * MSB BIT 3 =
872 * MSB BIT 4 = FC Tape Enable
873 * MSB BIT 5 = Enable FC Confirm
874 * MSB BIT 6 = Enable command queuing in target mode
875 * MSB BIT 7 = No Logo On Link Down
876 */
877 uint8_t add_firmware_options[2];
878
879 uint8_t response_accumulation_timer;
880 uint8_t interrupt_delay_timer;
881
882 /*
883 * LSB BIT 0 = Enable Read xfr_rdy
884 * LSB BIT 1 = Soft ID only
885 * LSB BIT 2 =
886 * LSB BIT 3 =
887 * LSB BIT 4 = FCP RSP Payload [0]
888 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
889 * LSB BIT 6 = Enable Out-of-Order frame handling
890 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
891 *
892 * MSB BIT 0 = Sbus enable - 2300
893 * MSB BIT 1 =
894 * MSB BIT 2 =
895 * MSB BIT 3 =
896 * MSB BIT 4 =
897 * MSB BIT 5 = enable 50 ohm termination
898 * MSB BIT 6 = Data Rate (2300 only)
899 * MSB BIT 7 = Data Rate (2300 only)
900 */
901 uint8_t special_options[2];
902
903 uint8_t reserved_3[26];
904 } init_cb_t;
905
906 /*
907 * Get Link Status mailbox command return buffer.
908 */
909 typedef struct {
910 uint32_t link_fail_cnt;
911 uint32_t loss_sync_cnt;
912 uint32_t loss_sig_cnt;
913 uint32_t prim_seq_err_cnt;
914 uint32_t inval_xmit_word_cnt;
915 uint32_t inval_crc_cnt;
916 } link_stat_t;
917
918 /*
919 * NVRAM Command values.
920 */
921 #define NV_START_BIT BIT_2
922 #define NV_WRITE_OP (BIT_26+BIT_24)
923 #define NV_READ_OP (BIT_26+BIT_25)
924 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
925 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
926 #define NV_DELAY_COUNT 10
927
928 /*
929 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
930 */
931 typedef struct {
932 /*
933 * NVRAM header
934 */
935 uint8_t id[4];
936 uint8_t nvram_version;
937 uint8_t reserved_0;
938
939 /*
940 * NVRAM RISC parameter block
941 */
942 uint8_t parameter_block_version;
943 uint8_t reserved_1;
944
945 /*
946 * LSB BIT 0 = Enable Hard Loop Id
947 * LSB BIT 1 = Enable Fairness
948 * LSB BIT 2 = Enable Full-Duplex
949 * LSB BIT 3 = Enable Fast Posting
950 * LSB BIT 4 = Enable Target Mode
951 * LSB BIT 5 = Disable Initiator Mode
952 * LSB BIT 6 = Enable ADISC
953 * LSB BIT 7 = Enable Target Inquiry Data
954 *
955 * MSB BIT 0 = Enable PDBC Notify
956 * MSB BIT 1 = Non Participating LIP
957 * MSB BIT 2 = Descending Loop ID Search
958 * MSB BIT 3 = Acquire Loop ID in LIPA
959 * MSB BIT 4 = Stop PortQ on Full Status
960 * MSB BIT 5 = Full Login after LIP
961 * MSB BIT 6 = Node Name Option
962 * MSB BIT 7 = Ext IFWCB enable bit
963 */
964 uint8_t firmware_options[2];
965
966 uint16_t frame_payload_size;
967 uint16_t max_iocb_allocation;
968 uint16_t execution_throttle;
969 uint8_t retry_count;
970 uint8_t retry_delay; /* unused */
971 uint8_t port_name[WWN_SIZE]; /* Big endian. */
972 uint16_t hard_address;
973 uint8_t inquiry_data;
974 uint8_t login_timeout;
975 uint8_t node_name[WWN_SIZE]; /* Big endian. */
976
977 /*
978 * LSB BIT 0 = Timer Operation mode bit 0
979 * LSB BIT 1 = Timer Operation mode bit 1
980 * LSB BIT 2 = Timer Operation mode bit 2
981 * LSB BIT 3 = Timer Operation mode bit 3
982 * LSB BIT 4 = Init Config Mode bit 0
983 * LSB BIT 5 = Init Config Mode bit 1
984 * LSB BIT 6 = Init Config Mode bit 2
985 * LSB BIT 7 = Enable Non part on LIHA failure
986 *
987 * MSB BIT 0 = Enable class 2
988 * MSB BIT 1 = Enable ACK0
989 * MSB BIT 2 =
990 * MSB BIT 3 =
991 * MSB BIT 4 = FC Tape Enable
992 * MSB BIT 5 = Enable FC Confirm
993 * MSB BIT 6 = Enable command queuing in target mode
994 * MSB BIT 7 = No Logo On Link Down
995 */
996 uint8_t add_firmware_options[2];
997
998 uint8_t response_accumulation_timer;
999 uint8_t interrupt_delay_timer;
1000
1001 /*
1002 * LSB BIT 0 = Enable Read xfr_rdy
1003 * LSB BIT 1 = Soft ID only
1004 * LSB BIT 2 =
1005 * LSB BIT 3 =
1006 * LSB BIT 4 = FCP RSP Payload [0]
1007 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1008 * LSB BIT 6 = Enable Out-of-Order frame handling
1009 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1010 *
1011 * MSB BIT 0 = Sbus enable - 2300
1012 * MSB BIT 1 =
1013 * MSB BIT 2 =
1014 * MSB BIT 3 =
1015 * MSB BIT 4 =
1016 * MSB BIT 5 = enable 50 ohm termination
1017 * MSB BIT 6 = Data Rate (2300 only)
1018 * MSB BIT 7 = Data Rate (2300 only)
1019 */
1020 uint8_t special_options[2];
1021
1022 /* Reserved for expanded RISC parameter block */
1023 uint8_t reserved_2[22];
1024
1025 /*
1026 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1027 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1028 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1029 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1030 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1031 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1032 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1033 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1034 *
1035 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1036 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1037 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1038 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1039 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1040 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1041 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1042 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1043 *
1044 * LSB BIT 0 = Output Swing 1G bit 0
1045 * LSB BIT 1 = Output Swing 1G bit 1
1046 * LSB BIT 2 = Output Swing 1G bit 2
1047 * LSB BIT 3 = Output Emphasis 1G bit 0
1048 * LSB BIT 4 = Output Emphasis 1G bit 1
1049 * LSB BIT 5 = Output Swing 2G bit 0
1050 * LSB BIT 6 = Output Swing 2G bit 1
1051 * LSB BIT 7 = Output Swing 2G bit 2
1052 *
1053 * MSB BIT 0 = Output Emphasis 2G bit 0
1054 * MSB BIT 1 = Output Emphasis 2G bit 1
1055 * MSB BIT 2 = Output Enable
1056 * MSB BIT 3 =
1057 * MSB BIT 4 =
1058 * MSB BIT 5 =
1059 * MSB BIT 6 =
1060 * MSB BIT 7 =
1061 */
1062 uint8_t seriallink_options[4];
1063
1064 /*
1065 * NVRAM host parameter block
1066 *
1067 * LSB BIT 0 = Enable spinup delay
1068 * LSB BIT 1 = Disable BIOS
1069 * LSB BIT 2 = Enable Memory Map BIOS
1070 * LSB BIT 3 = Enable Selectable Boot
1071 * LSB BIT 4 = Disable RISC code load
1072 * LSB BIT 5 = Set cache line size 1
1073 * LSB BIT 6 = PCI Parity Disable
1074 * LSB BIT 7 = Enable extended logging
1075 *
1076 * MSB BIT 0 = Enable 64bit addressing
1077 * MSB BIT 1 = Enable lip reset
1078 * MSB BIT 2 = Enable lip full login
1079 * MSB BIT 3 = Enable target reset
1080 * MSB BIT 4 = Enable database storage
1081 * MSB BIT 5 = Enable cache flush read
1082 * MSB BIT 6 = Enable database load
1083 * MSB BIT 7 = Enable alternate WWN
1084 */
1085 uint8_t host_p[2];
1086
1087 uint8_t boot_node_name[WWN_SIZE];
1088 uint8_t boot_lun_number;
1089 uint8_t reset_delay;
1090 uint8_t port_down_retry_count;
1091 uint8_t boot_id_number;
1092 uint16_t max_luns_per_target;
1093 uint8_t fcode_boot_port_name[WWN_SIZE];
1094 uint8_t alternate_port_name[WWN_SIZE];
1095 uint8_t alternate_node_name[WWN_SIZE];
1096
1097 /*
1098 * BIT 0 = Selective Login
1099 * BIT 1 = Alt-Boot Enable
1100 * BIT 2 =
1101 * BIT 3 = Boot Order List
1102 * BIT 4 =
1103 * BIT 5 = Selective LUN
1104 * BIT 6 =
1105 * BIT 7 = unused
1106 */
1107 uint8_t efi_parameters;
1108
1109 uint8_t link_down_timeout;
1110
1111 uint8_t adapter_id_0[4];
1112 uint8_t adapter_id_1[4];
1113 uint8_t adapter_id_2[4];
1114 uint8_t adapter_id_3[4];
1115
1116 uint8_t alt1_boot_node_name[WWN_SIZE];
1117 uint16_t alt1_boot_lun_number;
1118 uint8_t alt2_boot_node_name[WWN_SIZE];
1119 uint16_t alt2_boot_lun_number;
1120 uint8_t alt3_boot_node_name[WWN_SIZE];
1121 uint16_t alt3_boot_lun_number;
1122 uint8_t alt4_boot_node_name[WWN_SIZE];
1123 uint16_t alt4_boot_lun_number;
1124 uint8_t alt5_boot_node_name[WWN_SIZE];
1125 uint16_t alt5_boot_lun_number;
1126 uint8_t alt6_boot_node_name[WWN_SIZE];
1127 uint16_t alt6_boot_lun_number;
1128 uint8_t alt7_boot_node_name[WWN_SIZE];
1129 uint16_t alt7_boot_lun_number;
1130
1131 uint8_t reserved_3[2];
1132
1133 /* Offset 200-215 : Model Number */
1134 uint8_t model_number[16];
1135
1136 /* OEM related items */
1137 uint8_t oem_specific[16];
1138
1139 /*
1140 * NVRAM Adapter Features offset 232-239
1141 *
1142 * LSB BIT 0 = External GBIC
1143 * LSB BIT 1 = Risc RAM parity
1144 * LSB BIT 2 = Buffer Plus Module
1145 * LSB BIT 3 = Multi Chip Adapter
1146 * LSB BIT 4 = Internal connector
1147 * LSB BIT 5 =
1148 * LSB BIT 6 =
1149 * LSB BIT 7 =
1150 *
1151 * MSB BIT 0 =
1152 * MSB BIT 1 =
1153 * MSB BIT 2 =
1154 * MSB BIT 3 =
1155 * MSB BIT 4 =
1156 * MSB BIT 5 =
1157 * MSB BIT 6 =
1158 * MSB BIT 7 =
1159 */
1160 uint8_t adapter_features[2];
1161
1162 uint8_t reserved_4[16];
1163
1164 /* Subsystem vendor ID for ISP2200 */
1165 uint16_t subsystem_vendor_id_2200;
1166
1167 /* Subsystem device ID for ISP2200 */
1168 uint16_t subsystem_device_id_2200;
1169
1170 uint8_t reserved_5;
1171 uint8_t checksum;
1172 } nvram_t;
1173
1174 /*
1175 * ISP queue - response queue entry definition.
1176 */
1177 typedef struct {
1178 uint8_t data[60];
1179 uint32_t signature;
1180 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1181 } response_t;
1182
1183 typedef union {
1184 uint16_t extended;
1185 struct {
1186 uint8_t reserved;
1187 uint8_t standard;
1188 } id;
1189 } target_id_t;
1190
1191 #define SET_TARGET_ID(ha, to, from) \
1192 do { \
1193 if (HAS_EXTENDED_IDS(ha)) \
1194 to.extended = cpu_to_le16(from); \
1195 else \
1196 to.id.standard = (uint8_t)from; \
1197 } while (0)
1198
1199 /*
1200 * ISP queue - command entry structure definition.
1201 */
1202 #define COMMAND_TYPE 0x11 /* Command entry */
1203 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1204 typedef struct {
1205 uint8_t entry_type; /* Entry type. */
1206 uint8_t entry_count; /* Entry count. */
1207 uint8_t sys_define; /* System defined. */
1208 uint8_t entry_status; /* Entry Status. */
1209 uint32_t handle; /* System handle. */
1210 target_id_t target; /* SCSI ID */
1211 uint16_t lun; /* SCSI LUN */
1212 uint16_t control_flags; /* Control flags. */
1213 #define CF_WRITE BIT_6
1214 #define CF_READ BIT_5
1215 #define CF_SIMPLE_TAG BIT_3
1216 #define CF_ORDERED_TAG BIT_2
1217 #define CF_HEAD_TAG BIT_1
1218 uint16_t reserved_1;
1219 uint16_t timeout; /* Command timeout. */
1220 uint16_t dseg_count; /* Data segment count. */
1221 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1222 uint32_t byte_count; /* Total byte count. */
1223 uint32_t dseg_0_address; /* Data segment 0 address. */
1224 uint32_t dseg_0_length; /* Data segment 0 length. */
1225 uint32_t dseg_1_address; /* Data segment 1 address. */
1226 uint32_t dseg_1_length; /* Data segment 1 length. */
1227 uint32_t dseg_2_address; /* Data segment 2 address. */
1228 uint32_t dseg_2_length; /* Data segment 2 length. */
1229 } cmd_entry_t;
1230
1231 /*
1232 * ISP queue - 64-Bit addressing, command entry structure definition.
1233 */
1234 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1235 typedef struct {
1236 uint8_t entry_type; /* Entry type. */
1237 uint8_t entry_count; /* Entry count. */
1238 uint8_t sys_define; /* System defined. */
1239 uint8_t entry_status; /* Entry Status. */
1240 uint32_t handle; /* System handle. */
1241 target_id_t target; /* SCSI ID */
1242 uint16_t lun; /* SCSI LUN */
1243 uint16_t control_flags; /* Control flags. */
1244 uint16_t reserved_1;
1245 uint16_t timeout; /* Command timeout. */
1246 uint16_t dseg_count; /* Data segment count. */
1247 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1248 uint32_t byte_count; /* Total byte count. */
1249 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1250 uint32_t dseg_0_length; /* Data segment 0 length. */
1251 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1252 uint32_t dseg_1_length; /* Data segment 1 length. */
1253 } cmd_a64_entry_t, request_t;
1254
1255 /*
1256 * ISP queue - continuation entry structure definition.
1257 */
1258 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1259 typedef struct {
1260 uint8_t entry_type; /* Entry type. */
1261 uint8_t entry_count; /* Entry count. */
1262 uint8_t sys_define; /* System defined. */
1263 uint8_t entry_status; /* Entry Status. */
1264 uint32_t reserved;
1265 uint32_t dseg_0_address; /* Data segment 0 address. */
1266 uint32_t dseg_0_length; /* Data segment 0 length. */
1267 uint32_t dseg_1_address; /* Data segment 1 address. */
1268 uint32_t dseg_1_length; /* Data segment 1 length. */
1269 uint32_t dseg_2_address; /* Data segment 2 address. */
1270 uint32_t dseg_2_length; /* Data segment 2 length. */
1271 uint32_t dseg_3_address; /* Data segment 3 address. */
1272 uint32_t dseg_3_length; /* Data segment 3 length. */
1273 uint32_t dseg_4_address; /* Data segment 4 address. */
1274 uint32_t dseg_4_length; /* Data segment 4 length. */
1275 uint32_t dseg_5_address; /* Data segment 5 address. */
1276 uint32_t dseg_5_length; /* Data segment 5 length. */
1277 uint32_t dseg_6_address; /* Data segment 6 address. */
1278 uint32_t dseg_6_length; /* Data segment 6 length. */
1279 } cont_entry_t;
1280
1281 /*
1282 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1283 */
1284 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1285 typedef struct {
1286 uint8_t entry_type; /* Entry type. */
1287 uint8_t entry_count; /* Entry count. */
1288 uint8_t sys_define; /* System defined. */
1289 uint8_t entry_status; /* Entry Status. */
1290 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1291 uint32_t dseg_0_length; /* Data segment 0 length. */
1292 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1293 uint32_t dseg_1_length; /* Data segment 1 length. */
1294 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1295 uint32_t dseg_2_length; /* Data segment 2 length. */
1296 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1297 uint32_t dseg_3_length; /* Data segment 3 length. */
1298 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1299 uint32_t dseg_4_length; /* Data segment 4 length. */
1300 } cont_a64_entry_t;
1301
1302 /*
1303 * ISP queue - status entry structure definition.
1304 */
1305 #define STATUS_TYPE 0x03 /* Status entry. */
1306 typedef struct {
1307 uint8_t entry_type; /* Entry type. */
1308 uint8_t entry_count; /* Entry count. */
1309 uint8_t sys_define; /* System defined. */
1310 uint8_t entry_status; /* Entry Status. */
1311 uint32_t handle; /* System handle. */
1312 uint16_t scsi_status; /* SCSI status. */
1313 uint16_t comp_status; /* Completion status. */
1314 uint16_t state_flags; /* State flags. */
1315 uint16_t status_flags; /* Status flags. */
1316 uint16_t rsp_info_len; /* Response Info Length. */
1317 uint16_t req_sense_length; /* Request sense data length. */
1318 uint32_t residual_length; /* Residual transfer length. */
1319 uint8_t rsp_info[8]; /* FCP response information. */
1320 uint8_t req_sense_data[32]; /* Request sense data. */
1321 } sts_entry_t;
1322
1323 /*
1324 * Status entry entry status
1325 */
1326 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1327 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1328 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1329 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1330 #define RF_BUSY BIT_1 /* Busy */
1331
1332 /*
1333 * Status entry SCSI status bit definitions.
1334 */
1335 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1336 #define SS_RESIDUAL_UNDER BIT_11
1337 #define SS_RESIDUAL_OVER BIT_10
1338 #define SS_SENSE_LEN_VALID BIT_9
1339 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1340
1341 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1342 #define SS_BUSY_CONDITION BIT_3
1343 #define SS_CONDITION_MET BIT_2
1344 #define SS_CHECK_CONDITION BIT_1
1345
1346 /*
1347 * Status entry completion status
1348 */
1349 #define CS_COMPLETE 0x0 /* No errors */
1350 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1351 #define CS_DMA 0x2 /* A DMA direction error. */
1352 #define CS_TRANSPORT 0x3 /* Transport error. */
1353 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1354 #define CS_ABORTED 0x5 /* System aborted command. */
1355 #define CS_TIMEOUT 0x6 /* Timeout error. */
1356 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1357
1358 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1359 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1360 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1361 /* (selection timeout) */
1362 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1363 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1364 #define CS_PORT_BUSY 0x2B /* Port Busy */
1365 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1366 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1367 #define CS_UNKNOWN 0x81 /* Driver defined */
1368 #define CS_RETRY 0x82 /* Driver defined */
1369 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1370
1371 /*
1372 * Status entry status flags
1373 */
1374 #define SF_ABTS_TERMINATED BIT_10
1375 #define SF_LOGOUT_SENT BIT_13
1376
1377 /*
1378 * ISP queue - status continuation entry structure definition.
1379 */
1380 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1381 typedef struct {
1382 uint8_t entry_type; /* Entry type. */
1383 uint8_t entry_count; /* Entry count. */
1384 uint8_t sys_define; /* System defined. */
1385 uint8_t entry_status; /* Entry Status. */
1386 uint8_t data[60]; /* data */
1387 } sts_cont_entry_t;
1388
1389 /*
1390 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1391 * structure definition.
1392 */
1393 #define STATUS_TYPE_21 0x21 /* Status entry. */
1394 typedef struct {
1395 uint8_t entry_type; /* Entry type. */
1396 uint8_t entry_count; /* Entry count. */
1397 uint8_t handle_count; /* Handle count. */
1398 uint8_t entry_status; /* Entry Status. */
1399 uint32_t handle[15]; /* System handles. */
1400 } sts21_entry_t;
1401
1402 /*
1403 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1404 * structure definition.
1405 */
1406 #define STATUS_TYPE_22 0x22 /* Status entry. */
1407 typedef struct {
1408 uint8_t entry_type; /* Entry type. */
1409 uint8_t entry_count; /* Entry count. */
1410 uint8_t handle_count; /* Handle count. */
1411 uint8_t entry_status; /* Entry Status. */
1412 uint16_t handle[30]; /* System handles. */
1413 } sts22_entry_t;
1414
1415 /*
1416 * ISP queue - marker entry structure definition.
1417 */
1418 #define MARKER_TYPE 0x04 /* Marker entry. */
1419 typedef struct {
1420 uint8_t entry_type; /* Entry type. */
1421 uint8_t entry_count; /* Entry count. */
1422 uint8_t handle_count; /* Handle count. */
1423 uint8_t entry_status; /* Entry Status. */
1424 uint32_t sys_define_2; /* System defined. */
1425 target_id_t target; /* SCSI ID */
1426 uint8_t modifier; /* Modifier (7-0). */
1427 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1428 #define MK_SYNC_ID 1 /* Synchronize ID */
1429 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1430 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1431 /* clear port changed, */
1432 /* use sequence number. */
1433 uint8_t reserved_1;
1434 uint16_t sequence_number; /* Sequence number of event */
1435 uint16_t lun; /* SCSI LUN */
1436 uint8_t reserved_2[48];
1437 } mrk_entry_t;
1438
1439 /*
1440 * ISP queue - Management Server entry structure definition.
1441 */
1442 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1443 typedef struct {
1444 uint8_t entry_type; /* Entry type. */
1445 uint8_t entry_count; /* Entry count. */
1446 uint8_t handle_count; /* Handle count. */
1447 uint8_t entry_status; /* Entry Status. */
1448 uint32_t handle1; /* System handle. */
1449 target_id_t loop_id;
1450 uint16_t status;
1451 uint16_t control_flags; /* Control flags. */
1452 uint16_t reserved2;
1453 uint16_t timeout;
1454 uint16_t cmd_dsd_count;
1455 uint16_t total_dsd_count;
1456 uint8_t type;
1457 uint8_t r_ctl;
1458 uint16_t rx_id;
1459 uint16_t reserved3;
1460 uint32_t handle2;
1461 uint32_t rsp_bytecount;
1462 uint32_t req_bytecount;
1463 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1464 uint32_t dseg_req_length; /* Data segment 0 length. */
1465 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1466 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1467 } ms_iocb_entry_t;
1468
1469
1470 /*
1471 * ISP queue - Mailbox Command entry structure definition.
1472 */
1473 #define MBX_IOCB_TYPE 0x39
1474 struct mbx_entry {
1475 uint8_t entry_type;
1476 uint8_t entry_count;
1477 uint8_t sys_define1;
1478 /* Use sys_define1 for source type */
1479 #define SOURCE_SCSI 0x00
1480 #define SOURCE_IP 0x01
1481 #define SOURCE_VI 0x02
1482 #define SOURCE_SCTP 0x03
1483 #define SOURCE_MP 0x04
1484 #define SOURCE_MPIOCTL 0x05
1485 #define SOURCE_ASYNC_IOCB 0x07
1486
1487 uint8_t entry_status;
1488
1489 uint32_t handle;
1490 target_id_t loop_id;
1491
1492 uint16_t status;
1493 uint16_t state_flags;
1494 uint16_t status_flags;
1495
1496 uint32_t sys_define2[2];
1497
1498 uint16_t mb0;
1499 uint16_t mb1;
1500 uint16_t mb2;
1501 uint16_t mb3;
1502 uint16_t mb6;
1503 uint16_t mb7;
1504 uint16_t mb9;
1505 uint16_t mb10;
1506 uint32_t reserved_2[2];
1507 uint8_t node_name[WWN_SIZE];
1508 uint8_t port_name[WWN_SIZE];
1509 };
1510
1511 /*
1512 * ISP request and response queue entry sizes
1513 */
1514 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1515 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1516
1517
1518 /*
1519 * 24 bit port ID type definition.
1520 */
1521 typedef union {
1522 uint32_t b24 : 24;
1523
1524 struct {
1525 uint8_t d_id[3];
1526 uint8_t rsvd_1;
1527 } r;
1528
1529 struct {
1530 uint8_t al_pa;
1531 uint8_t area;
1532 uint8_t domain;
1533 uint8_t rsvd_1;
1534 } b;
1535 } port_id_t;
1536 #define INVALID_PORT_ID 0xFFFFFF
1537
1538 /*
1539 * Switch info gathering structure.
1540 */
1541 typedef struct {
1542 port_id_t d_id;
1543 uint8_t node_name[WWN_SIZE];
1544 uint8_t port_name[WWN_SIZE];
1545 uint32_t type;
1546 #define SW_TYPE_IP BIT_1
1547 #define SW_TYPE_SCSI BIT_0
1548 } sw_info_t;
1549
1550 /*
1551 * Inquiry command structure.
1552 */
1553 #define INQ_DATA_SIZE 36
1554
1555 /*
1556 * Inquiry mailbox IOCB packet definition.
1557 */
1558 typedef struct {
1559 union {
1560 cmd_a64_entry_t cmd;
1561 sts_entry_t rsp;
1562 } p;
1563 uint8_t inq[INQ_DATA_SIZE];
1564 } inq_cmd_rsp_t;
1565
1566 /*
1567 * Report LUN command structure.
1568 */
1569 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1570
1571 typedef struct {
1572 uint32_t len;
1573 uint32_t rsrv;
1574 } rpt_hdr_t;
1575
1576 typedef struct {
1577 struct {
1578 uint8_t b : 6;
1579 uint8_t address_method : 2;
1580 } msb;
1581 uint8_t lsb;
1582 uint8_t unused[6];
1583 } rpt_lun_t;
1584
1585 typedef struct {
1586 rpt_hdr_t hdr;
1587 rpt_lun_t lst[MAX_LUNS];
1588 } rpt_lun_lst_t;
1589
1590 /*
1591 * Report Lun mailbox IOCB packet definition.
1592 */
1593 typedef struct {
1594 union {
1595 cmd_a64_entry_t cmd;
1596 sts_entry_t rsp;
1597 } p;
1598 rpt_lun_lst_t list;
1599 } rpt_lun_cmd_rsp_t;
1600
1601 /*
1602 * Fibre channel port type.
1603 */
1604 typedef enum {
1605 FCT_UNKNOWN,
1606 FCT_RSCN,
1607 FCT_SWITCH,
1608 FCT_BROADCAST,
1609 FCT_INITIATOR,
1610 FCT_TARGET
1611 } fc_port_type_t;
1612
1613 /*
1614 * Fibre channel port structure.
1615 */
1616 typedef struct fc_port {
1617 struct list_head list;
1618 struct scsi_qla_host *ha;
1619 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1620
1621 uint8_t node_name[WWN_SIZE];
1622 uint8_t port_name[WWN_SIZE];
1623 port_id_t d_id;
1624 uint16_t loop_id;
1625 uint16_t old_loop_id;
1626
1627 fc_port_type_t port_type;
1628
1629 atomic_t state;
1630 uint32_t flags;
1631
1632 unsigned int os_target_id;
1633
1634 uint16_t iodesc_idx_sent;
1635
1636 int port_login_retry_count;
1637 int login_retry;
1638 atomic_t port_down_timer;
1639
1640 uint8_t device_type;
1641 uint8_t unused;
1642
1643 uint8_t mp_byte; /* multi-path byte (not used) */
1644 uint8_t cur_path; /* current path id */
1645
1646 struct fc_rport *rport;
1647 } fc_port_t;
1648
1649 /*
1650 * Fibre channel port/lun states.
1651 */
1652 #define FCS_UNCONFIGURED 1
1653 #define FCS_DEVICE_DEAD 2
1654 #define FCS_DEVICE_LOST 3
1655 #define FCS_ONLINE 4
1656 #define FCS_NOT_SUPPORTED 5
1657 #define FCS_FAILOVER 6
1658 #define FCS_FAILOVER_FAILED 7
1659
1660 /*
1661 * FC port flags.
1662 */
1663 #define FCF_FABRIC_DEVICE BIT_0
1664 #define FCF_LOGIN_NEEDED BIT_1
1665 #define FCF_FO_MASKED BIT_2
1666 #define FCF_FAILOVER_NEEDED BIT_3
1667 #define FCF_RESET_NEEDED BIT_4
1668 #define FCF_PERSISTENT_BOUND BIT_5
1669 #define FCF_TAPE_PRESENT BIT_6
1670 #define FCF_FARP_DONE BIT_7
1671 #define FCF_FARP_FAILED BIT_8
1672 #define FCF_FARP_REPLY_NEEDED BIT_9
1673 #define FCF_AUTH_REQ BIT_10
1674 #define FCF_SEND_AUTH_REQ BIT_11
1675 #define FCF_RECEIVE_AUTH_REQ BIT_12
1676 #define FCF_AUTH_SUCCESS BIT_13
1677 #define FCF_RLC_SUPPORT BIT_14
1678 #define FCF_CONFIG BIT_15 /* Needed? */
1679 #define FCF_RESCAN_NEEDED BIT_16
1680 #define FCF_XP_DEVICE BIT_17
1681 #define FCF_MSA_DEVICE BIT_18
1682 #define FCF_EVA_DEVICE BIT_19
1683 #define FCF_MSA_PORT_ACTIVE BIT_20
1684 #define FCF_FAILBACK_DISABLE BIT_21
1685 #define FCF_FAILOVER_DISABLE BIT_22
1686 #define FCF_DSXXX_DEVICE BIT_23
1687 #define FCF_AA_EVA_DEVICE BIT_24
1688
1689 /* No loop ID flag. */
1690 #define FC_NO_LOOP_ID 0x1000
1691
1692 /*
1693 * FC-CT interface
1694 *
1695 * NOTE: All structures are big-endian in form.
1696 */
1697
1698 #define CT_REJECT_RESPONSE 0x8001
1699 #define CT_ACCEPT_RESPONSE 0x8002
1700
1701 #define NS_N_PORT_TYPE 0x01
1702 #define NS_NL_PORT_TYPE 0x02
1703 #define NS_NX_PORT_TYPE 0x7F
1704
1705 #define GA_NXT_CMD 0x100
1706 #define GA_NXT_REQ_SIZE (16 + 4)
1707 #define GA_NXT_RSP_SIZE (16 + 620)
1708
1709 #define GID_PT_CMD 0x1A1
1710 #define GID_PT_REQ_SIZE (16 + 4)
1711 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1712
1713 #define GPN_ID_CMD 0x112
1714 #define GPN_ID_REQ_SIZE (16 + 4)
1715 #define GPN_ID_RSP_SIZE (16 + 8)
1716
1717 #define GNN_ID_CMD 0x113
1718 #define GNN_ID_REQ_SIZE (16 + 4)
1719 #define GNN_ID_RSP_SIZE (16 + 8)
1720
1721 #define GFT_ID_CMD 0x117
1722 #define GFT_ID_REQ_SIZE (16 + 4)
1723 #define GFT_ID_RSP_SIZE (16 + 32)
1724
1725 #define RFT_ID_CMD 0x217
1726 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1727 #define RFT_ID_RSP_SIZE 16
1728
1729 #define RFF_ID_CMD 0x21F
1730 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1731 #define RFF_ID_RSP_SIZE 16
1732
1733 #define RNN_ID_CMD 0x213
1734 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1735 #define RNN_ID_RSP_SIZE 16
1736
1737 #define RSNN_NN_CMD 0x239
1738 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1739 #define RSNN_NN_RSP_SIZE 16
1740
1741 /* CT command header -- request/response common fields */
1742 struct ct_cmd_hdr {
1743 uint8_t revision;
1744 uint8_t in_id[3];
1745 uint8_t gs_type;
1746 uint8_t gs_subtype;
1747 uint8_t options;
1748 uint8_t reserved;
1749 };
1750
1751 /* CT command request */
1752 struct ct_sns_req {
1753 struct ct_cmd_hdr header;
1754 uint16_t command;
1755 uint16_t max_rsp_size;
1756 uint8_t fragment_id;
1757 uint8_t reserved[3];
1758
1759 union {
1760 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1761 struct {
1762 uint8_t reserved;
1763 uint8_t port_id[3];
1764 } port_id;
1765
1766 struct {
1767 uint8_t port_type;
1768 uint8_t domain;
1769 uint8_t area;
1770 uint8_t reserved;
1771 } gid_pt;
1772
1773 struct {
1774 uint8_t reserved;
1775 uint8_t port_id[3];
1776 uint8_t fc4_types[32];
1777 } rft_id;
1778
1779 struct {
1780 uint8_t reserved;
1781 uint8_t port_id[3];
1782 uint16_t reserved2;
1783 uint8_t fc4_feature;
1784 uint8_t fc4_type;
1785 } rff_id;
1786
1787 struct {
1788 uint8_t reserved;
1789 uint8_t port_id[3];
1790 uint8_t node_name[8];
1791 } rnn_id;
1792
1793 struct {
1794 uint8_t node_name[8];
1795 uint8_t name_len;
1796 uint8_t sym_node_name[255];
1797 } rsnn_nn;
1798 } req;
1799 };
1800
1801 /* CT command response header */
1802 struct ct_rsp_hdr {
1803 struct ct_cmd_hdr header;
1804 uint16_t response;
1805 uint16_t residual;
1806 uint8_t fragment_id;
1807 uint8_t reason_code;
1808 uint8_t explanation_code;
1809 uint8_t vendor_unique;
1810 };
1811
1812 struct ct_sns_gid_pt_data {
1813 uint8_t control_byte;
1814 uint8_t port_id[3];
1815 };
1816
1817 struct ct_sns_rsp {
1818 struct ct_rsp_hdr header;
1819
1820 union {
1821 struct {
1822 uint8_t port_type;
1823 uint8_t port_id[3];
1824 uint8_t port_name[8];
1825 uint8_t sym_port_name_len;
1826 uint8_t sym_port_name[255];
1827 uint8_t node_name[8];
1828 uint8_t sym_node_name_len;
1829 uint8_t sym_node_name[255];
1830 uint8_t init_proc_assoc[8];
1831 uint8_t node_ip_addr[16];
1832 uint8_t class_of_service[4];
1833 uint8_t fc4_types[32];
1834 uint8_t ip_address[16];
1835 uint8_t fabric_port_name[8];
1836 uint8_t reserved;
1837 uint8_t hard_address[3];
1838 } ga_nxt;
1839
1840 struct {
1841 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1842 } gid_pt;
1843
1844 struct {
1845 uint8_t port_name[8];
1846 } gpn_id;
1847
1848 struct {
1849 uint8_t node_name[8];
1850 } gnn_id;
1851
1852 struct {
1853 uint8_t fc4_types[32];
1854 } gft_id;
1855 } rsp;
1856 };
1857
1858 struct ct_sns_pkt {
1859 union {
1860 struct ct_sns_req req;
1861 struct ct_sns_rsp rsp;
1862 } p;
1863 };
1864
1865 /*
1866 * SNS command structures -- for 2200 compatability.
1867 */
1868 #define RFT_ID_SNS_SCMD_LEN 22
1869 #define RFT_ID_SNS_CMD_SIZE 60
1870 #define RFT_ID_SNS_DATA_SIZE 16
1871
1872 #define RNN_ID_SNS_SCMD_LEN 10
1873 #define RNN_ID_SNS_CMD_SIZE 36
1874 #define RNN_ID_SNS_DATA_SIZE 16
1875
1876 #define GA_NXT_SNS_SCMD_LEN 6
1877 #define GA_NXT_SNS_CMD_SIZE 28
1878 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1879
1880 #define GID_PT_SNS_SCMD_LEN 6
1881 #define GID_PT_SNS_CMD_SIZE 28
1882 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1883
1884 #define GPN_ID_SNS_SCMD_LEN 6
1885 #define GPN_ID_SNS_CMD_SIZE 28
1886 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1887
1888 #define GNN_ID_SNS_SCMD_LEN 6
1889 #define GNN_ID_SNS_CMD_SIZE 28
1890 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1891
1892 struct sns_cmd_pkt {
1893 union {
1894 struct {
1895 uint16_t buffer_length;
1896 uint16_t reserved_1;
1897 uint32_t buffer_address[2];
1898 uint16_t subcommand_length;
1899 uint16_t reserved_2;
1900 uint16_t subcommand;
1901 uint16_t size;
1902 uint32_t reserved_3;
1903 uint8_t param[36];
1904 } cmd;
1905
1906 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1907 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1908 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1909 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1910 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1911 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1912 } p;
1913 };
1914
1915 /* IO descriptors */
1916 #define MAX_IO_DESCRIPTORS 32
1917
1918 #define ABORT_IOCB_CB 0
1919 #define ADISC_PORT_IOCB_CB 1
1920 #define LOGOUT_PORT_IOCB_CB 2
1921 #define LOGIN_PORT_IOCB_CB 3
1922 #define LAST_IOCB_CB 4
1923
1924 #define IODESC_INVALID_INDEX 0xFFFF
1925 #define IODESC_ADISC_NEEDED 0xFFFE
1926 #define IODESC_LOGIN_NEEDED 0xFFFD
1927
1928 struct io_descriptor {
1929 uint16_t used:1;
1930 uint16_t idx:11;
1931 uint16_t cb_idx:4;
1932
1933 struct timer_list timer;
1934
1935 struct scsi_qla_host *ha;
1936
1937 port_id_t d_id;
1938 fc_port_t *remote_fcport;
1939
1940 uint32_t signature;
1941 };
1942
1943 struct qla_fw_info {
1944 unsigned short addressing; /* addressing method used to load fw */
1945 #define FW_INFO_ADDR_NORMAL 0
1946 #define FW_INFO_ADDR_EXTENDED 1
1947 #define FW_INFO_ADDR_NOMORE 0xffff
1948 unsigned short *fwcode; /* pointer to FW array */
1949 unsigned short *fwlen; /* number of words in array */
1950 unsigned short *fwstart; /* start address for F/W */
1951 unsigned long *lfwstart; /* start address (long) for F/W */
1952 };
1953
1954 struct qla_board_info {
1955 char *drv_name;
1956
1957 char isp_name[8];
1958 struct qla_fw_info *fw_info;
1959 };
1960
1961 /* Return data from MBC_GET_ID_LIST call. */
1962 struct gid_list_info {
1963 uint8_t al_pa;
1964 uint8_t area;
1965 uint8_t domain;
1966 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
1967 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
1968 };
1969 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
1970
1971 /*
1972 * Linux Host Adapter structure
1973 */
1974 typedef struct scsi_qla_host {
1975 struct list_head list;
1976
1977 /* Commonly used flags and state information. */
1978 struct Scsi_Host *host;
1979 struct pci_dev *pdev;
1980
1981 unsigned long host_no;
1982 unsigned long instance;
1983
1984 volatile struct {
1985 uint32_t init_done :1;
1986 uint32_t online :1;
1987 uint32_t mbox_int :1;
1988 uint32_t mbox_busy :1;
1989 uint32_t rscn_queue_overflow :1;
1990 uint32_t reset_active :1;
1991
1992 uint32_t management_server_logged_in :1;
1993 uint32_t process_response_queue :1;
1994
1995 uint32_t disable_risc_code_load :1;
1996 uint32_t enable_64bit_addressing :1;
1997 uint32_t enable_lip_reset :1;
1998 uint32_t enable_lip_full_login :1;
1999 uint32_t enable_target_reset :1;
2000 uint32_t enable_led_scheme :1;
2001 } flags;
2002
2003 atomic_t loop_state;
2004 #define LOOP_TIMEOUT 1
2005 #define LOOP_DOWN 2
2006 #define LOOP_UP 3
2007 #define LOOP_UPDATE 4
2008 #define LOOP_READY 5
2009 #define LOOP_DEAD 6
2010
2011 unsigned long dpc_flags;
2012 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2013 #define RESET_ACTIVE 1
2014 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2015 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2016 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2017 #define LOOP_RESYNC_ACTIVE 5
2018 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2019 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2020 #define MAILBOX_RETRY 8
2021 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2022 #define FAILOVER_EVENT_NEEDED 10
2023 #define FAILOVER_EVENT 11
2024 #define FAILOVER_NEEDED 12
2025 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2026 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2027 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2028 #define ABORT_QUEUES_NEEDED 16
2029 #define RELOGIN_NEEDED 17
2030 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2031 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2032 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2033 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2034 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2035 #define IOCTL_ERROR_RECOVERY 23
2036 #define LOOP_RESET_NEEDED 24
2037
2038 uint32_t device_flags;
2039 #define DFLG_LOCAL_DEVICES BIT_0
2040 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2041 #define DFLG_FABRIC_DEVICES BIT_2
2042 #define SWITCH_FOUND BIT_3
2043 #define DFLG_NO_CABLE BIT_4
2044
2045 /* SRB cache. */
2046 #define SRB_MIN_REQ 128
2047 mempool_t *srb_mempool;
2048
2049 /* This spinlock is used to protect "io transactions", you must
2050 * aquire it before doing any IO to the card, eg with RD_REG*() and
2051 * WRT_REG*() for the duration of your entire commandtransaction.
2052 *
2053 * This spinlock is of lower priority than the io request lock.
2054 */
2055
2056 spinlock_t hardware_lock ____cacheline_aligned;
2057
2058 device_reg_t __iomem *iobase; /* Base I/O address */
2059 unsigned long pio_address;
2060 unsigned long pio_length;
2061 #define MIN_IOBASE_LEN 0x100
2062
2063 /* ISP ring lock, rings, and indexes */
2064 dma_addr_t request_dma; /* Physical address. */
2065 request_t *request_ring; /* Base virtual address */
2066 request_t *request_ring_ptr; /* Current address. */
2067 uint16_t req_ring_index; /* Current index. */
2068 uint16_t req_q_cnt; /* Number of available entries. */
2069 uint16_t request_q_length;
2070
2071 dma_addr_t response_dma; /* Physical address. */
2072 response_t *response_ring; /* Base virtual address */
2073 response_t *response_ring_ptr; /* Current address. */
2074 uint16_t rsp_ring_index; /* Current index. */
2075 uint16_t response_q_length;
2076
2077 uint16_t (*calc_request_entries)(uint16_t);
2078 void (*build_scsi_iocbs)(srb_t *, cmd_entry_t *, uint16_t);
2079
2080 /* Outstandings ISP commands. */
2081 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2082 uint32_t current_outstanding_cmd;
2083 srb_t *status_srb; /* Status continuation entry. */
2084
2085 unsigned long last_irq_cpu; /* cpu where we got our last irq */
2086
2087 uint16_t revision;
2088 uint8_t ports;
2089 u_long actthreads;
2090 u_long ipreq_cnt;
2091 u_long qthreads;
2092
2093 uint32_t total_isr_cnt; /* Interrupt count */
2094 uint32_t total_isp_aborts; /* controller err cnt */
2095 uint32_t total_lip_cnt; /* LIP cnt */
2096 uint32_t total_dev_errs; /* device error cnt */
2097 uint32_t total_ios; /* IO cnt */
2098 uint64_t total_bytes; /* xfr byte cnt */
2099 uint32_t total_mbx_timeout; /* mailbox timeout cnt */
2100 uint32_t total_loop_resync; /* loop resyn cnt */
2101 uint32_t dropped_frame_error_cnt;
2102
2103 /* ISP configuration data. */
2104 uint16_t loop_id; /* Host adapter loop id */
2105 uint16_t fb_rev;
2106
2107 port_id_t d_id; /* Host adapter port id */
2108 uint16_t max_public_loop_ids;
2109 uint16_t min_external_loopid; /* First external loop Id */
2110
2111 uint16_t link_data_rate; /* F/W operating speed */
2112
2113 uint8_t current_topology;
2114 uint8_t prev_topology;
2115 #define ISP_CFG_NL 1
2116 #define ISP_CFG_N 2
2117 #define ISP_CFG_FL 4
2118 #define ISP_CFG_F 8
2119
2120 uint8_t operating_mode; /* F/W operating mode */
2121 #define LOOP 0
2122 #define P2P 1
2123 #define LOOP_P2P 2
2124 #define P2P_LOOP 3
2125
2126 uint8_t marker_needed;
2127 uint8_t sns_retry_cnt;
2128 uint8_t mem_err;
2129
2130 uint8_t interrupts_on;
2131
2132 /* HBA serial number */
2133 uint8_t serial0;
2134 uint8_t serial1;
2135 uint8_t serial2;
2136
2137 /* NVRAM configuration data */
2138 uint16_t nvram_base;
2139
2140 uint16_t loop_reset_delay;
2141 uint16_t minimum_timeout;
2142 uint8_t retry_count;
2143 uint8_t login_timeout;
2144 uint16_t r_a_tov;
2145 int port_down_retry_count;
2146 uint8_t loop_down_timeout;
2147 uint8_t mbx_count;
2148 uint16_t max_probe_luns;
2149 uint16_t max_luns;
2150 uint16_t max_targets;
2151 uint16_t last_loop_id;
2152
2153 uint32_t login_retry_count;
2154
2155 /* Fibre Channel Device List. */
2156 struct list_head fcports;
2157 struct list_head rscn_fcports;
2158
2159 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2160 uint16_t iodesc_signature;
2161
2162 /* RSCN queue. */
2163 uint32_t rscn_queue[MAX_RSCN_COUNT];
2164 uint8_t rscn_in_ptr;
2165 uint8_t rscn_out_ptr;
2166
2167 /* SNS command interfaces. */
2168 ms_iocb_entry_t *ms_iocb;
2169 dma_addr_t ms_iocb_dma;
2170 struct ct_sns_pkt *ct_sns;
2171 dma_addr_t ct_sns_dma;
2172 /* SNS command interfaces for 2200. */
2173 struct sns_cmd_pkt *sns_cmd;
2174 dma_addr_t sns_cmd_dma;
2175
2176 pid_t dpc_pid;
2177 int dpc_should_die;
2178 struct completion dpc_inited;
2179 struct completion dpc_exited;
2180 struct semaphore *dpc_wait;
2181 uint8_t dpc_active; /* DPC routine is active */
2182
2183 /* Timeout timers. */
2184 uint8_t queue_restart_timer;
2185 uint8_t loop_down_abort_time; /* port down timer */
2186 atomic_t loop_down_timer; /* loop down timer */
2187 uint8_t link_down_timeout; /* link down timeout */
2188
2189 uint32_t timer_active;
2190 struct timer_list timer;
2191
2192 dma_addr_t gid_list_dma;
2193 struct gid_list_info *gid_list;
2194
2195 dma_addr_t rlc_rsp_dma;
2196 rpt_lun_cmd_rsp_t *rlc_rsp;
2197
2198 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2199 #define DMA_POOL_SIZE 256
2200 struct dma_pool *s_dma_pool;
2201
2202 dma_addr_t init_cb_dma;
2203 init_cb_t *init_cb;
2204
2205 dma_addr_t iodesc_pd_dma;
2206 port_database_t *iodesc_pd;
2207
2208 /* These are used by mailbox operations. */
2209 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2210
2211 mbx_cmd_t *mcp;
2212 unsigned long mbx_cmd_flags;
2213 #define MBX_INTERRUPT 1
2214 #define MBX_INTR_WAIT 2
2215 #define MBX_UPDATE_FLASH_ACTIVE 3
2216
2217 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2218
2219 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2220 struct semaphore mbx_intr_sem; /* Used for completion notification */
2221
2222 uint32_t mbx_flags;
2223 #define MBX_IN_PROGRESS BIT_0
2224 #define MBX_BUSY BIT_1 /* Got the Access */
2225 #define MBX_SLEEPING_ON_SEM BIT_2
2226 #define MBX_POLLING_FOR_COMP BIT_3
2227 #define MBX_COMPLETED BIT_4
2228 #define MBX_TIMEDOUT BIT_5
2229 #define MBX_ACCESS_TIMEDOUT BIT_6
2230
2231 mbx_cmd_t mc;
2232
2233 uint8_t *cmdline;
2234
2235 uint32_t failover_type;
2236 uint32_t failback_delay;
2237 unsigned long cfg_flags;
2238 #define CFG_ACTIVE 0 /* CFG during a failover, event update, or ioctl */
2239 #define CFG_FAILOVER 1 /* CFG during path change */
2240
2241 uint32_t binding_type;
2242 #define BIND_BY_PORT_NAME 0
2243 #define BIND_BY_PORT_ID 1
2244
2245 /* Basic firmware related information. */
2246 struct qla_board_info *brd_info;
2247 uint16_t fw_major_version;
2248 uint16_t fw_minor_version;
2249 uint16_t fw_subminor_version;
2250 uint16_t fw_attributes;
2251 uint32_t fw_memory_size;
2252 uint32_t fw_transfer_size;
2253
2254 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2255 uint8_t fw_seriallink_options[4];
2256
2257 /* Firmware dump information. */
2258 void *fw_dump;
2259 int fw_dump_order;
2260 int fw_dump_reading;
2261 char *fw_dump_buffer;
2262 int fw_dump_buffer_len;
2263
2264 uint8_t host_str[16];
2265 uint16_t pci_attr;
2266
2267 uint16_t product_id[4];
2268
2269 uint8_t model_number[16+1];
2270 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2271 char *model_desc;
2272
2273 uint8_t node_name[WWN_SIZE];
2274 uint8_t nvram_version;
2275 uint32_t isp_abort_cnt;
2276
2277 /* Adapter I/O statistics for failover */
2278 uint64_t IosRequested;
2279 uint64_t BytesRequested;
2280 uint64_t IosExecuted;
2281 uint64_t BytesExecuted;
2282
2283 /* Needed for BEACON */
2284 uint16_t beacon_blink_led;
2285 uint16_t beacon_green_on;
2286 } scsi_qla_host_t;
2287
2288
2289 /*
2290 * Macros to help code, maintain, etc.
2291 */
2292 #define LOOP_TRANSITION(ha) \
2293 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2294 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2295
2296 #define LOOP_NOT_READY(ha) \
2297 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2298 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2299 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2300 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2301 atomic_read(&ha->loop_state) == LOOP_DOWN)
2302
2303 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2304
2305 #define TGT_Q(ha, t) (ha->otgt[t])
2306
2307 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2308
2309 #define qla_printk(level, ha, format, arg...) \
2310 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2311
2312 /*
2313 * qla2x00 local function return status codes
2314 */
2315 #define MBS_MASK 0x3fff
2316
2317 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2318 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2319 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2320 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2321 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2322 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2323 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2324 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2325 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2326 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2327
2328 #define QLA_FUNCTION_TIMEOUT 0x100
2329 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2330 #define QLA_FUNCTION_FAILED 0x102
2331 #define QLA_MEMORY_ALLOC_FAILED 0x103
2332 #define QLA_LOCK_TIMEOUT 0x104
2333 #define QLA_ABORTED 0x105
2334 #define QLA_SUSPENDED 0x106
2335 #define QLA_BUSY 0x107
2336 #define QLA_RSCNS_HANDLED 0x108
2337
2338 /*
2339 * Stat info for all adpaters
2340 */
2341 struct _qla2x00stats {
2342 unsigned long mboxtout; /* mailbox timeouts */
2343 unsigned long mboxerr; /* mailbox errors */
2344 unsigned long ispAbort; /* ISP aborts */
2345 unsigned long debugNo;
2346 unsigned long loop_resync;
2347 unsigned long outarray_full;
2348 unsigned long retry_q_cnt;
2349 };
2350
2351 #define NVRAM_DELAY() udelay(10)
2352
2353 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2354
2355 /*
2356 * Flash support definitions
2357 */
2358 #define FLASH_IMAGE_SIZE 131072
2359
2360 #include "qla_gbl.h"
2361 #include "qla_dbg.h"
2362 #include "qla_inline.h"
2363
2364 /*
2365 * String arrays
2366 */
2367 #define LINESIZE 256
2368 #define MAXARGS 26
2369
2370 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2371 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2372 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2373 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2374 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2375 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2376
2377 #endif
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