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Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/gregkh/driver...
[linux-2.6/verdex.git] / drivers / scsi / sata_promise.c
blob19a13e3590f4eca5fab24675ffec12aaa56dd57f
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
13 * by reference.
14 *
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
25 *
26 */
27
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include "scsi.h"
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
39 #include <asm/io.h>
40 #include "sata_promise.h"
41
42 #define DRV_NAME "sata_promise"
43 #define DRV_VERSION "1.01"
44
45
46 enum {
47 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
48 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
49 PDC_TBG_MODE = 0x41, /* TBG mode */
50 PDC_FLASH_CTL = 0x44, /* Flash control register */
51 PDC_PCI_CTL = 0x48, /* PCI control and status register */
52 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
53 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
54 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
55 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
56
57 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
58 (1<<8) | (1<<9) | (1<<10),
59
60 board_2037x = 0, /* FastTrak S150 TX2plus */
61 board_20319 = 1, /* FastTrak S150 TX4 */
62
63 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
64
65 PDC_RESET = (1 << 11), /* HDMA reset */
66 };
67
68
69 struct pdc_port_priv {
70 u8 *pkt;
71 dma_addr_t pkt_dma;
72 };
73
74 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
75 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
76 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
77 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
78 static void pdc_eng_timeout(struct ata_port *ap);
79 static int pdc_port_start(struct ata_port *ap);
80 static void pdc_port_stop(struct ata_port *ap);
81 static void pdc_phy_reset(struct ata_port *ap);
82 static void pdc_qc_prep(struct ata_queued_cmd *qc);
83 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
84 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
85 static void pdc_irq_clear(struct ata_port *ap);
86 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
87
88 static Scsi_Host_Template pdc_ata_sht = {
89 .module = THIS_MODULE,
90 .name = DRV_NAME,
91 .ioctl = ata_scsi_ioctl,
92 .queuecommand = ata_scsi_queuecmd,
93 .eh_strategy_handler = ata_scsi_error,
94 .can_queue = ATA_DEF_QUEUE,
95 .this_id = ATA_SHT_THIS_ID,
96 .sg_tablesize = LIBATA_MAX_PRD,
97 .max_sectors = ATA_MAX_SECTORS,
98 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
99 .emulated = ATA_SHT_EMULATED,
100 .use_clustering = ATA_SHT_USE_CLUSTERING,
101 .proc_name = DRV_NAME,
102 .dma_boundary = ATA_DMA_BOUNDARY,
103 .slave_configure = ata_scsi_slave_config,
104 .bios_param = ata_std_bios_param,
105 .ordered_flush = 1,
106 };
107
108 static struct ata_port_operations pdc_ata_ops = {
109 .port_disable = ata_port_disable,
110 .tf_load = pdc_tf_load_mmio,
111 .tf_read = ata_tf_read,
112 .check_status = ata_check_status,
113 .exec_command = pdc_exec_command_mmio,
114 .dev_select = ata_std_dev_select,
115 .phy_reset = pdc_phy_reset,
116 .qc_prep = pdc_qc_prep,
117 .qc_issue = pdc_qc_issue_prot,
118 .eng_timeout = pdc_eng_timeout,
119 .irq_handler = pdc_interrupt,
120 .irq_clear = pdc_irq_clear,
121 .scr_read = pdc_sata_scr_read,
122 .scr_write = pdc_sata_scr_write,
123 .port_start = pdc_port_start,
124 .port_stop = pdc_port_stop,
125 };
126
127 static struct ata_port_info pdc_port_info[] = {
128 /* board_2037x */
129 {
130 .sht = &pdc_ata_sht,
131 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
132 ATA_FLAG_SRST | ATA_FLAG_MMIO,
133 .pio_mask = 0x1f, /* pio0-4 */
134 .mwdma_mask = 0x07, /* mwdma0-2 */
135 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
136 .port_ops = &pdc_ata_ops,
137 },
138
139 /* board_20319 */
140 {
141 .sht = &pdc_ata_sht,
142 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
143 ATA_FLAG_SRST | ATA_FLAG_MMIO,
144 .pio_mask = 0x1f, /* pio0-4 */
145 .mwdma_mask = 0x07, /* mwdma0-2 */
146 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
147 .port_ops = &pdc_ata_ops,
148 },
149 };
150
151 static struct pci_device_id pdc_ata_pci_tbl[] = {
152 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
153 board_2037x },
154 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
155 board_2037x },
156 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
157 board_2037x },
158 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
159 board_2037x },
160 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
161 board_2037x },
162 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
163 board_2037x },
164
165 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
166 board_20319 },
167 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
168 board_20319 },
169 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
170 board_20319 },
171
172 { } /* terminate list */
173 };
174
175
176 static struct pci_driver pdc_ata_pci_driver = {
177 .name = DRV_NAME,
178 .id_table = pdc_ata_pci_tbl,
179 .probe = pdc_ata_init_one,
180 .remove = ata_pci_remove_one,
181 };
182
183
184 static int pdc_port_start(struct ata_port *ap)
185 {
186 struct device *dev = ap->host_set->dev;
187 struct pdc_port_priv *pp;
188 int rc;
189
190 rc = ata_port_start(ap);
191 if (rc)
192 return rc;
193
194 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
195 if (!pp) {
196 rc = -ENOMEM;
197 goto err_out;
198 }
199 memset(pp, 0, sizeof(*pp));
200
201 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
202 if (!pp->pkt) {
203 rc = -ENOMEM;
204 goto err_out_kfree;
205 }
206
207 ap->private_data = pp;
208
209 return 0;
210
211 err_out_kfree:
212 kfree(pp);
213 err_out:
214 ata_port_stop(ap);
215 return rc;
216 }
217
218
219 static void pdc_port_stop(struct ata_port *ap)
220 {
221 struct device *dev = ap->host_set->dev;
222 struct pdc_port_priv *pp = ap->private_data;
223
224 ap->private_data = NULL;
225 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
226 kfree(pp);
227 ata_port_stop(ap);
228 }
229
230
231 static void pdc_reset_port(struct ata_port *ap)
232 {
233 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
234 unsigned int i;
235 u32 tmp;
236
237 for (i = 11; i > 0; i--) {
238 tmp = readl(mmio);
239 if (tmp & PDC_RESET)
240 break;
241
242 udelay(100);
243
244 tmp |= PDC_RESET;
245 writel(tmp, mmio);
246 }
247
248 tmp &= ~PDC_RESET;
249 writel(tmp, mmio);
250 readl(mmio); /* flush */
251 }
252
253 static void pdc_phy_reset(struct ata_port *ap)
254 {
255 pdc_reset_port(ap);
256 sata_phy_reset(ap);
257 }
258
259 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
260 {
261 if (sc_reg > SCR_CONTROL)
262 return 0xffffffffU;
263 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
264 }
265
266
267 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
268 u32 val)
269 {
270 if (sc_reg > SCR_CONTROL)
271 return;
272 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
273 }
274
275 static void pdc_qc_prep(struct ata_queued_cmd *qc)
276 {
277 struct pdc_port_priv *pp = qc->ap->private_data;
278 unsigned int i;
279
280 VPRINTK("ENTER\n");
281
282 switch (qc->tf.protocol) {
283 case ATA_PROT_DMA:
284 ata_qc_prep(qc);
285 /* fall through */
286
287 case ATA_PROT_NODATA:
288 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
289 qc->dev->devno, pp->pkt);
290
291 if (qc->tf.flags & ATA_TFLAG_LBA48)
292 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
293 else
294 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
295
296 pdc_pkt_footer(&qc->tf, pp->pkt, i);
297 break;
298
299 default:
300 break;
301 }
302 }
303
304 static void pdc_eng_timeout(struct ata_port *ap)
305 {
306 u8 drv_stat;
307 struct ata_queued_cmd *qc;
308
309 DPRINTK("ENTER\n");
310
311 qc = ata_qc_from_tag(ap, ap->active_tag);
312 if (!qc) {
313 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
314 ap->id);
315 goto out;
316 }
317
318 /* hack alert! We cannot use the supplied completion
319 * function from inside the ->eh_strategy_handler() thread.
320 * libata is the only user of ->eh_strategy_handler() in
321 * any kernel, so the default scsi_done() assumes it is
322 * not being called from the SCSI EH.
323 */
324 qc->scsidone = scsi_finish_command;
325
326 switch (qc->tf.protocol) {
327 case ATA_PROT_DMA:
328 case ATA_PROT_NODATA:
329 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
330 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
331 break;
332
333 default:
334 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
335
336 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
337 ap->id, qc->tf.command, drv_stat);
338
339 ata_qc_complete(qc, drv_stat);
340 break;
341 }
342
343 out:
344 DPRINTK("EXIT\n");
345 }
346
347 static inline unsigned int pdc_host_intr( struct ata_port *ap,
348 struct ata_queued_cmd *qc)
349 {
350 u8 status;
351 unsigned int handled = 0, have_err = 0;
352 u32 tmp;
353 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
354
355 tmp = readl(mmio);
356 if (tmp & PDC_ERR_MASK) {
357 have_err = 1;
358 pdc_reset_port(ap);
359 }
360
361 switch (qc->tf.protocol) {
362 case ATA_PROT_DMA:
363 case ATA_PROT_NODATA:
364 status = ata_wait_idle(ap);
365 if (have_err)
366 status |= ATA_ERR;
367 ata_qc_complete(qc, status);
368 handled = 1;
369 break;
370
371 default:
372 ap->stats.idle_irq++;
373 break;
374 }
375
376 return handled;
377 }
378
379 static void pdc_irq_clear(struct ata_port *ap)
380 {
381 struct ata_host_set *host_set = ap->host_set;
382 void *mmio = host_set->mmio_base;
383
384 readl(mmio + PDC_INT_SEQMASK);
385 }
386
387 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
388 {
389 struct ata_host_set *host_set = dev_instance;
390 struct ata_port *ap;
391 u32 mask = 0;
392 unsigned int i, tmp;
393 unsigned int handled = 0;
394 void *mmio_base;
395
396 VPRINTK("ENTER\n");
397
398 if (!host_set || !host_set->mmio_base) {
399 VPRINTK("QUICK EXIT\n");
400 return IRQ_NONE;
401 }
402
403 mmio_base = host_set->mmio_base;
404
405 /* reading should also clear interrupts */
406 mask = readl(mmio_base + PDC_INT_SEQMASK);
407
408 if (mask == 0xffffffff) {
409 VPRINTK("QUICK EXIT 2\n");
410 return IRQ_NONE;
411 }
412 mask &= 0xffff; /* only 16 tags possible */
413 if (!mask) {
414 VPRINTK("QUICK EXIT 3\n");
415 return IRQ_NONE;
416 }
417
418 spin_lock(&host_set->lock);
419
420 writel(mask, mmio_base + PDC_INT_SEQMASK);
421
422 for (i = 0; i < host_set->n_ports; i++) {
423 VPRINTK("port %u\n", i);
424 ap = host_set->ports[i];
425 tmp = mask & (1 << (i + 1));
426 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
427 struct ata_queued_cmd *qc;
428
429 qc = ata_qc_from_tag(ap, ap->active_tag);
430 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
431 handled += pdc_host_intr(ap, qc);
432 }
433 }
434
435 spin_unlock(&host_set->lock);
436
437 VPRINTK("EXIT\n");
438
439 return IRQ_RETVAL(handled);
440 }
441
442 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
443 {
444 struct ata_port *ap = qc->ap;
445 struct pdc_port_priv *pp = ap->private_data;
446 unsigned int port_no = ap->port_no;
447 u8 seq = (u8) (port_no + 1);
448
449 VPRINTK("ENTER, ap %p\n", ap);
450
451 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
452 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
453
454 pp->pkt[2] = seq;
455 wmb(); /* flush PRD, pkt writes */
456 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
457 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
458 }
459
460 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
461 {
462 switch (qc->tf.protocol) {
463 case ATA_PROT_DMA:
464 case ATA_PROT_NODATA:
465 pdc_packet_start(qc);
466 return 0;
467
468 case ATA_PROT_ATAPI_DMA:
469 BUG();
470 break;
471
472 default:
473 break;
474 }
475
476 return ata_qc_issue_prot(qc);
477 }
478
479 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
480 {
481 WARN_ON (tf->protocol == ATA_PROT_DMA ||
482 tf->protocol == ATA_PROT_NODATA);
483 ata_tf_load(ap, tf);
484 }
485
486
487 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
488 {
489 WARN_ON (tf->protocol == ATA_PROT_DMA ||
490 tf->protocol == ATA_PROT_NODATA);
491 ata_exec_command(ap, tf);
492 }
493
494
495 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
496 {
497 port->cmd_addr = base;
498 port->data_addr = base;
499 port->feature_addr =
500 port->error_addr = base + 0x4;
501 port->nsect_addr = base + 0x8;
502 port->lbal_addr = base + 0xc;
503 port->lbam_addr = base + 0x10;
504 port->lbah_addr = base + 0x14;
505 port->device_addr = base + 0x18;
506 port->command_addr =
507 port->status_addr = base + 0x1c;
508 port->altstatus_addr =
509 port->ctl_addr = base + 0x38;
510 }
511
512
513 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
514 {
515 void *mmio = pe->mmio_base;
516 u32 tmp;
517
518 /*
519 * Except for the hotplug stuff, this is voodoo from the
520 * Promise driver. Label this entire section
521 * "TODO: figure out why we do this"
522 */
523
524 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
525 tmp = readl(mmio + PDC_FLASH_CTL);
526 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
527 writel(tmp, mmio + PDC_FLASH_CTL);
528
529 /* clear plug/unplug flags for all ports */
530 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
531 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
532
533 /* mask plug/unplug ints */
534 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
535 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
536
537 /* reduce TBG clock to 133 Mhz. */
538 tmp = readl(mmio + PDC_TBG_MODE);
539 tmp &= ~0x30000; /* clear bit 17, 16*/
540 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
541 writel(tmp, mmio + PDC_TBG_MODE);
542
543 readl(mmio + PDC_TBG_MODE); /* flush */
544 msleep(10);
545
546 /* adjust slew rate control register. */
547 tmp = readl(mmio + PDC_SLEW_CTL);
548 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
549 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
550 writel(tmp, mmio + PDC_SLEW_CTL);
551 }
552
553 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
554 {
555 static int printed_version;
556 struct ata_probe_ent *probe_ent = NULL;
557 unsigned long base;
558 void *mmio_base;
559 unsigned int board_idx = (unsigned int) ent->driver_data;
560 int pci_dev_busy = 0;
561 int rc;
562
563 if (!printed_version++)
564 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
565
566 /*
567 * If this driver happens to only be useful on Apple's K2, then
568 * we should check that here as it has a normal Serverworks ID
569 */
570 rc = pci_enable_device(pdev);
571 if (rc)
572 return rc;
573
574 rc = pci_request_regions(pdev, DRV_NAME);
575 if (rc) {
576 pci_dev_busy = 1;
577 goto err_out;
578 }
579
580 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
581 if (rc)
582 goto err_out_regions;
583 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
584 if (rc)
585 goto err_out_regions;
586
587 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
588 if (probe_ent == NULL) {
589 rc = -ENOMEM;
590 goto err_out_regions;
591 }
592
593 memset(probe_ent, 0, sizeof(*probe_ent));
594 probe_ent->dev = pci_dev_to_dev(pdev);
595 INIT_LIST_HEAD(&probe_ent->node);
596
597 mmio_base = ioremap(pci_resource_start(pdev, 3),
598 pci_resource_len(pdev, 3));
599 if (mmio_base == NULL) {
600 rc = -ENOMEM;
601 goto err_out_free_ent;
602 }
603 base = (unsigned long) mmio_base;
604
605 probe_ent->sht = pdc_port_info[board_idx].sht;
606 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
607 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
608 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
609 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
610 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
611
612 probe_ent->irq = pdev->irq;
613 probe_ent->irq_flags = SA_SHIRQ;
614 probe_ent->mmio_base = mmio_base;
615
616 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
617 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
618
619 probe_ent->port[0].scr_addr = base + 0x400;
620 probe_ent->port[1].scr_addr = base + 0x500;
621
622 /* notice 4-port boards */
623 switch (board_idx) {
624 case board_20319:
625 probe_ent->n_ports = 4;
626
627 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
628 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
629
630 probe_ent->port[2].scr_addr = base + 0x600;
631 probe_ent->port[3].scr_addr = base + 0x700;
632 break;
633 case board_2037x:
634 probe_ent->n_ports = 2;
635 break;
636 default:
637 BUG();
638 break;
639 }
640
641 pci_set_master(pdev);
642
643 /* initialize adapter */
644 pdc_host_init(board_idx, probe_ent);
645
646 /* FIXME: check ata_device_add return value */
647 ata_device_add(probe_ent);
648 kfree(probe_ent);
649
650 return 0;
651
652 err_out_free_ent:
653 kfree(probe_ent);
654 err_out_regions:
655 pci_release_regions(pdev);
656 err_out:
657 if (!pci_dev_busy)
658 pci_disable_device(pdev);
659 return rc;
660 }
661
662
663 static int __init pdc_ata_init(void)
664 {
665 return pci_module_init(&pdc_ata_pci_driver);
666 }
667
668
669 static void __exit pdc_ata_exit(void)
670 {
671 pci_unregister_driver(&pdc_ata_pci_driver);
672 }
673
674
675 MODULE_AUTHOR("Jeff Garzik");
676 MODULE_DESCRIPTION("Promise SATA TX2/TX4 low-level driver");
677 MODULE_LICENSE("GPL");
678 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
679 MODULE_VERSION(DRV_VERSION);
680
681 module_init(pdc_ata_init);
682 module_exit(pdc_ata_exit);
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