include/asm-m32r/ptrace.h

   1 #ifndef _ASM_M32R_PTRACE_H
   2 #define _ASM_M32R_PTRACE_H
   3
   4 /*
   5  * linux/include/asm-m32r/ptrace.h
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  *
  11  * M32R version:
  12  *   Copyright (C) 2001-2002, 2004  Hirokazu Takata <takata at linux-m32r.org>
  13  */
  14
  15 #include <linux/config.h>
  16 #include <asm/m32r.h>           /* M32R_PSW_BSM, M32R_PSW_BPM */
  17
  18 /* 0 - 13 are integer registers (general purpose registers).  */
  19 #define PT_R4           0
  20 #define PT_R5           1
  21 #define PT_R6           2
  22 #define PT_REGS         3
  23 #define PT_R0           4
  24 #define PT_R1           5
  25 #define PT_R2           6
  26 #define PT_R3           7
  27 #define PT_R7           8
  28 #define PT_R8           9
  29 #define PT_R9           10
  30 #define PT_R10          11
  31 #define PT_R11          12
  32 #define PT_R12          13
  33 #define PT_SYSCNR       14
  34 #define PT_R13          PT_FP
  35 #define PT_R14          PT_LR
  36 #define PT_R15          PT_SP
  37
  38 /* processor status and miscellaneous context registers.  */
  39 #if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
  40 #define PT_ACC0H        15
  41 #define PT_ACC0L        16
  42 #define PT_ACC1H        17
  43 #define PT_ACC1L        18
  44 #define PT_ACCH         PT_ACC0H
  45 #define PT_ACCL         PT_ACC0L
  46 #define PT_PSW          19
  47 #define PT_BPC          20
  48 #define PT_BBPSW        21
  49 #define PT_BBPC         22
  50 #define PT_SPU          23
  51 #define PT_FP           24
  52 #define PT_LR           25
  53 #define PT_SPI          26
  54 #define PT_ORIGR0       27
  55 #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
  56 #define PT_ACCH         15
  57 #define PT_ACCL         16
  58 #define PT_PSW          17
  59 #define PT_BPC          18
  60 #define PT_BBPSW        19
  61 #define PT_BBPC         20
  62 #define PT_SPU          21
  63 #define PT_FP           22
  64 #define PT_LR           23
  65 #define PT_SPI          24
  66 #define PT_ORIGR0       25
  67 #else
  68 #error unknown isa conifiguration
  69 #endif
  70
  71 /* virtual pt_reg entry for gdb */
  72 #define PT_PC           30
  73 #define PT_CBR          31
  74 #define PT_EVB          32
  75
  76
  77 /* Control registers.  */
  78 #define SPR_CR0 PT_PSW
  79 #define SPR_CR1 PT_CBR          /* read only */
  80 #define SPR_CR2 PT_SPI
  81 #define SPR_CR3 PT_SPU
  82 #define SPR_CR4
  83 #define SPR_CR5 PT_EVB          /* part of M32R/E, M32R/I core only */
  84 #define SPR_CR6 PT_BPC
  85 #define SPR_CR7
  86 #define SPR_CR8 PT_BBPSW
  87 #define SPR_CR9
  88 #define SPR_CR10
  89 #define SPR_CR11
  90 #define SPR_CR12
  91 #define SPR_CR13 PT_WR
  92 #define SPR_CR14 PT_BBPC
  93 #define SPR_CR15
  94
  95 /* this struct defines the way the registers are stored on the
  96    stack during a system call. */
  97 struct pt_regs {
  98         /* Saved main processor registers. */
  99         unsigned long r4;
 100         unsigned long r5;
 101         unsigned long r6;
 102         struct pt_regs *pt_regs;
 103         unsigned long r0;
 104         unsigned long r1;
 105         unsigned long r2;
 106         unsigned long r3;
 107         unsigned long r7;
 108         unsigned long r8;
 109         unsigned long r9;
 110         unsigned long r10;
 111         unsigned long r11;
 112         unsigned long r12;
 113         long syscall_nr;
 114
 115         /* Saved main processor status and miscellaneous context registers. */
 116 #if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
 117         unsigned long acc0h;
 118         unsigned long acc0l;
 119         unsigned long acc1h;
 120         unsigned long acc1l;
 121 #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
 122         unsigned long acch;
 123         unsigned long accl;
 124 #else
 125 #error unknown isa configuration
 126 #endif
 127         unsigned long psw;
 128         unsigned long bpc;              /* saved PC for TRAP syscalls */
 129         unsigned long bbpsw;
 130         unsigned long bbpc;
 131         unsigned long spu;              /* saved user stack */
 132         unsigned long fp;
 133         unsigned long lr;               /* saved PC for JL syscalls */
 134         unsigned long spi;              /* saved kernel stack */
 135         unsigned long orig_r0;
 136 };
 137
 138 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
 139 #define PTRACE_GETREGS          12
 140 #define PTRACE_SETREGS          13
 141
 142 #define PTRACE_OLDSETOPTIONS    21
 143
 144 /* options set using PTRACE_SETOPTIONS */
 145 #define PTRACE_O_TRACESYSGOOD   0x00000001
 146
 147 #ifdef __KERNEL__
 148 #if defined(CONFIG_ISA_M32R2) || defined(CONFIG_CHIP_VDEC2)
 149 #define user_mode(regs) ((M32R_PSW_BPM & (regs)->psw) != 0)
 150 #elif defined(CONFIG_ISA_M32R)
 151 #define user_mode(regs) ((M32R_PSW_BSM & (regs)->psw) != 0)
 152 #else
 153 #error unknown isa configuration
 154 #endif
 155
 156 #define instruction_pointer(regs) ((regs)->bpc)
 157 #define profile_pc(regs) instruction_pointer(regs)
 158
 159 extern void show_regs(struct pt_regs *);
 160
 161 extern void withdraw_debug_trap(struct pt_regs *regs);
 162
 163 #endif /* __KERNEL */
 164
 165 #endif /* _ASM_M32R_PTRACE_H */