include/asm-mips/ip32/mace.h

   1 /*
   2  * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000 Harald Koerfgen
   9  * Copyright (C) 2004 Ladislav Michl
  10  */
  11
  12 #ifndef __ASM_MACE_H__
  13 #define __ASM_MACE_H__
  14
  15 /*
  16  * Address map
  17  */
  18 #define MACE_BASE       0x1f000000      /* physical */
  19
  20 #undef BIT
  21 #define BIT(x) (1UL << (x))
  22
  23 /*
  24  * PCI interface
  25  */
  26 struct mace_pci {
  27         volatile unsigned int error_addr;
  28         volatile unsigned int error;
  29 #define MACEPCI_ERROR_MASTER_ABORT              BIT(31)
  30 #define MACEPCI_ERROR_TARGET_ABORT              BIT(30)
  31 #define MACEPCI_ERROR_DATA_PARITY_ERR           BIT(29)
  32 #define MACEPCI_ERROR_RETRY_ERR                 BIT(28)
  33 #define MACEPCI_ERROR_ILLEGAL_CMD               BIT(27)
  34 #define MACEPCI_ERROR_SYSTEM_ERR                BIT(26)
  35 #define MACEPCI_ERROR_INTERRUPT_TEST            BIT(25)
  36 #define MACEPCI_ERROR_PARITY_ERR                BIT(24)
  37 #define MACEPCI_ERROR_OVERRUN                   BIT(23)
  38 #define MACEPCI_ERROR_RSVD                      BIT(22)
  39 #define MACEPCI_ERROR_MEMORY_ADDR               BIT(21)
  40 #define MACEPCI_ERROR_CONFIG_ADDR               BIT(20)
  41 #define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID   BIT(19)
  42 #define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID   BIT(18)
  43 #define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID    BIT(17)
  44 #define MACEPCI_ERROR_RETRY_ADDR_VALID          BIT(16)
  45 #define MACEPCI_ERROR_SIG_TABORT                BIT(4)
  46 #define MACEPCI_ERROR_DEVSEL_MASK               0xc0
  47 #define MACEPCI_ERROR_DEVSEL_FAST               0
  48 #define MACEPCI_ERROR_DEVSEL_MED                0x40
  49 #define MACEPCI_ERROR_DEVSEL_SLOW               0x80
  50 #define MACEPCI_ERROR_FBB                       BIT(1)
  51 #define MACEPCI_ERROR_66MHZ                     BIT(0)
  52         volatile unsigned int control;
  53 #define MACEPCI_CONTROL_INT(x)                  BIT(x)
  54 #define MACEPCI_CONTROL_INT_MASK                0xff
  55 #define MACEPCI_CONTROL_SERR_ENA                BIT(8)
  56 #define MACEPCI_CONTROL_ARB_N6                  BIT(9)
  57 #define MACEPCI_CONTROL_PARITY_ERR              BIT(10)
  58 #define MACEPCI_CONTROL_MRMRA_ENA               BIT(11)
  59 #define MACEPCI_CONTROL_ARB_N3                  BIT(12)
  60 #define MACEPCI_CONTROL_ARB_N4                  BIT(13)
  61 #define MACEPCI_CONTROL_ARB_N5                  BIT(14)
  62 #define MACEPCI_CONTROL_PARK_LIU                BIT(15)
  63 #define MACEPCI_CONTROL_INV_INT(x)              BIT(16+x)
  64 #define MACEPCI_CONTROL_INV_INT_MASK            0x00ff0000
  65 #define MACEPCI_CONTROL_OVERRUN_INT             BIT(24)
  66 #define MACEPCI_CONTROL_PARITY_INT              BIT(25)
  67 #define MACEPCI_CONTROL_SERR_INT                BIT(26)
  68 #define MACEPCI_CONTROL_IT_INT                  BIT(27)
  69 #define MACEPCI_CONTROL_RE_INT                  BIT(28)
  70 #define MACEPCI_CONTROL_DPED_INT                BIT(29)
  71 #define MACEPCI_CONTROL_TAR_INT                 BIT(30)
  72 #define MACEPCI_CONTROL_MAR_INT                 BIT(31)
  73         volatile unsigned int rev;
  74         unsigned int _pad[0xcf8/4 - 4];
  75         volatile unsigned int config_addr;
  76         union {
  77                 volatile unsigned char b[4];
  78                 volatile unsigned short w[2];
  79                 volatile unsigned int l;
  80         } config_data;
  81 };
  82 #define MACEPCI_LOW_MEMORY              0x1a000000
  83 #define MACEPCI_LOW_IO                  0x18000000
  84 #define MACEPCI_SWAPPED_VIEW            0
  85 #define MACEPCI_NATIVE_VIEW             0x40000000
  86 #define MACEPCI_IO                      0x80000000
  87 #define MACEPCI_HI_MEMORY               0x280000000
  88 #define MACEPCI_HI_IO                   0x100000000
  89
  90 /*
  91  * Video interface
  92  */
  93 struct mace_video {
  94         unsigned long xxx;      /* later... */
  95 };
  96
  97 /*
  98  * Ethernet interface
  99  */
 100 struct mace_ethernet {
 101         volatile unsigned long mac_ctrl;
 102         volatile unsigned long int_stat;
 103         volatile unsigned long dma_ctrl;
 104         volatile unsigned long timer;
 105         volatile unsigned long tx_int_al;
 106         volatile unsigned long rx_int_al;
 107         volatile unsigned long tx_info;
 108         volatile unsigned long tx_info_al;
 109         volatile unsigned long rx_buff;
 110         volatile unsigned long rx_buff_al1;
 111         volatile unsigned long rx_buff_al2;
 112         volatile unsigned long diag;
 113         volatile unsigned long phy_data;
 114         volatile unsigned long phy_regs;
 115         volatile unsigned long phy_trans_go;
 116         volatile unsigned long backoff_seed;
 117         /*===================================*/
 118         volatile unsigned long imq_reserved[4];
 119         volatile unsigned long mac_addr;
 120         volatile unsigned long mac_addr2;
 121         volatile unsigned long mcast_filter;
 122         volatile unsigned long tx_ring_base;
 123         /* Following are read-only registers for debugging */
 124         volatile unsigned long tx_pkt1_hdr;
 125         volatile unsigned long tx_pkt1_ptr[3];
 126         volatile unsigned long tx_pkt2_hdr;
 127         volatile unsigned long tx_pkt2_ptr[3];
 128         /*===================================*/
 129         volatile unsigned long rx_fifo;
 130 };
 131
 132 /*
 133  * Peripherals
 134  */
 135
 136 /* Audio registers */
 137 struct mace_audio {
 138         volatile unsigned long control;
 139         volatile unsigned long codec_control;           /* codec status control */
 140         volatile unsigned long codec_mask;              /* codec status input mask */
 141         volatile unsigned long codec_read;              /* codec status read data */
 142         struct {
 143                 volatile unsigned long control;         /* channel control */
 144                 volatile unsigned long read_ptr;        /* channel read pointer */
 145                 volatile unsigned long write_ptr;       /* channel write pointer */
 146                 volatile unsigned long depth;           /* channel depth */
 147         } chan[3];
 148 };
 149
 150 /* ISA Control and DMA registers */
 151 struct mace_isactrl {
 152         volatile unsigned long ringbase;
 153 #define MACEISA_RINGBUFFERS_SIZE        (8 * 4096)
 154
 155         volatile unsigned long misc;
 156 #define MACEISA_FLASH_WE                BIT(0)  /* 1=> Enable FLASH writes */
 157 #define MACEISA_PWD_CLEAR               BIT(1)  /* 1=> PWD CLEAR jumper detected */
 158 #define MACEISA_NIC_DEASSERT            BIT(2)
 159 #define MACEISA_NIC_DATA                BIT(3)
 160 #define MACEISA_LED_RED                 BIT(4)  /* 0=> Illuminate red LED */
 161 #define MACEISA_LED_GREEN               BIT(5)  /* 0=> Illuminate green LED */
 162 #define MACEISA_DP_RAM_ENABLE           BIT(6)
 163
 164         volatile unsigned long istat;
 165         volatile unsigned long imask;
 166 #define MACEISA_AUDIO_SW_INT            BIT(0)
 167 #define MACEISA_AUDIO_SC_INT            BIT(1)
 168 #define MACEISA_AUDIO1_DMAT_INT         BIT(2)
 169 #define MACEISA_AUDIO1_OF_INT           BIT(3)
 170 #define MACEISA_AUDIO2_DMAT_INT         BIT(4)
 171 #define MACEISA_AUDIO2_MERR_INT         BIT(5)
 172 #define MACEISA_AUDIO3_DMAT_INT         BIT(6)
 173 #define MACEISA_AUDIO3_MERR_INT         BIT(7)
 174 #define MACEISA_RTC_INT                 BIT(8)
 175 #define MACEISA_KEYB_INT                BIT(9)
 176 #define MACEISA_KEYB_POLL_INT           BIT(10)
 177 #define MACEISA_MOUSE_INT               BIT(11)
 178 #define MACEISA_MOUSE_POLL_INT          BIT(12)
 179 #define MACEISA_TIMER0_INT              BIT(13)
 180 #define MACEISA_TIMER1_INT              BIT(14)
 181 #define MACEISA_TIMER2_INT              BIT(15)
 182 #define MACEISA_PARALLEL_INT            BIT(16)
 183 #define MACEISA_PAR_CTXA_INT            BIT(17)
 184 #define MACEISA_PAR_CTXB_INT            BIT(18)
 185 #define MACEISA_PAR_MERR_INT            BIT(19)
 186 #define MACEISA_SERIAL1_INT             BIT(20)
 187 #define MACEISA_SERIAL1_TDMAT_INT       BIT(21)
 188 #define MACEISA_SERIAL1_TDMAPR_INT      BIT(22)
 189 #define MACEISA_SERIAL1_TDMAME_INT      BIT(23)
 190 #define MACEISA_SERIAL1_RDMAT_INT       BIT(24)
 191 #define MACEISA_SERIAL1_RDMAOR_INT      BIT(25)
 192 #define MACEISA_SERIAL2_INT             BIT(26)
 193 #define MACEISA_SERIAL2_TDMAT_INT       BIT(27)
 194 #define MACEISA_SERIAL2_TDMAPR_INT      BIT(28)
 195 #define MACEISA_SERIAL2_TDMAME_INT      BIT(29)
 196 #define MACEISA_SERIAL2_RDMAT_INT       BIT(30)
 197 #define MACEISA_SERIAL2_RDMAOR_INT      BIT(31)
 198
 199         volatile unsigned long _pad[0x2000/8 - 4];
 200
 201         volatile unsigned long dp_ram[0x400];
 202 };
 203
 204 /* Keyboard & Mouse registers
 205  * -> drivers/input/serio/maceps2.c */
 206 struct mace_ps2port {
 207         volatile unsigned long tx;
 208         volatile unsigned long rx;
 209         volatile unsigned long control;
 210         volatile unsigned long status;
 211 };
 212
 213 struct mace_ps2 {
 214         struct mace_ps2port keyb;
 215         struct mace_ps2port mouse;
 216 };
 217
 218 /* I2C registers
 219  * -> drivers/i2c/algos/i2c-algo-sgi.c */
 220 struct mace_i2c {
 221         volatile unsigned long config;
 222 #define MACEI2C_RESET           BIT(0)
 223 #define MACEI2C_FAST            BIT(1)
 224 #define MACEI2C_DATA_OVERRIDE   BIT(2)
 225 #define MACEI2C_CLOCK_OVERRIDE  BIT(3)
 226 #define MACEI2C_DATA_STATUS     BIT(4)
 227 #define MACEI2C_CLOCK_STATUS    BIT(5)
 228         volatile unsigned long control;
 229         volatile unsigned long data;
 230 };
 231
 232 /* Timer registers */
 233 typedef union {
 234         volatile unsigned long ust_msc;
 235         struct reg {
 236                 volatile unsigned int ust;
 237                 volatile unsigned int msc;
 238         } reg;
 239 } timer_reg;
 240
 241 struct mace_timers {
 242         volatile unsigned long ust;
 243 #define MACE_UST_PERIOD_NS      960
 244
 245         volatile unsigned long compare1;
 246         volatile unsigned long compare2;
 247         volatile unsigned long compare3;
 248
 249         timer_reg audio_in;
 250         timer_reg audio_out1;
 251         timer_reg audio_out2;
 252         timer_reg video_in1;
 253         timer_reg video_in2;
 254         timer_reg video_out;
 255 };
 256
 257 struct mace_perif {
 258         struct mace_audio audio;
 259         char _pad0[0x10000 - sizeof(struct mace_audio)];
 260
 261         struct mace_isactrl ctrl;
 262         char _pad1[0x10000 - sizeof(struct mace_isactrl)];
 263
 264         struct mace_ps2 ps2;
 265         char _pad2[0x10000 - sizeof(struct mace_ps2)];
 266
 267         struct mace_i2c i2c;
 268         char _pad3[0x10000 - sizeof(struct mace_i2c)];
 269
 270         struct mace_timers timers;
 271         char _pad4[0x10000 - sizeof(struct mace_timers)];
 272 };
 273
 274
 275 /*
 276  * ISA peripherals
 277  */
 278
 279 /* Parallel port */
 280 struct mace_parallel {  /* later... */
 281 };
 282
 283 struct mace_ecp1284 {   /* later... */
 284 };
 285
 286 /* Serial port */
 287 struct mace_serial {
 288         volatile unsigned long xxx;     /* later... */
 289 };
 290
 291 struct mace_isa {
 292         struct mace_parallel parallel;
 293         char _pad1[0x8000 - sizeof(struct mace_parallel)];
 294
 295         struct mace_ecp1284 ecp1284;
 296         char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
 297
 298         struct mace_serial serial1;
 299         char _pad3[0x8000 - sizeof(struct mace_serial)];
 300
 301         struct mace_serial serial2;
 302         char _pad4[0x8000 - sizeof(struct mace_serial)];
 303
 304         volatile unsigned char rtc[0x10000];
 305 };
 306
 307 struct sgi_mace {
 308         char _reserved[0x80000];
 309
 310         struct mace_pci pci;
 311         char _pad0[0x80000 - sizeof(struct mace_pci)];
 312
 313         struct mace_video video_in1;
 314         char _pad1[0x80000 - sizeof(struct mace_video)];
 315
 316         struct mace_video video_in2;
 317         char _pad2[0x80000 - sizeof(struct mace_video)];
 318
 319         struct mace_video video_out;
 320         char _pad3[0x80000 - sizeof(struct mace_video)];
 321
 322         struct mace_ethernet eth;
 323         char _pad4[0x80000 - sizeof(struct mace_ethernet)];
 324
 325         struct mace_perif perif;
 326         char _pad5[0x80000 - sizeof(struct mace_perif)];
 327
 328         struct mace_isa isa;
 329         char _pad6[0x80000 - sizeof(struct mace_isa)];
 330 };
 331
 332 extern struct sgi_mace *mace;
 333
 334 #endif /* __ASM_MACE_H__ */