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[linux-2.6/verdex.git] / include / asm-ppc64 / sigcontext.h
blob6f8aee768c5e9413627490ef805bce9ecc10c5b9
1 #ifndef _ASM_PPC64_SIGCONTEXT_H
2 #define _ASM_PPC64_SIGCONTEXT_H
4 /*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10 #include <linux/compiler.h>
11 #include <asm/ptrace.h>
12 #include <asm/elf.h>
15 struct sigcontext {
16 unsigned long _unused[4];
17 int signal;
18 int _pad0;
19 unsigned long handler;
20 unsigned long oldmask;
21 struct pt_regs __user *regs;
22 elf_gregset_t gp_regs;
23 elf_fpregset_t fp_regs;
25 * To maintain compatibility with current implementations the sigcontext is
26 * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
27 * followed by an unstructured (vmx_reserve) field of 69 doublewords. This
28 * allows the array of vector registers to be quadword aligned independent of
29 * the alignment of the containing sigcontext or ucontext. It is the
30 * responsibility of the code setting the sigcontext to set this pointer to
31 * either NULL (if this processor does not support the VMX feature) or the
32 * address of the first quadword within the allocated (vmx_reserve) area.
34 * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
35 * an array of 34 quadword entries (elf_vrregset_t). The entries with
36 * indexes 0-31 contain the corresponding vector registers. The entry with
37 * index 32 contains the vscr as the last word (offset 12) within the
38 * quadword. This allows the vscr to be stored as either a quadword (since
39 * it must be copied via a vector register to/from storage) or as a word.
40 * The entry with index 33 contains the vrsave as the first word (offset 0)
41 * within the quadword.
43 elf_vrreg_t __user *v_regs;
44 long vmx_reserve[ELF_NVRREG+ELF_NVRREG+1];
47 #endif /* _ASM_PPC64_SIGCONTEXT_H */